Reset circuit for digital output module and IO module

Abstract

The utility model belongs to IO module technical field discloses a reset circuit and IO module for digital quantity output module. The circuit includes main control unit and digital quantity output unit, main control unit includes main control chip, and digital quantity output unit includes shift register, delay power -on circuit, pull -down resistance, the shift register is integrated with storage register in, the storage register is used for storing the signal of main control chip's issue, the shift register with main control chip communication connection, delay power -on circuit and shift register's power end electricity is connected, pull -down resistance and shift register's enable end electricity is connected, the enable end low level of shift register is effective, when the enable end input is high level, the output of shift register is in high resistance state. The utility model can carry out signal preservation when the exception, and in the MCU reset process according to the original signal output.

Description

Technical Field

[0001] This utility model relates to the field of I / O module technology, specifically to a reset circuit and I / O module for a digital output module. Background Technology

[0002] An I / O module is an interface module that connects a computer system or control system to external devices. Its main function is to realize signal conversion and input / output. Based on this, I / O modules are further divided into digital output modules and digital input modules.

[0003] During the output of digital data, system crashes or field interference can cause sudden interruptions in the digital data output of the digital output module. While existing technologies offer various reset methods for output interruptions, such as NRST reset, WDT reset, and WWDT reset, the output cannot be maintained during the reset process. This not only reduces data transmission efficiency but also makes it difficult to identify the point of failure, thus compromising the normal and safe operation of the entire system.

[0004] Therefore, there is an urgent need for a reliable reset circuit to solve the problem of loss of output status of digital output modules when the computer system or control system is abnormally reset, thereby improving the anti-interference capability and continuous operation of industrial field equipment. Utility Model Content

[0005] The purpose of this invention is to provide a reset circuit and I / O module for a digital output module, so as to solve the technical problem of loss of output state when the digital output module is abnormally reset in a computer system or control system.

[0006] To achieve the above objectives, the present invention proposes the following technical solution:

[0007] In a first aspect, this technical solution provides a reset circuit for a digital output module, including a main control unit and a digital output unit electrically connected to each other; wherein, the main control unit includes a main control chip, and the digital output unit includes a shift register, a delayed power-on circuit, and a pull-down resistor; wherein, the shift register integrates a storage register; the storage register is used to store the signals sent by the main control chip;

[0008] The shift register is communicatively connected to the main control chip, the delayed power-on circuit is electrically connected to the power supply terminal of the shift register, and the pull-down resistor is electrically connected to the enable terminal of the shift register. The enable terminal of the shift register is active low; when the enable input of the shift register is high, the output of the shift register is in a high-impedance state. The SRCLR# pin of the shift register is always high.

[0009] Furthermore, the delayed power-on circuit includes a first capacitor and a first resistor; one end of the first capacitor is electrically connected to the power supply terminal of the shift register, and the other end is grounded; one end of the first resistor is electrically connected to the power supply terminal of the shift register, and the other end is electrically connected to an external power supply.

[0010] Furthermore, the pull-down resistor includes a second resistor and a third resistor; one end of the second resistor is electrically connected to the enable terminal of the shift register, and the other end is electrically connected to the enable terminal of the main control chip; one end of the third resistor is electrically connected to the enable terminal of the shift register, and the other end is grounded.

[0011] Furthermore, it includes an isolation circuit, which comprises a fourth resistor, an optocoupler, and a fifth resistor; the first pin of the optocoupler is electrically connected to the output of the shift register via the fourth resistor; the second pin is grounded; the third pin is grounded via the fifth resistor and also serves as a signal output; the fourth pin is connected to an external power supply.

[0012] Furthermore, the model of the main control chip is: AT32F425C8T7.

[0013] Furthermore, the shift register is model number SN74HC595.

[0014] Furthermore, it includes an extended digital output unit; the extended digital output unit is communicatively connected to the shift register.

[0015] Furthermore, the main control chip supports the following reset methods: NRST reset, WDT reset, WWDT reset, CPU software reset, low power management reset, POR reset, LVR reset, and standby return reset.

[0016] Furthermore, both the main control chip and the shift register include SER pin, OE pin, RCLK pin, and SRCLK pin; wherein, pins with the same name on the main control chip and the shift register are connected one-to-one.

[0017] Furthermore, the storage register is an 8-bit D-type storage register.

[0018] Secondly, this technical solution provides an I / O module, including the aforementioned reset circuit.

[0019] Beneficial effects:

[0020] To address the shortcomings of existing I / O modules in handling the loss of output status of digital output modules during abnormal resets of computer or control systems, this technical solution provides a new reset circuit.

[0021] The reset circuit includes a main control unit and a digital output unit electrically connected to each other. The main control unit includes a main control chip, and the digital output unit includes a shift register, a delayed power-on circuit, and a pull-down resistor. The shift register integrates a storage register for storing signals sent by the main control chip. The shift register is communicatively connected to the main control chip, the delayed power-on circuit is electrically connected to the power supply terminal of the shift register, and the pull-down resistor is electrically connected to the enable terminal of the shift register. The enable terminal of the shift register is active low; when the enable input is high, the output of the shift register is in a high-impedance state. The SRCLR# pin of the shift register is always high.

[0022] During normal output, the enable pin of the shift register is low to enable its output. The main control chip sends output data to the shift register via the data line and saves the data in the storage register. When an MCU abnormal reset occurs, the enable pin of the shift register remains low due to the pull-down resistor, ensuring the continuity of data output during reset. Specifically, the constant high level input to the SRCLR# pin of the shift register ensures that the data in the storage register is not accidentally cleared, guaranteeing the reliability of data output during reset. The pull-down resistor connected to the enable pin of the shift register ensures that the digital output unit continues to output even during an MCU abnormal reset. Simultaneously, the delayed power-on circuit at the power supply delays the power-on time of the digital output unit, mitigating potential abnormal output during power-on and further ensuring the reliability of data output during MCU abnormal reset.

[0023] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below can be considered as part of the utility model subject matter of this disclosure, provided that such concepts do not contradict each other.

[0024] The foregoing and other aspects, embodiments, and features of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0025] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings, wherein:

[0026] Figure 1 This is a circuit diagram of the reset circuit for the digital output module described in this embodiment;

[0027] Figure 2 This is a circuit diagram of the isolation circuit in the reset circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the described embodiments of this utility model without creative effort are within the scope of protection of this utility model. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which this utility model pertains.

[0029] The terms "first," "second," and similar words used in this utility model patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, unless the context clearly indicates otherwise, the singular forms of "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" indicate that the element or object preceding "comprising" encompasses the features, integrals, steps, operations, elements, and / or components listed following "comprising" or "including," and do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] During the output of digital data, sudden interruptions in the digital data output of digital output modules frequently occur. While various reset methods exist for output interruptions in the prior art, data transmission generally needs to be restarted during the reset process. This not only reduces data transmission efficiency but also makes it difficult to identify the point of failure, thereby hindering the normal and safe operation of the entire system. Therefore, this embodiment aims to provide a reset circuit for digital output modules to solve the aforementioned technical problems.

[0031] The reset circuit for a digital output module disclosed in this utility model will be further described in detail below with reference to the embodiments shown in the accompanying drawings.

[0032] Combination Figure 1-2 As shown, the reset circuit includes a main control unit and a digital output unit electrically connected to each other. The main control unit includes a main control chip, and the digital output unit includes a shift register, a delayed power-on circuit, and pull-down resistors. The shift register integrates a storage register, which stores signals sent by the main control chip.

[0033] The shift register is communicatively connected to the main control chip, the delayed power-on circuit is electrically connected to the power supply terminal of the shift register, and the pull-down resistor is electrically connected to the enable terminal of the shift register. The enable terminal of the shift register is active low; when the enable input of the shift register is high, the output of the shift register is in a high-impedance state. The SRCLR# pin of the shift register is always high.

[0034] Specifically, the delayed power-on circuit includes a first capacitor and a first resistor; one end of the first capacitor is electrically connected to the power supply terminal of the shift register, and the other end is grounded; one end of the first resistor is electrically connected to the power supply terminal of the shift register, and the other end is electrically connected to an external power supply. The pull-down resistor includes a second resistor and a third resistor; one end of the second resistor is electrically connected to the enable terminal of the shift register, and the other end is electrically connected to the enable terminal of the main control chip; one end of the third resistor is electrically connected to the enable terminal of the shift register, and the other end is grounded.

[0035] In this specific implementation, the storage register is an 8-bit D-type register to meet the temporary storage requirements of the output signal. Both the main control chip and the shift register include SER, OE, RCLK, and SRCLK pins; pins with the same name are connected one-to-one via data lines to meet communication requirements. The shift register includes 8 digital output signals, implemented through QA to QH pins. Based on this, the main control chip is model AT32F425C8T7; its supported reset methods include: NRST reset (external NRST pin reset), WDT reset (watchdog overflow reset), WWDT reset (window watchdog overflow reset), CPU software reset, low-power management reset, POR reset (power-on reset), LVR reset (power-down reset), and standby return reset. The shift register is model SN74HC595.

[0036] In practical implementation, after the corresponding IO module powers on, the main control unit performs peripheral initialization to enable it to control the digital output unit module and enable its output function. The main control unit sends output data to the digital output unit module via the SPI peripheral. During real-time data interaction between the main control unit and the digital output module, a low-level input is given to the RCLK pin of the digital output unit module before each data transmission. After the data transmission is completed, a low-level input is given to the RCLK pin again, causing the digital output unit to save the control data to the storage register. The enabled digital output unit then outputs the value stored in the storage register. If the main control unit experiences an abnormal MCU reset and cannot control the enable input signal, the enable pin of the digital output unit module is set low by an external circuit to ensure that the corresponding module can continue to output. When the main control unit recovers, it can continue to control the module output normally.

[0037] To ensure that the communication of the entire system is not affected during the abnormal handover recovery process and to improve the stability of the output signal, the reset circuit also includes an isolation circuit. This isolation circuit includes a fourth resistor, an optocoupler, and a fifth resistor. The first pin of the optocoupler is electrically connected to the output of the shift register via the fourth resistor; the second pin is grounded; and the third pin is grounded via the fifth resistor, simultaneously serving as a signal output. Specifically, the optocoupler is model QX3H7B-CuH-S.

[0038] To enable the reset circuit to be applied in scenarios with high digital input requirements, it further includes an extended digital output unit; the extended digital output unit is communicatively connected to the shift register. This allows for cascading expansion of the digital output units. In this embodiment, when the shift register is an SN74HC595, pin 14 (SER# pin) of the cascaded next shift register is electrically connected to pin 9 of the previous shift register; the next shift register is connected to pins 11, 12, and 13 of the previous shift register, respectively.

[0039] In summary, during normal output, this embodiment maintains a low-level input at the enable pin of the shift register to enable its output. The main control chip sends output data to the shift register via the data line and saves the data in the shift register to the storage register. When an abnormal MCU reset occurs, the enable pin of the shift register remains low due to the pull-down resistor, ensuring the continuity of data output during MCU reset. The constant high-level input at the SRCLR# pin of the shift register ensures that the data in the storage register is not accidentally cleared, guaranteeing the reliability of data output during MCU reset. The external pull-down resistor at the enable pin of the shift register ensures that the digital output unit continues to output even during an abnormal reset of the main control unit. Furthermore, the delayed power-on circuit at the power supply delays the power-on time of the digital output unit, mitigating potential abnormal output during power-on and further ensuring the reliability of data output during MCU abnormal reset. Meanwhile, the communication quality during abnormal switching is ensured by setting up corresponding isolation circuits, and the application scenarios of the reset circuit are expanded by extending the digital output unit.

[0040] Meanwhile, this embodiment also provides an IO module, which includes the above-mentioned reset circuit. Therefore, in specific applications, it also has the technical advantage of being able to save signals in case of abnormality and output the original signals during reset.

[0041] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the claims.

Claims

1. A reset circuit for a digital output module, characterized in that, The system includes a main control unit and a digital output unit that are electrically connected to each other. The main control unit includes a main control chip, and the digital output unit includes a shift register, a delayed power-on circuit, and a pull-down resistor. The shift register integrates a storage register, which is used to store the signals sent by the main control chip. The shift register is communicatively connected to the main control chip, the delayed power-on circuit is electrically connected to the power supply terminal of the shift register, and the pull-down resistor is electrically connected to the enable terminal of the shift register. The enable terminal of the shift register is active low; when the enable input of the shift register is high, the output of the shift register is in a high-impedance state. The SRCLR# pin of the shift register is always high.

2. The reset circuit for a digital output module according to claim 1, characterized in that, The delayed power-on circuit includes a first capacitor and a first resistor; one end of the first capacitor is electrically connected to the power supply terminal of the shift register, and the other end is grounded; one end of the first resistor is electrically connected to the power supply terminal of the shift register, and the other end is electrically connected to an external power supply.

3. The reset circuit for a digital output module according to claim 1, characterized in that, The pull-down resistor includes a second resistor and a third resistor; one end of the second resistor is electrically connected to the enable terminal of the shift register, and the other end is electrically connected to the enable terminal of the main control chip; one end of the third resistor is electrically connected to the enable terminal of the shift register, and the other end is grounded.

4. The reset circuit for a digital output module according to claim 1, characterized in that, The device includes an isolation circuit, which comprises a fourth resistor, an optocoupler, and a fifth resistor. The first pin of the optocoupler is electrically connected to the output of the shift register via the fourth resistor; the second pin is grounded; the third pin is grounded via the fifth resistor and also serves as a signal output; and the fourth pin is connected to an external power supply.

5. The reset circuit for a digital output module according to claim 1, characterized in that, The main control chip is model number AT32F425C8T7.

6. The reset circuit for a digital output module according to claim 1, characterized in that, The shift register is model number SN74HC595.

7. The reset circuit for a digital output module according to claim 1, characterized in that, It includes an extended digital output unit; the extended digital output unit is communicatively connected to the shift register.

8. The reset circuit for a digital output module according to claim 1, characterized in that, The main control chip supports the following reset methods: NRST reset, WDT reset, WWDT reset, CPU software reset, low power management reset, POR reset, LVR reset, and standby return reset.

9. The reset circuit for a digital output module according to claim 1, characterized in that, The storage register is an 8-bit D-type storage register.

10. An I / O module, characterized in that, Includes the reset circuit described in any one of claims 1 to 9.

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