Display substrate and display device

Abstract

The display substrate and display device relate to the field of display technology. The display substrate includes a display area and a gate driving circuit located on at least one side of the display area; wherein, the display area includes multiple scan lines extending along the row direction and multiple sub-pixels arranged in an array along the row and column directions, and at least one scan line is disposed between two adjacent rows of sub-pixels; the gate driving circuit located on the same side of the display area includes multiple cascaded shift registers, the shift registers are connected to the scan lines, and at least two shift registers connected to different scan lines are located in the same row.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] With decreasing costs and increasing aesthetic requirements, the use of Gate On Array (GOA) in display substrates is becoming increasingly common. Summary of the Invention

[0003] This disclosure provides a display substrate, including a display area and a gate driving circuit located on at least one side of the display area;

[0004] The display area includes multiple scan lines extending along the row direction, and multiple sub-pixels arranged in an array along the row and column directions, with at least one scan line between two adjacent rows of sub-pixels;

[0005] The gate drive circuit located on the same side of the display area includes multiple cascaded shift registers connected to the scan lines, with at least two shift registers connected to different scan lines located in the same row.

[0006] In some implementations, the plurality of shift registers includes a first shift register and a second shift register arranged in the same row, wherein the first shift register and the second shift register are respectively connected to different scan lines;

[0007] The first shift register and the second shift register are symmetrically translated along the row direction, or the first shift register and the second shift register are mirror symmetrical about a first axis, which extends along the column direction.

[0008] In some embodiments, the plurality of shift registers includes a first register column and a second register column arranged along the row direction, and both the first register column and the second register column include a plurality of shift registers arranged along the column direction;

[0009] The shift register in the first register column is connected to the first signal line group, and the shift register in the second register column is connected to the second signal line group. Both the first signal line group and the second signal line group include at least one signal line, and the signal lines in the first signal line group and the signal lines in the second signal line group are not shared.

[0010] In some implementations, the first register column and the second register column are translated symmetrically in the row direction, the first signal line group and the second signal line group are translated symmetrically, and the translation distance of the first register column relative to the second register column is approximately equal to the translation distance of the first signal line group relative to the second signal line group.

[0011] In some embodiments, the plurality of shift registers includes a third register column and a fourth register column arranged adjacent to each other along the row direction, wherein both the third register column and the fourth register column include a plurality of shift registers arranged along the column direction;

[0012] The shift register in the third register column is connected to the third signal line group, and the shift register in the fourth register column is connected to the fourth signal line group. Both the third signal line group and the fourth signal line group include a first signal line and share the first signal line.

[0013] In some implementations, the first signal line is located between the third register column and the fourth register column.

[0014] In some embodiments, the first signal line includes at least one of the following: a clock signal line, a gate enable signal line, and a first gate disable signal line, wherein the gate enable signal line is used to provide a gate enable voltage, the gate enable voltage is used to turn on the thin-film transistor of the sub-pixel, and the first gate disable signal line is used to provide a gate disable voltage, the gate disable voltage is used to turn off the thin-film transistor of the sub-pixel.

[0015] In some implementations, the third register column and the fourth register column are mirror-symmetric about a second axis that extends along the column direction.

[0016] In some embodiments, the third signal line group further includes: a second signal line located on the side of the third register column opposite to the fourth register column, and / or located between the third register column and the first signal line;

[0017] The fourth signal line group further includes: a third signal line located on the side of the fourth register column opposite to the third register column, and / or located between the fourth register column and the first signal line.

[0018] In some embodiments, the second signal line and the third signal line are mirror-symmetrical about a third axis that extends along the column direction.

[0019] In some embodiments, the second signal line and the third signal line each independently include at least one of the following: a gate-on signal line, a first gate-off signal line, a frame start signal line, a first noise reduction voltage signal line, a second noise reduction voltage signal line, an initialization signal line, a second gate-off signal line, and a low gate-off signal line;

[0020] The gate enable signal line is used to provide a gate enable voltage, which is used to turn on the thin-film transistor of the sub-pixel. The first gate disable signal line and the second gate disable signal line are both used to provide a gate disable voltage, which is used to turn off the thin-film transistor of the sub-pixel. The low gate disable signal line is used to provide a low gate disable voltage, which is less than the gate disable voltage.

[0021] In some implementations, the plurality of shift registers includes a third shift register and a fourth shift register, the output of the third shift register being connected to the input of the fourth shift register, and the third shift register and the fourth shift register being located in the same column.

[0022] In some implementations, the plurality of shift registers are arranged in a zigzag or bow-shaped pattern in a cascaded order.

[0023] In some implementations, the number of shift registers connected to different scan lines and located in the same row is 2, and the shift registers of odd-numbered levels are located in the same column, while the shift registers of even-numbered levels are located in the same column.

[0024] In some embodiments, the gate drive circuit is also connected to multiple clock signal lines for transmitting M clock signals with different timing sequences.

[0025] The number of shift registers connected to different scan lines and located in the same row is N, where M is greater than N and M is divisible by N, and both M and N are positive integers.

[0026] In some implementations, the number of shift registers connected to different scan lines and located in the same row is greater than or equal to 2 and less than or equal to 4.

[0027] In some implementations, the number of shift registers connected to different scan lines and located in the same row is N, and in the column direction, the arrangement period of the shift registers is approximately equal to N times the arrangement period of the sub-pixels.

[0028] In some implementations, in the column direction, a scan line and a row of subpixels are arranged alternately, and the distance between two adjacent scan lines is approximately equal to the arrangement period of the subpixels along the column direction.

[0029] In some embodiments, the plurality of shift registers includes a first shift register and a second shift register arranged in the same row, the first shift register being located on the side of the second shift register away from the display area, and at least one clock signal line extending along the column direction is further provided between the first shift register and the second shift register, and the first shift register and the second shift register are respectively connected to different scan lines;

[0030] The first shift register is connected to the scan line via a remote lead, the remote lead including a first line segment and a second line segment. The first shift register, the first line segment, the second line segment and the scan line are connected in sequence. The first line segment and the clock signal line are disposed on different layers and intersect each other.

[0031] The two adjacent remote leads are a first remote lead and a second remote lead. The distance between the first segment of the first remote lead and the first segment of the second remote lead is less than the distance between the second segment of the first remote lead and the second segment of the second remote lead.

[0032] In some implementations, the second shift register is connected to the scan line via a proximity lead, and two adjacent proximity leads are a first proximity lead and a second proximity lead;

[0033] The second segment of the first remote lead, the first short lead, the second segment of the second remote lead, and the second short lead all extend along the row direction and are arranged sequentially along the column direction. The distance between the second segment of the first remote lead and the first short lead, and the distance between the second segment of the second remote lead and the second short lead, are all smaller than the distance between the second segment of the first short lead and the second remote lead.

[0034] In some embodiments, the near lead is connected to the reverse extension line, the reverse extension line is located on the side of the near lead away from the display area, and the reverse extension line and the near lead are disposed on different layers, while the near lead and the remote lead are disposed on the same layer.

[0035] In the orthographic projection on the plane where the display substrate is located, the second segment of the first remote lead overlaps with the reverse extension line connecting the first near lead, and the second segment of the second remote lead overlaps with the reverse extension line connecting the second near lead.

[0036] In some implementations, the second shift register is connected to the scan line via a proximity lead, and two adjacent proximity leads are a first proximity lead and a second proximity lead;

[0037] The second segment of the first remote lead, the first short lead, the second short lead, and the second segment of the second remote lead all extend along the row direction and are arranged sequentially along the column direction. The distance between the second segment of the first remote lead and the first short lead, and the distance between the second short lead and the second segment of the second remote lead, are all smaller than the distance between the first short lead and the second short lead.

[0038] In some embodiments, the shift register is connected to a clock signal line, which is also connected to multiple clock patterns that are spaced apart along the column direction. The clock signal line and the clock patterns are disposed on different layers and connected through a first via.

[0039] In some embodiments, the clock signal line includes an adjacent first sub-clock signal line and a second sub-clock signal line, wherein the first sub-clock signal line and the second sub-clock signal line are connected by a connecting portion;

[0040] The clock pattern includes: a first sub-pattern corresponding to the position of the first sub-clock signal line, a second sub-pattern corresponding to the position of the second sub-clock signal line, and a third sub-pattern corresponding to the position of the connecting portion. The first sub-pattern and the second sub-pattern extend along the column direction, and the third sub-pattern connects the first sub-pattern and the second sub-pattern.

[0041] In some embodiments, the display area further includes: multiple data lines extending along the column direction;

[0042] The multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes multiple sub-pixels arranged in the column direction. Multiple sub-pixels located in the same pixel unit are connected to the same data line and are respectively connected to different scan lines. The size of the sub-pixel along the row direction is larger than the size of the sub-pixel along the column direction.

[0043] In some embodiments, the display substrate includes two gate driving circuits, and the two gate driving circuits are located on opposite sides of the display area.

[0044] This disclosure provides a display device, including:

[0045] The display substrate as described in any embodiment; and

[0046] A source drive circuit is connected to the display substrate and is used to drive the display substrate to perform display.

[0047] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0049] Figure 1 A schematic diagram of a planar structure of a display substrate in the related art is shown as an example;

[0050] Figure 2 An exemplary schematic diagram of the structure of the first type of display substrate provided in this disclosure is shown;

[0051] Figure 3 An exemplary schematic diagram of the structure of the second type of display substrate provided in this disclosure is shown;

[0052] Figure 4a An exemplary circuit layout diagram of a first type of gate drive circuit is shown;

[0053] Figure 4b An exemplary circuit layout diagram of a column of shift registers in a first type of gate drive circuit is shown;

[0054] Figure 4c An exemplary circuit layout diagram of another column of shift registers in a first type of gate drive circuit is shown;

[0055] Figure 4d An exemplary lead layout diagram of a first type of gate drive circuit is shown;

[0056] Figure 5a An exemplary circuit layout diagram of a second type of gate drive circuit is shown;

[0057] Figure 5b An exemplary circuit layout diagram of a column of shift registers in a second type of gate drive circuit is shown;

[0058] Figure 5c An exemplary circuit layout diagram of another column of shift registers in a second type of gate drive circuit is shown;

[0059] Figure 5dAn exemplary first signal line layout diagram of a second type of gate drive circuit is shown;

[0060] Figure 5e An exemplary lead layout diagram of a second type of gate drive circuit is shown;

[0061] Figure 6a An exemplary circuit layout diagram of a third type of gate drive circuit is shown;

[0062] Figure 6b An exemplary first signal line layout diagram of a third type of gate drive circuit is shown;

[0063] Figure 6c An exemplary clock signal line layout diagram is shown;

[0064] Figure 7 An exemplary schematic diagram of the connection structure of a gate drive circuit is shown.

[0065] Figure 8 An exemplary schematic diagram of the arrangement of multiple shift registers in a gate drive circuit is shown;

[0066] Figure 9 An exemplary schematic diagram of the arrangement of multiple shift registers in another gate drive circuit is shown;

[0067] Figure 10 An exemplary schematic diagram of the connection structure between the clock pattern and the clock signal line is shown. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0069] Reference Figure 1 A schematic diagram of a display substrate in the related art is shown. (Refer to...) Figure 2 and Figure 3 A schematic diagram of the structure of the display substrate provided in this disclosure is shown as an example.

[0070] like Figures 1 to 3As shown, the display substrate includes a display area AA and a gate driving circuit GOA located on at least one side of the display area AA. The display area AA includes multiple scan lines SC extending along the row direction f1 and multiple sub-pixels PX arranged in an array along the row direction f1 and the column direction f2. The gate driving circuit GOA located on the same side of the display area AA includes multiple shift registers GOA units cascaded together. The shift registers GOA units are connected to the scan lines SC, and different scan lines SC are connected to different shift registers GOA units.

[0071] exist Figure 1 In the related technology shown, multiple shift registers GOA units connected to different scan lines SC are arranged along the column direction f2, with only one shift register GOA unit set in each row. The height of the shift register GOA unit in the column direction f2 is approximately the height of a row of sub-pixels PX.

[0072] like Figure 2 or Figure 3 As shown, at least two shift registers GOA units connected to different scan lines SC are located in the same row. That is, multiple shift registers GOA units connected to different scan lines SC are arranged in an array along the row direction f1 and the column direction f2, and at least two shift registers GOA units connected to different scan lines SC are set in the same row.

[0073] The display substrate provided in this disclosure arranges multiple shift registers GOA units connected to different scan lines SC in the same row, such as two, three, four or more shift registers GOA units in one row. In this way, the shift registers GOA units can occupy the height of two, three, four or more rows of sub-pixels PX in the column direction f2, thereby increasing the height space of the shift registers GOA units in the column direction f2, which is beneficial to realizing a display substrate with a small sub-pixel PX arrangement period.

[0074] For example, multiple shift registers GOA units located on the same side of the display area AA and cascaded together include a first-level shift register GOA unit 1st connected to the first row of sub-pixels PX, a second-level shift register GOA unit 2nd connected to the second row of sub-pixels PX, a third-level shift register GOA unit 3rd connected to the third row of sub-pixels PX3, and so on. For each shift register GOA unit, the level of the shift register GOA unit is the number of rows of sub-pixels PX connected to that shift register GOA unit.

[0075] For example, such as Figure 2As shown, in the gate drive circuit GOA, two shift registers GOA units connected to different scan lines SC are set in parallel in a row. In this way, the shift registers GOA units can occupy the height of two rows of sub-pixels PX in the column direction f2.

[0076] For example, such as Figure 3 As shown, in the gate drive circuit GOA, four shift register GOA units connected to different scan lines SC are arranged in parallel in a row. In this way, the shift register GOA unit can occupy the height of four rows of sub-pixels PX in the column direction f2.

[0077] For example, for a display substrate with a pixel unit P size of 126.6μm * 126.6μm, the height of a row of sub-pixels PX is 42.2μm. Figure 1 In the display substrate shown, since the shift register GOAunit occupies the height of one row of sub-pixels PX in the column direction f2, the height of the shift register GOAunit in the column direction f2 is approximately 42.2 μm. Since the height of a thin-film transistor in the column direction f2 is approximately 39 μm, there is only enough space in the 42.2 μm height to place one thin-film transistor, leaving no extra space for related signal lines.

[0078] exist Figure 2 In the display substrate shown, since the shift register GOA unit can occupy the height of two rows of sub-pixels PX in the column direction f2, the height of the shift register GOA unit in the column direction f2 is approximately 84.4μm. This increases the height space of the shift register GOA unit in the column direction f2, which facilitates the arrangement of thin film transistors and related signal lines.

[0079] exist Figure 3 In the display substrate shown, since the shift register GOA unit occupies the height of four rows of sub-pixels PX in the column direction f2, the height of the shift register GOA unit in the column direction f2 is approximately 168.8μm. This increases the height space of the shift register GOA unit in the column direction f2, which facilitates the arrangement of thin film transistors and related signal lines.

[0080] In this disclosure, the gate drive circuit GOA is used to sequentially provide scan signals to the scan lines SC, the scan signals being, for example, pulse signals.

[0081] In some implementations, such as Figure 2 or Figure 3 As shown, at least one scan line SC is provided between two adjacent rows of sub-pixels PX. For example, in Figure 2 and Figure 3In the image, a scan line SC is set between two adjacent rows of sub-pixels PX.

[0082] In practice, to avoid crosstalk between adjacent sub-pixels PX, a gap is provided between two adjacent rows of sub-pixels PX. By setting at least one scan line SC between two adjacent rows of sub-pixels PX, the gap space can be fully utilized, which is beneficial to improving the aperture ratio.

[0083] In some implementations, such as Figure 2 or Figure 3 As shown, at least one row of sub-pixels PX is provided between two adjacent scan lines SC. For example, in Figure 2 and Figure 3 In the image, a row of sub-pixels PX is set between two adjacent scan lines SC.

[0084] For example, such as Figure 2 or Figure 3 As shown, a scan line SC and a row of sub-pixels PX are arranged alternately. This helps improve the display uniformity of the display substrate and avoids horizontal stripe defects caused by multiple scan lines SC and multiple rows of sub-pixels PX being arranged alternately.

[0085] In some implementations, such as Figure 2 or Figure 3 As shown, in the column direction f2, the distance between two adjacent scan lines SC is approximately equal to the arrangement period of sub-pixel PX along the column direction f2.

[0086] In some implementations, such as Figure 4a , Figure 5a or Figure 6a As shown, the multiple shift registers GOA unit include a first shift register GOA unit1 and a second shift register GOA unit2 arranged in the same row. The first shift register GOA unit1 and the second shift register GOA unit2 are respectively connected to different scan lines SC.

[0087] In this context, the first shift register GOAunit1 and the second shift register GOAunit2 can be any two shift registers GOAunit located in the same row. For example, the first shift register GOAunit1 can be the first-stage shift register GOAunit 1st, and the second shift register GOAunit2 can be the second-stage shift register GOAunit 2nd, as shown below. Figure 4a , Figure 5a or Figure 6a As shown.

[0088] For example, such as Figure 4a , Figure 5a or Figure 6aAs shown, the first shift register GOAunit1 is the third-level shift register GOAunit 3rd, and the second shift register GOAunit2 is the fourth-level shift register GOAunit 4th. Alternatively, the first shift register GOA unit1 can be the fifth-level shift register GOA unit 5th, and the second shift register GOA unit2 can be the sixth-level shift register GOA unit 6th. Another example is that the first shift register GOA unit1 can be the seventh-level shift register GOA unit 7th, and the second shift register GOA unit2 can be the eighth-level shift register GOA unit 8th.

[0089] For example, such as Figure 4a As shown, the first shift register GOA unit1 and the second shift register GOA unit2 are translated symmetrically along the row direction f1. That is, the first shift register GOA unit1 can at least partially overlap with the second shift register GOA unit2 after being translated a certain distance along the row direction f1.

[0090] For example, such as Figure 5a or Figure 6a As shown, the first shift register GOA unit1 and the second shift register GOA unit2 are mirror-symmetrical about a first axis, which extends along the column direction f2. That is, after rotating the first shift register GOA unit1 180° about the first axis, it can at least partially coincide with the second shift register GOA unit2.

[0091] In some implementations, such as Figure 4a As shown, the multiple shift register GOA units include a first register column 41 and a second register column 42 arranged along the row direction f1. Both the first register column 41 and the second register column 42 include multiple shift register GOA units arranged along the column direction f2. The shift register GOA units in the first register column 41 and the shift register GOA units in the second register column 42 are respectively connected to different scan lines SC.

[0092] like Figure 4a As shown, the shift register GOAunit in the first register column 41 is connected to the first signal line group 43, and the shift register GOA unit in the second register column 42 is connected to the second signal line group 44. Both the first signal line group 43 and the second signal line group 44 include at least one signal line, and the signal lines in the first signal line group 43 and the second signal line group 44 are not shared.

[0093] That is, such as Figure 4aAs shown, the signal lines in the second signal line group 44 are not connected to the shift register GOA unit in the first register column 41, and the signal lines in the first signal line group 43 are not connected to the shift register GOA unit in the second register column 42.

[0094] In some implementations, such as Figure 4a As shown, in the row direction f1, the first register column 41 and the second register column 42 are translated symmetrically, the first signal line group 43 and the second signal line group 44 are translated symmetrically, and the translation distance of the first register column 41 relative to the second register column 42 is approximately equal to the translation distance of the first signal line group 43 relative to the second signal line group 44.

[0095] For example, the translation distance of the first register column 41 relative to the second shift register GOA unit2 is the first distance, and the translation distance of the first signal line group 43 relative to the second signal line group 44 is also the first distance.

[0096] For example, the first signal line group 43 and the second signal line group 44 each independently include at least one of the following signal lines: clock signal line CLK, gate enable signal line VGH, first gate disable signal line VGL1, frame start signal line STV, first noise reduction voltage signal line VDDE, second noise reduction voltage signal line VDDO, initialization signal line INIT, second gate disable signal line VGL2, and low gate disable signal line LVGL.

[0097] For example, the gate-on signal line VGH provides a gate-on voltage to turn on the thin-film transistor of the sub-pixel PX. The first gate-off signal line VGL1 and the second gate-off signal line VGL2 both provide a gate-off voltage to turn off the thin-film transistor of the sub-pixel PX. The low gate-off signal line LVGL provides a low gate-off voltage, which is less than the gate-off voltage. The first gate-off signal line VGL1 and the second gate-off signal line VGL2 can be connected to the same signal input terminal.

[0098] In some implementations, such as Figure 4a As shown, the signal lines in the first signal line group 43 can be located on the side of the first register column 41 away from the second register column 42, and / or on the side closer to the second register column 42.

[0099] like Figure 4bAs shown, the first signal line group 43 includes: multiple clock signal lines CLK, gate enable signal line VGH, first gate disable signal line VGL1, frame start signal line STV, first noise reduction voltage signal line VDDE, second noise reduction voltage signal line VDDO, initialization signal line INIT, second gate disable signal line VGL2, and low gate disable signal line LVGL. The first signal line group 43 is divided into a first group 43-1 and a second group 43-2. ​​The first group 43-1 includes the frame start signal line STV, the first noise reduction voltage signal line VDDE, the second noise reduction voltage signal line VDDO, the initialization signal line INIT, the second gate disable signal line VGL2, and the low gate disable signal line LVGL, arranged sequentially along the row direction f1, and is located on the side of the first register column 41 away from the second register column 42. The second group 43-2 includes a gate enable signal line VGH, a first gate disable signal line VGL1, and multiple clock signal lines CLK arranged sequentially along the row direction f1, and is located on the side of the first register column 41 close to the second register column 42.

[0100] In some implementations, such as Figure 4a As shown, the signal lines in the second signal line group 44 can be located on the side of the second register column 42 away from the first register column 41, and / or on the side closer to the first register column 41.

[0101] like Figure 4c As shown, the second signal line group 44 includes: multiple clock signal lines CLK, gate enable signal line VGH, first gate disable signal line VGL1, frame start signal line STV, first noise reduction voltage signal line VDDE, second noise reduction voltage signal line VDDO, initialization signal line INIT, second gate disable signal line VGL2, and low gate disable signal line LVGL. The second signal line group 44 is further divided into a third group 44-1 and a fourth group 44-2. The third group 44-1 includes the frame start signal line STV, first noise reduction voltage signal line VDDE, second noise reduction voltage signal line VDDO, initialization signal line INIT, second gate disable signal line VGL2, and low gate disable signal line LVGL, arranged sequentially along the row direction f1, and is located on the side of the second register column 42 closest to the first register column 41. The fourth group 44-2 includes a gate enable signal line VGH, a first gate disable signal line VGL1, and multiple clock signal lines CLK arranged sequentially along the row direction f1, and is located on the side of the second register column 42 away from the first register column 41.

[0102] In specific implementation, the first register column 41 and the second register column 42 can also be mirror-symmetrical, and the first signal line group 43 and the second signal line group 44 can also be mirror-symmetrical. This disclosure does not limit this.

[0103] exist Figure 4a In the display substrate shown, because the clock signal line CLK in the first signal line group 43 and the clock signal line CLK in the second signal line group 44 are in different positions, the surrounding environment of the clock signal line CLK (such as the case where the clock signal line CLK is covered with a sealing glue and a light-shielding layer) is quite different, resulting in a large load difference between the clock signal line CLK in the first signal line group 43 and the clock signal line CLK in the second signal line group 44.

[0104] To address the issue of large load variations, in some implementation methods, such as... Figure 5a or Figure 6a As shown, the multiple shift register GOA units include a third register column 51 and a fourth register column 52 arranged adjacently along the row direction f1. Both the third register column 51 and the fourth register column 52 include multiple shift register GOA units arranged along the column direction f2. The shift registers GOA units in the third register column 51 and the shift registers GOA units in the fourth register column 52 are connected to different scan lines SC.

[0105] like Figure 5a or Figure 6a As shown, the shift register GOA unit in the third register column 51 is connected to the third signal line group 53, and the shift register GOA unit in the fourth register column 52 is connected to the fourth signal line group 54. Both the third signal line group 53 and the fourth signal line group 54 include the first signal line 55 and share the first signal line 55.

[0106] like Figure 5a or Figure 6a As shown, the first signal line 55 is connected not only to the shift register GOAunit in the third register column 51, but also to the shift register GOA unit in the fourth register column 52. By sharing the first signal line 55, the wiring space occupied by the signal line can be reduced, which is beneficial for reducing the bezel size.

[0107] In some implementations, such as Figure 5a or Figure 6a As shown, the first signal line 55 is located between the third register column 51 and the fourth register column 52.

[0108] Since the first signal line 55 is connected to the shift register GOAunit in the third register column 51 and the fourth register column 52, the wiring length and difficulty can be simplified by placing the first signal line 55 between the third register column 51 and the fourth register column 52.

[0109] In some implementations, the first signal line 55 includes at least one of the following: a clock signal line CLK, a gate enable signal line VGH, and a first gate disable signal line VGL1.

[0110] For example, such as Figure 5a As shown, the first signal line 55 includes multiple clock signal lines CLK, which are located between the third register column 51 and the fourth register column 52. Figure 5a In the third register column 51, the gate enable signal line VGH and the first gate disable signal line VGL1 are located between the third register column 51 and the first signal line 55; the gate enable signal line VGH and the first gate disable signal line VGL1 are located between the fourth register column 52 and the first signal line 55.

[0111] For example, such as Figure 6a As shown, the first signal line 55 includes multiple clock signal lines CLK, a gate enable signal line VGH, and a first gate disable signal line VGL1. These first signal lines 55 are located between the third register column 51 and the fourth register column 52. The gate enable signal line VGH and the first gate disable signal line VGL1 can be located on one side or both sides of the multiple clock signal lines CLK. Figure 6a In this configuration, the gate enable signal line VGH and the first gate disable signal line VGL1 are located on the side of the multiple clock signal lines CLK near the third register column 51. Of course, the gate enable signal line VGH and the first gate disable signal line VGL1 can also be located on the side of the multiple clock signal lines CLK near the fourth register column 52. This disclosure does not limit this.

[0112] For example, such as Figure 6a As shown, the shift register GOA unit in the third register column 51 and the shift register GOA unit in the fourth register column 52 are connected to the same gate enable signal line VGH and the same first gate disable signal line VGL1.

[0113] When the first signal line 55 includes a clock signal line CLK, the clock signal line CLK connected to the third register column 51 and the clock signal line CLK connected to the fourth register column 52 have the same surrounding environment, which can reduce the load difference between the clock signal line CLK connected to the third register column 51 and the clock signal line CLK connected to the fourth register column 52 and improve the display effect.

[0114] Furthermore, when the first signal line 55 includes a clock signal line CLK, a gate enable signal line VGH, and a first gate disable signal line VGL1, the space occupied by the signal line can be further reduced, and the bezel can be further reduced.

[0115] In some implementations, such as Figure 5a and Figure 6a As shown, the third register column 51 and the fourth register column 52 are mirror-symmetric about the second axis, which extends along the column direction f2. That is, the third register column 51 can at least partially coincide with the fourth register column 52 after being rotated 180° about the second axis.

[0116] In some implementations, such as Figure 5a or Figure 6a As shown, the third signal line group 53 further includes: a second signal line 56, located on the side of the third register column 51 opposite to the fourth register column 52, and / or located between the third register column 51 and the first signal line 55. The second signal line 56 is not connected to the shift register GOAunit in the fourth register column 52.

[0117] In some implementations, such as Figure 5a or Figure 6a As shown, the fourth signal line group 54 further includes: a third signal line 57, located on the side of the fourth register column 52 opposite to the third register column 51, and / or located between the fourth register column 52 and the first signal line 55. The third signal line 57 is not connected to the shift register GOAunit in the third register column 51.

[0118] For example, the second signal line 56 and the third signal line 57 each independently include at least one of the following: a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL.

[0119] For example, the second signal line 56 includes a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. Wherein, as... Figure 5a or Figure 5bAs shown, the second signal line 56 is divided into a first sub-line 56-1 and a second sub-line 56-2. The first sub-line 56-1 includes a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate turn-off signal line VGL2, and a low gate turn-off signal line LVGL, arranged sequentially along the row direction f1, and is located on the side of the third register column 51 opposite to the fourth register column 52. The second sub-line 56-2 includes a gate turn-on signal line VGH and a first gate turn-off signal line VGL1, arranged sequentially along the row direction f1, and is located between the third register column 51 and the first signal line 55.

[0120] For example, the third signal line 57 includes a gate-on signal line VGH, a first gate-off signal line VGL1, a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate-off signal line VGL2, and a low gate-off signal line LVGL. Wherein, as Figure 5a or Figure 5c As shown, the third signal line 57 is divided into a third sub-line 57-1 and a fourth sub-line 57-2. The third sub-line 57-1 includes a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate turn-off signal line VGL2, and a low gate turn-off signal line LVGL, arranged sequentially in the opposite direction of the row direction f1, and is located on the side of the fourth register column 52 opposite to the third register column 51. The fourth sub-line 57-2 includes a gate turn-on signal line VGH and a first gate turn-off signal line VGL1, arranged sequentially in the opposite direction of the row direction f1, and is located between the fourth register column 52 and the first signal line 55.

[0121] For example, such as Figure 6a As shown, the second signal line 56 includes a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate turn-off signal line VGL2, and a low gate turn-off signal line LVGL, arranged sequentially along the row direction f1. These second signal lines 56 are all located on the side of the third register column 51 opposite to the fourth register column 52. The third signal line 57 includes a frame start signal line STV, a first noise reduction voltage signal line VDDE, a second noise reduction voltage signal line VDDO, an initialization signal line INIT, a second gate turn-off signal line VGL2, and a low gate turn-off signal line LVGL, arranged sequentially in the opposite direction of the row direction f1. These third signal lines 57 are all located on the side of the fourth register column 52 opposite to the third register column 51.

[0122] For example, such as Figure 5a or Figure 6aAs shown, the second signal line 56 and the third signal line 57 are mirror-symmetrical about the third axis, which extends along the column direction f2. That is, the second signal line 56 can at least partially coincide with the third signal line 57 after rotating 180° about the third axis.

[0123] By setting the second signal line 56 to be mirror-symmetrical with the third signal line 57, the design and wiring difficulty can be simplified.

[0124] For example, when the third register column 51 and the fourth register column 52 are mirror-symmetric about the second axis, and the second signal line 56 and the third signal line 57 are mirror-symmetric about the third axis, the third axis and the second axis approximately coincide.

[0125] It should be noted that the third register column 51 and the fourth register column 52 can also be translated symmetrically along the row direction f1, and the second signal line 56 and the third signal line 57 can also be translated symmetrically along the row direction f1. This disclosure does not limit this.

[0126] To reduce the resistance of the clock signal line CLK, in the first example, as... Figure 5d As shown, the clock signal line CLK includes a first sub-clock signal line CLK1 and a second sub-clock signal line CLK2 that are close to and connected to each other. There is a gap between the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2, and they are connected by multiple connecting portions 58, which are spaced apart along the column direction f2. The linewidths of the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 are, for example, the same as the linewidths of other signal lines such as the gate-on signal line VGH and the first gate-off signal line VGL1. By connecting the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 in parallel, the resistance of the clock signal line CLK can be effectively reduced.

[0127] To reduce the resistance of the clock signal line CLK, in the second example, as... Figure 5d As shown, the clock signal line CLK is connected to multiple clock patterns 59, which are spaced apart along the column direction f2. The clock signal line CLK and the clock patterns 59 are on different layers and connected through the first via H1 (e.g., ...). Figure 10 (As shown). By connecting the clock signal line CLK in parallel with the clock pattern 59, the resistance of the clock signal line CLK can be effectively reduced. The clock signal line CLK is, for example, set on the same layer as the scan line SC, and the clock pattern 59 is, for example, set on the same layer as the data line DT.

[0128] like Figure 5dAs shown, when the clock signal line CLK includes an adjacent first sub-clock signal line CLK1 and a second sub-clock signal line CLK2, and the first sub-clock signal line CLK1 and the second sub-clock signal line CLK2 are connected by multiple connecting parts 58, the clock pattern 59 includes: a first sub-pattern 591 corresponding to the position of the first sub-clock signal line CLK1, a second sub-pattern 592 corresponding to the position of the second sub-clock signal line CLK2, and a third sub-pattern 593 corresponding to the position of the connecting part 58. The first sub-pattern 591 and the second sub-pattern 592 extend along the column direction f2. The third sub-pattern 593 connects the midpoint of the first sub-pattern 591 and the midpoint of the second sub-pattern 592. The interconnected first sub-pattern 591, second sub-pattern 592, and third sub-pattern 593 constitute an H-shaped clock pattern 59.

[0129] To reduce the resistance of the clock signal line CLK, in the third example, as... Figure 6c As shown, the linewidth of the clock signal line CLK is greater than that of other signal lines such as the gate-on signal line VGH and the first gate-off signal line VGL1. For example, the linewidth of the clock signal line CLK is twice the linewidth of other signal lines such as the gate-on signal line VGH or the first gate-off signal line VGL1. By widening the clock signal line CLK, the resistance of the clock signal line CLK can be effectively reduced.

[0130] In some implementations, such as Figure 7 As shown, the multiple shift registers GOA units include a third shift register GOAunit3 and a fourth shift register GOAunit4. The output Opt of the third shift register GOAunit3 is connected to the input Ipt of the fourth shift register GOAunit4. The third shift register GOAunit3 and the fourth shift register GOAunit4 are located in the same column. The output Opt of the third shift register GOAunit3 is also connected to the scan line SC.

[0131] For example, the output Opt of the first-stage shift register GOA unit 1st is connected to the input Ipt of the fifth-stage shift register GOA unit 5th. In this case, the third shift register GOA unit3 is the same as the first-stage shift register GOA unit 1st, and the fourth shift register GOA unit4 is the same as the fifth-stage shift register GOA unit 5th. The first-stage shift register GOA unit 1st and the fifth-stage shift register GOA unit 5th are located in the same column.

[0132] For example, the output Opt of the second-level shift register GOA unit 2nd is connected to the input Ipt of the sixth-level shift register GOA unit 6th. In this case, the third shift register GOA unit3 is the second-level shift register GOA unit 2nd, and the fourth shift register GOA unit4 is the sixth-level shift register GOA unit 6th. The second-level shift register GOA unit 2nd and the sixth-level shift register GOA unit 6th are located in the same column.

[0133] In some implementations, multiple shift register (GOA) units are arranged in a zigzag or bow-shaped cascade order.

[0134] For example, such as Figure 8 As shown, the first-level shift register GOA unit 1st, the second-level shift register GOA unit 2nd, and the third-level shift register GOA unit 3 are arranged in a Z-shape in a cascading order from the lowest to the highest level. For example, in Figure 8 In the middle, each row is arranged with two shift registers GOA unit according to the preset direction f3 (that is, the direction in which the gate drive circuit GOA points to the display area AA, such as the row direction f1). Along the preset direction f3, the first row is arranged with the first-level shift register GOA unit 1st and the second-level shift register GOA unit 2nd, the second row is arranged with the third-level shift register GOA unit 3rd and the fourth-level shift register GOA unit 4th, the third row is arranged with the fifth-level shift register GOA unit 5th and the sixth-level shift register GOA unit 6th, and the fourth row is arranged with the seventh-level shift register GOA unit 7th and the eighth-level shift register GOA unit 8th.

[0135] For example, such as Figure 9 As shown, the first-level shift register GOA unit 1st, the second-level shift register GOA unit 2nd, and the third-level shift register GOA unit 3 can also be arranged in a bow-shaped cascade order from the lowest to the highest level. For example, in Figure 9In the array, each row has two shift registers GOA unit arranged in a preset direction f3. Along the preset direction f3, the first row has the first-level shift register GOA unit 1st and the second-level shift register GOA unit 2nd, the second row has the fourth-level shift register GOA unit 4th and the third-level shift register GOA unit 3rd, the third row has the fifth-level shift register GOA unit 5th and the sixth-level shift register GOA unit 6th, and the fourth row has the eighth-level shift register GOA unit 8th and the seventh-level shift register GOA unit 7th.

[0136] In some implementations, such as Figure 8 As shown, there are 2 shift registers GOA units connected to different scan lines SC and located in the same row. The shift registers GOA units of odd-numbered levels are located in the same column, and the shift registers GOA units of even-numbered levels are located in the same column.

[0137] For example, in Figure 8 In the table, the odd-numbered shift registers GOAunit, such as the first-level shift register GOAunit 1st, the third-level shift register GOAunit 3rd, the fifth-level shift register GOA unit 5th, and the seventh-level shift register GOAunit 7th, are located in the same column; the even-numbered shift registers GOAunit, such as the second-level shift register GOA unit 2nd, the fourth-level shift register GOA unit 4th, the sixth-level shift register GOA unit 6th, and the eighth-level shift register GOA unit 8th, are located in the same column.

[0138] In some implementations, the gate drive circuit GOA is also connected to multiple clock signal lines CLK, which are used to transmit M clock signals with different timing sequences.

[0139] For example, the number of shift register GOA units connected to different scan lines SC and located in the same row is N, M is greater than N, and M is divisible by N. M and N are both positive integers, and N is a positive integer greater than or equal to 2.

[0140] For example, for the 4CLK product, M=4, N=2, meaning that two shift registers GOA units connected to different scan lines SC can be set in one row.

[0141] For 8CLK products, M=8, N=2 or 4, meaning two can be set in one row (e.g., ...). Figure 4a , Figure 5a as well as Figure 6a(As shown) or four shift registers GOA unit connected to different scan lines SC.

[0142] For the 10CLK product, M=10, N=2 or 5, meaning that two shift registers GOAunit with five connections to different scan lines SC can be set in one row.

[0143] For the 12CLK product, M=12, N=2, 3, 4 or 6, that is, two, three, four or six shift registers GOAunit connected to different scan lines SC can be set in one row.

[0144] For the 16CLK product, M=16, N=2, 4 or 8, meaning that two, four or eight shift registers GOAunit connected to different scan lines SC can be set in one row.

[0145] In some implementations, the number of shift registers GOAunit connected to different scan lines SC and located in the same row is greater than or equal to 2 and less than or equal to 4. This increases the height space of the shift registers GOAunit in the column direction f2 while avoiding the gate drive circuit GOA occupying too much space in the row direction f1.

[0146] In some implementations, the number of shift registers GOAunit connected to different scan lines SC and located in the same row is N. In the column direction f2, the arrangement period of the shift registers GOAunit is approximately equal to N times the arrangement period of the sub-pixel PX.

[0147] For example, such as Figure 2 As shown, each row is configured with two shift registers GOA units connected to different scan lines SC, i.e., N=2. In the column direction f2, the arrangement period of the shift registers GOA units is approximately twice the arrangement period of the sub-pixel PX.

[0148] For example, three shift registers GOAunit are set in a row, connected to different scan lines SC, i.e., N=3. In the column direction f2, the arrangement period of the shift registers GOAunit is approximately three times the arrangement period of the sub-pixel PX.

[0149] For example, such as Figure 3 As shown, four shift registers GOA units are set in a row, connected to different scan lines SC, i.e., N=4. In the column direction f2, the arrangement period of the shift registers GOA units is approximately 4 times the arrangement period of the sub-pixel PX.

[0150] In some implementations, such as Figure 4a , Figure 5a or Figure 6aAs shown, the multiple shift registers GOA units include a first shift register GOAunit1 and a second shift register GOA unit2 arranged in the same row. The first shift register GOA unit1 is located on the side of the second shift register GOA unit2 away from the display area AA. At least one clock signal line CLK extending along the column direction f2 is also provided between the first shift register GOA unit1 and the second shift register GOA unit2. The first shift register GOA unit1 and the second shift register GOA unit2 are respectively connected to different scan lines SC.

[0151] like Figure 5d As shown, the first shift register GOAunit1 is connected to the scan line SC via a remote lead 61. The remote lead 61 includes a first segment 61L and a second segment 61R. The first shift register GOAunit1, the first segment 61L, the second segment 61R, and the scan line SC are connected in sequence. The first segment 61L and the clock signal line CLK are set on different layers and cross each other.

[0152] like Figure 5d As shown, the two adjacent remote leads 61 are the first remote lead 611 and the second remote lead 612. The distance g1 between the first segment 61L of the first remote lead 611 and the first segment 61L of the second remote lead 612 is smaller than the distance g2 between the second segment 61R of the first remote lead 611 and the second segment 61R of the second remote lead 612.

[0153] In this embodiment, by clustering the first line segment 61L together, more wiring space can be provided (e.g., Figure 5d The black solid line frame (in the middle) indicates that these wiring spaces can be used, for example, to set up clock patterns 59 (e.g., Figure 5d As shown, the clock pattern 59 is set on the same layer as the remote lead 61 and is connected to the clock signal line CLK through the first via H1 to reduce the resistance of the clock signal line CLK.

[0154] The first remote lead 611 and the second remote lead 612 are connected between different first shift registers GOAunit1 and scan lines SC.

[0155] For example, in column direction f2, multiple shift registers GOA units may be provided between the second segment 61R of the first remote lead 611 and the second segment 61R of the second remote lead 612.

[0156] like Figure 5cAs shown, in the column direction f2, two shift registers GOAunit are provided between the second segment 61R of the first remote lead 611 and the second segment 61R of the second remote lead 612. In this case, the distance g2 between the second segment 61R of the first remote lead 611 and the second segment 61R of the second remote lead 612 is approximately the height of the two shift registers GOAunit in the column direction f2.

[0157] In some implementations, such as Figure 4d As shown in Figure 5e, the second shift register GOA unit2 is connected to the scan line SC via a proximity lead 62. The two adjacent proximity leads 62 are the first proximity lead 621 and the second proximity lead 622. The first proximity lead 621 and the second proximity lead 622 are connected between different second shift registers GOA unit2 and scan lines SC.

[0158] like Figure 5e As shown, the second segment 61R of the first long-range lead 611, the first short-range lead 621, the second segment 61R of the second long-range lead 612, and the second short-range lead 622 all extend along the row direction f1 and are arranged sequentially along the column direction f2. The distance g3 between the second segment 61R of the first long-range lead 611 and the first short-range lead 621, and the distance g4 between the second segment 61R of the second long-range lead 612 and the second short-range lead 622 are both smaller than the distance g5 between the second segment 61R of the first short-range lead 621 and the second segment 61R of the second long-range lead 612.

[0159] like Figure 5e As shown, the near-field lead 62 is connected to the reverse extension line 64. The reverse extension line 64 is located on the side of the near-field lead 62 away from the display area AA, and the reverse extension line 64 and the near-field lead 62 are disposed on different layers. The near-field lead 62 and the remote lead 61 are disposed on the same layer. In the orthographic projection on the plane where the display substrate is located, the second segment 61R of the first remote lead 611 overlaps with the reverse extension line 64 connecting the first near-field lead 621, and the second segment 61R of the second remote lead 612 overlaps with the reverse extension line 64 connecting the second near-field lead 622.

[0160] For example, such as Figure 5d As shown, the shift register GOA unit is connected to the clock signal line CLK via clock lead 63. Multiple clock leads 63 (such as...) Figure 5d The four shown are located between the first remote lead 611 and the second remote lead 612. Among them, the clock lead 63 is disposed on the same layer as the remote lead 61, and disposed on a different layer from the clock signal line CLK and connected through a via.

[0161] For example, such as Figure 5dAs shown, the first segment 61L of the first remote lead 611, the first segment 61L of the second remote lead 612, and the multiple clock leads 63 located between the first remote lead 611 and the second remote lead 612 are arranged at equal intervals in the column direction f2.

[0162] To further save wiring space, such as Figure 5d As shown, among the multiple clock leads 63 located between the first remote lead 611 and the second remote lead 612, the first clock lead 631 connecting the third register column 51 on the left and the second clock lead 632 connecting the fourth register column 52 on the right are arranged along the row direction f1, as follows. Figure 5d In the middle, the first clock lead 631 and the second clock lead 632 are arranged opposite to each other.

[0163] like Figure 4d As shown, the second segment 61R of the first long-range lead 611, the first short-range lead 621, the second short-range lead 622, and the second segment 61R of the second long-range lead 612 all extend along the row direction f1 and are arranged sequentially along the column direction f2. The distance g6 between the second segment 61R of the first long-range lead 611 and the first short-range lead 621, and the distance g7 between the second short-range lead 622 and the second segment 61R of the second long-range lead 612, are all smaller than the distance g8 between the first short-range lead 621 and the second short-range lead 622.

[0164] In some implementations, such as Figure 4d or Figure 5e As shown, the shift register GOA unit is connected to the scan line SC via leads 45. These leads 45 include a first lead, a second lead, and a third lead that are sequentially adjacent along the column direction. The distance between the first lead and the second lead is greater than or less than the distance between the second lead and the third lead. That is, the distance between the first lead and the second lead is not equal to the distance between the second lead and the third lead.

[0165] Among them, the first lead, the second lead, and the third lead can be any three adjacent leads 45.

[0166] For example, lead 45 may include a remote lead 61 and a short lead 62, etc. Lead 45 may be arranged on the same layer as data line DT, and signal lines extending along column direction f2 (such as clock signal line CLK, etc.) may be arranged on the same layer as scan line SC, for example.

[0167] For example, such as Figure 4d or Figure 5eAs shown, when the first, second, and third leads are Y1, Y2, and Y3 respectively, the distance between the first and second leads is less than the distance between the second and third leads. When the first, second, and third leads are Y6, Y7, and Y8 respectively, the distance between the first and second leads is greater than the distance between the second and third leads.

[0168] In some implementations, such as Figure 4d or Figure 5e As shown, multiple leads 45 are divided into multiple lead groups 46. Each lead group 46 includes two adjacent leads 45. The multiple lead groups 46 include a first lead group, a second lead group, and a third lead group that are sequentially adjacent along the column direction. The distance between the first lead group and the second lead group is greater than or less than the distance between the second lead group and the third lead group. That is, the distance between the first lead group and the second lead group is not equal to the distance between the second lead group and the third lead group.

[0169] like Figure 4d or Figure 5e As shown, two adjacent leads 45 form a lead group 46, and multiple lead groups 46 are arranged along the column direction f2. Each lead 45 belongs to only one lead group 46, and different lead groups 46 include different leads 45. For example, leads Y1 and Y2 form lead group Z1, leads Y3 and Y4 form lead group Z2, leads Y5 and Y6 form lead group Z3, and leads Y7 and Y8 form lead group Z4.

[0170] For example, such as Figure 4d or Figure 5e As shown, for each lead group 46, the distance between the two leads 45 is the second distance d2. The second distance d2 is approximately the same for different lead groups 46.

[0171] Among them, the first lead group, the second lead group, and the third lead group can be any three adjacent lead groups 46.

[0172] For example, such as Figure 4d or Figure 5e As shown, when the first lead group, the second lead group, and the third lead group are lead group Z1, lead group Z2, and lead group Z3 respectively, the distance between the first lead group and the second lead group is greater than the distance between the second lead group and the third lead group; when the first lead group, the second lead group, and the third lead group are lead group Z2, lead group Z3, and lead group Z4 respectively, the distance between the first lead group and the second lead group is less than the distance between the second lead group and the third lead group.

[0173] Furthermore, when the distance between the first and second lead groups is greater than the distance between the second and third lead groups, the distance between the first and second lead groups is greater than the second distance d2, and the distance between the second and third lead groups is less than or equal to the second distance d2. Conversely, when the distance between the first and second lead groups is less than the distance between the second and third lead groups, the distance between the first and second lead groups is less than or equal to the second distance d2, and the distance between the second and third lead groups is greater than the second distance d2.

[0174] For example, such as Figure 4d As shown, Y1, Y4, Y5, and Y8 are long-range leads 61, and Y2, Y3, Y6, and Y7 are short-range leads; as Figure 5e As shown, Y1, Y3, Y5, and Y8 are long-range leads 61, and Y2, Y4, Y6, and Y7 are short-range leads.

[0175] In some implementations, such as Figure 4d or Figure 5e As shown, multiple lead groups 46 are divided into multiple lead units 47 arranged periodically along the column direction f2. Each lead unit 47 includes two sub-units 471 arranged along the column direction f2. Different sub-units 471 include the same number of lead groups 46, and the two sub-units 471 are arranged axially symmetrically.

[0176] For example, such as Figure 4d or Figure 5e As shown, each subunit 471 includes two lead groups 46. One subunit 471 includes lead group Z1 and lead group Z2, and the other subunit 471 includes lead group Z3 and lead group Z4. These two subunits 471 are arranged symmetrically, and the axis of symmetry extends along the row direction f1.

[0177] In some implementations, such as Figure 4d or Figure 5e As shown, subunit 471 includes multiple lead groups 46, which are arranged symmetrically within the same subunit 471, with the axis of symmetry extending, for example, along the row direction f1.

[0178] For example, such as Figure 4d or Figure 5e As shown, lead groups Z1 and Z2, located within the same subunit 471, are symmetrically arranged, with the axis of symmetry extending along the row direction f1. Lead groups Z3 and Z4, also located within the same subunit 471, are symmetrically arranged, with the axis of symmetry extending along the row direction f1.

[0179] For example, such as Figure 4b or Figure 5bAs shown, the shift register GOA unit includes multiple transistors. At least one transistor in two shift register GOA units arranged along column direction f2 is mirror-symmetrical, and the axis of symmetry extends along row direction f1. For example, as Figure 4a As shown, the transistors in the first-stage shift register GOAunit 1st are mirror images of the transistors in the third-stage shift register GOAunit 3rd.

[0180] In a specific implementation, the display substrate may include one or more gate drive circuits (GOAs). For example, such as Figure 2 or Figure 3 As shown, the display substrate includes two gate driving circuits GOA, and the two gate driving circuits GOA are located on opposite sides of the display area AA.

[0181] like Figure 2 or Figure 3 As shown, multiple shift register (GOA) units located within the same gate drive circuit (GOA) are situated on the same side of the display area (AA). Different gate drive circuits (GOA) are located on different sides of the display area (AA). Figure 2 and Figure 3 In the display area AA, one gate drive circuit GOA is located on the left side, and the other gate drive circuit GOA is located on the right side.

[0182] In some implementations, such as Figure 2 or Figure 3 As shown, the display area AA also includes: multiple data lines DT extending along the column direction f2, multiple sub-pixels PX divided into multiple pixel units P, and pixel unit P including multiple sub-pixels PX arranged in the column direction f2. Multiple sub-pixels PX located in the same pixel unit P are connected to the same data line DT and are respectively connected to different scan lines SC. The size of sub-pixels PX along the row direction f1 is larger than the size of sub-pixels PX along the column direction f2.

[0183] By connecting multiple sub-pixels PX located in the same pixel unit P to the same data line DT, and then connecting them to different scan lines SC, the number of data lines DT can be reduced, thereby reducing the number of source driver chips and lowering costs. The source driver chip is used to provide data signals to the data line DT.

[0184] For example, such as Figure 2 or Figure 3 As shown, the pixel unit P includes three sub-pixels PX. The three sub-pixels PX are connected to the same data line DT and to different scan lines SC respectively. This enables Triple Rate Driving (TRD), which reduces the number of source driver chips by 2 / 3, thereby reducing costs.

[0185] For example, such as Figure 2 or Figure 3 As shown, the three sub-pixels PX located in the same pixel unit P are the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B, respectively.

[0186] In a three-speed drive display substrate, the number of scan lines (SC) is three times that of a single-speed drive display substrate. Therefore, the number of shift registers (GOAunits) in the gate drive circuit (GOA) also increases accordingly. If only one shift register (GOAunit) is set per row, the height space of each shift register (GOAunit) in the column direction (f2) is reduced, making wiring impossible. Using the display substrate provided in this disclosure, by placing multiple shift registers (GOAunits) in the same row, it is beneficial to increase the height space of the shift registers (GOAunits) in the column direction (f2), facilitating the arrangement of thin-film transistors and related signal lines, and enabling three-speed drive.

[0187] This disclosure provides a display device, including: a display substrate as provided in any embodiment; and a source driving circuit connected to the display substrate for driving the display substrate to perform display.

[0188] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the aforementioned display substrate or display substrate.

[0189] For example, the source drive circuit is a source drive chip.

[0190] For example, the source drive circuit is connected to the data line DT. When multiple sub-pixels PX located in the same pixel unit P are connected to the same data line DT and are respectively connected to different scan lines SC, the source drive circuit can provide data signals to the same data line DT in a time-division manner to drive the multiple sub-pixels PX connected to the same data line DT to be displayed sequentially.

[0191] The display device disclosed herein can be any product or component with display function, such as a display panel, display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc. The display panel can be, for example, a liquid crystal display panel.

[0192] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0193] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0194] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0195] The terms "an embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "example," "one example," "some examples," etc., used herein are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

[0196] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0197] In describing some embodiments, the terms "coupled" and "connected" may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0198] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0199] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0200] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0201] The use of “for” or “configured to” in this article implies an open and inclusive language that does not preclude the applicability to or configuration of devices to perform additional tasks or steps.

[0202] The use of "based on" or "according to" in this document implies openness and inclusiveness. A process, step, calculation, or other action based on one or more of the stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond those stated.

[0203] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0204] As used herein, “parallel,” “perpendicular,” “equal,” and “flush” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where the acceptable range of deviation for approximate parallelism can be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where the acceptable range of deviation for approximate perpendicularity can also be, for example, within 5°. “Equal” includes absolute equality and approximate equality, where the acceptable range of deviation for approximate equality can be, for example, the difference between the two equals being less than or equal to 5% of either one. “Flush” includes absolute flush and approximate flush, where the acceptable range of deviation for approximate flush can be, for example, the distance between the flush twos being less than or equal to 5% of either one of the dimensions.

[0205] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0206] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0207] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, comprising a display area and a gate driving circuit located on at least one side of the display area; in, The display area includes multiple scan lines extending along the row direction, and multiple sub-pixels arranged in an array along the row and column directions, with at least one scan line between two adjacent rows of sub-pixels; The gate driving circuit located on the same side of the display area includes a plurality of cascaded shift registers, which are connected to the scan lines, and at least two shift registers connected to different scan lines are located in the same row; The plurality of shift registers include a first shift register and a second shift register arranged in the same row. The first shift register is located on the side of the second shift register away from the display area. At least one clock signal line extending along the column direction is also provided between the first shift register and the second shift register. The first shift register and the second shift register are respectively connected to different scan lines. The first shift register is connected to the scan line via a remote lead, the remote lead including a first line segment and a second line segment. The first shift register, the first line segment, the second line segment and the scan line are connected in sequence. The first line segment and the clock signal line are disposed on different layers and intersect each other. The two adjacent remote leads are a first remote lead and a second remote lead. The distance between the first segment of the first remote lead and the first segment of the second remote lead is less than the distance between the second segment of the first remote lead and the second segment of the second remote lead.

2. The display substrate according to claim 1, wherein the first shift register and the second shift register are symmetrically translated along the row direction, or the first shift register and the second shift register are mirror symmetrical about a first axis, the first axis extending along the column direction. 3.The display substrate according to claim 1 or 2, wherein, The plurality of shift registers includes a first register column and a second register column arranged along the row direction, and both the first register column and the second register column include a plurality of shift registers arranged along the column direction; The shift register in the first register column is connected to the first signal line group, and the shift register in the second register column is connected to the second signal line group. Both the first signal line group and the second signal line group include at least one signal line, and the signal lines in the first signal line group and the signal lines in the second signal line group are not shared. 4.The display substrate of claim 3, wherein, In the row direction, the first register column and the second register column are translated symmetrically, the first signal line group and the second signal line group are translated symmetrically, and the translation distance of the first register column relative to the second register column is approximately equal to the translation distance of the first signal line group relative to the second signal line group. 5.The display substrate according to claim 1 or 2, wherein The plurality of shift registers includes a third register column and a fourth register column arranged adjacent to each other along the row direction, and both the third register column and the fourth register column include a plurality of shift registers arranged along the column direction; The shift register in the third register column is connected to the third signal line group, and the shift register in the fourth register column is connected to the fourth signal line group. Both the third signal line group and the fourth signal line group include a first signal line and share the first signal line. 6.The display substrate of claim 5, wherein, The first signal line is located between the third register column and the fourth register column. 7.The display substrate according to claim 5 or 6, wherein The first signal line includes at least one of the following: a clock signal line, a gate enable signal line, and a first gate disable signal line, wherein the gate enable signal line is used to provide a gate enable voltage, the gate enable voltage is used to turn on the thin-film transistor of the sub-pixel, and the first gate disable signal line is used to provide a gate disable voltage, the gate disable voltage is used to turn off the thin-film transistor of the sub-pixel. 8.The display substrate of claim 6, wherein, The third register column and the fourth register column are mirror-symmetric about a second axis that extends along the column direction. 9.The display substrate according to claim 6 or 8, wherein The third signal line group further includes: a second signal line located on the side of the third register column opposite to the fourth register column, and / or located between the third register column and the first signal line; The fourth signal line group further includes: a third signal line located on the side of the fourth register column opposite to the third register column, and / or located between the fourth register column and the first signal line. 10.The display substrate of claim 9, wherein, The second signal line and the third signal line are mirror-symmetrical about a third axis, which extends along the column direction. 11.The display substrate according to claim 9 or 10, wherein The second signal line and the third signal line each independently include at least one of the following: a gate-on signal line, a first gate-off signal line, a frame start signal line, a first noise reduction voltage signal line, a second noise reduction voltage signal line, an initialization signal line, a second gate-off signal line, and a low gate-off signal line; The gate enable signal line is used to provide a gate enable voltage, which is used to turn on the thin-film transistor of the sub-pixel. The first gate disable signal line and the second gate disable signal line are both used to provide a gate disable voltage, which is used to turn off the thin-film transistor of the sub-pixel. The low gate disable signal line is used to provide a low gate disable voltage, which is less than the gate disable voltage.

12. The display substrate according to any one of claims 1 to 11, wherein, The plurality of shift registers includes a third shift register and a fourth shift register, the output of the third shift register is connected to the input of the fourth shift register, and the third shift register and the fourth shift register are located in the same column.

13. The display substrate according to any one of claims 1 to 12, wherein, The multiple shift registers are arranged in a zigzag or bow-shaped pattern according to the cascade order. 14.The display substrate according to any one of claims 1 to 13, wherein The number of shift registers connected to different scan lines and located in the same row is 2, and shift registers of odd-numbered levels are located in the same column, while shift registers of even-numbered levels are located in the same column. 15.The display substrate according to any one of claims 1 to 14, wherein The gate drive circuit is also connected to multiple clock signal lines, which are used to transmit M clock signals with different timing sequences. The number of shift registers connected to different scan lines and located in the same row is N, where M is greater than N and M is divisible by N, and both M and N are positive integers. 16.The display substrate according to any one of claims 1 to 15, wherein The number of shift registers connected to different scan lines and located in the same row is greater than or equal to 2 and less than or equal to 4.

17. The display substrate according to any one of claims 1 to 16, wherein, The number of shift registers connected to different scan lines and located in the same row is N. In the column direction, the arrangement period of the shift registers is approximately equal to N times the arrangement period of the sub-pixels. 18.The display substrate according to any one of claims 1 to 17, wherein In the column direction, a scan line and a row of sub-pixels are arranged alternately, and the distance between two adjacent scan lines is approximately equal to the arrangement period of the sub-pixels along the column direction.

19. The display substrate according to any one of claims 1 to 18, wherein, The second shift register is connected to the scan line via a proximity lead, and the two adjacent proximity leads are the first proximity lead and the second proximity lead; The second segment of the first remote lead, the first short lead, the second segment of the second remote lead, and the second short lead all extend along the row direction and are arranged sequentially along the column direction. The distance between the second segment of the first remote lead and the first short lead, and the distance between the second segment of the second remote lead and the second short lead, are all smaller than the distance between the second segment of the first short lead and the second remote lead. 20.The display substrate of claim 19, wherein, The near lead is connected to the reverse extension line, the reverse extension line is located on the side of the near lead away from the display area, and the reverse extension line and the near lead are arranged on different layers, while the near lead and the remote lead are arranged on the same layer. In the orthographic projection on the plane where the display substrate is located, the second segment of the first remote lead overlaps with the reverse extension line connecting the first near lead, and the second segment of the second remote lead overlaps with the reverse extension line connecting the second near lead.

21. The display substrate according to any one of claims 1 to 18, wherein, The second shift register is connected to the scan line via a proximity lead, and the two adjacent proximity leads are the first proximity lead and the second proximity lead; The second segment of the first remote lead, the first short lead, the second short lead, and the second segment of the second remote lead all extend along the row direction and are arranged sequentially along the column direction. The distance between the second segment of the first remote lead and the first short lead, and the distance between the second short lead and the second segment of the second remote lead, are all smaller than the distance between the first short lead and the second short lead.

22. The display substrate according to any one of claims 1 to 21, wherein, The shift register is connected to a clock signal line, which is also connected to multiple clock patterns. The multiple clock patterns are separated from each other along the column direction. The clock signal line and the clock patterns are arranged on different layers and connected through a first via.

23. The display substrate according to claim 22, wherein, The clock signal line includes an adjacent first sub-clock signal line and a second sub-clock signal line, and the first sub-clock signal line and the second sub-clock signal line are connected by a connecting part; The clock pattern includes: a first sub-pattern corresponding to the position of the first sub-clock signal line, a second sub-pattern corresponding to the position of the second sub-clock signal line, and a third sub-pattern corresponding to the position of the connecting portion. The first sub-pattern and the second sub-pattern extend along the column direction, and the third sub-pattern connects the first sub-pattern and the second sub-pattern.

24. The display substrate according to any one of claims 1 to 23, wherein, The display area also includes: multiple data lines extending along the column direction; The multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes multiple sub-pixels arranged in the column direction. Multiple sub-pixels located in the same pixel unit are connected to the same data line and are respectively connected to different scan lines. The size of the sub-pixel along the row direction is larger than the size of the sub-pixel along the column direction.

25. The display substrate according to any one of claims 1 to 24, wherein, The display substrate includes two gate driving circuits, and the two gate driving circuits are located on opposite sides of the display area.

26. A display device, comprising: The display substrate as described in any one of claims 1 to 25; as well as A source drive circuit is connected to the display substrate and is used to drive the display substrate to perform display.

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