Display panel and display device

Abstract

The present invention relates to the technical field of display, and provides a display panel and a display device, used for optimizing the design of a shift register and reducing the space required to be occupied by the shift register in a panel bezel. The display panel comprises: a pixel circuit, comprising a first transistor and a second transistor; and a shift register, comprising a plurality of cascaded shift units, wherein each shift unit comprises a first end and at least one second end, the first end and the second end output different signals, the first end is electrically connected to a gate of the first transistor, and the second end is electrically connected to a gate of the second transistor.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202411855857.1, filed with the State Intellectual Property Office of China on December 16, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Display panels include pixel circuits and shift registers. Shift registers provide gate signals to the gates of transistors in the pixel circuits, controlling whether the transistors are turned on or off. However, current designs of shift registers in display panels are inadequate, occupying significant space within the bezel and hindering the optimization of narrow bezel designs. Summary of the Invention

[0004] This invention provides a display panel and display device for optimizing the design of shift registers and reducing the space they occupy in the panel bezel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, characterized in that it comprises:

[0006] The pixel circuit includes a first transistor and a second transistor;

[0007] A shift register consists of multiple cascaded shift units;

[0008] The shifting unit includes a first end and at least one second end, the first end and the second end output different signals, the first end is electrically connected to the gate of the first transistor, and the second end is electrically connected to the gate of the second transistor.

[0009] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0010] The technical solution provided by the embodiments of the present invention has the following beneficial effects:

[0011] When the gates of the first transistor and the second transistor need to receive different signals, in related technologies, two different sets of shift registers are needed to provide these two different signals separately. These two sets of shift registers are independent of each other, resulting in a large number of shift registers in the display panel, and the shift registers need to occupy a large space in the bezel.

[0012] In this embodiment of the invention, the original two sets of shift registers are merged into one shift register that can output two different signals simultaneously. In the merged shift register, some circuit logic of the original two sets of shift registers can be shared to simplify the circuit structure of the shift register. This type of shift register has a higher circuit integration, which can reduce the number of shift registers in the display panel and the number of switching transistors required in the shift register, thereby greatly reducing the space occupied by the shift register in the bezel, so as to better optimize the narrow bezel design of the display panel. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of one output signal of the shift register corresponding to Figure 1;

[0016] Figure 3 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of one output signal of the shift register corresponding to Figure 3;

[0018] Figure 5 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0019] Figure 6 is a schematic diagram of a shifting unit provided in an embodiment of the present invention;

[0020] Figure 7 is a schematic diagram of a shift register provided in an embodiment of the present invention;

[0021] Figure 8 is a timing diagram corresponding to Figure 7;

[0022] Figure 9 is a schematic diagram of a partition of a display panel provided in an embodiment of the present invention;

[0023] Figure 10 is a timing diagram of a first display mode provided in an embodiment of the present invention;

[0024] Figure 11 is a timing diagram of a second display mode provided in an embodiment of the present invention;

[0025] Figure 12 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0026] Figure 13 is a schematic diagram of a second circuit provided in an embodiment of the present invention;

[0027] Figure 14 is a timing diagram corresponding to Figure 13;

[0028] Figure 15 is a schematic diagram of another structure of the second circuit provided in an embodiment of the present invention;

[0029] Figure 16 is a timing diagram corresponding to Figure 15;

[0030] Figure 17 is another timing diagram corresponding to Figure 15;

[0031] Figure 18 is a schematic diagram of another structure of the second circuit provided in an embodiment of the present invention;

[0032] Figure 19 is a schematic diagram of another structure of the second circuit provided in an embodiment of the present invention;

[0033] Figure 20 is a timing diagram corresponding to Figure 19;

[0034] Figure 21 is a schematic diagram of another structure of the second circuit provided in an embodiment of the present invention;

[0035] Figure 22 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0036] Figure 23 is a schematic diagram of a connection between a shift register and a clock line provided in an embodiment of the present invention;

[0037] Figure 24 is a timing diagram showing how multiple clock lines in Figure 23 provide signals.

[0038] Figure 25 is a schematic diagram of another structure of the shift register provided in an embodiment of the present invention;

[0039] Figure 26 shows a timing diagram corresponding to 25;

[0040] Figure 27 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0041] Figure 28 shows a timing diagram corresponding to 27;

[0042] Figure 29 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0043] Figure 30 shows a timing diagram corresponding to 29;

[0044] Figure 31 is a schematic diagram of another structure of the second circuit provided in an embodiment of the present invention;

[0045] Figure 32 is a schematic diagram of a first circuit provided in an embodiment of the present invention;

[0046] Figure 33 is a timing diagram corresponding to Figure 32;

[0047] Figure 34 is a schematic diagram of a first circuit provided in an embodiment of the present invention;

[0048] Figure 35 is a schematic diagram of another structure of the first circuit provided in the embodiment of the present invention;

[0049] Figure 36 is a schematic diagram of another structure of the first circuit provided in the embodiment of the present invention;

[0050] Figure 37 is a schematic diagram of another structure of the first circuit provided in the embodiment of the present invention;

[0051] Figure 38 is a timing diagram corresponding to Figure 37;

[0052] Figure 39 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0053] Figure 40 is a timing diagram corresponding to Figure 39;

[0054] Figure 41 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0055] Figure 42 is a timing diagram corresponding to Figure 41;

[0056] Figure 43 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0057] Figure 44 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0058] Figure 45 is a timing diagram corresponding to Figure 44;

[0059] Figure 46 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0060] Figure 47 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0061] Figure 48 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0062] Figure 49 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0063] Figure 50 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0064] Figure 51 is a schematic diagram of another structure of the shifting unit provided in an embodiment of the present invention;

[0065] Figure 52 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0066] Figure 53 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0067] Figure 54 is a timing diagram corresponding to Figure 53;

[0068] Figure 55 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0069] Figure 56 is a timing diagram corresponding to Figure 55;

[0070] Figure 57 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0071] Figure 58 is a timing diagram corresponding to Figure 57;

[0072] Figure 59 is a schematic diagram of a connection between the shift register and the control line provided in an embodiment of the present invention;

[0073] Figure 60 is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0074] Figure 61 is a timing diagram of the signal output from the first end of the shift unit provided in an embodiment of the present invention;

[0075] Figure 62 is a schematic diagram of another connection between the shift register and the control line provided in an embodiment of the present invention;

[0076] Figure 63 is a timing diagram corresponding to Figure 62;

[0077] Figure 64 is a schematic diagram of another connection between the shift register and the control line provided in an embodiment of the present invention;

[0078] Figure 65 is a timing diagram corresponding to Figure 64;

[0079] Figure 66 is another timing diagram corresponding to Figure 64;

[0080] Figure 67 is a schematic diagram of another connection between the shift register and the control line provided in an embodiment of the present invention;

[0081] Figure 68 is a timing diagram corresponding to Figure 67;

[0082] Figure 69 is another timing diagram corresponding to Figure 67;

[0083] Figure 70 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0084] Figure 71 is a schematic diagram of another connection between the shift register and the control line provided in an embodiment of the present invention;

[0085] Figure 72 is a timing diagram corresponding to Figure 71;

[0086] Figure 73 is another timing diagram corresponding to Figure 71;

[0087] Figure 74 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0088] Figure 75 is a schematic diagram of another structure of the first circuit provided in an embodiment of the present invention;

[0089] Figure 76 is a timing diagram corresponding to Figure 12;

[0090] Figure 77 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0091] Figure 78 is a timing diagram corresponding to Figure 77;

[0092] Figure 79 is a schematic diagram of a display panel structure in the related art;

[0093] Figure 80 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0094] Figure 81 is a timing diagram corresponding to Figure 80;

[0095] Figure 82 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0096] Figure 83 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0097] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0098] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0099] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0100] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0101] This invention provides a display panel that can be an organic light-emitting diode (OLED) display panel, a light-emitting diode (LED) display panel, a micro light-emitting diode (micro LED) display panel, or other types.

[0102] As shown in Figures 1 to 5, Figure 1 is a schematic diagram of a display panel structure provided in an embodiment of the present invention, Figure 2 is a schematic diagram of an output signal of the shift register 2 corresponding to Figure 1, Figure 3 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention, Figure 4 is a schematic diagram of an output signal of the shift register 2 corresponding to Figure 3, and Figure 5 is a schematic diagram of a pixel circuit 1 provided in an embodiment of the present invention. The display panel includes a pixel circuit 1 and a shift register 2.

[0103] The pixel circuit 1 includes a first transistor M1 and a second transistor M2.

[0104] The shift register 2 includes multiple cascaded shift units 3. Each shift unit 3 includes a first terminal Out1 and at least one second terminal Out2. The first terminal Out1 is electrically connected to the gate of the first transistor M1, and the second terminal Out2 is electrically connected to the gate of the second transistor M2. The signals output by the first terminal Out1 and the second terminal Out2 are different.

[0105] In this embodiment of the invention, the shift unit 3 includes m second terminals Out2. Referring to Figures 1 and 2, m can be equal to 1, or referring to Figures 3 and 4, m can also be an integer greater than or equal to 2, for example, m = 2, 4, 6, etc.

[0106] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the i-th level shift unit is identified by reference numeral 3(i); the first end of the i-th level shift unit 3(i) is identified by reference numeral Out1(i); the shift unit 3 includes m second ends. When m = 1, the second end of the i-th level shift unit 3(i) is identified by reference numeral Out2(i). When m ≥ 2, the m second ends of the i-th level shift unit 3(i) are respectively identified by reference numerals Out2(m×i-m+1), Out2(m×i-m+2), ..., Out2(m×i). For example, referring to Figure 4, when m = 2, the two second ends of the i-th level shift unit 3(i) are respectively identified by reference numerals Out2(2i-1) and Out2(2i).

[0107] The different signals output from the first terminal Out1 and the second terminal Out2 of shift unit 3 mean that the gate signals of the first transistor M1 and the second transistor M2 in pixel circuit 1 are different. This difference in signals refers to the different waveforms of the two signals, including at least the following situations:

[0108] The first scenario: The first transistor M1 and the second transistor M2 are of different device types, and the effective levels of the signals output from the first terminal Out1 and the second terminal Out2 are opposite. For example, referring to Figures 2, 4, and 5, the first transistor M1 is an N-type transistor, and the effective level of the signal output from the first terminal Out1 is high; the second transistor M2 is a P-type transistor, and the effective level of the signal output from the second terminal Out2 is low.

[0109] The second scenario: The first transistor M1 and the second transistor M2 are of the same device type, and the effective level states of the signals output from the first terminal Out1 and the second terminal Out2 are the same, but the duration of the effective level in the two signals is different. For example, the first transistor M1 and the second transistor M2 are both P-type transistors, and the effective level of the signals output from the first terminal Out1 and the second terminal Out2 is both low, but the pulse widths of the two signals are different.

[0110] The following explanations of this invention will all use the first scenario as an example.

[0111] When the gates of the first transistor M1 and the second transistor M2 need to receive different signals, in related technologies, two different sets of shift registers are needed to provide these two different signals separately. These two sets of shift registers are independent of each other, resulting in a large number of shift registers in the display panel, and the shift registers need to occupy a large space in the bezel.

[0112] In this embodiment of the invention, the original two sets of shift registers are merged into one shift register that can output two different signals simultaneously. In the merged shift register, some circuit logic of the original two sets of shift registers can be shared to simplify the circuit structure of the shift register. This type of shift register has a higher circuit integration, which can reduce the number of shift registers in the display panel and the number of switching transistors required in the shift register, thereby greatly reducing the space occupied by the shift register in the bezel, so as to better optimize the narrow bezel design of the display panel.

[0113] In one feasible implementation, as shown in FIG6, FIG6 is a schematic diagram of a shifting unit 3 provided in an embodiment of the present invention. The shifting unit 3 includes a first circuit 4 and a second circuit 5. The first circuit 4 includes a first terminal Out1, and the second circuit 5 includes a second terminal Out2.

[0114] The first circuit 4 includes a first driving module 6 and a first output module 7.

[0115] The first driving module 6 controls the signals of the first node N1 and the second node N2; the first output module 7 responds to the voltage output signals of the first node N1 and the second node N2.

[0116] That is, the first node N1 and the second node N2 are the two output control nodes of the first output module 7. The first output module 7 is used to select whether to output a high level or a low level according to the level state of the first node N1 and the second node N2.

[0117] The second circuit 5 includes a second driving module 8 and at least one second output module 9.

[0118] The second output module 9 responds to the voltage of the third node N3 by outputting the voltage of the first power supply terminal VGH to the second terminal Out2, and responds to the voltage of the fourth node N4 by outputting the voltage of the first clock terminal ck1 to the second terminal Out2. The first power supply terminal VGH is used to provide a high-level constant voltage signal. The third node N3 is electrically connected to the first circuit 4, and the signal levels of the third node N3 and the second node N2 are consistent for at least a portion of the time. The second drive module 8 controls the signal of the fourth node N4.

[0119] That is, the third node N3 and the fourth node N4 are the two output control nodes of the second output module 9. The second output module 9 is used to output the high level of the first power supply terminal VGH to the second terminal Out2 when the third node N3 is low, and to output the pulse of the first clock terminal ck1 to the second terminal Out2 when the fourth node N4 is low.

[0120] Regarding the statement "the signal levels of the third node N3 and the second node N2 are consistent for at least a portion of the time period," in one structure, this could mean that when the second node N2 is low, the third node N3 is low, and for at least a portion of the time period when the second node N2 is high, the third node N3 is high. For example, referring to Figure 8, the signals of the third node N3 and the second node N2 are at the same high or low level.

[0121] For at least a portion of the time, the signal levels of the third node N3 and the second node N2 are consistent, which means that the signal of the third node N3 and the signal of the second node N2 are correlated. The third node N3 may be directly connected to the second node N2, or the third node N3 may be connected to other nodes in the first circuit 4 that are correlated with the second node N2, such as the shift output terminal Next, the sixth node N6, the seventh node N7, the eighth node N8, etc. mentioned later.

[0122] The correlation between the signals of the third node N3 and the second node N2 indicates that the third node N3 and the second node N2 share a set of logic circuits to provide voltage. Referring to Figure 6, the first driving module 6 in the first circuit 4 provides voltage to the second node N2, which in turn directly or indirectly determines the voltage of the third node N3. In this way, in the second circuit 5, there is no need to configure an additional driving module for the third node N3. The shift unit 3 has a higher integration level, its circuit structure is simpler, and the space occupied by the shift unit 3 in the frame is reduced to a greater extent.

[0123] Regarding the connection method between the third node N3 and the first circuit 4, in one feasible implementation, as shown in Figures 7 and 8, Figure 7 is a structural schematic diagram of the shift register 2 provided in the embodiment of the present invention, and Figure 8 is a timing diagram corresponding to Figure 7. The first circuit 4 includes a shift control sub-circuit 10 and a partition control sub-circuit 11.

[0124] The shift control sub-circuit 10 includes a first driving module 6 and a first output module 7. The first driving module 6 includes a shift input terminal In, and the first output module 7 includes a shift output terminal Next. In two adjacent shift units 3, the shift output terminal Next of the previous shift unit 3 is electrically connected to the shift input terminal In of the next shift unit 3.

[0125] The partition control sub-circuit 11 includes a first terminal Out1, and the partition control sub-circuit 11 outputs a signal to the first terminal Out1 according to the partition control signal.

[0126] The third node N3 is electrically connected to the shift output terminal Next.

[0127] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the first circuit and the second circuit corresponding to the i-th level shift unit 3(i) are respectively identified by reference numerals 4(i) and 5(i); the shift input terminal and the shift output terminal corresponding to the i-th level shift unit 3(i) are respectively identified by reference numerals In(i) and Next(i); and the first node to the fourth node N4 corresponding to the i-th level shift unit 3(i) are respectively identified by reference numerals N1(i) to N4(i).

[0128] The shift unit 3 includes m second terminals Out2. When m = 1, the first clock terminal corresponding to the i-th shift unit 3(i) is identified by the attached reference numeral ck(i); when m ≥ 2, the m first clock terminals corresponding to the i-th shift unit 3(i) are identified by the attached reference numerals ck1(m×i-m+1), ck1(m×i-m+2), ..., ck1(m×i). For example, referring to Figure 6, when m = 2, the two first clock terminals corresponding to the i-th shift unit 3(i) are identified by the attached reference numerals ck1(2i-1) and ck1(2i).

[0129] The display panel with this structure has a zone-based frequency function.

[0130] As shown in Figure 9, Figure 9 is a schematic diagram of a partition of a display panel provided in an embodiment of the present invention. The display panel includes a first partition AA1 and a second partition AA2.

[0131] In the first display mode (FD), the first partition AA1 and the second partition AA2 have the same driving frequency; in the second display mode (SD), the first partition AA1 and the second partition AA2 have different driving frequencies, with the first partition AA1 driven at a high frequency and the second partition AA2 driven at a low frequency. This driving frequency can be understood as the data refresh rate.

[0132] It should be noted that in the second display mode SD, the positions of the first partition AA1 and the second partition AA2 can be fixed or not.

[0133] The pixel circuit 1 also includes a driving transistor M00. In this embodiment of the invention, the signal output by the first terminal Out1 of at least one shift unit 3 is used to control whether the driving transistor M00 in the pixel circuit 1 can perform data writing. When the first terminal Out1 of the shift register 2 outputs a high level, the first transistor M1 connected to the first terminal Out1 is turned on, allowing the data voltage to be written to the gate of the driving transistor M00, thus charging the driving transistor M00. When the first terminal Out1 of the shift register 2 outputs a low level, the first transistor M1 connected to the first terminal Out1 is turned off, preventing the data voltage from being written to the gate of the driving transistor M00, thus not charging the driving transistor M00.

[0134] As shown in Figures 10 and 11, Figure 10 is a timing diagram of the first display mode FD provided in the embodiment of the present invention, and Figure 11 is a timing diagram of the second display mode SD provided in the embodiment of the present invention. For the shift control sub-circuit 10, whether in the first display mode FD or the second display mode SD, the shift output terminal Next of the shift control sub-circuit 10 in each shift unit 3 outputs a high level in sequence to ensure that each shift unit 3 can shift normally.

[0135] Regarding the partition control sub-circuit 11, in the first display mode FD (see Figure 10), under the action of the partition control signal, the second terminal Out2 of the partition control sub-circuit 11 in each level of the shift unit 3 sequentially outputs a high level, so that the pixel circuits 1 in the first partition AA1 and the second partition AA2 can perform charging operations normally, and the data refresh frequency of the two partitions is the same. Specifically, in the same level shift unit 3, the level states of the signals output by the second terminal Out2 and the shift output terminal Next are consistent.

[0136] In the second display mode SD, referring to Figure 11, under the action of the partition control signal: the first terminal Out1 of the partition control sub-circuit 11 of the multi-level shift unit 3 corresponding to the first partition AA1 normally outputs a high level sequentially, enabling the pixel circuit 1 in the first partition AA1 to perform charging operations normally, and this partition has a high data refresh rate; in some frames, the first terminal Out1 of the partition control sub-circuit 11 of the multi-level shift unit 3 corresponding to the second partition AA2 stops outputting a high level, causing the pixel circuit 1 in the second partition AA2 to not perform charging operations, thereby lowering the data refresh rate of this partition. Here, a frame can be understood as one frame time corresponding to the driving frequency of the first partition.

[0137] In the shift register 2 with segmented frequency control, the signal at the shift output terminal Next and the signal at the second node N2 are correlated. For example, referring to Figure 8, the signal levels of the shift output terminal Next and the second node N2 are consistent, both being high or low. Therefore, in this embodiment of the invention, the third node N3 can be electrically connected to the shift output terminal Next to provide a signal to the third node N3 using the shift control sub-circuit 10, thereby improving the integration between the first circuit 4 and the second circuit 5.

[0138] Furthermore, unlike the first terminal Out1, regardless of the display mode, the shift output terminal Next of each shift unit 3 outputs a high level sequentially. The third node N3 is electrically connected to the shift output terminal Next. In the second display mode SD, the third node N3 of each shift unit 3 can still be set high normally, ensuring that the second terminal Out2 of each shift unit 3 can output a low level sequentially, so that the second transistor M2 of the pixel circuit 1 in the second partition AA2 can be turned on normally. Taking the first transistor M1 including the threshold compensation transistor M01 and the second transistor M2 including the data writing transistor M02 as an example, in the second display mode SD, the threshold compensation transistor M01 of the pixel circuit 1 in the second partition AA2 is turned off, but the data writing transistor M02 is turned on. At this time, the voltage can be written to the first terminal of the driving transistor M00 by the turned data writing transistor M02 to adjust the bias state of the driving transistor M00 and prevent the threshold voltage of the driving transistor M00 from drifting during low-frequency driving.

[0139] Furthermore, as shown in FIG12, FIG12 is another structural schematic diagram of the pixel circuit 1 provided in the embodiment of the present invention. The pixel circuit 1 further includes a driving transistor M00.

[0140] The first transistor M1 includes a threshold compensation transistor M01, which is electrically connected between the second terminal and the gate of the driving transistor M00. At least one shift register 2 has its first terminal Out1 electrically connected to the gate of the threshold compensation transistor M01.

[0141] In the second display mode SD, when the high-frequency first partition AA1 enters the low-frequency second partition AA2, the first terminal Out1 of the shift register 2 continuously stops outputting an effective level (for example, when the threshold compensation transistor M01 is an N-type transistor, the effective level is high). The threshold compensation transistor M01 of the pixel circuit 1 in the second partition AA2 is turned off, cutting off the path for the data voltage to be written to the gate of the driving transistor M00, thereby stopping the charging of this part of the pixel circuit 1.

[0142] Alternatively, the first transistor M1 includes a data write transistor M02, which is electrically connected between the data line and the first terminal of the drive transistor M00. At least one first terminal Out1 of the shift register 2 is electrically connected to the gate of the data write transistor M02.

[0143] In the second display mode SD, when the high-frequency first partition AA1 enters the low-frequency second partition AA2, the first terminal Out1 of the shift register 2 continuously stops outputting an effective level (for example, when the data writing transistor M02 is a P-type transistor, the effective level is low). The data writing transistor M02 of the pixel circuit 1 in the second partition AA2 is turned off, cutting off the path for the data voltage to be written to the gate of the driving transistor M00, thereby stopping the charging of this part of the pixel circuit 1.

[0144] Regarding the second driving module 8, in one feasible implementation, as shown in Figures 13 and 14, Figure 13 is a structural schematic diagram of the second circuit 5 provided in an embodiment of the present invention, and Figure 14 is a timing diagram corresponding to Figure 13. The second driving module 8 includes a first switching transistor T1 and a second switching transistor T2.

[0145] Among them, the first switching transistor T1 is an N-type transistor. The gate of the first switching transistor T1 is electrically connected to the third node N3, the first terminal is electrically connected to the second power supply terminal VGL, and the second terminal is electrically connected to the fourth node N4. The second power supply terminal VGL is used to provide a low-level constant voltage signal.

[0146] The second switch T1 is a P-type transistor. The gate of the second switch T2 is electrically connected to the third node N3, the first terminal is electrically connected to the first power supply terminal VGH, and the second terminal is electrically connected to the fourth node N4.

[0147] Based on the above structure, when the third node N3 is high, the first switch T1 is turned on, setting the fourth node N4 low, and the second output module 9 outputs the pulse of the first clock terminal ck1 to the second terminal Out2. When the third node N3 is low, the second switch T2 is turned on, setting the fourth node N4 high, so that the second output module 9 does not output the signal of the first clock terminal ck1.

[0148] The above structure utilizes only an N-type first switch T1 and a P-type second switch T2 to reverse the signal levels of the fourth node N4 and the third node N3. This ensures that the second output module 9 can only respond to a low level of the third node N3 or a low level of the fourth node N4 at any given time, resulting in higher accuracy of the output signal. Furthermore, this structure makes the second drive module 8 simpler and requires fewer switches.

[0149] In one feasible implementation, as shown in Figures 15 to 17, Figure 15 is another structural schematic diagram of the second circuit 5 provided in the embodiment of the present invention, Figure 16 is a timing diagram corresponding to Figure 15, and Figure 17 is another timing diagram corresponding to Figure 15. The second terminal of the first switch T1 is electrically connected to the fourth node N4 through the third switch T3.

[0150] In this case, the gate of the first switch T1 in the i-th shift unit 3(i) is electrically connected to the third node N3(i) in the i-th shift unit 3(i), and the gate of the third switch T3 in the i-th shift unit 3(i) is electrically connected to the third node N3(i0) in the i0-th shift unit 3(i0), i≠i0.

[0151] Referring to Figure 16, during the time period t1 when the first switch T1 and the third switch T3 in the i-th stage shift unit 3(i) are simultaneously turned on, the first clock terminal ck1 connected to the i-th stage shift unit 3(i) provides a valid pulse. That is, during the time period t1 when the high level of the third node N3(i) in the i-th stage shift unit 3(i) and the low level of the third node N3(i0) in the i-th stage shift unit 3(i0) overlap, both the first clock terminal ck1(2i-1) and the first clock terminal ck1(2i) connected to the i-th stage shift unit 3(i) provide only one valid pulse.

[0152] In Figure 15, i0 is represented as i+2.

[0153] In some driving methods, the second terminal Out2 of shift unit 3 needs to output a single pulse.

[0154] Under this design requirement, when the third switch T3 is not set in the second drive module 8, according to Figures 13 and 14, for the i-th stage shift unit 3(i), in order to ensure that its second terminal Out2 outputs a single pulse, the high level of the third node N4(i) can only cover one valid pulse of the first clock terminal ck1 connected to the i-th stage shift unit 3(i). This means that the high level of the shift output terminal Next(i) of the i-th stage shift unit 3(i) and the high level of the first terminal Out1(i) can also only cover one valid pulse of the first clock terminal ck1 connected to the i-th stage shift unit 3(i). This will impose some limitations on the pulse width of the signal output by the first terminal Out1.

[0155] In the structure shown in Figure 15, by further adding a third switch T3, it is only necessary to ensure that the time period t1 covers one effective pulse of the first clock terminal ck1 connected to the i-th stage shift unit 3(i). The high level of the third node N4(i) of the i-th stage shift unit 3(i) can be extended as shown in Figure 17, thereby eliminating the limitation on the duration of the high level of the third node N3, the shift output terminal Next, and the first terminal Out1 of the shift unit 3, and allowing for a more flexible design of the pulse width of the signal output by the first terminal Out1 of the shift unit 3.

[0156] It should be noted that i0 = i + 2 is only for illustrative purposes. Under the condition that the time period t1 only covers one valid pulse of the first clock terminal ck1 connected to the i-th shift unit 3(i), the value of i0 can be set according to the actual timing situation.

[0157] Further, as shown in Figure 18, which is a schematic diagram of another structure of the second circuit 5 provided in the embodiment of the present invention, the second driving module 8 further includes a fourth switching transistor T4, which is an N-type transistor. The gate of the fourth switching transistor T4 is electrically connected to the gate of the third switching transistor T3, the first terminal is electrically connected to the first power supply terminal VGH, and the second terminal is electrically connected to the fourth node N4.

[0158] Referring to Figure 17, when both the third node N3(i) in the i-th stage shift unit 3(i) and the third node N3(i0) in the i0-th stage shift unit 3(i0) are at a high level, the second switch T2 and the third switch T3 are turned off. After adding the fourth switch T, the fourth switch T4 turns on in response to the high level of the third node N3(i0), thereby providing a stable high level to the fourth node N4 and preventing the fourth node N4 from being disturbed by the jump of the first clock terminal ck1 signal while floating.

[0159] Regarding the second driving module 8, in another feasible implementation, as shown in Figures 19 and 20, Figure 19 is a schematic diagram of another structure of the second circuit 5 provided in the embodiment of the present invention, and Figure 20 is a timing diagram corresponding to Figure 19. The second output module 9 responds to the first level of the third node N3 to output the voltage of the first power supply terminal VGH to the second terminal Out2, and responds to the first level of the fourth node N4 to output the voltage of the first clock terminal ck1 to the second terminal Out2.

[0160] The second drive module 8 includes a fifth switch T5, the gate of which is electrically connected to the second clock terminal ck2, and the second terminal is electrically connected to the fourth node N4.

[0161] In this shift unit 3(i), the first terminal of the fifth switch T5 is electrically connected to the second terminal Out2 of the (i-1)th shift unit 3. For the same shift unit 3, during the time period when the third node N3 is at the second level, the second terminal Out2 connected to the fifth switch T5 outputs a first level, and this first level overlaps with the first level provided by the second clock terminal ck2 connected to the fifth switch T5.

[0162] The first level is low, and the second level is high.

[0163] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the second clock terminal corresponding to the i-th shift unit 3(i) is identified by ck2(i).

[0164] As mentioned earlier, in some driving methods, the second terminal Out2 of the shift unit 3 performs a single pulse output.

[0165] In the above structure, referring to Figure 20, during the time period when the third node N3(i) of the i-th shift unit 3(i) is high, when the second terminal Out2(2i-2) outputs low, the second clock terminal ck2(i) provides a pulse. For the i-th shift unit 3(i), the fifth switch T5 is turned on, setting the fourth node N4(i) low. Then, the second clock terminal ck2(i) jumps high, the fifth switch T5 is turned off, and the fourth node N4(i) remains low. When the first clock terminal ck1(2i-1) provides a pulse, the second terminal Out2(2i-1) outputs a low level; when the first clock terminal ck1(2i) provides a pulse, the second terminal Out2(2i) outputs a low level. Then, the second clock terminal ck2(i) is set low again, but because the second terminal Out2(2i-2) outputs a high level at this time, the fourth node N4(i) will jump to high. When the first clock terminal ck1(2i-1) and the first clock terminal ck1(2i) provide pulses, the second terminal Out2(2i-1) and the second terminal Out2(2i) will no longer output a low level, thus enabling the second terminal Out2 to achieve single pulse output.

[0166] This structure eliminates the limitation on the duration of the high level of the third node N3, the shift output terminal Next, and the first terminal Out1 of the shift unit 3 when implementing the single-pulse output of the second terminal Out2. This allows for more flexible design of the pulse width of the signal output from the first terminal Out1 of the shift unit 3. Moreover, this structure includes fewer transistors in the second drive module 8, and the structure of the second circuit 5 is simpler.

[0167] Further, as shown in Figure 21, which is another structural schematic diagram of the second circuit 5 provided in the embodiment of the present invention, the second driving module 8 may also include a thirty-first switch T31, the gate of the thirty-first switch T31 ​​being electrically connected to the third node N3, the first terminal being electrically connected to the first power supply terminal VGH, and the second terminal being electrically connected to the fourth node N4.

[0168] When the third node N3(i) is low, the thirty-first switch T31 ​​is turned on, writing a stable high level to the fourth node N4(i). The potential of the fourth node N4 is stable and not easily affected by interference.

[0169] Furthermore, referring to Figures 19, 20 and 22, Figure 22 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention. The pixel circuit 1 includes a plurality of circuit rows 20 arranged along a first direction, and the circuit rows 20 include a plurality of pixel circuits 1 arranged along a second direction. The first direction and the second direction intersect.

[0170] The second circuit 5 includes m second output modules 9, where m ≥ 2. Each of the m second output modules 9 is electrically connected to a second transistor M2 in each of the m circuit rows 20 via a second terminal Out2. The m second output modules 9 are also electrically connected to each of the m first clock terminals ck1. Figure 22 is a schematic diagram using m = 2 as an example.

[0171] Among them, the first to the mth second terminals Out2 in the (i-1)th level shift unit 3(i-1) are electrically connected to the jth to the j+(m-1)th circuit row 20 respectively, j≥1, and the fifth switch T5 in the i-th level shift unit 3(i) is electrically connected to the mth second terminal Out2 in the (i-1)th level shift unit 3(i-1).

[0172] The fifth switch T5 in the i-th stage shift unit 3(i) is electrically connected to the second terminal Out2 of the last low-level output in the (i-1)-th stage shift unit 3(i-1), so that the second terminal Out2 of each stage shift unit 3 can output low level sequentially.

[0173] The first clock terminal ck1 and the second clock terminal ck2 in the shift unit 3 need to be electrically connected to the clock line respectively, and the clock line is used to transmit signals to the clock terminal.

[0174] Regarding the connection method between the clock terminal and the clock line of the shift unit 3, in one feasible implementation, referring to Table 1 and Figure 21, as shown in Figures 23 and 24, Figure 23 is a schematic diagram of the connection between the shift register 2 and the clock line provided in the embodiment of the present invention, and Figure 24 is a timing diagram of multiple clock lines providing signals corresponding to Figure 23, where m = 2.

[0175] The display panel includes a first clock line CK1', a second clock line CK2', a third clock line CK3', and a fourth clock line CK4'.

[0176] Specifically, the second clock terminal ck2 corresponding to the odd-numbered shift unit 3 is electrically connected to the first clock line CK1', and the two first clock terminals ck1 corresponding to the odd-numbered shift unit 3 are electrically connected to the second clock line CK2' and the third clock line CK3', respectively. The second clock terminal ck2 corresponding to the even-numbered shift unit 3 is electrically connected to the third clock line CK3', and the two first clock terminals ck1 corresponding to the even-numbered shift unit 3 are electrically connected to the fourth clock line CK4' and the first clock line CK1', respectively.

[0177] Table 1

[0178] In the table, ck-1 and ck1-2 represent the two first clock terminals ck1 of the shift unit 3, respectively.

[0179] For example, as shown in Figures 25 and 26, Figure 25 is another structural schematic diagram of the shift register 2 provided in the embodiment of the present invention, and Figure 26 is a timing diagram corresponding to 25. It is assumed that the i-th level shift unit 3(i) is the odd-numbered level shift unit, and the (i+1)-th level shift unit 3 is the even-numbered level shift unit 3.

[0180] In the i-th shift unit 3(i), the second clock terminal ck2(i) is connected to the first clock line CK1', the first clock terminal ck1(2i-1) is connected to the second clock line CK2', and the first clock terminal ck1(2i) is connected to the third clock line CK3'.

[0181] In the (i+1)th shift unit 3(i+1), the second clock terminal ck2(i+1) is connected to the third clock line CK3', the first clock terminal ck1(2i+1) is connected to the fourth clock line CK4', and the first clock terminal ck1(2i+2) is connected to the first clock line CK1'.

[0182] One second clock terminal ck2 and two first clock terminals ck1 of shift unit 3 are connected to three clock lines that output valid pulses sequentially. For the i-th stage shift unit 3(i), the low level output by the second terminal Out2(2i-1) and the second terminal Out2(2i) is provided by the second clock line CK2' and the third clock line CK3'. If we want the second terminal Out2(2i+1) and the second terminal Out2(2i+2) of the (i+1)-th stage shift unit 3(i+1) to continue to output low levels sequentially, the low level output by the second terminal Out2(2i+1) and the second terminal Out2(2i+2) needs to be provided by the fourth clock line CK4' and the first clock line CK1'. Accordingly, the second clock terminal ck2(i+1) of the (i+1)-th stage shift unit 3(i+1) is connected to the third clock line CK3', thus enabling the shift register 2 to work normally.

[0183] Regarding the connection method between the clock terminal and the clock line of the shift unit 3, in another feasible implementation, in conjunction with Table 2 and Figure 21, as shown in Figures 27 and 28, Figure 27 is another structural schematic diagram of the display panel provided in the embodiment of the present invention, and Figure 28 is a timing diagram corresponding to 27, where m = 2.

[0184] The display panel includes a first clock line CK1', a second clock line CK2', and a third clock line CK3'.

[0185] In this configuration, the second clock terminal ck2 of the 3x-2 stage shift unit 3 is electrically connected to the first clock line CK1', and the two corresponding first clock terminals ck1 are electrically connected to the second clock line CK2' and the third clock line CK3', respectively, where x = 1, 2, 3, ... In the 3x-1 stage shift unit 3, the second clock terminal ck2 is electrically connected to the third clock line CK3', and the two corresponding first clock terminals ck1 are electrically connected to the first clock line CK1' and the second clock line CK2', respectively. In the 3x stage shift unit 3, the second clock terminal ck2 is electrically connected to the second clock line CK2', and the two corresponding first clock terminals ck1 are electrically connected to the third clock line CK3' and the first clock line CK1', respectively.

[0186] Table 2

[0187] The display panel of this structure includes an odd number of clock lines. Similar to the previous embodiment, based on the connection method between the clock terminal of the shift unit 3 and the clock lines, the second terminal Out2 of the shift register 2 can also be made to output low levels sequentially.

[0188] Furthermore, the first circuit 4 also includes some clock terminals. In some configurations, some clock terminals in the first circuit 4 can transmit the same signal as the second clock terminal ck2 in the second circuit 5, that is, they are connected to the same clock line. This will be explained in detail in subsequent embodiments. This arrangement will result in a larger load on the clock line connected to the second clock terminal ck2. By adopting the connection method between the clock terminals of the shift unit 3 and the clock lines, and referring to Table 2, each clock line will be connected to the second clock terminal ck2 in turn, thereby making the load of each clock line more balanced.

[0189] Regarding the connection method between the clock terminal and the clock line of the shift unit 3, in another feasible embodiment, referring to Table 3 and Figure 21, as shown in Figures 29 and 30, Figure 29 is another structural schematic diagram of the display panel provided by the embodiment of the present invention, and Figure 30 is a timing diagram corresponding to 29, where m = 2.

[0190] The display panel includes a first clock line CK1', a second clock line CK2', a third clock line CK3', a fourth clock line CK4', and a fifth clock line CK5'.

[0191] In this system, the second clock terminal ck2 of shift unit 3 at level 5x-4 is electrically connected to the first clock line CK1', and the two corresponding first clock terminals ck1 are electrically connected to the second clock line CK2' and the third clock line CK3', respectively, where x = 1, 2, 3, ... . The second clock terminal ck2 of shift unit 3 at level 5x-3 is electrically connected to the third clock line CK3', and the two corresponding first clock terminals ck1 are electrically connected to the fourth clock line CK4' and the fifth clock line CK5', respectively. The second clock terminal ck2 of shift unit 3 at level 5x-2 is electrically connected to the fifth clock line CK5', and the two corresponding first clock terminals ck1 are electrically connected to the first clock line CK1' and the second clock line CK2', respectively. The second clock terminal ck2 of shift unit 3 at level 5x-1 is electrically connected to the second clock line CK2', and the two corresponding first clock terminals ck1 are electrically connected to the third clock line CK3' and the fourth clock line CK4', respectively. The second clock terminal ck2 of the 5x-stage shift unit 3 is electrically connected to the fourth clock line CK4', and the two corresponding first clock terminals ck1 are electrically connected to the fifth clock line CK5' and the first clock line CK1', respectively.

[0192] Table 3

[0193] The display panel of this structure includes an odd number of clock lines. Similar to the previous embodiment, based on the connection method between the clock terminal of the shift unit 3 and the clock lines, the second terminal Out2 of the shift register 2 can also be made to output low levels sequentially.

[0194] Furthermore, the first circuit 4 also includes some clock terminals. In some configurations, some clock terminals in the first circuit 4 can transmit the same signal as the second clock terminal ck2 in the second circuit 5, that is, they are connected to the same clock line. This will be explained in detail in subsequent embodiments. This arrangement will result in a larger load on the clock line connected to the second clock terminal ck2. By adopting the connection method of the clock terminals and clock lines of the shift unit 3, and referring to Table 3, each clock line will be connected to the second clock terminal ck2 in turn, thereby making the load of each clock line more balanced.

[0195] In one feasible implementation, referring to FIG19, the second circuit 5 further includes a sixth switch T6, the second drive module 8 is electrically connected to the fourth node N4 through the sixth switch T6, and the gate of the sixth switch T6 is electrically connected to the second power supply terminal VGL.

[0196] Alternatively, as shown in Figure 31, which is another structural schematic diagram of the second circuit 5 provided in an embodiment of the present invention, the second circuit 5 further includes at least one sixth switch transistor T6, with each sixth switch transistor T6 corresponding to one second output module 9. The sixth switch transistor T6 is electrically connected between the fourth node N4 and its corresponding second output module 9, and the gate of the sixth switch transistor T6 is electrically connected to the second power supply terminal VGL.

[0197] The sixth switch transistor T6 can play a protective role in the circuit. When the potential of the second terminal of the sixth switch transistor T6 is too low, the sixth switch transistor T6 can protect the switches in the second drive module 8, such as the first switch transistor T1 or the fifth switch transistor T5, from being broken down.

[0198] In one feasible implementation, referring to FIG13, the second output module 9 includes a thirty-second switch T32 and a thirty-third switch T33.

[0199] Among them, the gate of the thirty-second switch T32 is electrically connected to the third node N3, the first terminal is electrically connected to the first power supply terminal VGH, and the second terminal is electrically connected to the second terminal Out2. The gate of the thirty-third switch T33 is electrically connected to the fourth node N4, the first terminal is electrically connected to the first clock terminal ck1, and the second terminal is electrically connected to the second terminal Out2.

[0200] When the third node N3 is low, the thirty-second switch T32 is turned on, writing the high level provided by the first power supply terminal VGH into the second terminal Out2. When the fourth node N4 is low, the thirty-third switch T33 is turned on, writing the pulse of the first clock terminal ck1 into the second terminal Out2.

[0201] In addition, the second output module 9 may also include a fourth capacitor C4, the first plate of the fourth capacitor C4 being electrically connected to the gate of the thirty-third switch T33, and the second plate being electrically connected to the second terminal Out2.

[0202] In one feasible implementation, referring to Figures 7 and 8, the second circuit 5 includes m second output modules 9, where m ≥ 2. The m second output modules 9 are electrically connected to m second terminals Out2 and to m first clock terminals ck1, respectively, and the m first clock terminals ck1 sequentially provide valid pulses.

[0203] In this structure, the first-level shift unit 3 is used to provide gate signals to the second transistor M2 in at least two circuit rows 20. Compared with the first-level shift unit 3 driving only one second transistor M2 in one circuit row 20, this structure can reduce the number of shift units 3, thereby reducing the space required for the shift register 2 in the frame.

[0204] Furthermore, when the second circuit 5 includes m second terminals Out2, only the m second output modules 9 are independent of each other. These m second output modules 9 share a second drive module 8 for driving, making the overall structure of the second circuit 5 simpler.

[0205] In this embodiment of the invention, m can be equal to 2, 4, 6, etc. When the value of m is large, the size of the switching transistor in the second output module 9 can be increased to improve the stability of the second circuit 5.

[0206] Regarding the first driving module 6, in one feasible implementation, as shown in Figures 32 and 33, Figure 32 is a structural schematic diagram of the first circuit 4 provided in an embodiment of the present invention, and Figure 33 is a timing diagram corresponding to Figure 32. The first driving module 6 includes a seventh switch T7 and a first control unit 12.

[0207] In this configuration, the gate of the seventh switch T7 is electrically connected to the third clock terminal ck3, the first terminal is electrically connected to the shift input terminal In, and the second terminal is electrically connected to the second node N2. The first control unit 12 controls the signal of the first node N1.

[0208] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the third clock terminal corresponding to the i-th shift unit 3(i) is identified by the reference numeral ck3(i).

[0209] In the first driving module 6, the first control unit 12 controls the voltage of the first node N1, and the seventh switch T7 controls the voltage of the second node N2. The control logic circuits of the first node N1 and the second node N2 are independent of each other, resulting in stronger signal stability for both nodes. Moreover, the voltage of the second node N2 is determined solely by the seventh switch T7, and the control logic circuit structure corresponding to the second node N2 is simple, requiring fewer switches.

[0210] In one feasible implementation, referring to Figures 32 and 33, the first control unit 12 includes an eighth switch T8 and a ninth switch T9.

[0211] Among them, the eighth switch T8 is an N-type transistor, with its gate electrically connected to the second node N2, its first terminal electrically connected to the second power supply terminal VGL, and its second terminal electrically connected to the first node N1. The ninth switch T9 is a P-type transistor, with its gate electrically connected to the second node N2, its first terminal electrically connected to the third clock terminal ck3, and its second terminal electrically connected to the first node N1.

[0212] The first output module 7 responds to the voltage of the first node N1 and outputs the signal of the third clock terminal ck3.

[0213] More specifically, the first output module 7 includes a twentieth switch T20 and a twenty-first switch T21. The gate of the twentieth switch T20 is electrically connected to the first node N1, and its first terminal is electrically connected to the third clock terminal ck3. The gate of the twentieth switch T20 is electrically connected to the second node N2, and its first terminal is electrically connected to the second power supply terminal VGL. The second terminals of both the twentieth switch T20 and the twenty-first switch T21 are electrically connected to either the shift output terminal Next or the first terminal Out1.

[0214] Referring to Figure 33, the working process of the first driving module 6 includes the p1 period to the p5 period.

[0215] During period p1, the third clock terminal ck3 is at a low level, the shift input terminal In is at a low level, the seventh switch T7 is turned on, setting the second node N2 low, which in turn turns on the ninth switch T9, setting the first node N1 low. The first output module 7 responds to the low level of the first node N1 by outputting the low level of the third clock terminal ck3.

[0216] During the p2 period, the third clock terminal ck3 is at a high level, the seventh switch T7 is cut off, the second node N2 remains at a low level, the ninth switch T9 remains on, the first node N1 is set high, and the first output module 7 maintains a low output level.

[0217] During the p3 period, the third clock terminal ck3 is at a low level, the shift input terminal In jumps high, the second node N2 is set high, the eighth switch T8 is turned on, the first node N1 is set low, and the first output module 7 responds to the low level of the first node N1 by outputting the low level of the third clock terminal ck3.

[0218] During period p4, the third clock terminal ck3 is at a high level, the second node N2 remains at a high level, and the first node N1 remains at a low level. The first output module 7 responds to the low level of the second node N2 by outputting the high level of the third clock terminal ck3. The pulse width of the signal output by the first output module 7 is the duration of one high level output by the third clock terminal ck3.

[0219] During the p5 period, the third clock terminal ck3 is at a low level, the shift input terminal In is at a low level, the second node N2 is set low, the ninth switch T9 is turned on, setting the first node N1 low, and the first output module 7 responds to the low level of the first node N1 by outputting the low level of the third clock terminal ck3.

[0220] In this structure, by setting an N-type transistor in the first driving module 6, the pulse output by the first output module 7 can be normally shifted relative to the pulse at the shift input terminal In using only the seventh switch T7, the eighth switch T8, and the ninth switch T9, making the structure of the first circuit 4 simpler.

[0221] Alternatively, in another feasible implementation, as shown in FIG34, FIG34 is a schematic diagram of a structure of the first circuit 4 provided in an embodiment of the present invention, the first control unit 12 includes an eighth switch T8 and a ninth switch T9.

[0222] Among them, the eighth switch T8 is an N-type transistor, with its gate electrically connected to the second node N2, its first terminal electrically connected to the second power supply terminal VGL, and its second terminal electrically connected to the first node N1. The ninth switch T9 is a P-type transistor, with its gate electrically connected to the second node N2, its first terminal electrically connected to the first power supply terminal VGH, and its second terminal electrically connected to the first node N1.

[0223] The first output module 7 responds to the voltage of the first node N1 and outputs the signal of the first power supply terminal VGH.

[0224] More specifically, the first output module 7 includes a twentieth switch T20 and a twenty-first switch T21. The gate of the twentieth switch T20 is electrically connected to the first node N1, and its first terminal is electrically connected to the first power supply terminal VGH. The gate of the twentieth switch T20 is electrically connected to the second node N2, and its first terminal is electrically connected to the second power supply terminal VGL. The second terminals of both the twentieth switch T20 and the twenty-first switch T21 are electrically connected to either the shift output terminal Next or the first terminal Out1.

[0225] In this structure, the first output module 7 outputs a high signal in response to a low level of the first node N1 and a low signal in response to a low level of the second node N2. When the second node N2 is low, the ninth switch T9 is turned on, setting the first node N1 high; when the second node N2 is high, the eighth switch T8 is turned on, setting the first node N1 low. This keeps the signal levels of the first node N1 and the second node N2 opposite, ensuring that the first output module 7 can only respond to a low level of either the first node N1 or the second node N2 at any given time, thus guaranteeing the accuracy of the signal output by the first output module 7.

[0226] In one feasible implementation, as shown in FIG35, FIG35 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention. The first terminal of the eighth switch T8 is electrically connected to the second power supply terminal VGL through the tenth switch T10, and the gate of the tenth switch T10 is electrically connected to the second power supply terminal VGL.

[0227] There is a node N01 between the eighth switch T8 and the tenth switch T10. The tenth switch T10 is a P-type transistor, and its gate and first terminal are both electrically connected to the second power supply terminal VGL. When the voltage at node N01 is higher than VGL + |Vth|, the tenth switch T10 turns on. The low level of the second power supply terminal VGL writes node N01 low until the voltage written to node N01 equals VGL + |Vth|, at which point the tenth switch T10 turns off. That is, it can be understood that the tenth switch T10 only turns on when it is first powered on or when node N01 is disturbed. After turning on, it writes the voltage at node N01 to the target voltage and then remains in a state of just being cut off. For example, when VGL is -8V and the voltage at node N01 is higher than -8V+|Vth|, the tenth switch T10 is turned on. The VGL signal writes node N01 low until the potential of node N01 becomes -8V+|Vth|, at which point the tenth switch T10 is turned off, keeping the potential of node N01 at -8V+|Vth|, for example, at -6V. This prevents the first terminal potential of the eighth switch T8 from being too negative. The eighth switch T8 is an N-type transistor, which is turned off when its gate-source voltage is less than its threshold voltage. Compared to directly connecting the eighth switch T8 to the second power supply terminal VGL, the above design allows the eighth switch T8 to be in the off state even when the voltage at the second node N2 is not too negative. This avoids the simultaneous conduction of the eighth switch T8 and the ninth switch T9, improving circuit reliability and preventing power consumption degradation.

[0228] In one feasible implementation, as shown in FIG36, FIG36 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention. The second terminal of the ninth switch T9 and the second terminal of the eighth switch T8 are electrically connected to the first node N1 through the eleventh switch T11. The gate of the eleventh switch T11 is electrically connected to the second power supply terminal VGL.

[0229] There is a node N02 between the second terminal of the ninth switch T9 and the second terminal of the eighth switch T8 and the eleventh switch T11. When the ninth switch T9 or the eighth switch T8 writes a low level to node N02, there is a voltage drop in the eleventh switch T11, which can make the voltage of the first node N1 more negative, thereby eliminating the trailing of the signal output by the first output module 7.

[0230] In one feasible implementation, referring to Figure 36, the seventh switch T7 can be electrically connected to the second node N2 via a first protection switch T34, the gate of which is electrically connected to the second power supply terminal VGL. The gate of the ninth switch T9 is also electrically connected to the second node N2 via the first protection switch T34. The first protection switch T34 can protect the seventh switch T7 from breakdown when the potential of the second node N2 is too low.

[0231] Furthermore, referring to Figure 36, the first circuit 4 may also include a fifth capacitor C5 and / or a sixth capacitor C6. The fifth capacitor C5 is connected between the first terminal of the twentieth switch T20 and the first node N1. The sixth capacitor C6 is connected between the second terminal of the twentieth switch T21 and the second node N2.

[0232] In one feasible implementation, as shown in Figures 37 and 38, Figure 37 is a schematic diagram of another structure of the first circuit 4 provided in the embodiment of the present invention, and Figure 38 is a timing diagram corresponding to Figure 37. The first driving module 6 further includes a twelfth switch transistor T12. The gate of the twelfth switch transistor T12 is electrically connected to the second node N2, the first terminal is electrically connected to the fourth clock terminal ck4, and the second terminal is electrically connected to the second node N2 through the first capacitor C1.

[0233] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the fourth clock terminal corresponding to the i-th shift unit 3(i) is identified by ck4(i).

[0234] Referring to Figure 38, when the second node N2 is at a low level, the twelfth switch T12 is turned on. When the fourth clock terminal ck4 jumps to low, based on the effect of the first capacitor C1, the potential of the second node N2 can be pulled even lower, thereby making the first output module 7 output a low level more stably.

[0235] In the above structure, the third clock terminal ck3 and the fourth clock terminal ck4 are connected to different clock lines.

[0236] In one feasible implementation, as shown in Figures 39 and 40, Figure 39 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, and Figure 40 is a timing diagram corresponding to Figure 39. In the embodiment of the present invention, the display panel further includes a sixth clock line CK6', a seventh clock line CK7', an eighth clock line CK8', and a ninth clock line CK9'.

[0237] Specifically, in the 4x-3 level shift unit 3, the third clock terminal ck3 and the fourth clock terminal ck4 are electrically connected to the sixth clock line CK6' and the seventh clock line CK7', respectively; in the 4x-2 level shift unit 3, the third clock terminal ck3 and the fourth clock terminal ck4 are electrically connected to the seventh clock line CK7' and the eighth clock line CK8', respectively; in the 4x-1 level shift unit 3, the third clock terminal ck3 and the fourth clock terminal ck4 are electrically connected to the eighth clock line CK8' and the ninth clock line CK9', respectively; and in the 4x level shift unit 3, the third clock terminal ck3 and the fourth clock terminal ck4 are electrically connected to the ninth clock line CK9' and the sixth clock line CK6', respectively. x = 1, 2, 3, ...

[0238] In one feasible implementation, as shown in Figures 41 and 42, Figure 41 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention, and Figure 42 is a timing diagram corresponding to Figure 41. The first driving module 6 further includes a thirteenth switch T13, a fourteenth switch T14 and a fifteenth switch T15.

[0239] Specifically, the gate of the thirteenth switch T13 is electrically connected to the third clock terminal ck3, and its first terminal is electrically connected to the shift input terminal In. The gate and first terminal of the fourteenth switch T14 are both electrically connected to the second terminal of the thirteenth switch T13, and its second terminal is electrically connected to the second node N2. The gate of the fifteenth switch T15 is electrically connected to the second terminal of the thirteenth switch T13, its first terminal is electrically connected to the fourth clock terminal ck4, and its second terminal is electrically connected to the gate of the fourteenth switch T14 through the second capacitor C2.

[0240] Referring to Figure 42, when the thirteenth switch T13 is turned on and the eighth node N8 is set low, the fifteenth switch T15 is turned on. During the conduction of the fifteenth switch T15, when the fourth clock terminal ck4 jumps low, the potential of the eighth node N8 is pulled even lower due to the effect of the second capacitor C2, stabilizing the low potential of the second node N2. In this way, on the one hand, it can prevent the eighth switch T8 from turning on due to insufficient voltage of the second node N2; on the other hand, when the display panel is driven at low frequency, it can also improve the problem of insufficiently negative low level output by the first output module 7 due to leakage current of the second node N2.

[0241] Further, as shown in Figure 43, which is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention, the first driving module 6 further includes a sixteenth switch transistor T16, the gate of the sixteenth switch transistor T16 is electrically connected to the first node N1, the first terminal is electrically connected to the first power supply terminal VGH, and the second terminal is electrically connected to the second terminal of the fifteenth switch transistor T15.

[0242] When the first node N1 is low, the sixteenth switch T16 is turned on, raising the voltage of the first plate of the second capacitor C2, which in turn raises the voltage of the second plate of the second capacitor C2, i.e., the eighth node N8, cutting off the path for the fourteenth switch T14 to transmit signals to the second node N2.

[0243] In one feasible implementation, referring to Figure 43, the thirteenth switch T13 can be electrically connected to the eighth node N8 through the second protection switch T35, and the gate of the second protection switch T35 is electrically connected to the second power supply terminal VGL.

[0244] Regarding the first control unit 12, in another feasible embodiment, as shown in Figures 44 and 45, Figure 44 is another structural schematic diagram of the shift unit 3 provided in the embodiment of the present invention, and Figure 45 is a timing diagram corresponding to Figure 44. The first control unit 12 includes a seventeenth switch T17, an eighteenth switch T18, and a nineteenth switch T19.

[0245] Specifically, the gate of the seventeenth switch T17 is electrically connected to the shift input terminal In, its first terminal is electrically connected to the first power supply terminal VGH, and its second terminal is electrically connected to the third clock terminal ck3 through the third capacitor C3. The gate of the eighteenth switch T18 is electrically connected to the second terminal of the seventeenth switch T17, its first terminal is electrically connected to the third clock terminal ck3, and its second terminal is electrically connected to the first node N1. The gate of the nineteenth switch T19 is electrically connected to the second node N2, its first terminal is electrically connected to the first power supply terminal VGH, and its second terminal is electrically connected to the first node N1.

[0246] The second output module 9 responds to the first level of the third node N3 by outputting the voltage of the first power supply terminal VGH to the second terminal Out2, and responds to the first level of the fourth node N4 by outputting the voltage of the first clock terminal ck1 to the second terminal Out2. The first level is a low level.

[0247] The second drive module 8 includes a fifth switch T5, the gate of which is electrically connected to the second clock terminal ck2, and the second terminal is electrically connected to the fourth node N4.

[0248] In the i-th shift unit 3(i), the first terminal of the fifth switch T5 is electrically connected to the second terminal Out2 of the (i-1)-th shift unit 3. For the same shift unit 3, during the time period when the third node N3 is at the second level, the second terminal Out2 connected to the fifth switch T5 outputs a first level, and the first level overlaps with the first level provided by the second clock terminal ck2 connected to the fifth switch T5.

[0249] In the same shift unit 3, the third clock terminal ck3 and the second clock terminal ck2 are electrically connected to the same first signal pin 31.

[0250] Specifically, the third clock terminal ck3 and the second clock terminal ck2 are connected to the same clock line, which is then led to the same first signal pin 31. Alternatively, the third clock terminal ck3 is electrically connected to a clock line, and the second clock terminal ck2 is electrically connected to a clock line, with both clock lines led to the same first signal pin 31.

[0251] Furthermore, when the first driving module 6 also includes a twelfth switch T12 or a fifteenth switch T15, in the same shift unit 3, the fourth clock terminal ck4 and the first clock terminal ck1 are electrically connected to the same second signal pin 32. Wherein, when the second circuit 5 includes at least two first clock terminals ck1, the fourth clock terminal ck4 can be electrically connected to any one of the first clock terminals ck1.

[0252] Based on the above structure, the working process of shift unit 3 includes the time period q1 to q7.

[0253] During period q1, the shift input In(i) is low, and the second clock input ck2(i) and the third clock input ck3(i) are also low. The seventh switch T7 is turned on, setting the second node N2(i) low. The seventeenth switch T17 is turned on, setting the tenth node N10(i) high and controlling the eighteenth switch T18 to turn off. The nineteenth switch T19 is turned on, setting the first node N1(i) high. During this period, the shift output Next(i) and the first output Out1(i) are low. For the second circuit 5, the third node N3(i) is low, and both the second output Out2(2i-1) and the second output Out2(2i) are high.

[0254] During the q2 period, the shift input In(i) is low, and the first clock input ck1(2i-1) and the fourth clock input ck4(i) are low. The shift output Next(i) and the first input Out1(i) continuously output low, while the two second inputs Out2 continuously output high.

[0255] During the q3 period, the shift input terminal In(i) is at a high level, the second clock terminal ck2(i) and the third clock terminal ck3(i) are at a high level, the shift output terminal Next(i) and the first terminal Out1(i) continuously output a low level, and the second terminal Out2(2i-1) and the second terminal Out2(2i) continuously output a high level.

[0256] During period q4, the shift input In(i) is high, while the second clock input ck2(i) and the third clock input ck3(i) are low. The seventh switch T7 is turned on, setting the second node N2 high. The tenth node N10(i) is set low, and the eighteenth switch T18 is turned on, setting the first node N1 low. The shift output Next(i) and the first output Out1(i) are both high. For the second circuit 5, since the second output Out2(2i-2) of the previous shift unit 3(i-1) is high, the second output Out2(2i-1) and the second output Out2(2i) continue to output high levels.

[0257] During period q5, the shift input In(i) is high, while the second clock input ck2(i) and the third clock input ck3(i) are low. The seventh switch T7 is turned on, writing high to the second node N2. The tenth node N10(i) is set low, and the eighteenth switch T18 is turned on, writing low to the first node N1. The shift output Next(i) and the first output Out1(i) are high. For the second circuit 5, the fifth switch T5 is turned on, and the second output Out2(2i-2) of the previous shift unit 3(i-1) is low, writing low to the fourth node N4.

[0258] During the q6 period, the first clock terminal ck1(2i-1) outputs a valid pulse, and the second terminal Out2(2i-1) outputs a low level.

[0259] During the q7 period, the first clock terminal ck1(2i) outputs a valid pulse, and the second terminal Out2(2i) outputs a low level.

[0260] In the above configuration, the third clock terminal ck3 and the second clock terminal ck2 are electrically connected to the same first signal pin 31. Under the premise of ensuring the normal operation of the circuit, the number of clock lines and / or quotation mark pins set in the display panel can be reduced.

[0261] Furthermore, when the third clock terminal ck3 and the second clock terminal ck2 are electrically connected to the same clock line, this type of clock line has more connected clock terminals, resulting in a correspondingly larger load. In this case, the connection relationship between the clock terminals and the clock lines can adopt the connection methods shown in Figures 27 and 29. Under these two connection methods, each clock line will be connected to the second clock terminal ck2 and the fourth clock terminal ck4 in turn, thereby making the load of each clock line more balanced.

[0262] Alternatively, in another feasible implementation, as shown in FIG46, FIG46 is a schematic diagram of another structure of the first circuit 4 provided in the embodiment of the present invention, the first control unit 12 includes a seventeenth switch T17, an eighteenth switch T18 and a nineteenth switch T19.

[0263] The gate of the seventeenth switch T17 is electrically connected to the shift input terminal In, its first terminal is electrically connected to the first power supply terminal VGH, and its second terminal is electrically connected to the fourth clock terminal ck4 through the third capacitor C3. The gate of the eighteenth switch T18 is electrically connected to the second terminal of the seventeenth switch T17, its first terminal is electrically connected to the fourth clock terminal ck4, and its second terminal is electrically connected to the first node N1. The gate of the nineteenth switch T19 is electrically connected to the second node N2, its first terminal is electrically connected to the first power supply terminal VGH, and its second terminal is electrically connected to the first node N1.

[0264] Compared to Figure 44, the first terminal of the eighteenth switch T18 is electrically connected to the fourth clock terminal ck4, which can also ensure the normal operation of the first circuit 4. The only difference is that the transition time of the high level output by the shift output terminal Next and the first terminal Out1 is changed from the time when the first clock terminal ck1 goes low to the time when the fourth clock terminal ck4 goes low. The high level duration of the output by the shift output terminal Next and the first terminal Out1 will be shorter.

[0265] Further, as shown in Figure 47, which is another structural schematic diagram of the shift unit 3 provided in the embodiment of the present invention, the second output module 9 outputs the voltage of the first power supply terminal VGH to the second terminal Out2 in response to the first level of the third node N3, and outputs the voltage of the first clock terminal ck1 to the second terminal Out2 in response to the first level of the fourth node N4.

[0266] The second drive module 8 includes a fifth switch T5, the gate of which is electrically connected to the second clock terminal ck2, and the second terminal is electrically connected to the fourth node N4.

[0267] In the i-th shift unit 3(i), the first terminal of the fifth switch T5 is electrically connected to the second terminal Out2 of the (i-1)-th shift unit 3. For the same shift unit 3, during the time period when the third node N3 is at the second level, the second terminal Out2 connected to the fifth switch T5 outputs a first level, and the first level overlaps with the first level provided by the second clock terminal ck2 connected to the fifth switch T5.

[0268] Among them, the third clock terminal ck3 and the second clock terminal ck2 are electrically connected to the same first signal pin 31, and the fourth clock terminal ck4 and the first clock terminal ck1 are electrically connected to the same second signal pin 32.

[0269] Specifically, the third clock terminal ck3 and the second clock terminal ck2 are connected to the same clock line, which is then led to the same first signal pin 31. Alternatively, the third clock terminal ck3 is electrically connected to a clock line, and the second clock terminal ck2 is electrically connected to a clock line. These two clock lines are then electrically connected and led to the same first signal pin 31.

[0270] The fourth clock terminal ck4 and the first clock terminal ck1 are connected to the same clock line, which is then led to the same second signal pin 32. Alternatively, the fourth clock terminal ck4 is electrically connected to a clock line, and the first clock terminal ck1 is electrically connected to a clock line. These two clock lines are then electrically connected to the same second signal pin 32.

[0271] In one feasible implementation, the fourth clock terminal ck4 of the i-th shift unit 3(i) and the first clock terminal ck1(2i-1) are electrically connected to the same second signal pin 32. Thus, the transition time between the high levels output by the shift output terminal Next(i) and the first terminal Out1(i) is the moment when the first clock terminal ck1(2i-1) goes low, and the pulse width of the signals output by the shift output terminal Next(i) and the first terminal Out1(i) can be larger.

[0272] The above configuration method can reduce the number of clock lines and / or quotation mark pins on the display panel, while ensuring the normal operation of the circuit.

[0273] In one feasible implementation, as shown in FIG48, FIG48 is another structural schematic diagram of the shifting unit 3 provided in the embodiment of the present invention, wherein the third node N3 is electrically connected to the second node N2.

[0274] Alternatively, as shown in Figure 49, which is another structural schematic diagram of the shift unit 3 provided in the embodiment of the present invention, the seventh switch T7 is electrically connected to the second node N2 through the first protection switch T34, the gate of the first protection switch T34 is electrically connected to the second power supply terminal VGL, and the third node N3 is electrically connected to the second electrode of the seventh switch T7, that is, electrically connected to the sixth node N6.

[0275] Alternatively, as shown in Figure 50, which is another structural schematic diagram of the shift unit 3 provided in the embodiment of the present invention, the third node N3 is electrically connected to the first pole of the fourteenth switch T14, that is, electrically connected to the eighth node N8.

[0276] Alternatively, as shown in Figure 51, which is another structural schematic diagram of the shift unit 3 provided in the embodiment of the present invention, the thirteenth switch T13 is electrically connected to the fourteenth switch T14 through the second protection switch T35, the gate of the second protection switch T35 is electrically connected to the second power supply terminal VGL, and the third node N3 is electrically connected to the second pole of the thirteenth switch T13, that is, electrically connected to the seventh node N7.

[0277] Referring to Figure 45, based on the structure of the first circuit 4, the signal levels of the second node N2, the sixth node N6, the eighth node N8, and the seventh node N7 are basically consistent. The third node N3 can be selected from the second node N2, the sixth node N6, the eighth node N8, or the seventh node N7 to ensure the normal operation of the second circuit 5.

[0278] In one feasible implementation, referring to Figures 32 and 34, the first output module 7 includes a twentieth switch T20 and a twenty-first switch T21.

[0279] Specifically, the gate of the twentieth switch T20 is electrically connected to the first node N1, its first terminal is electrically connected to the third clock terminal ck3 or the first power supply terminal VGH, and its second terminal is electrically connected to the output terminal. The gate of the twenty-first switch T21 is electrically connected to the second node N2, its first terminal is electrically connected to the second power supply terminal VGL, and its second terminal is electrically connected to the output terminal. This output terminal can be either the shift output terminal Next or the first terminal Out1.

[0280] When the first node N1 is low, the twentieth switch T20 is turned on, outputting either the signal from the third clock terminal ck3 or the high level from the first power supply terminal VGH. When the second node N2 is low, the twenty-first switch T21 is turned on, outputting the low level provided by the second power supply terminal VGL.

[0281] When the twentieth switch T20 is connected to the third clock terminal ck3, the first terminal of the ninth switch T9 can be connected to the third clock terminal ck3. When the twentieth switch T20 is electrically connected to the first power supply terminal VGH, the first terminal of the ninth switch T9 can be electrically connected to the first power supply terminal VGH. The operation of these two structures has been described in the above embodiments and will not be repeated here.

[0282] In one feasible implementation, as shown in FIG52, FIG52 is a schematic diagram of another structure of the first circuit 4 provided in the embodiment of the present invention. The first output module 7 includes a first terminal Out1, and the first output module 7 provides a signal to the first terminal Out1. In this structure, the signal output by the first output module 7 is directly used as the gate signal of the first transistor M1.

[0283] In one feasible implementation, as shown in FIG53, FIG53 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention. The first circuit 4 includes a shift control sub-circuit 10 and a partition control sub-circuit 11.

[0284] The shift control sub-circuit 10 includes a first drive module 6 and a first output module 7. The first drive module 6 includes a shift input terminal In, and the first output module 7 includes a shift output terminal Next. In two adjacent shift units 3, the shift output terminal Next of the previous shift unit 3 is electrically connected to the shift input terminal In of the next shift unit 3.

[0285] The partition control sub-circuit 11 includes a first terminal Out1, and the partition control sub-circuit 11 outputs a signal to the first terminal Out1 according to the partition control signal.

[0286] In this structure, the signal output by the first output module 7 serves as the shift control signal, and the signal output by the partition control sub-circuit 11 serves as the gate signal of the first transistor M1.

[0287] In one feasible implementation, referring to FIG53, the partition control sub-circuit 11 includes a twenty-second switch T22 and a twenty-third switch T23.

[0288] Specifically, the gate of the twenty-second switch T22 is electrically connected to the first node N1, the first terminal is electrically connected to the partition control terminal ctrl, and the second terminal is electrically connected to the first terminal Out1. The gate of the twenty-third switch T23 is electrically connected to the second node N2, the first terminal is electrically connected to the second power supply terminal VGL, and the second terminal is electrically connected to the first terminal Out1.

[0289] In this structure, the signal output by the first terminal Out1 is controlled by the signal of the partition control terminal ctrl. When a part of the display area needs to be driven at a low frequency, in some frames, the first terminal Out1 of the shift unit 3 corresponding to this part of the display area can be controlled by the partition control terminal ctrl to not output pulses.

[0290] Furthermore, referring to Figures 9, 53 and 54, Figure 54 is a timing diagram corresponding to Figure 53. The first output module 7 responds to the voltage of the first node N1 and outputs the signal of the third clock terminal ck3.

[0291] The display panel includes a first partition AA1 and a second partition AA2.

[0292] In the first display mode (FD), the driving frequencies of the first partition AA1 and the second partition AA2 are the same, and the level of the signal provided by the partition control terminal ctrl is consistent with the level of the signal provided by the third clock terminal ck3. In the second display mode (SD), the driving frequency of the second partition AA2 is lower than the driving frequency of the first partition AA1. In some frames, when driving the second partition AA2, the partition control terminal ctrl provides a low level to control the first transistor M1 to turn off.

[0293] In the first display mode FD, the partition control terminal ctrl provides the same signal as the third clock terminal ck3, that is, the first pole of the twentieth switch T20 and the twelfth switch T22 receives the same signal. The twentieth switch T20 and the twelfth switch T22 are synchronously turned on and off, so that the first terminal Out1 and the shift output terminal Next output the same signal, and the first terminal Out1 of multiple shift units 3 outputs a high level in sequence.

[0294] In the second display mode SD, the second partition AA2 is driven at a low frequency. In some frames, when driving the second partition AA2, the partition control terminal ctrl provides a low level, so that the first terminal Out1 of the shift unit 3 corresponding to the second partition AA2 cannot output a high level, thereby reducing the data refresh frequency of the second partition AA2.

[0295] Alternatively, in conjunction with Figures 9, 55 and 56, Figure 55 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention, and Figure 56 is a timing diagram corresponding to Figure 55. The first output module 7 responds to the voltage of the first node N1 and outputs the signal of the first power supply terminal VGH.

[0296] The display panel includes a first partition AA1 and a second partition AA2.

[0297] In the first display mode (FD), the driving frequencies of the first partition AA1 and the second partition AA2 are the same, and the partition control terminal ctrl provides a high level to control the first transistor M1 to turn on. In the second display mode (SD), the driving frequency of the second partition AA2 is lower than the driving frequency of the first partition AA1. In some frames, when driving the second partition AA2, the partition control terminal ctrl provides a low level to control the first transistor M1 to turn off.

[0298] In the first display mode FD, the partition control terminal ctrl provides the same signal as the third clock terminal ck3, that is, the first pole of the twentieth switch T20 and the twelfth switch T22 receives the same signal. The twentieth switch T20 and the twelfth switch T22 are synchronously turned on and off, so that the first terminal Out1 and the shift output terminal Next output the same signal, and the first terminal Out1 of multiple shift units 3 outputs a high level in sequence.

[0299] In the second display mode SD, in some frames, when driving the second partition AA2, the partition control terminal ctrl provides a low level, and the first terminal Out1 of the shift unit 3 corresponding to the second partition AA2 cannot output a high level, thereby reducing the data refresh frequency of the second partition AA2.

[0300] Regarding the partition control sub-circuit 11, in another feasible implementation, as shown in FIG57, FIG57 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention. The partition control sub-circuit 11 includes a third driving module 13 and a third output module 14.

[0301] The third output module 14 responds to the voltage of the fifth node N5 by outputting a high level to the first terminal Out1 to control the first transistor M1 to turn on, and responds to the voltage of the second node N2 by outputting a low level to the first terminal Out1 to control the first transistor M1 to turn off.

[0302] More specifically, the third output module 14 includes a thirty-sixth switch T36 and a thirty-seventh switch T37. The gate of the thirty-sixth switch T36 is electrically connected to the fifth node N5, the first terminal is electrically connected to the first power supply terminal VGH, and the second terminal is electrically connected to the first terminal Out1. The gate of the thirty-seventh switch T37 is electrically connected to the second node N2, the first terminal is electrically connected to the second power supply terminal VGL, and the second terminal Out2 is electrically connected to the first terminal Out1.

[0303] The third drive module 13 includes a twenty-fourth switch transistor T24 and a second control unit 15. The gate of the twenty-fourth switch transistor T24 is electrically connected to the shift control sub-circuit 10, its first terminal is electrically connected to the second power supply terminal VGL, and its second terminal is electrically connected to the fifth node N5. For at least a portion of the time, the signal levels of the gate of the twenty-fourth switch transistor T24 and the signal levels of the second node N2 are consistent. The second control unit 15 is electrically connected to the partition control terminal ctrl and the first drive module 6, and the second control unit 15 controls the signal of the fifth node N5.

[0304] In the above structure, the 37th switch T37 in the third output module 14, which is used to output a low level, and the 21st switch T21 in the first output module 7, which is also used to output a low level, both respond to the voltage of the second node N2. The two switches are turned on or off simultaneously, so that the timing of the second terminal Out2 and the shift output terminal Next outputting a low level is consistent. The 36th switch T36 in the third output module 14, which is used to output a high level, responds to the voltage of the fifth node N5. The signal of the fifth node N5 is controlled independently by the second control unit 15. The second control unit 15 can provide the corresponding signal to the fifth node N5 according to whether the display panel needs to be driven by frequency division, thereby controlling whether the first terminal Out1 can output a high level.

[0305] In one feasible implementation, referring to FIG57, the second control unit 15 includes a twenty-fifth switch T25. The gate of the twenty-fifth switch T25 is electrically connected to the partition control terminal ctrl, the first terminal is electrically connected to the first node N1, and the second terminal is electrically connected to the fifth node N5.

[0306] Referring to Figure 58, which is a timing diagram corresponding to Figure 57, in the first display mode FD, the driving frequencies of the first partition AA1 and the second partition AA2 are the same. At this time, the partition control terminal ctrl of each shift unit 3 can be controlled to provide a low level, so that the voltage of the fifth node N5 is consistent with that of the first node N1, thereby making the working states of the thirty-sixth switch T36 and the thirty-seventh switch T37 consistent. When the shift output terminal Next outputs a pulse, the first terminal Out1 also outputs a pulse synchronously.

[0307] In the second display mode SD, the driving frequency of the second partition AA2 is lower than that of the first partition AA1. In some frames, when driving the second partition AA2, the partition control terminal ctrl of the shift unit 3 corresponding to the second partition AA2 can be controlled to provide a high level, thus preventing the low level of the first node N1 from being written to the fifth node N5, and the second terminal Out2 cannot output a high level.

[0308] In one feasible implementation, as shown in FIG59, FIG59 is a schematic diagram of a connection between the shift register 2 and the control line provided in an embodiment of the present invention. The partition control terminal ctrl in the multiple shift units 3 can be electrically connected to a control line CTRL'.

[0309] In the first display mode FD, the control line CTRL' provides a low level; in the second display mode SD, the control line CTRL' provides a low level when driving the first partition AA1; and the control line CTRL' provides a high level when driving the second partition AA2.

[0310] However, the inventors discovered during the research process that when the pulse width of the signal output by the first terminal Out1 is large, or when the first terminal Out1 performs multi-pulse output, this structure may result in incomplete waveforms output by the first terminal Out1 of some shift units 3 in the second display mode SD.

[0311] Taking the first terminal Out1 for multi-pulse output as an example, as shown in Figure 60, Figure 60 is another structural schematic diagram of the pixel circuit 1 provided in the embodiment of the present invention. The pixel circuit 1 also includes a bias transistor M04. The gate of the bias transistor M04 is electrically connected to the fourth scan line SP', the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the first terminal of the driving transistor M00.

[0312] When the first terminal Out1 of the shift unit 3 is used to provide a signal to the gate of the threshold compensation transistor M01, in one driving mode, as shown in FIG61, FIG61 is a timing diagram of the signal output by the first terminal Out1 of the shift unit 3 provided in the embodiment of the present invention. The first terminal Out1 can output two pulses. When the first terminal Out1 outputs the first high level, the threshold compensation transistor M01 is turned on, and the bias voltage is written to the driving transistor M00 to adjust the bias state of the driving transistor M00. When the first terminal Out1 outputs the second high level, the threshold compensation transistor M01 is turned on, and the data voltage is written to the driving transistor M00 to charge the gate of the driving transistor M00.

[0313] When the partition control terminal ctrl in multiple shift units 3 is electrically connected to a control line CTRL', as shown in Figure 62, Figure 62 is another connection diagram of shift register 2 and control line provided in the embodiment of the present invention. For two adjacent first partitions AA1 and second partitions AA2, it is assumed that the (i-1)th level shift unit 3(i-1) is the last level shift unit 3 corresponding to the first partition AA1, and the i-th level shift unit 3(i) is the first level shift unit 3 corresponding to the second partition AA2.

[0314] The moment when the control line CTRL' jumps to a high level determines the moment when the first terminal Out1(i) of the i-th shift unit 3(i) stops outputting a high level.

[0315] As shown in Figure 63, which is a timing diagram corresponding to Figure 62, if the control line CTRL' jumps high at time k1, although it can ensure that the i-th level shift unit 3(i) stops outputting a high level, the 25th switch T25 in the subsequent shift units 3 corresponding to the first partition AA1 will be cut off at time k1. This will cause the first terminal Out1(i-1) of these shift units 3 to be unable to output a second high level, affecting the display of the last few rows of the first partition AA1.

[0316] In this regard, the present invention further proposes that the partition control terminal ctrl in the plurality of shift units 3 can be electrically connected to two control lines respectively.

[0317] As shown in Figures 64 to 66, Figure 64 is a schematic diagram of another connection between the shift register 2 and the control line provided in the embodiment of the present invention, Figure 65 is a timing diagram corresponding to Figure 64, and Figure 66 is another timing diagram corresponding to Figure 64. The shift register 2 includes at least two cascaded unit groups 40, and the unit group 40 includes multiple cascaded shift units 3.

[0318] In two adjacent unit groups 40, the partition control terminal ctrl of the shift unit 3 in one unit group 40 is electrically connected to the first control line CTRL1', and the partition control terminal ctrl of the shift unit 3 in the other unit group 40 is electrically connected to the second control line CTRL2'.

[0319] In one structure, one partition corresponds to one unit group. In the second display mode SD, referring to Figure 65, it is assumed that the low-frequency partition corresponds to the y1th unit group 40(y1), and the y1th unit group 40(y1) is connected to the second control line CTRL2'. When entering this low-frequency partition, the second control line CTRL2' is controlled to go high, and the first control line CTRL1' continues to output low. This ensures that the first terminal Out1 of the y1th unit group 40(y1) stops outputting a high level, while avoiding affecting the signal waveform output by the first terminal Out1 of the (y1-1)th unit group 40(y1-1).

[0320] Alternatively, in another structure, one partition corresponds to at least two unit groups. In the second display mode SD, referring to Figure 66, it is assumed that the low-frequency partition corresponds to the y1th unit group 40(y1) and the y1+1th unit group 40(y1+1), and the y1th unit group 40(y1) is connected to the second control line CTRL2', and the y1+1th unit group 40(y1+1) is connected to the first control line CTRL1'. When entering the low-frequency zone, first control the second control line CTRL2' to jump high, and control the first control line CTRL1' to continue outputting low, until the first terminal Out1 of the last shift unit 3 of the (y1-1)th unit group 40 outputs a complete waveform, then control the first control line CTRL1' to jump high. In this way, while ensuring that the first terminal Out1 of the y1th unit group 40(y1) and the y1+1th unit group 40(y1+1) stops outputting a high level, it avoids affecting the signal waveform output by the first terminal Out1 of the (y1-1)th unit group 40(y1-1).

[0321] This structure allows the first terminal Out1 of each partition's corresponding shift unit 3 to output a complete waveform, making it more suitable for driving modes where the pulse width of the signal output by the first terminal Out1 is large or where the first terminal Out1 performs multi-pulse output.

[0322] Based on the above-mentioned connection method between unit group 40 and control lines, in an optional structure, as shown in Figures 67 to 69, Figure 67 is a schematic diagram of another connection between the shift register 2 and control lines provided in an embodiment of the present invention, Figure 68 is a timing diagram corresponding to Figure 67, and Figure 69 is another timing diagram corresponding to Figure 67. The display panel includes a first partition AA1 and a second partition AA2. Unit group 40 includes a first unit group 40-1 and a second unit group 40-2.

[0323] The first partition AA1 corresponds to the first unit group 40-1, and the second partition AA2 corresponds to the second unit group 40-2. The first unit group 40-1 is electrically connected to the first control line CTRL1', and the second unit group 40-2 is electrically connected to the second control line CTRL2'.

[0324] In the first display mode FD, both the first control line CTRL1' and the second control line CTRL2' provide a low level, and the first terminal Out1 of the shift unit 3 in the first unit group 40-1 and the second unit group 40-2 outputs a high level in sequence.

[0325] In the second display mode SD, the first control line CTRL1' provides a low level, and the second control line CTRL2' provides a high level. Alternatively, when entering the second partition AA2, the second control line CTRL2' jumps to a high level, so that the first terminal Out1 of the first unit group 40-1 outputs a high level sequentially, and the first terminal Out1 of the second unit group 40-2 does not output a high level.

[0326] Regarding the second control unit 15, in another feasible implementation, as shown in FIG70, FIG70 is another structural schematic diagram of the first circuit 4 provided in the embodiment of the present invention, the second control unit 15 may further include a twenty-sixth switch T26 and a twenty-seventh switch T27.

[0327] Specifically, the gate of the 26th switch T26 is electrically connected to the shift control sub-circuit 10, and its first terminal is electrically connected to the partition control terminal ctrl. For at least a portion of the time, the gate of the 26th switch T26 has the same signal level as the second node N2. The gate of the 27th switch T27 is electrically connected to the second terminal of the 26th switch T26, its first terminal is electrically connected to the first node N1, and its second terminal is electrically connected to the fifth node N5.

[0328] Based on this structure, the shift output terminals Next of multiple shift units 3 are connected to only one control line CTRL', which can also ensure that the first terminal Out1 of each shift unit 3 outputs a normal waveform.

[0329] Specifically, as shown in Figures 71 to 73, Figure 71 is another schematic diagram of the connection between the shift register 2 and the control line provided in this embodiment of the invention, Figure 72 is a timing diagram corresponding to Figure 71, and Figure 73 is another timing diagram corresponding to Figure 71. In the first display mode FD, the control line CTRL' provides a low level. When the second node N2 is low, the twenty-sixth switch T26 is turned on, setting the gate voltage of the twenty-seventh switch T27 low. The twenty-seventh switch T27 is turned on, making the potential of the fifth node N5 consistent with that of the first node N1. When the second node N2 jumps to a high level, the twenty-sixth switch T26 is turned off, and the twenty-seventh switch T27 remains on, so that the potential of the fifth node N5 remains consistent with that of the first node N1. In this way, the gate signals of the thirty-sixth switch T36 and the twentieth switch T20 are consistent, and the gate signals of the thirty-seventh switch T37 and the twenty-first switch T21 are consistent, making the level states of the signals output by the shift output terminal Next and the first terminal Out1 consistent.

[0330] In the second display mode SD, assume that the (i-1)th level shift unit 3 is the last level shift unit 3 corresponding to the first partition AA1, and the i-th level shift unit 3(i) is the first level shift unit 3 corresponding to the second partition AA2. Referring to Figure 72, the control line CTRL' can jump high at time k2. At time t2, the second node N2 in the (i-1)th level shift unit 3 is high, and the second node N2 in the i-th level shift unit 3(i) is low. At this time, the second node N2 in the i-th level shift unit 3(i) is low, so the high level provided by the control line CTRL' will be written to the gate of the twenty-seventh switch T27, causing the twenty-seventh switch T27 to be turned off. When the first node N1 is low later, the low level cannot be written to the fifth node N5, so the first terminal Out1(i) cannot output a high level. Meanwhile, since the second node N2 in the (i-1)th stage shift unit 3 is at a high level, even if the signal provided by the control line CTRL' jumps to high, this high level will not be written into the twenty-seventh switch T27 in the (i-1)th stage shift unit 3. The twenty-seventh switch T27 will remain in the conducting state, so that the potentials of the subsequent fifth node N5 and the first node N1 are consistent, and will not affect, and thus will not affect, the normal output of the first terminal Out1 of the (i-1)th stage shift unit 3.

[0331] In summary, this structure can enable the first terminal Out1 of each partition's corresponding shift unit 3 to output a complete waveform using only one control line. It is more suitable for driving modes where the pulse width of the signal output by the first terminal Out1 is large or where the first terminal Out1 performs multi-pulse output, and requires fewer signal lines.

[0332] In one feasible implementation, referring to Figure 70, the gate of the twenty-sixth switch T26 is electrically connected to the second node N2.

[0333] Alternatively, the gate of the 26th switch T26 can also be electrically connected to the shift output terminal Next.

[0334] Alternatively, in other alternative embodiments, the gate of the 26th switch T26 may also be electrically connected to the sixth node N6, the seventh node N7, or the eighth node N8.

[0335] Based on the structure of the shift control sub-circuit 10, the signal levels of the second node N2, the shift output terminal Next, the sixth node N6, the eighth node N8, and the seventh node N7 are basically consistent. Therefore, the gate selection of the twenty-sixth switch T26 can ensure the normal operation of the partition control sub-circuit 11 by selecting either the second node N2, the shift output terminal Next, the sixth node N6, the eighth node N8, or the seventh node N7.

[0336] In one feasible implementation, referring to Figure 70, the gate of the twenty-fourth switch T24 is electrically connected to the second node N2.

[0337] Alternatively, in other alternative embodiments, the gate of the 26th switch T26 may also be electrically connected to the sixth node N6, the seventh node N7, or the eighth node N8.

[0338] Based on the structure of the shift control sub-circuit 10, the signal levels of the second node N2, the sixth node N6, the eighth node N8, and the seventh node N7 are basically consistent. Therefore, the gate of the twenty-fourth switch T24 can be electrically connected to the second node N2, the sixth node N6, the eighth node N8, or the seventh node N7 to ensure the normal operation of the partition control sub-circuit 11.

[0339] Furthermore, compared to the shift output terminal Next, the second node N2, the sixth node N6, the eighth node N8, and the seventh node N7 are internal nodes of the circuit, and their signal stability will be higher. The twenty-fourth switch T24 directly affects the potential of the fifth node N5. Therefore, if the twenty-fourth switch T24 is connected to one of the above nodes, its device stability will be better.

[0340] In this embodiment of the invention, the gate of the twenty-sixth switch T26 can be electrically connected to one of the second node N2, the shift output terminal Next, the sixth node N6, the seventh node N7, and the eighth node N8, and the gate of the twenty-fourth switch T24 can be electrically connected to one of the second node N2, the sixth node N6, the seventh node N7, and the eighth node N8. The nodes connected to the gate of the twenty-sixth switch T26 and the gate of the twenty-fourth switch T24 can be the same or different.

[0341] In addition, referring to Figure 70, the partition control sub-circuit 11 may also include a seventh capacitor C7, the first plate of the seventh capacitor C7 is electrically connected to the first plate of the thirty-sixth switch transistor T36, and the second plate is electrically connected to the fifth node N5.

[0342] Regarding the partition control sub-circuit 11, in another feasible implementation, as shown in Figures 74 and 75, Figure 74 is a schematic diagram of another structure of the first circuit 4 provided in the embodiment of the present invention, and Figure 75 is a schematic diagram of another structure of the first circuit 4 provided in the embodiment of the present invention. The partition control sub-circuit 11 includes a third driving module 13 and a third output module 14.

[0343] The third output module 14 responds to the first level of the fifth node N5 by outputting a level to the first terminal Out1 to control the first transistor M1 to turn on, and responds to the voltage of the second node N2 by outputting a level to the first terminal Out1 to control the first transistor M1 to turn off. The first level can be a low level.

[0344] The first driving module 6 includes a 28th switching transistor T28 and a third control unit 16. The gate of the 28th switching transistor T28 is electrically connected to the shift control sub-circuit 10, and its first terminal is electrically connected to the partition control terminal ctrl. For at least a portion of the time, the gate of the 28th switching transistor T28 is in the same voltage level as the signal at the second node N2. The control terminal of the third control unit 16 is electrically connected to the second terminal of the 28th switching transistor T28. When the third control unit 16 is turned on, it provides a second voltage level to the fifth node N5, which can be a high voltage level.

[0345] Based on the above structure, both the 37th switch T37 and the 21st switch T21 are used to output a low level. The level states of the nodes they respond to are consistent, so the two switches operate in the same state, synchronously turning on and off, thereby enabling the shift output terminal Next and the first terminal Out1 to output a low level synchronously.

[0346] The thirty-sixth switch, T36, responds to the voltage of the fifth node, N5. The signal of the fifth node, N5, is controlled independently by the third control unit 16. The third control unit 16 can provide the corresponding signal to the fifth node, N5, according to whether the display panel needs to be divided into zones and frequency drives, thereby controlling whether the first terminal, Out1, can output a high level.

[0347] Further, referring to Figures 74 and 75, the second control unit 15 includes a twenty-ninth switch T29 and a thirtieth switch T30, where the twenty-ninth switch T29 is an N-type transistor and the thirtieth switch T30 is a P-type transistor.

[0348] The gates of the twenty-ninth switch T29 and the thirtieth switch T30 are both electrically connected to the second terminal of the twenty-eighth switch T28. The second terminals of the twenty-ninth switch T29 and the thirtieth switch T30 are both electrically connected to the fifth node N5.

[0349] Referring to Figure 75, the first terminal of the twenty-ninth switch T29 is electrically connected to the first node N1, and the first terminal of the thirtieth switch T30 is electrically connected to the first power supply terminal VGH.

[0350] In the first display mode (FD), the partition control terminal ctrl provides a high level. The 29th switch T29 remains on, and the potentials of the fifth node N5 and the first node N1 are consistent. In the second display mode (SD), in some frames, when entering the second partition AA2, the signal provided by the partition control terminal ctrl goes low, the 29th switch T29 is turned off, and the 30th switch T30 is turned on, setting the fifth node N5 high.

[0351] Alternatively, referring to Figure 74, the first terminal of the twenty-ninth switch T29 is electrically connected to the first power supply terminal VGH, and the first terminal of the thirtieth switch T30 is electrically connected to the first node N1.

[0352] In the first display mode (FD), the partition control terminal ctrl provides a low level. The thirtieth switch T30 remains on, and the potentials of the fifth node N5 and the first node N1 are consistent. In the second display mode (SD), in some frames, when entering the second partition AA2, the signal provided by the partition control terminal ctrl jumps high, the thirtieth switch T30 is turned off, the twenty-ninth switch T29 is turned on, and the fifth node N5 is set high.

[0353] By setting the N-type 29th switch T29 in the partition control sub-circuit 11, the signal of the fifth node N5 can be controlled using only the 29th switch T29 and the 30th switch T30, so that the signal of the fifth node N5 varies according to the display mode. This partition control sub-circuit 11 has a simple structure and a small number of transistors.

[0354] In one feasible implementation, referring to Figure 75, the gate of the twenty-eighth switch T28 is electrically connected to the shift output terminal Next.

[0355] Alternatively, the gate of the twenty-eighth switch T28 is electrically connected to the second node N2.

[0356] Based on the structure of the shift control sub-circuit 10, the signal levels of the shift output terminal Next and the second node N2 are basically consistent. Therefore, the gate of the twenty-eighth switch T28 can be electrically connected to either the shift output terminal Next or the second node N2 to ensure the normal operation of the partition control sub-circuit 11.

[0357] In addition, referring to Figure 75, the third drive module 13 may also include an eighth capacitor C8, which is electrically connected between the second power supply terminal VGL and the gate of the twenty-ninth switch T30.

[0358] In shift unit 3, the switching transistors in the first output module 7, the second output module 9 and the third output module 14 are connected to the first power supply terminal VGH and / or the second power supply terminal VGL, and the switching transistors in the first drive module 6, the second drive module 8 and the third drive module 13 are also connected to the first power supply terminal VGH and / or the second power supply terminal VGL.

[0359] In one feasible implementation, the first power supply terminal VGH corresponding to the output module is connected to the first power supply line, and the second power supply terminal VGL corresponding to the output module is connected to the second power supply line. The first power supply terminal VGH corresponding to the drive module is connected to the third power supply line, and the second power supply terminal VGL corresponding to the output module is connected to the fourth power supply line.

[0360] The first power line has a wider line width than the third power line, and the second power line has a wider line width than the fourth power line, thereby reducing the signal voltage drop at the power supply terminal of the output module and improving the accuracy of the voltage output by the output module.

[0361] In one feasible implementation, referring to Figures 12 and 76, Figure 76 is a timing diagram corresponding to Figure 12, the pixel circuit 1 further includes a driving transistor M00.

[0362] The first transistor M1 includes a gate reset transistor M03 and a threshold compensation transistor M01, both of which are N-type transistors. Specifically, the gate of the gate reset transistor M03 is electrically connected to the first scan line SIN, its first terminal is electrically connected to the first reset line Ref1, and its second terminal is electrically connected to the gate of the driving transistor M00. The gate of the threshold compensation transistor M01 is electrically connected to the second scan line S2N, its first terminal is electrically connected to the second terminal of the driving transistor M00, and its second terminal is electrically connected to the gate of the driving transistor M00.

[0363] The second transistor M2 includes a data writing transistor M02, which is a P-type transistor. The gate of the data writing transistor M02 is electrically connected to the third scan line SP, the first terminal is electrically connected to the data line, and the second terminal is electrically connected to the first terminal of the driving transistor M00.

[0364] Referring to Figures 77 and 80, at least part of the first end Out1 of the shifting unit 3 is electrically connected to the first scan line S1N and / or the second scan line S2N, and at least part of the second end Out2 of the shifting unit 3 is electrically connected to the third scan line SP.

[0365] In this structure, the first terminal Out1 of the shift unit 3 outputs a first scan signal s1n and / or a second scan signal s2n with an effective level of high, which are used to drive the gate reset transistor M03 and / or the threshold compensation transistor M01 in the pixel circuit 1. The second terminal Out2 of the shift unit 3 outputs a third scan signal sp with an effective level of low, which is used to drive the data writing transistor M02 in the pixel circuit 1.

[0366] In one feasible implementation, as shown in Figures 77 and 78, Figure 77 is another structural schematic diagram of the display panel provided in the embodiment of the present invention, and Figure 78 is a timing diagram corresponding to Figure 77. The shift register 2 includes a first shift register 2-1 and a second shift register 2-2.

[0367] In this system, the first end Out1 of shift unit 3 in the first shift register 2-1 is electrically connected to the second scan line S2N, and the second end Out2 of shift unit 3 in the first shift register 2-1 is electrically connected to the third scan line SP.

[0368] The shift register 2 also includes a second shift register 2-2. The first end Out1 of the shift unit 3 in the second shift register 2-2 is electrically connected to the first scan line SIN, and the second end Out2 of part of the shift unit 3 in the second shift register 2-2 is electrically connected to the third scan line SP.

[0369] The shift unit 3 includes m second terminals Out2, where m ≥ 2.

[0370] The pixel circuit 1 includes a plurality of circuit groups 50 arranged along a first direction, the circuit group 50 includes m circuit rows 20 arranged along the first direction, and the circuit row 20 includes a plurality of pixel circuits 1 arranged along a second direction, the first direction and the second direction intersect.

[0371] For ease of understanding, in the accompanying drawings of the embodiments of the present invention, the i-th circuit group is identified by reference numeral 50(i), and the i-th circuit row is identified by reference numeral 20(i).

[0372] In the first shift register 2-1, the m second terminals Out2 of the a1-level shift unit 3 are electrically connected to the third scan line SP corresponding to the m circuit rows 20 in the a1-level circuit group 50, and the first terminal Out1 of the a1-level shift unit 3 is electrically connected to the second scan line S2N corresponding to the a1-level circuit group 50, where a1≥1.

[0373] In the second shift register 2-2, the m second terminals Out2 of the a2-level shift unit 3 are electrically connected to the third scan lines SP corresponding to the m circuit rows 20 in the a1-level circuit group 50, and the first terminal Out1 of the a2-level shift unit 3 is electrically connected to the first scan line SIN corresponding to the a3-level circuit group 50, where a2 > a1 and a3 > a1.

[0374] The embodiments of the present invention are illustrated using a2 = a1 + 1 and a3 = a1 + 1 as examples. It can be understood that, depending on the different timing designs, the differences between a2 and a1, and between a3 and a1, can also be other values.

[0375] To make it easier to understand, the following explanation will use a1 = 1 and a2 = 2 as an example.

[0376] In this structure, for the first circuit group 50(1), the required third scan signal sp is provided by the first-stage shift unit 3(1) in the second shift register 2-2 and by the second-stage shift unit 3(2) in the first shift register 2-1. This means that the first-stage shift unit 3(1) in the second shift register 2-2 and the second-stage shift unit 3(2) in the first shift register 2-1 output pulses synchronously, which in turn means that the first-stage shift unit 3(1) in the first shift register 2-1 outputs pulses earlier than the first-stage shift unit 3(1) in the second shift register 2-2.

[0377] The first shift unit 3(1) in the first shift register 2-1 provides the first scan signal s1n required by the first circuit group 50(1), and the first shift unit 3(1) in the second shift register 2-2 provides the second scan signal s2n required by the first circuit group 50(1). This can make the pulse of the second scan signal s2n corresponding to the first circuit group 50(1) later than the pulse of the first scan signal s1n, so that the timing of the first scan signal s1n, the second scan signal s2n and the third scan signal sp corresponding to the first circuit group 50(1) is correct.

[0378] Based on the connection relationship between the first shift register 2-1, the second shift register 2-2 and the scan line corresponding to the circuit row 20, while ensuring the normal output timing of the first scan signal s1n, the second scan signal s2n and the third scan signal sp in each row of pixel circuit 1, the first shift register 2-1 and the second shift register 2-2 are also made to drive the third scan line SP on both sides, thereby improving the charging effect of each row of pixel circuit 1.

[0379] Furthermore, in related technologies, when the signals for the first scan line S1N and the second scan line S2N are provided by different shift registers, and the third scan line SP is driven on both sides, two sets of shift registers are typically provided on each side of the display area. That is, as shown in Figure 79, which is a schematic diagram of a display panel structure in related technologies, the display panel includes shift register 101, shift register 102, and two shift registers 103. Shift register 101 is used to provide signals to the first scan line S1N, shift register 102 is used to provide signals to the second scan line S2N, and shift register 103 is used to provide signals to the third scan line SP. Shift register 101 and one of the shift registers 103 are located on one side of the display area, while shift register 102 and the other shift register 103 are located on the other side of the display area.

[0380] In this embodiment of the invention, shift register 101 and shift register 103 can be merged into shift register 2-2, and shift register 102 and another shift register 103 can be merged into shift register 2-1, so that there is only one shift register on each side of the display area, reducing the number of shift registers and significantly narrowing the border space required by the shift registers.

[0381] Alternatively, in another feasible implementation, as shown in Figures 80 and 81, Figure 80 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, and Figure 81 is a timing diagram corresponding to Figure 80. The shift register 2 includes a third shift register 2-3. The first end Out1 of the shift unit 3 in the third shift register 2-3 is electrically connected to the first scan line SIN and the second scan line S2N. The second end Out2 of part of the shift unit 3 in the third shift register 2-3 is electrically connected to the third scan line SP and the second scan line S2N.

[0382] The shift unit 3 includes m second terminals Out2, where m ≥ 2.

[0383] The pixel circuit 1 includes a plurality of circuit groups 50 arranged along a first direction, the circuit group 50 includes m circuit rows 20 arranged along the first direction, and the circuit row 20 includes a plurality of pixel circuits 1 arranged along a second direction, the first direction and the second direction intersect.

[0384] For the b-th circuit group 50, the third scan line SP corresponding to its m circuit rows 20 is electrically connected to the m second terminals Out2 of the c1-th shift unit 3 in the third shift register 2-3, and its corresponding second scan line S2N is electrically connected to the first terminal Out1 of the c1-th shift unit 3 in the third shift register 2-3, and its corresponding first scan line S1N is electrically connected to the first terminal Out1 of the c2-th shift unit 3 in the third shift register 2-3, where b≥1, c1>b, and c2<c1.

[0385] This embodiment of the invention illustrates the case with c1 = b + 1 and c2 = b as an example. It can be understood that, depending on the different timing designs, the difference between c1 and b, and the difference between c2 and c1, can be other values.

[0386] To make it easier to understand, the following explanation will use b=1, c1=2, c2=1 as an example.

[0387] In this structure, for the first circuit group 50(1), the corresponding third scan signal sp is provided by the second terminal Out2 of the second-level shift unit 3(2) of the third shift register 2-3, the corresponding second scan signal s2n is provided by the first terminal Out1 of the second-level shift unit 3(2) of the third shift register 2-3, and the corresponding first scan signal s1n is provided by the first-level shift unit 3(1) of the third shift register 2-3. Since the first-level shift unit 3(1) outputs a pulse earlier than the second-level shift unit 3(2), the pulse of the first scan signal s1n of the first circuit group 50(1) is earlier than the pulse of the second scan signal s2n. The timing of the first scan signal s1n, the second scan signal s2n and the third scan signal sp of the first circuit group 50(1) is correct.

[0388] Among them, the first end Out1 of the first shift unit 3(1) of the third shift register 2-3 is only connected to the first scan line S1N of the first circuit group 50(1) and not connected to the second scan line S2N. The second end of the first shift unit 3(1) of the third shift register 2-3 is floating and is not connected to the third scan line SP.

[0389] In this structure, the first terminal Out1 of the shift unit 3 is electrically connected to the first scan line SIN and the second scan line S2N, which means that the first terminal Out1 is electrically connected to the first scan line SIN and the second scan line S2N corresponding to different circuit groups 50.

[0390] Based on the connection relationship between the third shift register 2-3 and the scan line corresponding to the circuit row 20, the normal output timing of the first scan signal s1n, the second scan signal s2n and the third scan signal sp in each row pixel circuit 1 can be guaranteed.

[0391] Furthermore, as shown in Figure 82, which is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, the display panel may include two third shift registers 2-3, which are located on opposite sides of the display area, and perform bilateral driving on the first scan line SIN, the second scan line S2N and the third scan line SP to improve signal performance.

[0392] In this embodiment of the invention, referring to FIG12, the pixel circuit 1 may further include an anode reset transistor M05, a first light-emitting control transistor M06, a second light-emitting control transistor M07, and a storage capacitor Cst.

[0393] Among them, the gate of the anode reset transistor M05 is electrically connected to the third scan line SP, the first electrode is electrically connected to the second reset line Ref2, and the second electrode is electrically connected to the light-emitting element D.

[0394] The gate of the first light-emitting control transistor M06 is electrically connected to the light-emitting control signal line Emit, the first terminal is electrically connected to the power supply line PVDD, and the second terminal is electrically connected to the first terminal of the driving transistor M00.

[0395] The gate of the second light-emitting control transistor M07 is electrically connected to the light-emitting control signal line Emit, the first terminal is electrically connected to the second terminal of the driving transistor M00, and the second terminal is electrically connected to the light-emitting element D of the driving transistor M00.

[0396] The first plate of the storage capacitor Cst is electrically connected to the power supply line PVDD, and the second plate is electrically connected to the gate of the driving transistor M00.

[0397] Based on the same inventive concept, this embodiment of the invention also provides a display device, as shown in FIG83. FIG83 is a schematic diagram of a structure of the display device provided in this embodiment of the invention, which includes the aforementioned display panel 100. Of course, the display device shown in FIG83 is merely illustrative, and the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0398] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0399] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: The pixel circuit includes a first transistor and a second transistor; A shift register consists of multiple cascaded shift units; The shifting unit includes a first end and at least one second end, the first end and the second end output different signals, the first end is electrically connected to the gate of the first transistor, and the second end is electrically connected to the gate of the second transistor.

2. The display panel according to claim 1, characterized in that, The shifting unit includes a first circuit and a second circuit, the first circuit including a first terminal and the second circuit including a second terminal; The first circuit includes a first driving module and a first output module; the first output module responds to the voltage output signals of the first node and the second node; the first driving module controls the signals of the first node and the second node. The second circuit includes a second driving module and at least one second output module. The second output module responds to the voltage of the third node by outputting the voltage of the first power supply terminal to the second terminal, and responds to the voltage of the fourth node by outputting the voltage of the first clock terminal to the second terminal. The third node is electrically connected to the first circuit, and the signal levels of the third node and the second node are consistent for at least a portion of the time; the second driving module controls the signal of the fourth node.

3. The display panel according to claim 2, characterized in that, The first circuit includes a shift control sub-circuit and a partition control sub-circuit; The shift control sub-circuit includes a first driving module and a first output module. The first driving module includes a shift input terminal, and the first output module includes a shift output terminal. In two adjacent shift units, the shift output terminal of the previous shift unit is electrically connected to the shift input terminal of the next shift unit. The partition control sub-circuit includes the first terminal, and the partition control sub-circuit outputs a signal to the first terminal according to the partition control signal; The third node is electrically connected to the shift output terminal.

4. The display panel according to claim 3, characterized in that, The pixel circuit also includes a driving transistor; The first transistor includes a threshold compensation transistor electrically connected between the second terminal and the gate of the driving transistor, and at least one of the first terminals of the shift register is electrically connected to the gate of the threshold compensation transistor. Alternatively, the first transistor may include a data write transistor electrically connected between a data line and a first terminal of the driving transistor, and at least one first terminal of the shift register may be electrically connected to the gate of the data write transistor.

5. The display panel according to claim 2, characterized in that, The second drive module includes: The first switching transistor is an N-type transistor. The gate of the first switching transistor is electrically connected to the third node, the first terminal is electrically connected to the second power supply terminal, and the second terminal is electrically connected to the fourth node. The second switching transistor is a P-type transistor. Its gate is electrically connected to the third node, its first terminal is electrically connected to the first power supply terminal, and its second terminal is electrically connected to the fourth node.

6. The display panel according to claim 5, characterized in that, The second terminal of the first switching transistor is electrically connected to the fourth node through the third switching transistor; In this shift unit, the gate of the first switch in the i-th stage is electrically connected to the third node in the i-th stage, and the gate of the third switch in the i-th stage is electrically connected to the third node in the i0-th stage, i ≠ i0. During the time period when the first switch and the third switch in the i-th stage are simultaneously turned on, the first clock terminal connected to the i-th stage shift unit provides an effective pulse.

7. The display panel according to claim 6, characterized in that, The second drive module also includes a fourth switching transistor, which is an N-type transistor; The gate of the fourth switch is electrically connected to the gate of the third switch, the first terminal is electrically connected to the first power supply terminal, and the second terminal is electrically connected to the fourth node.

8. The display panel according to claim 2, characterized in that, The second output module responds to the first level of the third node by outputting the voltage of the first power supply terminal to the second terminal, and responds to the first level of the fourth node by outputting the voltage of the first clock terminal to the second terminal; The second driving module includes a fifth switching transistor, the gate of which is electrically connected to the second clock terminal and the second terminal is electrically connected to the fourth node; In this case, the first terminal of the fifth switch in the i-th stage shift unit is electrically connected to the second terminal of the (i-1)-th stage shift unit. For the same shift unit, during the time period when the third node is at the second level, the second terminal connected to the fifth switch outputs a first level, and the first level overlaps with the first level provided by the second clock terminal connected to the fifth switch.

9. The display panel according to claim 8, characterized in that, The pixel circuit includes a plurality of circuit rows arranged along the first direction, and the circuit rows include a plurality of the pixel circuits arranged along the second direction, wherein the first direction intersects the second direction; The second circuit includes m second output modules, where m ≥ 2. The m second output modules are electrically connected to the second transistors in the m circuit rows through m second terminals. The m second output modules are also electrically connected to the m first clock terminals. Wherein, the first to the mth second terminals of the shift unit of the (i-1)th stage are electrically connected to the jth to the j+(m-1)th circuit row, respectively, j≥1, and the fifth switch in the shift unit of the i-th stage is electrically connected to the mth second terminal of the shift unit of the (i-1)th stage.

10. The display panel according to claim 9, characterized in that, m＝2； The display panel includes a first clock line, a second clock line, a third clock line, and a fourth clock line; Wherein, the second clock terminal corresponding to the odd-numbered shift unit is electrically connected to the first clock line, and the two first clock terminals corresponding to the odd-numbered shift unit are electrically connected to the second clock line and the third clock line, respectively; The second clock terminal corresponding to the shift unit of the even-numbered stage is electrically connected to the third clock line, and the two first clock terminals corresponding to the shift unit of the even-numbered stage are electrically connected to the fourth clock line and the first clock line, respectively.

11. The display panel according to claim 9, characterized in that, m＝2； The display panel includes a first clock line, a second clock line, and a third clock line; Wherein, the second clock terminal corresponding to the shift unit of the 3x-2th stage is electrically connected to the first clock line, and the two corresponding first clock terminals are electrically connected to the second clock line and the third clock line respectively, x = 1, 2, 3, ...; The second clock terminal corresponding to the shift unit of the 3x-1 stage is electrically connected to the third clock line, and the two corresponding first clock terminals are electrically connected to the first clock line and the second clock line, respectively. The second clock terminal corresponding to the shift unit of the 3x stage is electrically connected to the second clock line, and the two corresponding first clock terminals are electrically connected to the third clock line and the first clock line, respectively.

12. The display panel according to claim 9, characterized in that, m＝2； The display panel includes a first clock line, a second clock line, a third clock line, a fourth clock line, and a fifth clock line; Wherein, the second clock terminal corresponding to the shift unit of the 5x-4th ​​level is electrically connected to the first clock line, and the two corresponding first clock terminals are electrically connected to the second clock line and the third clock line respectively, x = 1, 2, 3, ...; The second clock terminal corresponding to the shift unit of the 5x-3 level is electrically connected to the third clock line, and the two corresponding first clock terminals are electrically connected to the fourth clock line and the fifth clock line, respectively. The second clock terminal corresponding to the shift unit of the 5x-2 level is electrically connected to the fifth clock line, and the two corresponding first clock terminals are electrically connected to the first clock line and the second clock line, respectively. The second clock terminal corresponding to the shift unit of the 5x-1 stage is electrically connected to the second clock line, and the two corresponding first clock terminals are electrically connected to the third clock line and the fourth clock line, respectively. The second clock terminal corresponding to the shift unit of the 5x stage is electrically connected to the fourth clock line, and the two corresponding first clock terminals are electrically connected to the fifth clock line and the first clock line, respectively.

13. The display panel according to claim 2, characterized in that, The second circuit also includes a sixth switching transistor. The second driving module is electrically connected to the fourth node through the sixth switching transistor, and the gate of the sixth switching transistor is electrically connected to the second power supply terminal. Alternatively, the second circuit may further include at least one sixth switch, one sixth switch corresponding to one second output module, the sixth switch being electrically connected between the fourth node and the corresponding second output module, and the gate of the sixth switch being electrically connected to the second power supply terminal.

14. The display panel according to claim 2, characterized in that, The second circuit includes m second output modules, where m ≥ 2. The m second output modules are electrically connected to m second terminals and to m first clock terminals respectively. The m first clock terminals sequentially provide valid pulses.

15. The display panel according to claim 2, characterized in that, The first driving module includes: The seventh switch is electrically connected to the third clock terminal, the first terminal to the shift input terminal, and the second terminal to the second node. The first control unit controls the signals of the first node.

16. The display panel according to claim 15, characterized in that, The first control unit includes: The eighth switching transistor is an N-type transistor. The gate of the eighth switching transistor is electrically connected to the second node, the first terminal is electrically connected to the second power supply terminal, and the second terminal is electrically connected to the first node. The ninth switching transistor is a P-type transistor, and its gate is electrically connected to the second node, its first terminal is electrically connected to the third clock terminal, and its second terminal is electrically connected to the first node. Specifically, the first output module responds to the voltage of the first node and outputs the signal of the third clock terminal.

17. The display panel according to claim 15, characterized in that, The first control unit includes: The eighth switching transistor is an N-type transistor. The gate of the eighth switching transistor is electrically connected to the second node, the first terminal is electrically connected to the second power supply terminal, and the second terminal is electrically connected to the first node. The ninth switching transistor is a P-type transistor, and its gate is electrically connected to the second node, its first terminal is electrically connected to the first power supply terminal, and its second terminal is electrically connected to the first node. The first output module responds to the voltage of the first node and outputs the signal from the first power supply terminal.

18. The display panel according to claim 16 or 17, characterized in that, The first terminal of the eighth switch is electrically connected to the second power supply terminal through the tenth switch, and the gate of the tenth switch is electrically connected to the second power supply terminal.

19. The display panel according to claim 16 or 17, characterized in that, The second terminal of the ninth switch and the second terminal of the eighth switch are electrically connected to the first node through the eleventh switch, and the gate of the eleventh switch is electrically connected to the second power supply terminal.

20. The display panel according to claim 15, characterized in that, The first driving module further includes a twelfth switching transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to the fourth clock terminal, and the second terminal of which is electrically connected to the second node through a first capacitor.

21. The display panel according to claim 15, characterized in that, The first driver module also includes: The thirteenth switching transistor has its gate electrically connected to the third clock terminal and its first terminal electrically connected to the shift input terminal. The fourteenth switch has its gate and first terminal electrically connected to the second terminal of the thirteenth switch, and its second terminal electrically connected to the second node. The fifteenth switch has its gate electrically connected to the second terminal of the thirteenth switch, its first terminal electrically connected to the fourth clock terminal, and its second terminal electrically connected to the gate of the fourteenth switch through a second capacitor.

22. The display panel according to claim 21, characterized in that, The first driving module further includes a sixteenth switching transistor, the gate of which is electrically connected to the first node, the first terminal of which is electrically connected to the first power supply terminal, and the second terminal of which is electrically connected to the second terminal of the fifteenth switching transistor.

23. The display panel according to claim 15, characterized in that, The first control unit includes: The seventeenth switching transistor has its gate electrically connected to the shift input terminal, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the third clock terminal through a third capacitor. The eighteenth switching transistor has its gate electrically connected to the second terminal of the seventeenth switching transistor, its first terminal electrically connected to the third clock terminal, and its second terminal electrically connected to the first node. The nineteenth switching transistor has its gate electrically connected to the second node, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the first node. The second output module responds to the first level of the third node by outputting the voltage of the first power supply terminal to the second terminal, and responds to the first level of the fourth node by outputting the voltage of the first clock terminal to the second terminal; The second driving module includes a fifth switching transistor, the gate of which is electrically connected to the second clock terminal and the second terminal is electrically connected to the fourth node; Wherein, the first terminal of the fifth switch in the i-th stage shift unit is electrically connected to the second terminal of the (i-1)-th stage shift unit. For the same shift unit, during the time period when the third node is at the second level, the second terminal connected to the fifth switch outputs a first level, and the first level overlaps with the first level provided by the second clock terminal connected to the fifth switch. The third clock terminal and the second clock terminal are electrically connected to the same first signal pin.

24. The display panel according to claim 15, characterized in that, The first control unit includes: The seventeenth switching transistor has its gate electrically connected to the shift input terminal, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the fourth clock terminal through a third capacitor. The eighteenth switch has its gate electrically connected to the second terminal of the seventeenth switch, its first terminal electrically connected to the fourth clock terminal, and its second terminal electrically connected to the first node. The nineteenth switching transistor has its gate electrically connected to the second node, its first terminal electrically connected to the first power supply terminal, and its second terminal electrically connected to the first node.

25. The display panel according to claim 24, characterized in that, The second output module responds to the first level of the third node by outputting the voltage of the first power supply terminal to the second terminal, and responds to the first level of the fourth node by outputting the voltage of the first clock terminal to the second terminal; The second driving module includes a fifth switching transistor, the gate of which is electrically connected to the second clock terminal and the second terminal is electrically connected to the fourth node; Wherein, the first terminal of the fifth switch in the i-th stage shift unit is electrically connected to the second terminal of the (i-1)-th stage shift unit. For the same shift unit, during the time period when the third node is at the second level, the second terminal connected to the fifth switch outputs a first level, and the first level overlaps with the first level provided by the second clock terminal connected to the fifth switch. The third clock terminal and the second clock terminal are electrically connected to the same first signal pin, and the fourth clock terminal and the first clock terminal are electrically connected to the same second signal pin.

26. The display panel according to claim 15, characterized in that, The third node is electrically connected to the second node; Alternatively, the seventh switch is electrically connected to the second node through a first protection switch, the gate of the first protection switch is electrically connected to the second power supply terminal, and the third node is electrically connected to the second electrode of the seventh switch.

27. The display panel according to claim 15, characterized in that, The first output module includes: The twentieth switching transistor has its gate electrically connected to the first node, its first terminal electrically connected to the third clock terminal or the first power supply terminal, and its second terminal electrically connected to the output terminal. The 21st switching transistor has its gate electrically connected to the second node, its first terminal electrically connected to the second power supply terminal, and its second terminal electrically connected to the output terminal.

28. The display panel according to claim 2, characterized in that, The first output module includes the first terminal, and the first output module provides a signal to the first terminal.

29. The display panel according to claim 2, characterized in that, The first circuit includes a shift control sub-circuit and a partition control sub-circuit; The shift control sub-circuit includes a first driving module and a first output module. The first driving module includes a shift input terminal, and the first output module includes a shift output terminal. In two adjacent shift units, the shift output terminal of the previous shift unit is electrically connected to the shift input terminal of the next shift unit. The partition control sub-circuit includes the first terminal, and the partition control sub-circuit outputs a signal to the first terminal according to the partition control signal.

30. The display panel according to claim 29, characterized in that, The partition control sub-circuit includes: The 22nd switching transistor has its gate electrically connected to the first node, its first electrode electrically connected to the partition control terminal, and its second electrode electrically connected to the first terminal. The 23rd switching transistor has its gate electrically connected to the second node, its first terminal electrically connected to the second power supply terminal, and its second terminal electrically connected to the first terminal.

31. The display panel according to claim 30, characterized in that, The first output module responds to the voltage of the first node and outputs the signal at the third clock terminal; The display panel includes a first partition and a second partition; In the first display mode, the first partition and the second partition have the same driving frequency, and the level of the signal provided by the partition control terminal is consistent with the level of the signal provided by the third clock terminal. In the second display mode, the driving frequency of the second partition is lower than that of the first partition. In some frames, when driving the second partition, the partition control terminal provides a level that controls the first transistor to turn off.

32. The display panel according to claim 30, characterized in that, The first output module responds to the voltage of the first node and outputs the signal from the first power supply terminal; The display panel includes a first partition and a second partition; In the first display mode, the first partition and the second partition have the same driving frequency, and the partition control terminal provides the level to control the first transistor to turn on; In the second display mode, the driving frequency of the second partition is lower than that of the first partition. In some frames, when driving the second partition, the partition control terminal provides a level that controls the first transistor to turn off.

33. The display panel according to claim 30, characterized in that, The partition control sub-circuit includes a third drive module and a third output module; The third output module responds to the voltage of the fifth node by outputting a level that controls the first transistor to turn on to the first terminal, and responds to the voltage of the second node by outputting a level that controls the first transistor to turn off to the first terminal. The third driving module includes a twenty-fourth switching transistor and a second control unit; wherein, the gate of the twenty-fourth switching transistor is electrically connected to the shift control sub-circuit, the first terminal is electrically connected to the second power supply terminal, and the second terminal is electrically connected to the fifth node, and the gate of the twenty-fourth switching transistor and the signal level of the second node are consistent for at least a portion of the time period; the second control unit is electrically connected to the partition control terminal and the first driving module, and the second control unit controls the signal of the fifth node.

34. The display panel according to claim 33, characterized in that, The second control unit includes: The 25th switching transistor has its gate electrically connected to the partition control terminal, its first electrode electrically connected to the first node, and its second electrode electrically connected to the fifth node.

35. The display panel according to claim 34, characterized in that, The shift register includes at least two cascaded cell groups, each cell group including a plurality of cascaded shift cells; In two adjacent unit groups, the partition control terminal of the shift unit in one unit group is electrically connected to the first control line, and the partition control terminal of the shift unit in the other unit group is electrically connected to the second control line.

36. The display panel according to claim 33, characterized in that, The second control unit includes: The 26th switch has its gate electrically connected to the shift control sub-circuit and its first terminal electrically connected to the partition control terminal. For at least a portion of the time, the gate of the 26th switch and the signal level of the second node are consistent. The gate of the 27th switch is electrically connected to the second terminal of the 26th switch, the first terminal is electrically connected to the first node, and the second terminal is electrically connected to the fifth node.

37. The display panel according to claim 36, characterized in that, The gate of the 26th switch is electrically connected to the second node, or the gate of the 26th switch is electrically connected to the shift output terminal.

38. The display panel according to claim 33, characterized in that, The gate of the 24th switch is electrically connected to the 2nd node.

39. The display panel according to claim 29, characterized in that, The partition control sub-circuit includes a third drive module and a third output module; The third output module responds to the first level of the fifth node by outputting a level that controls the first transistor to be turned on to the first terminal, and responds to the voltage of the second node by outputting a level that controls the first transistor to be turned off to the first terminal. The first driving module includes a 28th switching transistor and a third control unit; the gate of the 28th switching transistor is electrically connected to the shift control sub-circuit, and the first electrode is electrically connected to the partition control terminal. For at least a portion of the time period, the gate of the 28th switching transistor is consistent with the signal level of the second node; the control terminal of the third control unit is electrically connected to the second electrode of the 28th switching transistor, and the third control unit provides a second level to the fifth node when it is turned on.

40. The display panel according to claim 39, characterized in that, The second control unit includes a twenty-ninth switching transistor and a thirtieth switching transistor, wherein the twenty-ninth switching transistor is an N-type transistor and the thirtieth switching transistor is a P-type transistor; The gates of the 29th and 30th switching transistors are both electrically connected to the second terminal of the 28th switching transistor, and the second terminals of the 29th and 30th switching transistors are both electrically connected to the fifth node. The first terminal of the 29th switch is electrically connected to the first node, and the first terminal of the 30th switch is electrically connected to the first power supply terminal; or, the first terminal of the 29th switch is electrically connected to the first power supply terminal, and the first terminal of the 30th switch is electrically connected to the first node.

41. The display panel according to claim 39, characterized in that, The gate of the 28th switch is electrically connected to the shift output terminal or the second node.

42. The display panel according to claim 1, characterized in that, The pixel circuit also includes a driving transistor; The first transistor includes a gate reset transistor and a threshold compensation transistor, both of which are N-type transistors. The gate of the gate reset transistor is electrically connected to a first scan line, its first terminal is electrically connected to a first reset line, and its second terminal is electrically connected to the gate of the driving transistor. The gate of the threshold compensation transistor is electrically connected to a second scan line, its first terminal is electrically connected to the second terminal of the driving transistor, and its second terminal is electrically connected to the gate of the driving transistor. The second transistor includes a data writing transistor, which is a P-type transistor. The gate of the data writing transistor is electrically connected to the third scan line, the first terminal is electrically connected to the data line, and the second terminal is electrically connected to the first terminal of the driving transistor. At least a portion of the first end of the shifting unit is electrically connected to the first scan line and / or the second scan line, and at least a portion of the second end of the shifting unit is electrically connected to the third scan line.

43. The display panel according to claim 42, characterized in that, The shift register includes a first shift register, wherein the first end of the shift unit in the first shift register is electrically connected to the second scan line, and the second end of the shift unit in the first shift register is electrically connected to the third scan line; The shift register further includes a second shift register, wherein the first end of the shift unit in the second shift register is electrically connected to the first scan line, and the second end of a portion of the shift units in the second shift register is electrically connected to the third scan line; The shifting unit includes m second ends, where m ≥ 2; The pixel circuit includes a plurality of circuit groups arranged along a first direction, the circuit group includes m circuit rows arranged along the first direction, and the circuit row includes a plurality of pixel circuits arranged along a second direction, wherein the first direction intersects the second direction; In the first shift register, the m second terminals of the shift unit of the a1th stage are respectively electrically connected to the third scan lines corresponding to the m circuit rows in the a1th circuit group, and the first terminal of the shift unit of the a1th stage is electrically connected to the second scan line corresponding to the a1th circuit group, where a1≥1; In the second shift register, the m second terminals of the shift unit of the a2th stage are respectively electrically connected to the third scan lines corresponding to the m circuit rows in the a1th circuit group, and the first terminal of the shift unit of the a2th stage is electrically connected to the first scan line corresponding to the a3th circuit group, where a2 > a1 and a3 > a1.

44. The display panel according to claim 42, characterized in that, The shift register includes a third shift register, wherein the first end of the shift unit in the third shift register is electrically connected to the first scan line and the second scan line, and the second end of a portion of the shift units in the third shift register is electrically connected to the third scan line and the second scan line; The shifting unit includes m second ends, where m ≥ 2; The pixel circuit includes a plurality of circuit groups arranged along a first direction, the circuit group includes m circuit rows arranged along the first direction, and the circuit row includes a plurality of pixel circuits arranged along a second direction, wherein the first direction intersects the second direction; Wherein, for the b-th circuit group, the third scan lines corresponding to the m circuit rows are respectively electrically connected to the m second terminals of the shift unit of the c1-th stage in the third shift register, the corresponding second scan lines are electrically connected to the first terminals of the shift unit of the c1-th stage in the third shift register, and the corresponding first scan lines are electrically connected to the first terminals of the shift unit of the c2-th stage in the third shift register, b≥1, c1>b, c2<c1.

45. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 44.

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