Microsecond time display device
By designing a microsecond-level time display device and utilizing an FPGA control unit and dot matrix display lights, microsecond-level time display was achieved, solving the problem of inconsistent frame times in high-speed shooting and improving the accuracy of image intersection calculation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ROCKETECH TECH CORP LTD
- Filing Date
- 2023-10-12
- Publication Date
- 2026-06-23
AI Technical Summary
The lack of microsecond-level time display devices in existing technologies leads to inconsistent frame times during high-speed shooting, resulting in significant intersection errors.
Design a microsecond-level time display device, including an FPGA control device and a display device. Use a PLL module for frequency division, and combine D flip-flops and shift registers to drive dot matrix display lamps to achieve microsecond-level time display.
By accurately providing absolute time at the microsecond level, errors in image intersection calculations are reduced, thereby improving the accuracy of image processing.
Smart Images
Figure CN117348371B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of time display technology, and more particularly to a microsecond-level time display device. Background Technology
[0002] Today, the demand for high-speed measurement and photography using binoculars, multi-view cameras, and multiple fields of view is increasing. High-speed measurement cameras are used for spatial positioning and measurement of high-speed or instantaneous bursts of motion. High-speed photography can capture thousands or even tens of thousands of frames per second, with frame intervals on the order of tens to hundreds of microseconds. This requires extremely precise recording of the timing of actions. When performing image intersection calculations, it is necessary to process photos taken at the same time. If the shooting is not synchronized, resulting in inconsistent frame times, a large intersection error will inevitably occur. Therefore, ensuring that the synchronization accuracy of the shooting time of each frame in binocular or multi-view photography reaches the microsecond level or even higher is an urgent requirement.
[0003] If absolute time with microsecond precision can be displayed on the screen during the shooting process, providing absolute time information and synchronization reference information for image intersection calculation, the error of the intersection calculation can be reduced.
[0004] Therefore, there is an urgent need to provide a microsecond-level time display device that can provide absolute time with accuracy at the microsecond level.
[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The main objective of this invention is to overcome the problem of the lack of microsecond-level time display devices and to provide a microsecond-level time display device that can accurately provide absolute time with an accuracy at the microsecond level.
[0007] To achieve the above objectives, the first aspect of the present invention provides a microsecond-level time display device, comprising: an FPGA control device and a display device;
[0008] The FPGA control device includes a PLL module, which includes a 1MHz main frequency output terminal, a 1 / 32MHz frequency divider output terminal and a 1 / 1024MHz frequency divider output terminal;
[0009] The display device includes a microsecond display module, which comprises more than 32 unit modules, each unit module including a D flip-flop, a shift register, and 32 display lamp components;
[0010] Each D flip-flop includes a signal input terminal, a signal output terminal, and a clock enable terminal;
[0011] Each shift register includes a signal input terminal, 32 signal output terminals, and a clock enable terminal;
[0012] The 1MHz main frequency output terminal is connected to the clock enable terminal of each D flip-flop;
[0013] The 1 / 32MHz divider output is connected to the clock enable terminal of each shift register;
[0014] The 1 / 1024MHz frequency divider output is connected to the signal input of the D flip-flop in the first unit module, and the signal inputs of the D flip-flops in other unit modules are connected to the signal outputs of the D flip-flops in the unit module above them; the signal outputs of the D flip-flops are connected to the signal inputs of the shift register in the same unit module.
[0015] Each indicator light assembly is connected to the signal output of a shift register.
[0016] According to an exemplary embodiment of the present invention, the display lamp assembly includes a display lamp and a driving circuit for the display lamp; the display device employs a dot matrix display lamp, which includes 32 rows of display lamps, with each row containing 32 or more display lamps.
[0017] In a preferred embodiment, the number of indicator lights in each row is 32.
[0018] According to an exemplary embodiment of the present invention, each column of indicator lights corresponds to 32 indicator lights in a unit module.
[0019] According to an exemplary embodiment of the present invention, each unit module further includes 32 buffer circuits, each buffer circuit being disposed between the signal output terminal of a shift register and an indicator light.
[0020] According to an exemplary embodiment of the present invention, the FPGA control device further includes a precision counting module; the display device further includes a millisecond display module; the precision counting module accumulates data through a timer, incrementing by 1 every 1 millisecond, and outputs the result to the millisecond display module.
[0021] According to an exemplary embodiment of the present invention, the millisecond display module includes a binary lamp or binary digital display unit with more than 10 bits.
[0022] According to an exemplary embodiment of the present invention, the FPGA control device further includes a PPS second pulse output terminal; the D flip-flop further includes a reset signal terminal, and the shift register further includes a reset signal terminal; the PPS second pulse output terminal is connected to the reset signal terminal of the D flip-flop and the reset signal terminal of the shift register.
[0023] According to an exemplary embodiment of the present invention, the microsecond-level time display device further includes a GNSS receiver, which is used to provide absolute time information and PPS second pulse information to the FPGA control device.
[0024] According to an exemplary embodiment of the present invention, the GNSS receiving device includes a GNSS multi-frequency receiving antenna and a PPS second pulse generator, wherein the GNSS multi-frequency receiving antenna is used to search for satellites and obtain satellite navigation time; the FPGA control device further includes a PPS second pulse input terminal, wherein the PPS second pulse generator is connected to the PPS second pulse input terminal.
[0025] According to an exemplary embodiment of the present invention, the display device further includes a second-level display module, which is used to display year, month, day, tens, minutes, and seconds; the FPGA control device further includes a second-level time processing module, which is used to receive absolute time information from the GNSS receiver and provide it to the second-level display module.
[0026] The advantages of this invention are that it displays time in decimal (seconds and above), milliseconds in 10-bit binary, and microseconds in a dot matrix format with more than 1000 dots. Through the combination of D flip-flops and shift registers, indicator lights are illuminated, with the number of illuminated dots corresponding to the number of microseconds elapsed within one millisecond. By capturing microsecond-level time information with a camera, the absolute time can be clearly seen at a glance, accurate to the microsecond level. This reduces errors in image intersection calculations and improves the accuracy of image processing. Attached Figure Description
[0027] The above and other objects, features, and advantages of this application will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings. The drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0028] Figure 1 A schematic diagram of a microsecond-level time display device is shown.
[0029] Figure 2 The schematic diagram illustrates the structure of the unit module.
[0030] Figure 3 The diagram illustrates the display method of the display device. Detailed Implementation
[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.
[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0034] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0035] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this application. As used herein, the term "and / or" includes all combinations of any one and more of the associated listed items.
[0036] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.
[0037] According to a first specific embodiment of the present invention, the present invention provides a microsecond-level display device, such as... Figure 1 As shown, there is a GNSS receiver, an FPGA control unit, and a display unit.
[0038] The GNSS receiver provides absolute time information and PPS (Positive Time Stamp) information to the FPGA control unit. The GNSS receiver includes a GNSS multi-frequency receiving antenna, a PPS second pulse generator, and a TXCO crystal oscillator. The GNSS multi-frequency receiving antenna searches for satellites, acquires satellite navigation time, and sends it to the second-level time processing module of the FPGA control unit. The GNSS multi-frequency receiving antenna ensures the quantity and quality of satellite searches, providing highly reliable, accurate, and stable real-time timing performance. The TXCO crystal oscillator provides a stable crystal signal to the GNSS receiver, enabling the output PPS to achieve stable nanosecond-level accuracy. The PPS second pulse generator is connected to the PPS second pulse input terminal of the FPGA control unit to provide the PPS second pulse to the FPGA control unit.
[0039] The FPGA control unit includes a PLL module, a PPS second pulse input terminal, a PPS second pulse output terminal, a second-level time processing module, a precision counting module, and an OCXO crystal oscillator. The PLL module provides microsecond data, i.e., it is used for frequency division to generate pulses at frequencies of 1MHz, 1 / 32MHz, and 1 / 1024MHz. The PLL module includes a 1MHz main frequency output terminal, a 1 / 32MHz divider output terminal, and a 1 / 1024MHz divider output terminal. The PPS second pulse output module provides second pulses to the display device, enabling the timing of milliseconds and microseconds to be reset at predetermined intervals. The precision counting module accumulates data using a timer, incrementing by 1 every millisecond and outputting the result to the millisecond display module. The second-level time processing module receives absolute time information from the GNSS receiver and provides it to the second-level display module. The OCXO crystal oscillator enables a reference frequency accuracy of ±0.5ppm, further enhancing the accuracy and synchronization of the entire system's clock signal. The entire FPGA control device performs clock and timing signal processing under a precise clock system. The edges of each frequency divider clock, frequency multiplier clock signal and PPS trigger edge are strictly aligned, so that the accuracy is maintained at the same level as the standard PPS.
[0040] The display device includes second-level display modules, millisecond-level display modules, and microsecond-level display modules. For example... Figure 3 As shown, the top is a second-level display module, displaying year, month, day, tens, minutes, and seconds in decimal; the lower left is a millisecond display module, which includes more than 10 binary LEDs or binary digit display units, displaying milliseconds in binary, capable of displaying 2 to the power of 10, or 1024 digits, but only 1000 digits are needed to display milliseconds; the lower right is a microsecond display module, with a 32×32 dot matrix of LEDs, which are the display lights for the microsecond display module. One column corresponds to one unit module, and there can be more than 32 columns, as long as there are more than 1000 LEDs. A 32×32 dot matrix is preferred, and LEDs are preferred for the display lights. The number of LEDs that are lit is consistent with the number of microseconds.
[0041] Specifically, such as Figure 2 As shown, the microsecond display module includes more than 32 unit modules, each of which includes a D flip-flop, a shift register, 32 buffer circuits, and 32 display lamp components.
[0042] Each D flip-flop includes signal input terminal 1, signal output terminal 2, clock enable terminal 3, and reset signal terminal 4.
[0043] Each shift register includes a signal input terminal 5, 32 signal output terminals 6, a reset signal terminal 8, and a clock enable terminal 7.
[0044] The 1MHz main frequency output terminal is connected to the clock enable terminal 3 of each D flip-flop.
[0045] The 1 / 32MHz divider output is connected to the clock enable pin 7 of each shift register.
[0046] The 1 / 1024MHz divider output is connected to signal input 1 of the D flip-flop in the first unit module. Signal input 1 of the D flip-flops in other unit modules is connected to signal output 2 of the D flip-flop in the previous unit module. Signal output 2 of the D flip-flops is connected to signal input 5 of the shift register in the same unit module.
[0047] Each indicator light assembly includes an indicator light and its driving circuit. The driving circuit of the indicator light assembly is connected to the signal output terminal 6 of a shift register, and the driving circuit drives the indicator light to light up. Each buffer circuit is disposed between the signal output terminal 6 of a shift register and an indicator light assembly.
[0048] The PPS second pulse output terminal is connected to the reset signal terminal 4 of the D flip-flop and the reset signal terminal 8 of the shift register.
[0049] Specifically, every 1 microsecond, one LED is lit and remains lit for 1 PPS. With the coordination of all clocks and signals, the dot matrix LEDs will start lighting up from the first LED of the first unit module. After 1 microsecond, the first LED of the second unit module will light up. After 32 microseconds, the first LED of all unit modules will light up. After 33 microseconds, the second LED of the first unit module will light up. Then, after 1 microsecond, the second LED of the second unit module will light up. In this way, the 32x32 dot matrix LEDs are lit up and held in sequence every 1 microsecond clock cycle until the 1 PPS reset signal arrives, at which point they all turn off and begin the next cycle.
[0050] The 1PPS signal is input to the FPGA. The FPGA uses the rising edge of 1PPS to force synchronization and alignment of all clock signals (D flip-flops, shift registers, and internal clock system). The cumulative error of all signals will be cleared to zero within 1 second. Within 1 second, the FPGA uses the OCXO temperature-controlled crystal oscillator and PLL to accurately divide the frequency and output. The OCXO error does not exceed ±0.5ppm, and its cumulative error does not exceed 0.5 microseconds within 1 second. The system can achieve a timing accuracy of 1 microsecond.
[0051] By displaying time with microsecond precision on a display device, the multi-view camera captures the time in the image during shooting, thus obtaining the time when multiple high-speed cameras photographed the target object. By selecting images within a specified microsecond time range for intersection calculation, the selected time range can be reduced from the original hundreds of microseconds to 1 microsecond, greatly reducing the error.
[0052] The display device in this solution can also be set up in multi-scene shooting to ensure that the content shot in multiple scenes is synchronized.
[0053] Exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, arrangements, or implementations described herein; rather, the present invention is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.
Claims
1. A microsecond-level time display device, characterized in that, include: FPGA control and display devices; The FPGA control device includes a PLL module, which includes a 1MHz main frequency output terminal, a 1 / 32MHz frequency divider output terminal and a 1 / 1024MHz frequency divider output terminal; The display device includes a microsecond display module, which comprises more than 32 unit modules, each unit module including a D flip-flop, a shift register, and 32 display lamp components; Each D flip-flop includes a signal input terminal, a signal output terminal, and a clock enable terminal; Each shift register includes a signal input terminal, 32 signal output terminals, and a clock enable terminal; The 1MHz main frequency output terminal is connected to the clock enable terminal of each D flip-flop; The 1 / 32MHz divider output is connected to the clock enable terminal of each shift register; The 1 / 1024MHz frequency divider output is connected to the signal input of the D flip-flop in the first unit module, and the signal inputs of the D flip-flops in other unit modules are connected to the signal output of the D flip-flop in the previous unit module; the signal output of the D flip-flop is also connected to the signal input of the shift register in the same unit module. Each indicator light assembly is connected to the signal output of a shift register; The FPGA control device further includes a PPS second pulse output terminal; the D flip-flop further includes a reset signal terminal, and the shift register further includes a reset signal terminal; the PPS second pulse output terminal is connected to the reset signal terminal of the D flip-flop and the reset signal terminal of the shift register. It also includes a GNSS receiver, which is used to provide absolute time information and PPS second pulse information to the FPGA control device; The display device shows the time with microsecond precision. When the multi-view camera is shooting, it captures the time into the image, so the time when multiple high-speed cameras shoot the target object can be obtained. The images are selected within the microsecond time range for intersection calculation.
2. The microsecond-level time display device according to claim 1, characterized in that, Each display light assembly includes a display light and a driving circuit for the display light; the display device uses a dot matrix display light, which includes 32 rows of display lights, with each row containing more than 32 display lights.
3. The microsecond-level time display device according to claim 2, characterized in that, Each column of indicator lights corresponds to 32 indicator lights in one unit module.
4. The microsecond-level time display device according to claim 1, characterized in that, Each unit module also includes 32 buffer circuits, each of which is located between the signal output of a shift register and an indicator light.
5. The microsecond-level time display device according to claim 1, characterized in that, The FPGA control device also includes a precision counting module; the display device also includes a millisecond display module; the precision counting module accumulates data through a timer, incrementing by 1 every millisecond and outputting the result to the millisecond display module.
6. The microsecond-level time display device according to claim 5, characterized in that, The millisecond display module includes a binary LED or binary digital display unit with more than 10 bits.
7. The microsecond-level time display device according to claim 1, characterized in that, The GNSS receiving device includes a GNSS multi-frequency receiving antenna and a PPS second pulse generator. The GNSS multi-frequency receiving antenna is used to search for satellites and obtain the time for satellite navigation. The FPGA control device also includes a PPS second pulse input terminal, which is connected to the PPS second pulse generator.
8. The microsecond-level time display device according to claim 1, characterized in that, The display device further includes a second-level display module, which is used to display year, month, day, hour, minute, and second; the FPGA control device further includes a second-level time processing module, which is used to receive absolute time information from the GNSS receiver and provide it to the second-level display module.