A pulse width modulation method for pulse spreading

Abstract

The application belongs to the technical field of LED display and relates to a pulse width modulation method for dispersing pulses, comprising the following steps: obtaining N-bit PWM gray scale data; inputting the N-bit PWM gray scale data into one end of an adder; dividing the output end of the adder into an M+1-bit high bit group and an N-M-bit low bit group; feeding back the N-M-bit low bit group data of the output end of the adder to the other end of the adder; taking the M+1-bit high bit group data of the output end of the adder as the input of a sub-PWM signal generation module to generate a sub-PWM signal after the pulses are dispersed; wherein N is a natural number, is the gray scale bit number of an input PWM signal, M is a natural number smaller than N, and is the gray scale bit number of the sub-PWM signal after being dispersed. The structure is simple and reliable; the complex mantissa compensation algorithm is avoided; the SPWM sub-period has good uniformity, which is beneficial to improving the LED display effect.

Description

Technical Field

[0001] This invention relates to the field of LED display technology, and more specifically, to a pulse width modulation method for scattering pulses. Background Technology

[0002] In LED display applications, digital pulse width modulation (PWM) signals are generally used to control the display brightness of LED pixels. Limited by the system's maximum clock frequency, if the number of grayscale levels displayed by a pixel is very high (e.g., 65,536 grayscale levels for 16-bit data), the corresponding refresh rate will be very low, with the refresh cycle being the number of grayscale levels multiplied by the clock cycle. A low refresh rate affects the display of high dynamic range images and causes a noticeable flicker, which inevitably impacts display quality, causes eye discomfort, and reduces user satisfaction. Summary of the Invention

[0003] The technical problem this invention aims to solve is that when the grayscale number of pixels is high and the refresh rate is low, it affects the display of high dynamic range images and causes a flickering effect that is perceptible to the human eye. This inevitably affects the display effect, causes discomfort to the human eye, and reduces user satisfaction. To address the above-mentioned deficiencies of existing technologies, this invention provides a pulse width modulation method for scattering pulses, comprising the following steps:

[0004] Obtain N-bit PWM grayscale data;

[0005] Input N-bit PWM grayscale data to one end of the adder, divide the output of the adder into M+1 high-bit combinations and NM low-bit groups, and feed back the NM low-bit group data from the output of the adder to the other end of the adder.

[0006] The M+1 high-order bits of the adder's output are used as the input to the sub-PWM signal generation module to generate the scattered pulse sub-PWM signal.

[0007] Where N is a natural number, representing the number of gray levels in the input PWM signal, and M is a natural number less than N, representing the number of gray levels in the shuffled sub-PWM signal.

[0008] Preferably, the step of acquiring N-bit PWM grayscale data includes:

[0009] Acquire data;

[0010] The data is processed to obtain N-bit PWM grayscale data.

[0011] Preferably, the PWM signal includes a grayscale signal for black and white display.

[0012] Preferably, the PWM signal includes: red, green, and blue brightness signals for color display.

[0013] Preferably, the sub-PWM signal generation module includes a receiving module and an output module.

[0014] Preferably, the step of processing the data to obtain N-bit PWM grayscale data specifically includes:

[0015] The chromaticity data is decomposed into RGB data, and the RGB data is converted into the required N bits by truncation or padding.

[0016] The luminance signal is extracted from the chrominance signal and adjusted to N bits by truncation or padding.

[0017] Preferably, the receiving module is used to receive the high-order bit data of the M+1 bits from the adder.

[0018] Preferably, the output module is used to output high and low levels.

[0019] Preferably, the sub-PWM signal after the scattering pulse refers to the high level and the low level.

[0020] Preferably, the value of N is determined by the input PWM grayscale data, and the value of M is determined by the clock frequency, the number of bits of the input PWM grayscale data, and the target refresh frequency after scattering.

[0021] The pulse width modulation method for scattering pulses according to the present invention has the following advantages: First, N-bit PWM grayscale data is acquired; then, the N-bit PWM grayscale data is input to one end of an adder, and the output of the adder is divided into an M+1-bit high-order group and an NM-bit low-order group. The NM-bit low-order group data from the adder's output is fed back to the other end of the adder; then, the M+1-bit high-order group data from the adder's output is used as the input to a sub-PWM signal generation module to generate a scattering pulse sub-PWM signal; where N is a natural number representing the number of grayscale bits in the input PWM signal, and M is a natural number less than N representing the number of grayscale bits in the scattering sub-PWM signal; the structure is simple and reliable; complex tail-number compensation algorithms are avoided; the SPWM sub-cycle has excellent uniformity, which is beneficial for improving the LED display effect. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort. The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0023] Figure 1 This is a flowchart of the pulse width modulation method for scattering pulses according to the present invention;

[0024] Figure 2 This is a schematic diagram of PWM and SPWM signals in the existing technology;

[0025] Figure 3 This is a schematic diagram of the mathematical model for mantissa compensation used in the existing technology for converting PWM signals to SPWM signals;

[0026] Figure 4 This is a schematic diagram of the PWM signal to SPWM signal conversion used in the pulse width modulation method for scattering pulses in this invention.

[0027] Figure 5 This is a schematic diagram of the mathematical model for converting PWM signals to SPWM signals used in the pulse width modulation method for scattering pulses in this invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0030] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0031] PWM (Pulse Width Modulation) is an analog control method that modulates the bias of the base of a transistor or the gate of a MOSFET according to changes in the load, thereby altering the conduction time of the transistor or MOSFET and thus changing the output of a switching power supply. This method allows the power supply's output voltage to remain constant despite changes in operating conditions, making it a highly effective technique for controlling analog circuits using digital signals from a microprocessor. It is widely used in many fields, from measurement and communication to power control and conversion.

[0032] The basic principle of pulse width modulation (PWM) is as follows: the control method involves controlling the on / off state of the switching devices in the inverter circuit, resulting in a series of pulses with equal amplitude but inconsistent widths at the output. These pulses are used to replace a sine wave or the desired waveform. In other words, multiple pulses are generated within half a cycle of the output waveform, ensuring that the equivalent voltage of each pulse is a sine wave, resulting in a smooth output with fewer low-order harmonics. By modulating the width of each pulse according to certain rules, both the magnitude of the inverter circuit's output voltage and the output frequency can be changed.

[0033] An image can be defined as a two-dimensional function f(x,y), where x and y are spatial plane coordinates. At any pair of coordinate axes (x,y), the magnitude of f is called the intensity or gray level of the image at that point. In other words, gray level refers to the degree of lightness or darkness of the electromagnetic radiation intensity of ground features in a black-and-white image; it is a scale for classifying the spectral characteristics of ground features. Generally, gray level is defined as dividing the brightness variation between the brightest and darkest areas into several segments to facilitate corresponding screen brightness control for signal input.

[0034] Please see Figure 1 This is a flowchart of the pulse width modulation method for scattering pulses according to the present invention. Figure 1 As shown, the pulse width modulation method for scattering pulses provided in the first embodiment of the present invention includes the following steps:

[0035] S1. Obtain N-bit PWM grayscale data.

[0036] Figure 2 This is a schematic diagram of PWM and SPWM signals in existing technology. (Example:) Figure 2 As shown, Figure 2 This displays a 5-bit digital PWM signal. Its grayscale signal is represented by 5 bits of data. One PWM cycle requires 32 clock cycles, and the grayscale value indicates how many clock cycles the PWM signal is high within one PWM cycle. Figure 2The corresponding grayscale data is 21, indicating that within one PWM cycle, there are 21 clock cycles of high level and the remaining 11 clock cycles of low level. From Figure 2 As can be seen, with a constant clock frequency, the more bits of grayscale data there are, the longer the PWM period and the lower the refresh rate. To improve the refresh rate, the PWM pulse can be scattered, such as... Figure 2 The SPWM signal in the circuit is divided into 8 SPWM clock cycles (8*4CLK) within one PWM clock cycle (32CLK). Each SPWM clock cycle maintains a duty cycle that is as uniform as possible. Within the entire PWM cycle, the SPWM signal is high for 21 cycles and low for 11 cycles, consistent with the PWM signal, but its refresh rate is 8 times that of the PWM signal.

[0037] In some optional implementations of this embodiment, step S1, the step of obtaining N-bit PWM grayscale data, may further include the following steps:

[0038] S11, Obtain data.

[0039] In practical implementation, this can be achieved by receiving digital television signals, decoding the image data to obtain the RGB and luminance signals of the corresponding pixels, or by receiving and decoding digital image signals through digital audio-visual interfaces such as HDMI and DisplayPort to obtain the RGB and luminance signals of the corresponding pixels. Alternatively, an image sensor can acquire image information and generate the RGB and luminance signals of the corresponding pixel matrix. Another approach is to use a microprocessor to read image or video files, decode them to obtain the color or grayscale data of the pixels, or directly generate the RGB and luminance signals of the pixel matrix for the image display interface from the microprocessor.

[0040] S12. The data is processed to obtain N-bit PWM grayscale data.

[0041] The chromaticity data is decomposed into RGB data, and then converted to the required N bits by truncation or padding. Alternatively, the luminance signal is extracted from the chromaticity signal and adjusted to N bits by truncation or padding.

[0042] PWM grayscale data represents the brightness of each pixel. In some optional implementations of this embodiment, PWM grayscale data can be transmitted through the control circuitry of the system to obtain N-bit PWM grayscale data.

[0043] S2. Input N-bit PWM grayscale data to one end of the adder, divide the output of the adder into M+1 high-bit groups and NM low-bit groups, and feed back the NM low-bit group data from the output of the adder to the other end of the adder.

[0044] The adder is clock-controlled and its output is latched by a register to ensure that the result of the current adder operation remains unchanged until the next calculation. The NM low-order bits of the current calculation result can be correctly fed back to the input for the next addition calculation.

[0045] Still with Figure 2 The example shown illustrates a common method for breaking down a PWM signal into an SPWM signal. Figure 3 This is a schematic diagram of the mathematical model for mantissa compensation used in existing technologies for converting PWM signals to SPWM signals. For example... Figure 3 As shown, 21 is converted to binary as 10101. These 5 bits represent the grayscale value of the LED. To obtain an SPWM signal with an 8x refresh rate, the lower 3 bits of the original data are removed, and only the two highest bits, 10, are used as the basic grayscale value for SPWM. The SPWM period is 4 clock cycles, and the duty cycle of the basic grayscale is 2 clock cycles (binary grayscale value 10). The duty cycle of the basic grayscale contributes 16 clock cycles of pulse width within 8 SPWM cycles.

[0046] The original PWM pulse width is 5 clock cycles shorter than the original PWM data, and these 5 clock cycles correspond to the lower three bits of the PWM grayscale data, which are 101. To obtain the same duty cycle as the original PWM data, these 5 clock cycles need to be evenly padded across the 8 SPWM cycles.

[0047] In the existing compensation method, the pulse widths for each SPWM cycle are: 3, 2, 3, 2, 3, 2, 3, 3, as follows: Figure 2 The SPWM signal is shown below. The input is N-bit grayscale data, f clk / 2 N The refresh rate of the grayscale data is defined as follows: The grayscale data is divided into M bits of high-order bits D[N-1:NM], which serve as the basic SPWM pulse width; and NM bits of mantissa D[NM-1:0], which are compensated into the SPWM. The NM bits of low-order data are input to the mantissa compensation algorithm module to compensate the mantissa as evenly as possible into each SPWM sub-cycle using a certain algorithm. Its output is 0 or 1, indicating whether a compensation pulse needs to be added in the current sub-cycle, respectively. The output of the mantissa compensation module is added to the basic SPWM pulse width to obtain the pulse width data DS[M:0] of the current sub-cycle. Considering the possibility of carry, the output of the adder is increased by one bit. This data is input to the "SPWM generation" module to generate the SPWM signal corresponding to the current sub-cycle. Currently, the PWM signal is broken down into SPWM signals based on the above method, but the mantissa compensation strategy varies in different implementations.

[0048] S3. Use the M+1 high-order bits of the adder's output as the input to the sub-PWM signal generation module to generate the sub-PWM signal after the pulses are scattered.

[0049] Figure 4 This is a schematic diagram illustrating the framework of the PWM signal to SPWM signal conversion method used in the pulse width modulation method for scattering pulses in this invention. (See diagram below.) Figure 4 As shown, in some optional implementations of this embodiment, the PWM signal may include, but is not limited to, grayscale signals for black and white display, or luminance signals of red, green, and blue for color display.

[0050] In some optional implementations of this embodiment, the sub-PWM signal generation module includes a receiving module and an output module. The receiving module is used to receive the high-order data of bit M+1 from the adder, which is based on the input value (0~2). M ), decided in the next 2 M The output should include a certain number of high-level cycles and a certain number of low-level cycles within each clock cycle. If the input data is n (0 ≤ n ≤ 2^n), then the output should contain the number of high-level cycles and low-level cycles. M If the sub-PWM signal generation module first outputs a high level for n clock cycles, then outputs 2... M -n clock cycles of low level. The output module outputs high and low levels. In some optional implementations of this embodiment, the sub-PWM signal after scattering the pulse refers to: the high level of the above n clock cycles and 2 M -n clock cycles of low level.

[0051] In some optional implementations of this embodiment, the sub-PWM signal after scattering the pulses refers to: the high level of the above n clock cycles and 2 M -n clock cycles of low level.

[0052] In some optional implementations of this embodiment, the two inputs of the adder have N bits and NM bits respectively. The NM bits of one of the inputs are less, so the implementation requires less resources than a general adder. The output is N+1 bits to include any possible carry.

[0053] From an application perspective, the optimal refresh rate for a display is around 2kHz, at which the human eye perceives no flicker. Higher refresh rates do not significantly improve display quality but instead increase power consumption. In some optional implementations of this embodiment, the value of N is determined by the input raw grayscale data. For example, if the input raw grayscale data is 8-bit, 10-bit, or 16-bit, then N will be 8, 10, or 16, respectively. The value of M can be determined based on the clock frequency, the number of bits in the input raw grayscale data, and the target refresh rate after scattering.

[0054] Figure 5 This is a schematic diagram of the mathematical model for converting a PWM signal to an SPWM signal used in the pulse width modulation method for scattering pulses in this invention. For example... Figure 5 As shown, the OUT signal is the result of setting the lower NM bits of the output DS[N:0] of the first adder to 0. Mathematically, this is equivalent to subtracting the value of NM LSBs from DS[N:0] (+E = -LSBs). Therefore, the higher M+1 bits of OUT are MSBs, and the lower bits are all 0. The lower bits DS[NM-1:0] of DS[N:0] are LSBs, and there is a clock delay when they are fed back to the input of the adder. The input-output relationship can be written as follows:

[0055] OUT = IN + E(1 – z) -1 ), where z represents the complex frequency symbol in the discrete domain.

[0056] Therefore, it can be seen that E (E = -LSBs) composed of LSBs is (1-z) -1 The high-pass filter removes OUT and IN, making them equal in the long run. Therefore, the average pulse width of the SPWM signal generated by MSBs is also equal to the pulse width of the PWM input.

[0057] The following example, using the previous input grayscale data of 21, illustrates the working process of this scheme, as shown in Table 1:

[0058] Table 1

[0059]

[0060]

[0061] Within one PWM cycle, the adder's input remains constant at 21. During the first addition, the feedback input is initialized to 0, resulting in an adder output of 21, with corresponding LSB and MSB of 5 and 2, respectively. During the second addition, the LSB from the first output is fed back to the adder's input, resulting in LSB and MSB of 2 and 3, respectively. This process continues, with the MSB values ​​for the eight additions being 2, 3, 2, 3, 3, 2, 3, 3. Using this MSB value as the duty cycle for the SPWM sub-cycle, the total high-level width is 21 clock cycles, perfectly matching the input grayscale data. Considering multiple consecutive PWM cycles, it can be seen that the uniformity of the sub-cycle distribution with values ​​of 2 and 3 is better than in the previous example.

[0062] The beneficial effects of this invention, through the design of the above embodiments, are as follows: First, N-bit PWM grayscale data is acquired; then, the N-bit PWM grayscale data is input to one end of an adder, and the output of the adder is divided into an M+1-bit high-order group and an NM-bit low-order group. The NM-bit low-order group data at the output of the adder is fed back to the other end of the adder; then, the M+1-bit high-order group data at the output of the adder is used as the input of a sub-PWM signal generation module to generate a scattered pulse sub-PWM signal; where N is a natural number representing the number of grayscale bits of the input PWM signal, and M is a natural number less than N representing the number of grayscale bits of the scattered sub-PWM signal; the structure is simple and reliable; complex tail-number compensation algorithms are avoided; the SPWM sub-cycle has good uniformity, which is beneficial to improving the effect of LED display.

[0063] This invention has been described with reference to specific embodiments, but those skilled in the art will understand that various changes and equivalent substitutions can be made without departing from the scope of the invention. Furthermore, numerous modifications can be made to this invention to suit specific applications without departing from its protection scope. Therefore, this invention is not limited to the specific embodiments disclosed herein, but includes all embodiments falling within the scope of the claims.

Claims

1. A pulse width modulation method for scattering pulses, characterized in that, Including the following steps: Obtain N-bit PWM grayscale data; Input N-bit PWM grayscale data to one end of the adder, divide the output of the adder into M+1 high-bit combinations and NM low-bit groups, and feed back the NM low-bit group data from the output of the adder to the other end of the adder. The M+1 high-order bits of the adder's output are used as the input to the sub-PWM signal generation module to generate the scattered pulse sub-PWM signal. Where N is a natural number, representing the number of gray levels in the input PWM signal, and M is a natural number less than N, representing the number of gray levels in the shuffled sub-PWM signal.

2. The pulse width modulation method for scattering pulses according to claim 1, characterized in that, The steps for obtaining N-bit PWM grayscale data include: Acquire data; The data is processed to obtain N-bit PWM grayscale data.

3. The pulse width modulation method for scattering pulses according to claim 1, characterized in that, The PWM signal includes a grayscale signal for black and white display.

4. The pulse width modulation method for scattering pulses according to claim 1, characterized in that, The PWM signal includes the brightness signals of red, green, and blue for color display.

5. The pulse width modulation method for scattering pulses according to claim 1, characterized in that, The sub-PWM signal generation module includes a receiving module and an output module.

6. The pulse width modulation method for scattering pulses according to claim 2, characterized in that, The step of processing the data to obtain N-bit PWM grayscale data specifically includes: The chromaticity data is decomposed into RGB data, and the RGB data is converted into the required N bits by truncation or padding. The luminance signal is extracted from the chrominance signal and adjusted to N bits by truncation or padding.

7. The pulse width modulation method for scattering pulses according to claim 5, characterized in that, The receiving module is used to receive the high-order data of the M+1 bits from the adder.

8. The pulse width modulation method for scattering pulses according to claim 5, characterized in that, The output module is used to output high and low levels.

9. The pulse width modulation method for scattering pulses according to claim 8, characterized in that, The sub-PWM signal after the pulse is broken refers to the high level and the low level.

10. The pulse width modulation method for scattering pulses according to any one of claims 1 to 9, characterized in that, The value of N is determined by the input PWM grayscale data, and the value of M is determined by the clock frequency, the number of bits of the input PWM grayscale data, and the target refresh frequency after scattering.

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