Control circuit and semiconductor memory

Abstract

This disclosure provides a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit is composed of at least one target transistor, the substrate of which is connected to the output of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode, where the transmission speed of the first speed mode is lower than that of the second speed mode. The bias switching circuit receives a target signal. If the target signal is enabled, it outputs a target bias voltage to increase the threshold voltage of the target transistor. The enabled state of the target signal indicates that the first logic gate circuit is in the first speed mode. Thus, while ensuring that the semiconductor performance meets the requirements, this control circuit can reduce the leakage current between the source and drain, achieving power saving.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a control circuit and a semiconductor memory. Background Technology

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. In order to obtain faster data transmission speeds, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] In Dynamic Random Access Memory (DRAM), the main concern is currently the leakage current of logic gate circuits, such as source / substrate leakage current, drain / substrate leakage current, source / drain leakage current, gate / substrate leakage current, etc. However, when the substrate voltage and source voltage are the same, the transistor's threshold voltage is low, the saturation current is large, and the speed is fast. In this case, the leakage current between the source and drain is relatively large, resulting in high power consumption. Summary of the Invention

[0004] This disclosure provides a control circuit and a semiconductor memory that, while ensuring that the semiconductor performance meets the requirements, can reduce the leakage current between the source and drain, thereby saving power consumption.

[0005] In a first aspect, embodiments of this disclosure provide a control circuit, which includes a bias switching circuit and a first logic gate circuit; wherein, the first logic gate circuit is composed of at least one target transistor, the substrate of the target transistor is connected to the output terminal of the bias switching circuit, the first logic gate circuit has a first speed mode and a second speed mode, the transmission speed of the first speed mode is lower than the transmission speed of the second speed mode; the bias switching circuit is used to receive a target signal, and if the target signal is in an enabled state, it outputs a target bias voltage to increase the threshold voltage of the target transistor, the enabled state of the target signal indicates that the first logic gate circuit is in the first speed mode.

[0006] In some embodiments, the bias switching circuit is further configured to output an initial bias voltage if the target signal is in an disabled state, so as to reduce the threshold voltage of the target transistor. The disabled state of the target signal indicates that the first logic gate circuit is in a second speed mode.

[0007] In some embodiments, the target transistor includes a PMOS transistor and / or an NMOS transistor.

[0008] In some embodiments, the bias switching circuit includes a first switching circuit and a second switching circuit; wherein, the first switching circuit is configured to receive a first bias signal; and when the first bias signal is in an enabled state, output a first target bias voltage corresponding to a first type of transistor; and when the first bias signal is in an disabled state, output a first initial bias voltage corresponding to a first type of transistor; the second switching circuit is configured to receive a second bias signal; and when the second bias signal is in an enabled state, output a second target bias voltage corresponding to a second type of transistor; and when the second bias signal is in an disabled state, output a second initial bias voltage corresponding to a second type of transistor.

[0009] In some embodiments, the first type of transistor is a PMOS transistor, the second type of transistor is an NMOS transistor, the first target bias voltage corresponding to the first type of transistor is higher than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is lower than the second initial bias voltage; or, the first type of transistor is an NMOS transistor, the second type of transistor is a PMOS transistor, the first target bias voltage corresponding to the first type of transistor is lower than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is higher than the second initial bias voltage.

[0010] In some embodiments, the first switching circuit includes a first NOT gate, a first transistor, and a second transistor; wherein the drain of the first transistor is connected to a first target bias voltage, and the drain of the second transistor is connected to a first initial bias voltage; the gate of the first transistor is connected to the input of the first NOT gate to receive a first bias signal; the gate of the second transistor is connected to the output of the first NOT gate; and the source of the first transistor is connected to the source of the second transistor to output the first target bias voltage when the first bias signal is enabled.

[0011] In some embodiments, the first switching circuit further includes a first selection circuit, and the first selection circuit includes multiple ports, with different ports corresponding to different first candidate bias voltages; wherein, the first selection circuit is used to receive a first selection signal, determine a target port according to the first selection signal, and determine the first candidate bias voltage corresponding to the target port as the first target bias voltage.

[0012] In some embodiments, the second switching circuit includes a second NOT gate, a third transistor, and a fourth transistor; wherein the source of the third transistor is connected to a second target bias voltage, and the source of the fourth transistor is connected to a second initial bias voltage; the gate of the third transistor is connected to the input of the second NOT gate for receiving a second bias signal; the gate of the fourth transistor is connected to the output of the second NOT gate; and the drain of the third transistor is connected to the drain of the fourth transistor for outputting a second target bias voltage when the second bias signal is enabled.

[0013] In some embodiments, the second switching circuit further includes a second selection circuit, and the second selection circuit includes multiple ports, with different ports corresponding to different second candidate bias voltages; wherein, the second selection circuit is used to receive a second selection signal, determine a target port according to the second selection signal, and determine the second candidate bias voltage corresponding to the target port as the second target bias voltage.

[0014] In some embodiments, the first type of transistor is a PMOS transistor, the second type of transistor is an NMOS transistor, the first candidate bias voltage corresponding to each port is greater than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is less than the second initial bias voltage; or, the first type of transistor is an NMOS transistor, the second type of transistor is a PMOS transistor, the first candidate bias voltage corresponding to each port is less than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is greater than the second initial bias voltage.

[0015] In some embodiments, the control circuit includes a plurality of first-type transistors and a plurality of second-type transistors, and the number of first switching circuits and the number of second switching circuits are both plurality of; wherein, the bias switching circuit is further configured to provide a first output bias voltage to the plurality of first-type transistors through the plurality of first switching circuits, and to provide a second output bias voltage to the plurality of second-type transistors through the plurality of second switching circuits.

[0016] In some embodiments, the control circuit further includes a control module; wherein the control module is configured to control the target signal to be in an enabled state when the first logic gate circuit is in a first speed mode and the leakage current of the target transistor is greater than or equal to a preset value; and to control the target signal to be in an disabled state when the first logic gate circuit is in a second speed mode, or when the first logic gate circuit is in a first speed mode and the leakage current of the target transistor is less than a preset value.

[0017] In some embodiments, the control circuit further includes a switching module and a second logic gate circuit; wherein, the switching module is used to control the switching switch inside the switching module to select the first logic gate circuit when the transmission speed meets the first speed mode or the second speed mode; or, to control the switching switch inside the switching module to select the second logic gate circuit when the transmission speed meets the third speed mode; the second logic gate circuit is composed of at least one target transistor, the substrate of the target transistor is connected to the output terminal of the bias switching circuit, and is used to receive the initial bias voltage output by the bias switching circuit to reduce the threshold voltage of the target transistor; wherein, the second logic gate circuit has a third speed mode, and the transmission speed corresponding to the second speed mode is lower than the transmission speed corresponding to the third speed mode.

[0018] In a second aspect, embodiments of this disclosure provide a semiconductor memory that includes the control circuitry described in any one of the first aspects.

[0019] This disclosure provides a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit is composed of at least one target transistor, the substrate of which is connected to the output of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode, where the transmission speed of the first speed mode is lower than that of the second speed mode. The bias switching circuit receives a target signal. If the target signal is enabled, it outputs a target bias voltage to increase the threshold voltage of the target transistor. The enabled state of the target signal indicates that the first logic gate circuit is in the first speed mode. Thus, while ensuring that the semiconductor performance meets requirements, the control circuit receives the target signal through the bias switching circuit to switch the bias voltage, thereby increasing the threshold voltage of the target transistor, reducing the saturation current, and simultaneously reducing the leakage current between the source and drain, achieving the purpose of saving power consumption. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of an LP DDR memory device;

[0021] Figure 2 This is a schematic diagram of the structure of a NOT gate device;

[0022] Figure 3 This is a schematic diagram of the leakage current distribution of an NMOS transistor.

[0023] Figure 4 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 1 ;

[0024] Figure 5 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 2 ;

[0025] Figure 6A A schematic diagram of the composition structure of a first switching circuit provided in an embodiment of this disclosure. Figure 1 ;

[0026] Figure 6B A schematic diagram of the composition structure of a first switching circuit provided in an embodiment of this disclosure. Figure 2 ;

[0027] Figure 7A A schematic diagram of the composition structure of a second switching circuit provided in an embodiment of this disclosure. Figure 1 ;

[0028] Figure 7B A schematic diagram of the composition structure of a second switching circuit provided in an embodiment of this disclosure. Figure 2 ;

[0029] Figure 8 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 3 ;

[0030] Figure 9 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 4 ;

[0031] Figure 10 This is a signal timing diagram of a control circuit provided in an embodiment of the present disclosure;

[0032] Figure 11 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0033] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0035] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0036] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0037] It should also be noted that the high and low levels used for signals in the embodiments of this disclosure refer to the logic levels of the signals. A signal having a high level is different from having a low level. For example, a high level may correspond to a signal having a first voltage, while a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. Furthermore, the logic level of a signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0038] For semiconductor memories, a power supply voltage can be applied to the respective logic circuits configuring the semiconductor memory via a control circuit, thereby allowing the semiconductor memory to perform various operations. Depending on the operating frequency of the semiconductor memory, the semiconductor memory can selectively use at least one of a high power supply voltage and a low power supply voltage. This selective use of an appropriate power supply voltage from two or more power supply voltages according to the operating frequency of the semiconductor memory is commonly referred to as the Dynamic Voltage Frequency Scaling Core (DVFSC) mode.

[0039] Specifically, the semiconductor memory can execute DVFSC mode, determining a first speed mode and a second speed mode based on the semiconductor memory's transfer speed. For example, the first speed mode could refer to a mode where the semiconductor memory operates at a relatively low transfer speed in sync with a low-frequency clock signal, and the second speed mode could refer to a mode where the semiconductor memory operates at a relatively high transfer speed in sync with a high-frequency clock signal. Assuming the semiconductor memory can be operated by being supplied with a first power supply voltage and a second power supply voltage, then one of the first and second power supply voltages is selected and used according to the semiconductor memory's transfer speed. For example, the semiconductor memory can operate at a relatively low transfer speed in the first speed mode by being supplied with a first power supply voltage with a higher level, and the semiconductor memory can operate at a relatively high transfer speed in the second speed mode by being supplied with a second power supply voltage with a lower level.

[0040] Understandably, such as Figure 1 As shown, a low-power (LP) double-data-rate (DDR) memory device can contain thousands of logic gate devices, such as NOT gates, NOR gates, NAND gates, etc. These logic devices form different logic gate circuits, and then perform various operations by applying power supply voltage.

[0041] Taking NOT gate devices as an example, see Figure 2 A NOT gate can be constructed from two types of transistors. One type is the P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), abbreviated as PMOS; the other type is the N-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), abbreviated as NMOS. Furthermore, PMOS transistors use an N-type substrate, while NMOS transistors use a P-type substrate. (Details follow...) Figure 2 As shown, MP0 is a PMOS transistor and MN0 is an NMOS transistor. Here, the source terminal of MP0 is connected to the vdd signal, the back gate terminal of MP0 is connected to the vbp signal, the source terminal of MN0 is connected to the vss signal, and the back gate terminal of MN0 is connected to the vbn signal. The gate terminal of MP0 is connected to the gate terminal of MN0 to form the input terminal of the NOT gate (denoted by A). The drain terminal of MP0 is connected to the drain terminal of MN0 to form the output terminal of the NOT gate (denoted by Y).

[0042] In the design of LPDDR memory devices, the main concern is the leakage current of logic gate circuits, such as source / substrate leakage current, drain / substrate leakage current, source / drain leakage current, gate / substrate leakage current, etc. Taking NMOS transistors as an example... Figure 3 A schematic diagram of the leakage current distribution of an NMOS transistor is shown. (For example...) Figure 3 As shown, the source / drain current can be represented by Ileak_SD, the source / substrate drain current by Ileak_SB, the drain / substrate drain current by Ileak_DB, and the gate / substrate drain current by Ileak_GB. Additionally, it should be noted that the source / drain current can also be represented by Ioff.

[0043] However, currently, when the substrate voltage and source voltage are the same, the threshold voltage of the transistor is low, the saturation current is large, and the transmission speed is fast. In this case, the leakage current between the source and drain is relatively large, resulting in high power consumption.

[0044] Based on this, the present disclosure provides a control circuit. Based on this control circuit, while ensuring that the semiconductor performance meets the requirements, the bias switching circuit can receive the target signal to perform bias voltage switching, thereby increasing the threshold voltage of the target transistor, reducing the saturation current, and reducing the leakage current between the source and drain, thus achieving the purpose of saving power consumption.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] In one embodiment of this disclosure, see Figure 4 It illustrates a schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 1 .like Figure 4 As shown, the control circuit 40 may include a bias switching circuit 41 and a first logic gate circuit 42; wherein,

[0047] The first logic gate circuit 42 is composed of at least one target transistor. The substrate of the target transistor is connected to the output terminal of the bias switching circuit 41. The first logic gate circuit 42 has a first speed mode and a second speed mode. The transmission speed of the first speed mode is lower than the transmission speed of the second speed mode.

[0048] The bias switching circuit 41 is used to receive the target signal. If the target signal is in an enabled state, it outputs the target bias voltage to increase the threshold voltage of the target transistor. The enabled state of the target signal indicates that the first logic gate circuit 42 is in the first speed mode.

[0049] It should be noted that, in the embodiments of this disclosure, after receiving the target signal, if the target signal is in an enabled state, that is, the first logic gate circuit 42 is in the first speed mode, the bias switching circuit 41 can output the target bias voltage; and provide the target bias voltage to the substrate of the target transistor forming the first logic gate circuit 42 to increase the threshold voltage of the target transistor, thereby reducing the leakage current between the source and drain of the target transistor.

[0050] Furthermore, for the bias switching circuit 41, after receiving the target signal, the target signal may still be in a disabled state. Therefore, in some embodiments, the bias switching circuit 41 is also used to output an initial bias voltage if the target signal is in a disabled state, so as to reduce the threshold voltage of the target transistor. The disabled state of the target signal indicates that the first logic gate circuit is in the second speed mode.

[0051] In this embodiment, whether the target signal is in an enabled or disabled state can be determined based on whether the first logic gate 42 is operating in a high-speed state. Specifically, if the first logic gate 42 is operating in a high-speed state, i.e., in the second speed mode, then the target signal is in a disabled state; if the first logic gate 42 is operating in a low-speed state, i.e., in the first speed mode, then the target signal is in an enabled state. That is to say, in this embodiment, in the DVFSC mode (i.e., low-speed mode), the threshold voltage (denoted by Vth) can be increased by changing the bias voltage, thereby reducing the leakage current (denoted by Ioff) between the source and drain of the target transistor. At this time, power saving can be achieved while ensuring that the transmission speed meets the requirements.

[0052] In some embodiments, if the target signal is in a first level state, it is determined that the target signal is in an enabled state; if the target signal is in a second level state, it is determined that the target signal is in a disabled state (i.e., an enabled-disabled state). For example, the first level state is a high level and the second level state is a low level, but this is not specifically limited here.

[0053] Thus, in this embodiment, the bias voltage can be changed using the bias switching circuit 41. For the bias switching circuit 41, after receiving the target signal, if the target signal is in an enabled state, the initial bias voltage needs to be switched, and the output is the target bias voltage, which is different from the initial bias voltage. In this case, the target bias voltage is provided to the substrate of the target transistor to increase the threshold voltage of the target transistor, thereby reducing the leakage current between the source and drain of the target transistor. Conversely, if the target signal is in an disabled state, there is no need to switch the initial bias voltage; the initial bias voltage is directly output. In this case, the initial bias voltage is provided to the substrate of the target transistor, meaning the substrate voltage of the target transistor does not switch, and there is no need to reduce the leakage current between the source and drain of the target transistor.

[0054] In some embodiments, the target transistor forming the first logic gate circuit 42 may include two types of transistors, specifically a first type of transistor and a second type of transistor, with different threshold voltage adjustment methods for the different types of transistors. The first type of transistor may be a PMOS transistor, and the second type of transistor may be an NMOS transistor; or, the first type of transistor may be an NMOS transistor, and the second type of transistor may be a PMOS transistor.

[0055] Furthermore, for these two types of transistors, in Figure 4 Based on the control circuit 40 shown, as Figure 5 As shown, the bias switching circuit 41 may include a first switching circuit 411 and a second switching circuit 412; wherein,

[0056] The first switching circuit 411 is used to receive a first bias signal; and when the first bias signal is in an enabled state, it outputs a first target bias voltage corresponding to the first type of transistor; and when the first bias signal is in an disabled state, it outputs a first initial bias voltage corresponding to the first type of transistor.

[0057] The second switching circuit 412 is used to receive the second bias signal; and when the second bias signal is in an enabled state, to output the second target bias voltage corresponding to the second type of transistor; and when the second bias signal is in an disabled state, to output the second initial bias voltage corresponding to the second type of transistor.

[0058] It should be noted that, in this embodiment, the first switching circuit 411 corresponds to a first type of transistor. After receiving the first bias signal, it determines whether to switch the initial bias voltage (i.e., the first initial bias voltage) of the first type of transistor based on whether the first bias signal is in an enabled state. The second switching circuit 412 corresponds to a second type of transistor. After receiving the second bias signal, it determines whether to switch the initial bias voltage (i.e., the second initial bias voltage) of the second type of transistor based on whether the second bias signal is in an enabled state.

[0059] In one specific embodiment, if the first type of transistor is a PMOS transistor and the second type of transistor is an NMOS transistor, then the first target bias voltage corresponding to the first type of transistor is higher than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is lower than the second initial bias voltage; or, if the first type of transistor is an NMOS transistor and the second type of transistor is a PMOS transistor, then the first target bias voltage corresponding to the first type of transistor is lower than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is higher than the second initial bias voltage.

[0060] In other words, in this embodiment of the present disclosure, for the PMOS transistor, the corresponding target bias voltage is higher than the initial bias voltage; for the NMOS transistor, the corresponding target bias voltage is lower than the initial bias voltage. In this way, the threshold voltage of the PMOS transistor / NMOS transistor can be increased, the saturation current can be reduced, and the leakage current between the source and drain of the target transistor can be reduced.

[0061] Furthermore, for the first switching circuit 411, in some embodiments, such as Figure 6A As shown, the first switching circuit 411 may include a first NOT gate a1, a first transistor b1, and a second transistor c1; wherein,

[0062] The drain of the first transistor b1 is connected to the first target bias voltage, and the drain of the second transistor c1 is connected to the first initial bias voltage. The gate of the first transistor b1 is connected to the input terminal of the first NOT gate a1 to receive the first bias signal. The gate of the second transistor c1 is connected to the output terminal of the first NOT gate a1. The source of the first transistor b1 is connected to the source of the second transistor c1 to output the first output bias voltage.

[0063] It should be noted that, in the embodiments of this disclosure, when the first bias signal is in an enabled state, the first transistor b1 is turned on, and the first output bias voltage is determined to be the first target bias voltage; and when the first bias signal is in an disabled state, the second transistor c1 is turned on, and the first output bias voltage is determined to be the first initial bias voltage.

[0064] It should also be noted that, in this embodiment of the disclosure, assuming that the first switching circuit 411 corresponds to a PMOS transistor, the first bias signal can be represented by vbpEn, the first target bias voltage can be represented by vbp, the first initial bias voltage can be represented by vdd, and the voltage value corresponding to vdd is lower than the voltage value corresponding to vbp.

[0065] In other words, if the vbpEn signal is enabled, the first transistor b1 can be turned on, and the first output bias voltage is vbp. If the vbpEn signal is disabled, the second transistor c1 can be turned on through the inversion of the first NOT gate a1, and the first output bias voltage is vdd. Thus, for the PMOS transistor, if the vbpEn signal is enabled, the substrate voltage supplied to the PMOS transistor is vbp, which is higher than the initial vdd, thereby increasing the threshold voltage of the PMOS transistor and reducing the leakage current between the source and drain of the PMOS transistor.

[0066] Furthermore, for the first switching circuit 411, in some embodiments, such as Figure 6B As shown, the first switching circuit 411 may further include a first selection circuit d1, and the first selection circuit d1 includes multiple ports, with different ports corresponding to different first candidate bias voltages; wherein,

[0067] The first selection circuit d1 is used to receive the first selection signal, determine the target port according to the first selection signal, and determine the first candidate bias voltage corresponding to the target port as the first target bias voltage.

[0068] It should be noted that in this embodiment, multiple voltage levels can be set for the Vbp voltage. Each port corresponds to one voltage level, and each voltage level corresponds to a different first candidate bias voltage. Once the target port is determined, the first candidate bias voltage corresponding to that target port (i.e., the voltage level) can be used as the first target bias voltage to be output.

[0069] For example, such as Figure 6B As shown, the first selection circuit d1 includes four ports, with the vdd voltage as a reference. The first candidate bias voltages corresponding to these four ports are vdd+0.20V, vdd+0.15V, vdd+0.10V, and vdd+0.05V, respectively. Thus, if the vbpEn signal is enabled, the substrate voltage supplied to the PMOS transistor will definitely be greater than vdd, thereby raising the substrate voltage and reducing the leakage current between the source and drain of the PMOS transistor.

[0070] Furthermore, for the first switching circuit 412, in some embodiments, such as Figure 7A As shown, the second switching circuit 412 may include a second NOT gate a2, a third transistor b2, and a fourth transistor c2; wherein,

[0071] The source of the third transistor b2 is connected to the second target bias voltage, and the source of the fourth transistor c2 is connected to the second initial bias voltage; the gate of the third transistor b2 is connected to the input of the second NOT gate a2 to receive the second bias signal; the gate of the fourth transistor c2 is connected to the output of the second NOT gate a2; the drain of the third transistor b2 is connected to the drain of the fourth transistor c2 to output the second output bias voltage.

[0072] It should be noted that, in the embodiments of this disclosure, when the second bias signal is in an enabled state, the third transistor b2 is turned on to determine the second output bias voltage as the second target bias voltage; and when the second bias signal is in an disabled state, the fourth transistor c2 is turned on to determine the second output bias voltage as the second initial bias voltage.

[0073] It should also be noted that, in this embodiment of the disclosure, assuming that the second switching circuit 412 corresponds to an NMOS transistor, the second bias signal can be represented by vbnEn, the second target bias voltage can be represented by vbn, the second initial bias voltage can be represented by vss, and the voltage value corresponding to vss is higher than the voltage value corresponding to vbn.

[0074] In other words, if the vbnEn signal is enabled, the third transistor b2 can be turned on, and the second output bias voltage is vbn. If the vbnEn signal is disabled, the fourth transistor c2 can be turned on through the inversion of the second NOT gate a2, and the second output bias voltage is vss. Thus, for the NMOS transistor, if the vbnEn signal is enabled, the substrate voltage supplied to the NMOS transistor is vbn. Compared with the initial vss, the substrate voltage is reduced, thereby increasing the threshold voltage of the PMOS transistor and reducing the leakage current between the source and drain of the NMOS transistor.

[0075] Furthermore, regarding the second switching circuit 412, in some embodiments, such as Figure 7B As shown, the second switching circuit 412 may further include a second selection circuit d2, and the second selection circuit d2 includes multiple ports, with different ports corresponding to different second candidate bias voltages; wherein,

[0076] The second selection circuit d2 is used to receive the second selection signal, determine the target port according to the second selection signal, and determine the second candidate bias voltage corresponding to the target port as the second target bias voltage.

[0077] It should be noted that, in this embodiment of the disclosure, multiple levels can be set for the VBN voltage. Here, each port corresponds to one level, and each level corresponds to a different second candidate bias voltage. Once the target port is determined, the second candidate bias voltage corresponding to the target port (i.e., the level) can be used as the second target bias voltage to be output.

[0078] For example, such as Figure 7B As shown, assuming the second selection circuit d2 includes four ports, with the VSS voltage as a reference, the corresponding second candidate bias voltages for these four ports are VSS-0.20V, VSS-0.15V, VSS-0.10V, and VSS-0.05V, respectively. Thus, if the VBNEn signal is enabled, the substrate voltage supplied to the NMOS transistor will always be less than VSS, thereby reducing the substrate voltage and decreasing the leakage current between the source and drain of the NMOS transistor.

[0079] Furthermore, for these two types of transistors (the first type of transistor and the second type of transistor), in some embodiments, when the first type of transistor is a PMOS transistor and the second type of transistor is an NMOS transistor, it is determined that the first candidate bias voltage corresponding to each port is greater than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is less than the second initial bias voltage; or,

[0080] When the first type of transistor is an NMOS transistor and the second type of transistor is a PMOS transistor, it is determined that the first candidate bias voltage corresponding to each port is less than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is greater than the second initial bias voltage.

[0081] In simple terms, at low speeds, to reduce the leakage current between the source and drain of a transistor, the substrate voltage needs to be increased for a PMOS transistor and decreased for an NMOS transistor. Furthermore, this embodiment also provides an adjustable substrate voltage, where the substrate voltage of a PMOS transistor is adjusted via a first selection circuit d1, and the substrate voltage of an NMOS transistor is adjusted via a second selection circuit d2, to prevent the selection of the substrate voltage from causing excessive gate / substrate leakage current.

[0082] Furthermore, in embodiments of this disclosure, such as Figure 8 As shown, the control circuit 40 may include a plurality of first-type transistors and a plurality of second-type transistors.

[0083] In one possible implementation, if the number of first switching circuits 411 is one and the number of second switching circuits 412 is also one, then the bias switching circuit 41 is also used to simultaneously provide a first output bias voltage to multiple first-type transistors through a first switching circuit 411 and simultaneously provide a second output bias voltage to multiple second-type transistors through a second switching circuit 412.

[0084] In another possible implementation, if there are multiple first switching circuits 411 and multiple second switching circuits 412, then the bias switching circuit 41 is also used to simultaneously provide a first output bias voltage to multiple first-type transistors through a first switching circuit 411 and simultaneously provide a second output bias voltage to multiple second-type transistors through a second switching circuit 412.

[0085] In another possible implementation, if there are multiple first switching circuits 411 and multiple second switching circuits 412, then the bias switching circuit 41 is also used to provide a first output bias voltage to multiple first-type transistors through multiple first switching circuits 411, and to provide a second output bias voltage to multiple second-type transistors through multiple second switching circuits 412.

[0086] It should be noted that, in this embodiment, the switching of the substrate voltage is time-limited and needs to be completed within the period when the target signal is enabled / disabled. This is because the capacitance accumulated between the source and substrate of millions of logic gates constitutes a large capacitance, requiring charging / discharging. Therefore, the first switching circuit 411 and the second switching circuit 412 need to be distributed within the control circuit 40, and the number of enabled first switching circuits 411 and second switching circuits 412 can be selected according to actual needs.

[0087] In other words, if the control circuit 40 can include multiple first-type transistors and second-type transistors, then when both the number of first switching circuits 411 and the number of second switching circuits 412 are multiple, for the multiple first-type transistors, one first switching circuit can be enabled, meaning that power is supplied to multiple first-type transistors simultaneously through one first switching circuit; or multiple first switching circuits can be enabled, meaning that power is supplied to multiple first-type transistors respectively through multiple first switching circuits; or a portion of the first switching circuits can be enabled, meaning that power is supplied to multiple first-type transistors through a portion of the multiple first switching circuits. Similarly, for the multiple second-type transistors, one second switching circuit can be enabled, meaning that power is supplied to multiple second-type transistors simultaneously through one second switching circuit; or multiple second switching circuits can be enabled, meaning that power is supplied to multiple second-type transistors respectively through multiple second switching circuits; or a portion of the first switching circuits can be enabled, meaning that power is supplied to multiple second-type transistors through a portion of the multiple second switching circuits. Thus, if each first switching circuit corresponds to one first-type transistor for charging and each second switching circuit corresponds to one second-type transistor for discharging, the charging and discharging speed can be increased.

[0088] In some embodiments, Figure 4 Based on the control circuit 40 shown, as Figure 5 As shown, the control circuit 40 may further include a control module 43; wherein,

[0089] Control module 43 is configured to enable the target signal when the first logic gate circuit 42 is in the first speed mode and the leakage current of the target transistor is greater than or equal to a preset value; and

[0090] When the first logic gate 42 is in the second speed mode, or when the first logic gate 42 is in the first speed mode and the leakage current of the target transistor is less than a preset value, the control target signal is in an enabled state.

[0091] It should be noted that in this embodiment, if the leakage current of the target transistor is less than a preset value, it means that the performance of the target transistor has met the requirements, and therefore there is no need to change the substrate voltage of the target transistor to reduce the leakage current. That is, only when the first logic gate circuit 42 is in the first speed mode and the leakage current of the target transistor is greater than or equal to the preset value, will it be necessary to switch the substrate voltage of the target transistor to reduce the leakage current between the source and drain.

[0092] It should also be noted that, in the embodiments of this disclosure, the target transistor may include a PMOS transistor and / or an NMOS transistor. Wherein, if the target transistor is a PMOS transistor, then the target signal is a first bias signal (represented by the vbpEn signal); if the target transistor is an NMOS transistor, then the target signal is a second bias signal (represented by the vbnEn signal); the following will describe in detail whether the substrate voltage of the PMOS transistor and the NMOS transistor are switched in several cases.

[0093] In one possible implementation, when the first logic gate 42 is in the first speed mode and the leakage current of both the PMOS transistor and the NMOS transistor is greater than or equal to a preset value,

[0094] The control module 43 is used to control the first bias signal to be in an enabled state and to control the second bias signal to be in an enabled state.

[0095] The first logic gate circuit 42 is used to provide a first target bias voltage to the substrate of the PMOS transistor and a second target bias voltage to the substrate of the NMOS transistor, so that the substrate voltage of the PMOS transistor and the substrate voltage of the NMOS transistor are switched, thereby reducing the leakage current between the source and drain of the PMOS transistor and the leakage current between the source and drain of the NMOS transistor.

[0096] In another possible implementation, when the first logic gate 42 is in the first speed mode, and the leakage current of the PMOS transistor is greater than or equal to a preset value, and the leakage current of the NMOS transistor is less than a preset value,...

[0097] The control module 43 is used to control the first bias signal to be in an enabled state and to control the second bias signal to be in an disabled state.

[0098] The first logic gate circuit 42 is used to provide a first target bias voltage to the substrate of the PMOS transistor and a second initial bias voltage to the substrate of the NMOS transistor, so that the substrate voltage of the PMOS transistor is switched to reduce the leakage current between the source and drain of the PMOS transistor.

[0099] In another possible implementation, when the first logic gate 42 is in the first speed mode, and the leakage current of the PMOS transistor is less than a preset value, and the leakage current of the NMOS transistor is greater than or equal to a preset value,

[0100] The control module 43 is used to control the first bias signal to be in a disabled state and to control the second bias signal to be in an enabled state.

[0101] The first logic gate circuit 42 is used to provide a first initial bias voltage to the substrate of the PMOS transistor and a second target bias voltage to the substrate of the NMOS transistor, so that the substrate voltage of the NMOS transistor is switched to reduce the leakage current between the source and drain of the NMOS transistor.

[0102] In another possible implementation, when the first logic gate 42 is in the first speed mode and the leakage current of both the PMOS and NMOS transistors is less than a preset value,

[0103] The control module 43 is used to control the first bias signal to be in a disabled state and to control the second bias signal to be in a disabled state.

[0104] The first logic gate circuit 42 is used to provide a first initial bias voltage to the substrate of the PMOS transistor and a second initial bias voltage to the substrate of the NMOS transistor, so that the substrate voltage of the PMOS transistor and the substrate voltage of the NMOS transistor do not switch.

[0105] In other words, in the embodiments of this disclosure, substrate voltage switching is not suitable for all transistors. For example, for high-speed transistors or transistors with low threshold voltages (thin gate oxide), excessive gate / substrate leakage current may occur. If this leakage current exceeds the reduction value of the leakage current between the source and drain, voltage switching should not be performed, and the initial bias voltage should still be supplied to the transistor substrate to avoid excessive gate / substrate leakage current. Furthermore, even for low-speed transistors, due to significant variations in process conditions, the Vbp and Vbn voltages can be enabled separately depending on the process conditions. For example, if after silicon fabrication, it is found that the leakage current of the PMOS transistor is very small and does not affect the overall circuit leakage current, but the leakage current of the NMOS transistor has a greater impact, then the substrate voltage of the NMOS transistor can be switched only through the Vbn voltage. The embodiments of this disclosure do not impose any limitations on this.

[0106] In some embodiments, Figure 4 Based on the control circuit 40 shown, as Figure 5 As shown, the control circuit 40 may further include a switch module 44 and a second logic gate circuit 45; wherein,

[0107] The switching module 44 is used to control the switching switch inside the switching module to select the first logic gate circuit 42 when the transmission speed meets the first speed mode or the second speed mode; or, when the transmission speed meets the third speed mode, control the switching switch inside the switching module to select the second logic gate circuit 45.

[0108] The second logic gate circuit 45 is composed of at least one target transistor. The substrate of the target transistor is connected to the output terminal of the bias switching circuit to receive the initial bias voltage output by the bias switching circuit in order to reduce the threshold voltage of the target transistor. The second logic gate circuit has a third speed mode, and the transmission speed corresponding to the second speed mode is lower than the transmission speed corresponding to the third speed mode.

[0109] Here, for the first logic gate 42 or the second logic gate 45, the transmission speed can be divided into ultra-high speed state, high speed state, and low speed state. Among them, the transmission speed corresponding to the third speed mode conforms to the ultra-high speed state, the transmission speed corresponding to the second speed mode conforms to the high speed state, and the transmission speed corresponding to the first speed mode conforms to the low speed state.

[0110] If the current transmission speed meets the third speed mode, the switching switch inside the switching module 44 selects the second logic gate circuit 45, and then provides an initial bias voltage to the substrate of the target transistor forming the second logic gate circuit 45 to reduce the threshold voltage of the target transistor. If the current transmission speed meets the first speed mode or the second speed mode, the switching switch inside the switching module 44 selects the first logic gate circuit 42. In this case, there are two situations: If the current transmission speed meets the first speed mode, it means that the target signal is in an enabled state. The target bias voltage can be output by the bias switching circuit 41, and then the target bias voltage is provided to the substrate of the target transistor forming the first logic gate circuit 41 to increase the threshold voltage of the target transistor, thereby reducing the leakage current between the source and drain of the target transistor; If the current transmission speed meets the second speed mode, it means that the target signal is in an disabled state. The initial bias voltage can be output by the bias switching circuit 41, and then the initial bias voltage is provided to the substrate of the target transistor forming the first logic gate circuit to reduce the threshold voltage of the target transistor, avoiding excessive gate / substrate leakage current of the transistor, which would affect the leakage current of the overall circuit.

[0111] This disclosure provides a control circuit. Based on the control circuit 40, while ensuring that the semiconductor performance meets the requirements, the control circuit switches the initial bias voltage through a bias switching circuit, thereby increasing the threshold voltage of the target transistor, reducing the saturation current, and reducing the leakage current between the source and drain, thus achieving the purpose of saving power consumption.

[0112] In another embodiment of this disclosure, see Figure 9 It illustrates a schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 4 .like Figure 9As shown, the control circuit 40 may include a first switching circuit 901, a second switching circuit 902, a first switching switch S1, a second switching switch S2, an ultra-high-speed logic gate circuit 903, a high-speed / low-speed logic gate circuit 904, and an equivalent capacitor C1. The specific structure of the first switching circuit 901 is as described above. Figure 6A or Figure 6B As shown, the specific structure of the second switching circuit 902 is as described above. Figure 7A or Figure 7B As shown.

[0113] It should be noted that, in this embodiment, if the first switching switch S1 is selected to the ultra-high-speed logic gate circuit 903, the substrate voltage of the PMOS transistor in the ultra-high-speed logic gate circuit 903 can be powered by the Vdd voltage output by the first switching circuit 901; if the second switching switch S2 is selected to the ultra-high-speed logic gate circuit 903, the substrate voltage of the NMOS transistor in the ultra-high-speed logic gate circuit 903 can be powered by the VSS voltage output by the second switching circuit 902. It should be noted that, since both the Vdd and VSS voltages are initial bias voltages, for the ultra-high-speed logic gate circuit 903, it is also possible to bypass the first and second switching circuits 901 and 902, allowing the substrate voltage of the PMOS transistor to be directly connected to the Vdd voltage and the substrate voltage of the NMOS transistor to be directly connected to the VSS voltage.

[0114] Specifically, if the first switching switch S1 is selected to the high-speed / low-speed logic gate circuit 904, the substrate voltage of the PMOS transistor in the high-speed / low-speed logic gate circuit 904 can be powered by the Vdd / Vbp voltage output by the first switching circuit 901. Specifically, if the high-speed / low-speed logic gate circuit 904 operates in low-speed mode, and the VbpEn signal is enabled, the first switching circuit 901 outputs the Vbp voltage and provides it to the substrate of the PMOS transistor. Otherwise, if the high-speed / low-speed logic gate circuit 904 operates in high-speed mode, and the VbpEn signal is disabled, the first switching circuit 901 outputs the Vdd voltage and provides it to the substrate of the PMOS transistor. It should also be noted that the first switching circuit 901 can also be considered as a switching switch. Here, if the vbpEn signal is enabled, the switching switch is controlled to select the first terminal to output the vdd voltage, in which case the substrate voltage of the PMOS transistor remains unchanged; if the vbpEn signal is disabled, the switching switch is controlled to select the second terminal to output the vbp voltage, in which case the substrate voltage of the PMOS transistor changes. That is to say, the specific structure of the first switching circuit 901 is not limited in this embodiment.

[0115] Similarly, if the second switching switch S2 is selected to the high-speed / low-speed logic gate circuit 904, the substrate voltage of the NMOS transistor in the high-speed / low-speed logic gate circuit 904 can be powered by the VSS voltage / VBN voltage output by the second switching circuit 902. Specifically, if the high-speed / low-speed logic gate circuit 904 operates in low-speed mode, and the VBNEn signal is enabled, the second switching circuit 902 outputs the VBN voltage and supplies it to the substrate of the NMOS transistor. Otherwise, if the high-speed / low-speed logic gate circuit 904 operates in high-speed mode, and the VBNEn signal is disabled, the second switching circuit 902 outputs the VSS voltage and supplies it to the substrate of the NMOS transistor. Additionally, it should be noted that the second switching circuit 902 can also be considered as a switching switch. Here, if the vbnEn signal is enabled, the switching switch is controlled to select the first terminal to output the VSS voltage, in which case the substrate voltage of the NMOS transistor remains unchanged; if the vbnEn signal is disabled, the switching switch is controlled to select the second terminal to output the vbn voltage, in which case the substrate voltage of the NMOS transistor changes. That is to say, the specific structure of the second switching circuit 902 is not limited in this embodiment.

[0116] It should also be noted that, in this embodiment, taking the high-speed / low-speed logic gate circuit 904 as an example, the PMOS transistor increases the substrate voltage to charge the substrate, and the NMOS transistor decreases the substrate voltage to discharge the substrate. Thus, the PMOS transistors, NMOS transistors, and other transistors in the high-speed / low-speed logic gate circuit 904 can be equivalent to a capacitor C1. That is, the substrate voltage switching of these transistors needs to be time-limited and must be completed within the enable / disable cycle of the low-speed state (i.e., the DVFSC signal), because the accumulated capacitance between the source and substrate of millions of logic gates constitutes a large equivalent capacitance, requiring charging / discharging.

[0117] For example, see Figure 10 This illustrates a signal timing diagram of a control circuit provided in an embodiment of the present disclosure. Figure 10 As shown, the DVFSC signal indicates whether the control circuit is operating in a low-speed state, i.e., whether the aforementioned target signal is enabled; the vbp voltage signal indicates whether the substrate voltage of the PMOS transistor is switched, and the vbn voltage signal indicates whether the substrate voltage of the NMOS transistor is switched. Figure 10 In the process, when the DVFSC signal changes from low to high (i.e., it is in the enabled state, and the control circuit operates at low speed), both the Vbp and Vbn voltage signals change from low to high, requiring switching of the substrate voltage of the PMOS / NMOS transistor for charging / discharging. Additionally, in... Figure 10 Taking a PMOS transistor as an example, for the same PMOS transistor, due to process reasons, the substrate voltage may switch to different voltage values ​​(e.g., 1.2V, 1.15V, 1.10V, 1.05V, etc.); moreover, due to the different equivalent capacitance C1, the different charging voltages lead to differences in charging speed, which in turn results in different slopes of the vbp voltage signal; similarly, for the same NMOS transistor, due to differences in discharge speed, the slopes of the vbn voltage signal will also be different.

[0118] In one specific embodiment, in DRAM design (especially LPDDR5), there are several constraints regarding the design of the switching substrate:

[0119] (1) The substrate voltage needs to be switched according to the working state of the DRAM. At high frequency, performance is the main factor. The substrate voltage = power supply / ground voltage (at this time, it is a dual power supply design, controlled by a switching switch).

[0120] (2) The switching of substrate voltage has a time limit and needs to be completed within the enable / disable cycle of the DVFSC signal because the capacitance between the source and substrate of millions of logic gates accumulates into a large capacitance that needs to be charged / discharged. At this time, the first switching circuit and the second switching circuit need to be distributed in the control circuit, and the number of multiple first switching circuits and multiple second switching circuits can be selected according to actual needs.

[0121] (3) Substrate voltage switching is not suitable for all transistors. For example, high-speed transistors or low-threshold transistors (with very thin gate oxide) will cause the gate / substrate leakage current to be too large, which is greater than the reduction value of the source / drain leakage current. In this case, substrate voltage switching should not be performed.

[0122] (4) For the switching circuit, the selection of the substrate voltage should not lead to excessive gate / substrate leakage current, so an adjustable substrate voltage can be provided (e.g., by a first selection circuit or a second selection circuit).

[0123] (5) Because the process conditions vary greatly, the Vbp voltage and Vbn voltage can be enabled separately according to the process conditions. For example, if the leakage current of the PMOS transistor is found to be very small after silicon treatment, it will not affect the leakage current of the entire control circuit, but the leakage current of the NMOS transistor will have a greater impact. In this case, only the Vbn voltage can be turned on to switch the substrate voltage of the NMOS transistor.

[0124] Based on this, the present disclosure provides a control circuit. The specific implementation of the foregoing embodiments is described in detail in this embodiment. It can be seen that, based on the technical solution of the present disclosure, for DVFSC mode (i.e., low-speed mode), while ensuring that the semiconductor performance meets the requirements, the bias voltage is switched by the first switching circuit and / or the second switching circuit, thereby increasing the threshold voltage of the target transistor, reducing the saturation current, and reducing the leakage current between the source and drain, thereby achieving the purpose of saving power consumption.

[0125] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 11 This illustrates a schematic diagram of the structural composition of a semiconductor memory 110 provided in an embodiment of this disclosure. For example... Figure 11 As shown, the semiconductor memory 110 may include the control circuit 40 described in any of the foregoing embodiments.

[0126] In this embodiment of the disclosure, the semiconductor memory 110 may be a DRAM chip.

[0127] Furthermore, in some embodiments, the DRAM chip conforms to the DDR5 memory specification.

[0128] It should be noted that the embodiments disclosed herein relate to semiconductor integrated circuit design, and particularly to power-saving circuits. Specifically, the technical solution of the embodiments disclosed herein mainly provides a power-saving circuit design that can realize LP DDR5 DVFSC mode. In this way, in DVFSC mode, by changing the Bulk bias voltage to increase the threshold voltage of the transistor, the leakage current between the source and drain can be reduced; at this time, while ensuring the required transmission speed, lower power consumption can also be achieved.

[0129] In simple terms, in this embodiment of the disclosure, the semiconductor memory 110 includes a control circuit 40. Therefore, while ensuring that the semiconductor performance meets the requirements, the control circuit switches the bias voltage through the bias switching circuit, thereby increasing the threshold voltage of the target transistor, reducing the saturation current, and reducing the leakage current between the source and drain, thus achieving the purpose of saving power consumption.

[0130] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0131] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0132] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0133] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0134] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0135] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0136] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A control circuit, characterized by The control circuit includes a bias switching circuit and a first logic gate circuit; wherein... The first logic gate circuit is composed of at least one target transistor, the substrate of the target transistor is connected to the output terminal of the bias switching circuit, and the first logic gate circuit has a first speed mode and a second speed mode, wherein the transmission speed of the first speed mode is lower than the transmission speed of the second speed mode. The bias switching circuit is used to receive the target signal. If the target signal is in an enabled state, it outputs a target bias voltage to increase the threshold voltage of the target transistor. The enabled state of the target signal indicates that the first logic gate circuit is in a first speed mode. The target transistor includes a PMOS transistor and / or an NMOS transistor; The bias switching circuit includes a first switching circuit and a second switching circuit; wherein... The first switching circuit is configured to receive a first bias signal; and when the first bias signal is in an enabled state, output a first target bias voltage corresponding to the first type of transistor; and when the first bias signal is in an disabled state, output a first initial bias voltage corresponding to the first type of transistor. The second switching circuit is used to receive a second bias signal; and when the second bias signal is in an enabled state, to output a second target bias voltage corresponding to the second type of transistor; and when the second bias signal is in an disabled state, to output a second initial bias voltage corresponding to the second type of transistor. The first switching circuit includes a first NOT gate, a first transistor, and a second transistor; wherein, The drain of the first transistor is connected to the first target bias voltage, and the drain of the second transistor is connected to the first initial bias voltage; the gate of the first transistor is connected to the input of the first NOT gate to receive the first bias signal; the gate of the second transistor is connected to the output of the first NOT gate; the source of the first transistor is connected to the source of the second transistor to output the first target bias voltage when the first bias signal is enabled.

2. The control circuit according to claim 1, characterized in that, The bias switching circuit is further configured to output an initial bias voltage if the target signal is in an disabled state, so as to reduce the threshold voltage of the target transistor. The disabled state of the target signal indicates that the first logic gate circuit is in a second speed mode.

3. The control circuit according to claim 1, characterized in that, The first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. The first target bias voltage corresponding to the first type of transistor is higher than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is lower than the second initial bias voltage. or, The first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. The first target bias voltage corresponding to the first type of transistor is lower than the first initial bias voltage, and the second target bias voltage corresponding to the second type of transistor is higher than the second initial bias voltage.

4. The control circuit of claim 1, wherein, The first switching circuit further includes a first selection circuit, and the first selection circuit includes multiple ports, with different ports corresponding to different first candidate bias voltages; wherein, The first selection circuit is used to receive a first selection signal, determine a target port based on the first selection signal, and determine the first candidate bias voltage corresponding to the target port as the first target bias voltage.

5. The control circuit of claim 4, wherein, The second switching circuit includes a second NOT gate, a third transistor, and a fourth transistor; wherein, The source of the third transistor is connected to the second target bias voltage, and the source of the fourth transistor is connected to the second initial bias voltage; the gate of the third transistor is connected to the input of the second NOT gate to receive the second bias signal; the gate of the fourth transistor is connected to the output of the second NOT gate; the drain of the third transistor is connected to the drain of the fourth transistor to output the second target bias voltage when the second bias signal is enabled.

6. The control circuit according to claim 5, characterized in that, The second switching circuit further includes a second selection circuit, and the second selection circuit includes multiple ports, with different ports corresponding to different second candidate bias voltages; wherein, The second selection circuit is used to receive a second selection signal, determine a target port based on the second selection signal, and determine the second candidate bias voltage corresponding to the target port as the second target bias voltage.

7. The control circuit according to claim 6, characterized in that, The first type of transistor is a PMOS transistor, the second type of transistor is an NMOS transistor, the first candidate bias voltage corresponding to each port is greater than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is less than the second initial bias voltage. or, The first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. The first candidate bias voltage corresponding to each port is less than the first initial bias voltage, and the second candidate bias voltage corresponding to each port is greater than the second initial bias voltage.

8. The control circuit according to claim 1, characterized in that, The control circuit includes multiple first-type transistors and multiple second-type transistors, and both the number of the first switching circuits and the number of the second switching circuits are multiple; wherein, The bias switching circuit is further configured to provide a first output bias voltage to a plurality of first-type transistors through a plurality of first switching circuits, and to provide a second output bias voltage to a plurality of second-type transistors through a plurality of second switching circuits.

9. The control circuit according to claim 1, characterized in that, The control circuit further includes a control module; wherein... The control module is configured to control the target signal to be in an enabled state when the first logic gate circuit is in a first speed mode and the leakage current of the target transistor is greater than or equal to a preset value; and When the first logic gate is in the second speed mode, or when the first logic gate is in the first speed mode and the leakage current of the target transistor is less than a preset value, the target signal is controlled to be in an enabled state.

10. The control circuit according to claim 1, characterized in that, The control circuit further includes a switching module and a second logic gate circuit; wherein... The switching module is used to control the switching switch inside the switching module to select the first logic gate circuit when the transmission speed meets the first speed mode or the second speed mode; or, when the transmission speed meets the third speed mode, control the switching switch inside the switching module to select the second logic gate circuit. The second logic gate circuit is composed of at least one target transistor. The substrate of the target transistor is connected to the output terminal of the bias switching circuit to receive the initial bias voltage output by the bias switching circuit in order to reduce the threshold voltage of the target transistor. The second logic gate circuit has a third speed mode, and the transmission speed corresponding to the second speed mode is lower than the transmission speed corresponding to the third speed mode.

11. A semiconductor memory, characterized in that, Includes the control circuit as described in any one of claims 1 to 10.

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