A method for automatically deploying HMP architecture applications

Abstract

The present invention discloses a method for automatically deploying HMP architecture applications. When a process or thread that needs to use an acceleration instruction is deployed to a non-acceleration instruction CPU core for execution, an illegal instruction exception is triggered because the current CPU core does not support the acceleration instruction, and a kernel exception interrupt is entered. In the kernel illegal instruction exception handling function, the current thread is bound to a CPU core that supports acceleration extension instructions. When the exception is returned, the thread is directly switched to the CPU core that supports acceleration extension instructions for normal operation.

Description

Technical Field

[0001] The present invention belongs to the field of chips, and in particular relates to a method for automatically deploying HMP architecture applications. Background Art

[0002] SoCs with an HMP architecture typically consist of multiple CPU clusters, each with multiple CPU cores. These clusters run a common operating system, but each cluster has microarchitectural differences, such as support for different acceleration extensions. When running a Linux-based system on the SoC, only the Linux kernel typically considers the core's microarchitecture and processing capabilities. Applications that require extended instruction acceleration must run on specific CPU cores. Existing technologies typically address this by requiring applications to proactively bind themselves to specific cores to utilize acceleration instructions.

[0003] When an application uses acceleration instructions, it must clearly understand the extended instruction support of each CPU core in the current SoC to accurately determine which CPU core it should be bound to. This means that the application must be aware of the hardware details of the current SoC, which poses a significant challenge to the application's versatility and prevents the application from automatically adapting to run on different SoC platforms. This invention aims to solve the problem of enabling applications to adaptively run on different hardware platforms, while being able to use acceleration instructions without having to worry about the architectural implementation of each CPU core.

[0004] For example, there is the following CPU architecture, which has two clusters and generally belongs to SMP. Several cores of one cluster have special acceleration instructions, while several cores of the other cluster do not have special acceleration instructions.

[0005] When acceleration instructions are used in a program and the program is executed on several cores without acceleration instructions, an illegal instruction exception will be triggered.

[0006] When an acceleration instruction application runs, the operating system randomly deploys the acceleration instruction process to one of the eight cores. This means that the kernel process scheduler cannot accurately assign the acceleration instruction process or thread to the acceleration instruction core. To specify whether a process or thread runs on a specific CPU or CPUs, the traditional approach is to assign the process or thread to a CPU core through user-mode programming. When the number and number of acceleration instruction cores in a CPU change, the application code needs to be modified to adapt to the CPU architecture. This results in poor application portability and a poor user experience. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for automatically deploying HMP architecture applications. For different SoC chips, executing the method of the present invention can automatically switch the thread to the core containing the acceleration instruction without additionally modifying the code of the corresponding application.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] A method for automatically deploying an HMP architecture application includes the following steps:

[0010] (1) The CPU has n cores, including core a with acceleration instructions and core b without acceleration instructions. The operating system randomly runs instructions on the n cores.

[0011] (2) When running general instructions to core b, the general instructions run smoothly;

[0012] (3) When the acceleration instruction is first executed on any b-core, the illegal instruction exception state is triggered, the illegal instruction exception handling function of the operating system is entered, the thread is bound to the a-core containing the acceleration instruction, and the thread is inserted into the run queue of the a-core;

[0013] (4) In core a, the thread is scheduled to execute and will continue to execute the second half of the illegal instruction exception handling function, that is, restore the thread's context segment code and return to the address where the acceleration instruction is located;

[0014] (5) When the acceleration instruction appears again, the acceleration instruction is executed on the bound core a.

[0015] Preferably, the general instructions include addition, subtraction, multiplication, division, left shift, and right shift instructions.

[0016] Preferably, the acceleration instruction is a special customized instruction, which is used to accelerate the execution of the program. The acceleration instruction can be a matrix multiplication instruction, which is an instruction that does not exist in the ARM and RISC-V architectures and is a customized instruction.

[0017] Preferably, in step (3), when entering the illegal instruction exception handling function of the operating system, the thread context segment code is first saved, then the current thread is bound to the core a containing the acceleration instruction, and finally the thread context is restored and the thread execution is returned to. The thread context refers to the contents of the CPU registers and program counter at a certain point in time.

[0018] Preferably, in step (3), the specific method of triggering the illegal instruction exception state is: when the CPU core runs an unsupported instruction, the CPU core triggers the exception state, and the program counter of the CPU core jumps to the exception handling function to run.

[0019] Preferably, in step (3), the specific method for binding the thread to the a core containing the acceleration instruction is: by querying the acceleration instruction status register in the CPU, obtaining the corresponding status value, and determining which cores are a cores containing the acceleration instruction and which cores are b cores without the acceleration instruction based on the status value.

[0020] Preferably, in step (3), the thread has been inserted into the run queue of core a. When the run queue of core a is idle, core a will immediately schedule the execution of the thread. When the run queue of core a is busy, the threads in the run queue will be scheduled for execution in sequence. When core a schedules the execution of the thread, it will execute the second half of the exception handling function described in step (3), that is, restore the thread context segment code, and after execution, it will return to the address where the acceleration instruction is located to run.

[0021] Preferably, if the number of a-cores in the CPU is greater than 1, all a-cores can execute acceleration instructions at the same time point, and the CPU can execute multiple acceleration instructions at the same time.

[0022] Due to the adoption of the above technical solution, the present invention has the following beneficial effects:

[0023] 1. When a process or thread that needs to use an acceleration instruction is deployed to a non-acceleration instruction CPU core, an illegal instruction exception will be triggered because the current CPU core does not support the acceleration instruction and enters the kernel exception interrupt. In the kernel illegal instruction exception handling function, the current thread is bound to the CPU core that supports the acceleration extension instruction. When the exception returns, the thread is directly switched to the CPU core that supports the acceleration extension instruction and runs normally.

[0024] 2. For different SoC chips, executing the method of the present invention can automatically switch the thread to the CPU core containing the acceleration instruction. The user programming does not need to care about the SoC chip architecture, and the application does not need to care about which CPU cores on the current SoC support acceleration instructions. There is no need to add additional self-binding code, and it can be executed directly, which is more convenient to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of a method for automatically deploying HMP architecture applications when a CPU executes a single thread. DETAILED DESCRIPTION

[0026] Example 1

[0027] like Figure 1 As shown, a method for automatically deploying HMP architecture applications includes the following steps:

[0028] (1) The CPU has 8 cores, including 4 a-cores with acceleration instructions and 4 b-cores without acceleration instructions. The operating system randomly runs instructions on the 8 cores.

[0029] (2) When a thread runs general instructions 1 to core b, the general instructions run smoothly. General instructions include addition, subtraction, multiplication, division, left shift, and right shift instructions.

[0030] (3) When the acceleration instruction 1 is run to the b core for the first time, an illegal instruction exception state is triggered, that is, when the b core in the CPU runs an unsupported instruction (such as the acceleration instruction in this embodiment), the CPU core triggers the exception state, and the program counter of the CPU core jumps to the exception handling function to run. The illegal instruction exception handling function of the operating system first saves the thread context segment code, then binds the current thread to the a core containing the acceleration instruction, and finally restores the thread context, returns to the thread execution, and binds the thread to the a core containing the acceleration instruction, that is, by querying the acceleration instruction status register in the CPU, the corresponding status value is obtained, and according to the status value, it is determined which cores are the a cores containing the acceleration instruction and which cores are the b cores without the acceleration instruction, and the thread is inserted into the running queue of the a core.

[0031] The thread context refers to the contents of the CPU registers and program counter at a certain point in time.

[0032] The status value has 32 bits, each bit representing whether each CPU core contains acceleration instructions. For example, if the status value is 0x00000001 and its bit 0 value is 1, it means that core 0 supports acceleration instructions, and cores 1 to 31 do not contain acceleration instructions. This is used to determine which cores contain acceleration instructions and which cores do not.

[0033] The illegal instruction exception handling function has different names in different operating systems. For example, in Linux, it is the do_trap_insn_illegal function.

[0034] In this embodiment, the acceleration instruction is a matrix multiplication instruction, which does not exist in the ARM and RISC architectures. It is a customized instruction designed to accelerate program execution. The principle of matrix multiplication operation is as follows:

[0035] Let A be an m×p matrix, B be a p×n matrix, and the m×n matrix C be the product of matrices A and B, denoted as C=A×B, where the element in the i-th row and j-th column of matrix C can be expressed as:

[0036]

[0037] As shown below:

[0038]

[0039]

[0040]

[0041] (4) The thread has been inserted into the run queue of core a. When the run queue of core a is idle, core a will immediately schedule the execution of the thread. When the run queue of core a is busy, the threads in the run queue will be scheduled and executed in order. When core a schedules the execution of the thread, it will execute the second half of the exception handling function described in step (3), that is, restore the thread context segment code. After execution, it will return to the address where the acceleration instruction is located. Figure 1 shown.

[0042] (5) Core a continues to run the instructions of the thread, such as general instruction 2 and acceleration instruction 2, while core b does not run any instructions of the thread. Core b can be idle or run instructions of other threads.

[0043] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications based on the present invention to solve substantially the same technical problems and achieve substantially the same technical effects are included within the scope of protection of the present invention.

Claims

1. A method for automatically deploying HMP architecture applications, characterized in that: The steps include: (1) The CPU has n cores, including core a with acceleration instructions and core b without acceleration instructions. The operating system randomly runs instructions on the n cores. (2) When running general instructions to core b, the general instructions run smoothly; (3) When the acceleration instruction is first executed on any b core, the illegal instruction exception state is triggered, the illegal instruction exception handling function of the operating system is entered, the thread is bound to the a core containing the acceleration instruction, and the thread is inserted into the run queue of the a core; (4) In the a core, the thread is scheduled for execution and will continue to execute the second half of the illegal instruction exception handling function, that is, restore the thread context segment code and return to the address where the acceleration instruction is located; (5) When the acceleration instruction appears again, the acceleration instruction is executed on the bound core a; wherein, when entering the illegal instruction exception handling function of the operating system, the thread context segment code is first saved, and then the current thread is bound to the core a containing the acceleration instruction, and finally the thread context is restored and the thread execution is returned to; the specific method of binding the thread to the core a containing the acceleration instruction is: by querying the acceleration instruction status register in the CPU, the corresponding status value is obtained, and according to the status value, it is determined which cores are the core a containing the acceleration instruction and which cores are the core b without the acceleration instruction; the thread has been inserted into the running queue of core a, when the running queue of core a is idle, core a will immediately schedule the execution of the thread, when the running queue of core a is busy, the threads in the running queue will be scheduled for execution in sequence, when core a schedules the execution of the thread, it will execute the second half of the exception handling function described in step (3), that is, restore the thread context segment code, and after execution, it will return to the address where the acceleration instruction is located to run; if the number of core a in the CPU is greater than 1, then all core a can execute the acceleration instruction at the same time point, and the CPU can execute multiple acceleration instructions at the same time.

2. The method for automatically deploying HMP architecture applications according to claim 1, characterized in that: The general instructions in step (2) include addition, subtraction, multiplication, division, left shift, and right shift instructions.

3. The method for automatically deploying HMP architecture applications according to claim 1, characterized in that: The acceleration instruction is a special customized instruction, which is used to accelerate the running of the program.

4. A method for automatically deploying HMP architecture applications according to claim 1, characterized in that: In step (3), the specific method of triggering the illegal instruction exception state is: when the CPU core runs an unsupported instruction, the CPU core triggers the exception state, and the program counter of the CPU core jumps to the exception handling function to run.

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