A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel is divided into a display area and a non-display area. The display area includes a central area and an edge area adjacent to the central area along a first direction. The non-display area includes a wiring area. The display panel includes: multiple data lines disposed within the display area, extending along a second direction and spaced apart along the first direction; multiple fan-out wirings disposed within the wiring area, arranged sequentially and spaced apart along the first direction and corresponding one-to-one with the multiple data lines, with one end of each fan-out wiring corresponding to and electrically connected to a data line of the same arrangement order; and multiple switching structures, at least disposed within the display area, wherein a portion of the switching structures connects the data lines in the edge area to the corresponding fan-out wirings, and another portion of the switching structures connects the data lines in the central area to the corresponding fan-out wirings. This invention provides a display panel and a display device that can achieve a narrow bezel design for the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for the screen ratio of display panels, and narrow bezel design has become a major development trend for display panels.

[0003] The non-display area of ​​a display panel typically includes a wiring area and a bonding area. The bonding area is used to bond the driver chip, and the wiring area is used to lay out fan-out traces, which are used to connect the data lines of the display area to the driver chip.

[0004] In existing display panels, to reduce the span of the trace area, jumper wiring is usually required for the fan-out traces within the trace area. Jumper wiring leads to the disordered arrangement of the fan-out traces, increasing the difficulty of aligning and binding the fan-out traces with the driver chip. At the same time, jumper wiring also increases the width of the trace area, causing the trace area to still occupy a large space and unable to be reduced, resulting in a large area of ​​non-display area and making it impossible to achieve a narrow bezel design. Summary of the Invention

[0005] The present invention provides a display panel and a display device that can realize a narrow bezel design for the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, the display panel being divided into a display area and a non-display area, the display area including a central region and an edge region adjacent to the central region along a first direction, the non-display area including a wiring area adjacent to one side of the display area along a second direction, the first direction and the second direction intersecting each other; the display panel includes:

[0007] Multiple data lines are located within the display area, extending along a second direction and spaced apart along a first direction;

[0008] Multiple fan-out traces are located within the trace area. These fan-out traces are arranged sequentially and at intervals along a first direction, each corresponding to a data line. Each fan-out trace corresponds to and is electrically connected to a data line in the same arrangement order.

[0009] Multiple switching structures are provided, at least within the display area. One part of the switching structures connects the data lines in the edge area to the corresponding fan-out routing lines, while the other part connects the data lines in the center area to the corresponding fan-out routing lines.

[0010] Optionally, all data lines in the edge area are electrically connected to the corresponding fan-out routing lines via a cable swap structure;

[0011] Each data line in the central area is electrically connected to its corresponding fan-out routing line through a switching structure; or, the data lines in the central area include a first data line and a second data line, wherein: the first data line and its corresponding fan-out routing line are staggered in the second direction, and the first data line and its corresponding fan-out routing line are electrically connected through a switching structure; the second data line and its corresponding fan-out routing line are aligned in the second direction, and the first end of the second data line and its corresponding fan-out routing line are directly electrically connected.

[0012] Optionally, the central region includes two first regions and a second region connected between the two first regions along the first direction, wherein the data lines of the first regions are first data lines and the data lines of the second regions are second data lines.

[0013] Optionally, each switching structure includes a second signal line and a first signal line that are electrically connected to each other; the second signal line extends along a second direction, and the first signal line extends along a first direction; the second signal line is located in the central area.

[0014] For the same cabling structure: the second signal line is electrically connected to the corresponding fan-out trace, and the first signal line is electrically connected to the corresponding data line.

[0015] Optionally, in the first direction, the arrangement order of each second signal line is the same as the arrangement order of the data lines electrically connected to it.

[0016] Optionally, in the first direction, the arrangement order of each second signal line and the data line not electrically connected to the switching structure is the same as the arrangement order of each second signal line connected to the data line and the data line not electrically connected to the switching structure.

[0017] Optionally, the first signal line and the data line can be set on different layers.

[0018] Optionally, the plurality of second signal lines include a first extended trace and a second extended trace, wherein:

[0019] The first extended trace is on a different layer from the data line, and the orthographic projection of the first extended trace on the film layer where the first data line is located overlaps with the first data line.

[0020] The orthographic projection of the second extended trace on the film layer where the data line is located is between two adjacent data lines.

[0021] Optionally, in the second signal lines corresponding to the data lines in the same edge region, the first extended trace and the second extended trace are arranged alternately;

[0022] Optionally, the spacing between two adjacent second signal lines in the first direction is less than the distance between two adjacent data lines in the first direction.

[0023] Optionally, the first extension trace and the second extension trace can be on different layers.

[0024] Optionally, the first extended trace is set on the same layer as the first signal line;

[0025] The second extension trace is on a different layer than the data line.

[0026] Optionally, the display area of ​​the display panel also includes multiple first virtual traces and multiple second virtual traces. The first virtual traces extend along the second direction and are located between two adjacent data lines. The second virtual traces extend along the first direction and are located between two adjacent rows of sub-pixels.

[0027] A portion of the multiple first virtual traces is configured as second signal lines, and a portion of the multiple second virtual traces is configured as first signal lines of the switching structure;

[0028] Another portion of the multiple first virtual traces and / or another portion of the multiple second virtual traces are electrically connected to other preset DC voltage traces in the display panel, which include at least one of the first power signal line, the second power signal line, and the initialization signal line.

[0029] Optionally, the dimension of the wiring area along the first direction is less than or equal to the dimension of the central area along the first direction.

[0030] Optionally, the fan-out routing trace is a straight line.

[0031] According to another aspect of the present invention, a display device is provided, the display device including the display panel provided in any embodiment of the present invention.

[0032] This embodiment provides a display panel in which data lines in the edge area are electrically connected to a portion of fan-out traces via a switching structure, and at least a portion of data lines in the central area are electrically connected to another portion of fan-out traces via the same switching structure. All fan-out traces can be arranged only in the non-display area adjacent to the central area, avoiding the fan-out traces from crossing into the non-display area adjacent to the edge area, thus reducing the non-display area occupied by the fan-out traces in the first direction. Furthermore, the arrangement order of multiple fan-out traces is the same as the arrangement order of the data lines, which avoids jumper processing between fan-out traces, further reducing the non-display area occupied by the fan-out traces in the second direction, reducing the size of the non-display area in the second direction, and realizing the narrow bezel design of the display panel.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art;

[0036] Figure 2 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art, for reference. Figure 1 The display panel includes a central region 11 and two edge regions 12 located on either side of the central region 11 in a first direction X. The display area also includes multiple second transmission lines 10 extending along the first direction X, multiple first transmission lines 20 extending along the second direction Y, and multiple data lines 30 extending along the second direction Y and connected to sub-pixel columns. The data lines 30 of the edge regions 12 are connected to the first transmission lines 20 of the central region 11 via the second transmission lines 10. This connection method results in a different arrangement order of the first transmission lines 20 connected to the data lines 30 of the edge regions 12 and the data lines 30 located in the central region 11 in the first direction X compared to the arrangement order of their respective connected sub-pixel columns in the first direction X. See details below. Figure 1 The order of the sub-pixel columns in the first direction X is: N1, N2, N3, N4, N5, N6, N7, N8, N9, N10. It can be seen that the sub-pixel columns are arranged sequentially. However, the order of the first transmission line 20 connected to the data line 30 and the data line 30 located in the central region 11 in the first direction X is: M1, M3, M2, M4, M5, M6, M9, M7, M10, M8. This arrangement is out of order. The arrangement order of the ports connected to the data line 30 in the display panel's driver chip is the same as the sub-pixel column arrangement order. Therefore, when the first transmission line 20 and the data line 30 in the central region 11 are connected to the driver chip, jumper wiring is required. After jumper wiring, the first transmission line 20 can be connected to its corresponding port in the driver chip, and the data line in the central region 11 can be connected to its corresponding port in the driver chip, ultimately allowing the sub-pixel columns to receive their corresponding data signals. Jumper wiring requires a large amount of space in the non-display area, resulting in a large non-display area on the display panel, making it impossible to achieve a narrow bezel design.

[0044] To address the issue of large bezels on display panels, this embodiment provides a display panel that allows for a narrower bezel design. Figure 2 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention, with reference to... Figure 2The display panel provided in this embodiment is divided into a display area 100 and a non-display area 400. The display area 100 includes a central area 200 and an edge area 300 adjacent to the central area 200 along a first direction X. The non-display area 400 includes a wiring area 401, which is adjacent to the central area 200 of the display area 100 along a second direction Y. The display panel includes: multiple data lines 110 disposed within the display area 100, the data lines 110 extending along the second direction Y and spaced apart along the first direction X; the first direction X and the second direction Y intersect each other; multiple fan-out wiring... Line 410 is disposed in the wiring area 401. Multiple fan-out wiring lines 410 are arranged sequentially at intervals along the first direction X and correspond one-to-one with multiple data lines 110. Each fan-out wiring line 410 corresponds to and is electrically connected to the data lines 110 arranged in the same order. In addition, multiple switching structures 210 are disposed at least in the display area 100. A portion of the switching structures 210 are connected between the data lines 110 in the edge area 300 and the corresponding fan-out wiring lines 410, and another portion of the switching structures 210 are connected between the data lines 110 in the center area 200 and the corresponding fan-out wiring lines 410.

[0045] Specifically, the display panel includes a substrate 101, which includes a display area 100 and a non-display area 400. Multiple fan-out traces 410 are electrically connected to data lines 110 in a one-to-one correspondence. Specifically, some fan-out traces 410 have their first ends electrically connected to data lines 110 via a switching structure 210; some fan-out traces 410 have their first ends directly connected to data lines 110; or all fan-out traces 410 have their first ends electrically connected to data lines 110 via the switching structure 210.

[0046] The second end of all fan-out traces 410 is directly electrically connected to the driver chip 102.

[0047] The switching structure 210 may include a conductor extending in the first direction X and a conductor extending in the second direction Y. All switching structures 210 are connected to the fan-out trace 410 via the central region 200. The fan-out trace 410 may be located only in the non-display area 400 adjacent to the central region 200, avoiding the fan-out trace 410 from crossing into the non-display area 400 adjacent to the edge region 300, reducing the space occupied by the fan-out trace 410 in the non-display area 400, and thus reducing the bezel of the display panel.

[0048] The arrangement order of the multiple fan-out traces 410 is the same as the arrangement order of the data lines 110. That is, the arrangement order of the first ends and the second ends of the multiple fan-out traces 410 are the same as the arrangement order of the data lines 110. For example, in the first direction X, the numbering order of each data line 110 is 1-10. In the same direction, the numbering order of the first ends and the second ends of each fan-out trace 410 is also 1-10. With this configuration, there is no need to perform jumper processing on the fan-out traces 410 in the non-display area 400. The fan-out traces 410 that do not require jumper processing can occupy a smaller area in the second direction Y. Therefore, the display panel provided in this embodiment can reduce the size of the non-display area 400 in the second direction Y, reduce the size of the display panel bezel, achieve a narrow bezel design, and at the same time, it does not increase the bonding difficulty of the fan-out traces and the driver chip.

[0049] This embodiment provides a display panel in which data lines in the edge area are electrically connected to a portion of fan-out traces via a switching structure, and at least a portion of data lines in the central area are electrically connected to another portion of fan-out traces via the same switching structure. All fan-out traces can be arranged only in the non-display area adjacent to the central area, avoiding the fan-out traces from crossing into the non-display area adjacent to the edge area, thus reducing the non-display area occupied by the fan-out traces in the first direction. Furthermore, the arrangement order of multiple fan-out traces is the same as the arrangement order of the data lines, which avoids jumper processing between fan-out traces, further reducing the non-display area occupied by the fan-out traces in the second direction, reducing the size of the non-display area in the second direction, and realizing the narrow bezel design of the display panel.

[0050] Optional, Figure 3 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention, with reference to... Figure 3 Each switching structure 210 includes a second signal line 120 and a first signal line 130 that are electrically connected to each other; the second signal line 120 extends along a second direction Y, and the first signal line 130 extends along a first direction X; the second signal line 120 is located in the central area; for the same switching structure 210: the second signal line 120 is electrically connected to the corresponding fan-out trace 410, and the first signal line 130 is electrically connected to the corresponding data line 110.

[0051] Specifically, the materials of the second signal line 120 and the first signal line 130 can be the same as or different from the material of the data line 110. The second signal line 120 can be parallel to the data line 110, and the first signal line 130 can intersect the data line 110, for example, they can be perpendicular to each other. The length of the second signal line 120 can be equal to, greater than, or less than the length of the data line 110.

[0052] The second signal line 120 and the data line 110 can be on different layers or on the same layer. The display panel provided in this embodiment also includes sub-pixel columns, each sub-pixel column being connected to a data line 110. Each sub-pixel column includes a plurality of sub-pixels 140 arranged sequentially along the second direction Y. The correspondence between the sub-pixel columns and the second signal line 120 is not specifically limited in this embodiment. The position and number of the second signal line 120 can be set according to actual needs. For example, one or more second signal lines 120 can be set between some adjacent sub-pixel columns, and no second signal lines 120 can be set between some adjacent sub-pixel columns. Alternatively, one or more second signal lines 120 can be set for each sub-pixel column.

[0053] Similarly, one or more first signal lines 130 may be set between some adjacent sub-pixel rows, while no first signal lines 130 may be set between some adjacent sub-pixel rows; or one or more first signal lines 130 may be set for each sub-pixel row. The correspondence between sub-pixel rows and first signal lines 130 is not specifically limited in this embodiment, and the position and number of first signal lines 130 may be set according to actual needs.

[0054] The first signal line 130 and the data line 110 are set to be on different layers. The specific connection method between the first signal line 130 and the data line 110 can be: the first signal line 130 is connected to the data line 110 through a through hole provided on the film layer between the first signal line 130 and the data line 110.

[0055] In this embodiment, at least some of the second signal lines 120 can be set to different layers from the first signal lines 130, thereby making the wiring method of the second signal lines 120 more flexible and the wiring position easier to adjust.

[0056] Specifically, the connection method between the first signal line 130 and the second signal line 120 can be as follows: when the first signal line 130 and the second signal line 120 are not on the same layer, the first signal line 130 is connected to the second signal line 120 through a through hole provided on the film layer between the first signal line 130 and the second signal line 120; when the first signal line 130 and the second signal line 120 are on the same layer, the first signal line 130 is directly in contact with the second signal line 120.

[0057] Optional, continue to refer to Figure 3 In the first direction X, the arrangement order of each second signal line 120 is the same as the arrangement order of the data lines 110 that are electrically connected to it.

[0058] Specifically, if the arrangement order of the second signal lines 120 along the first direction X is 1, 2, 3, 4, 5, then among the data lines 110 electrically connected to each second signal line 120 along the first direction X, the data lines 110 electrically connected to the second signal line 120 with the arrangement order 1 are arranged in the order 1, the data lines 110 electrically connected to the second signal line 120 with the arrangement order 2 are arranged in the order 2, and so on, until the data lines 110 electrically connected to the second signal line 120 with the arrangement order 5 are arranged in the order 5. This configuration eliminates the need for jumper wiring on the fan-out traces 410 when the second signal lines 120 are electrically connected to them, thus achieving a narrow bezel design for the display panel.

[0059] Optional, continue to refer to Figure 3 In the first direction X, the arrangement order of each second signal line 120 and the data line 110 not electrically connected to the switching structure 210 is the same as the arrangement order of each second signal line 120 connected to the data line 110 and the data line 110 not electrically connected to the switching structure 210.

[0060] Specifically, the data line 110 corresponding to the second signal line 120 is the data line 110 electrically connected to the second signal line 120, and the data line 110 corresponding to the data line 110 not electrically connected to the switching structure 210 is itself.

[0061] If the arrangement of each second signal line 120 and the data line 110 not electrically connected to the switching structure 210 in the first direction X is sequential, then the arrangement of the data line 110 corresponding to the second signal line 120 and the data line 110 not electrically connected to the switching structure 210 in the first direction X is also sequential. For example, along the first direction X, each second signal line 120 and data line 110 not electrically connected to the switching structure 210 are arranged. If arrangement order 1 corresponds to the second signal line 120, arrangement order 2 corresponds to the second signal line 120, arrangement order 3 corresponds to the data line 110 not electrically connected to the switching structure 210, arrangement order 4 corresponds to the data line 110 not electrically connected to the switching structure 210, then along the first direction X, the arrangement order of the data line 110 corresponding to the second signal line 120 with arrangement order 1 is also 1, the arrangement order of the data line 110 corresponding to the second signal line 120 with arrangement order 2 is also 2, the arrangement order of the data line 110 corresponding to the data line 110 not electrically connected to the switching structure 210 with arrangement order 3 is also 3... With this setting, there is no need to fan out the trace 410 to perform jumper processing in the non-display area 400, thus realizing the narrow bezel design of the display panel. Optionally, all data lines in the edge area are electrically connected to their corresponding fan-out traces via a switching structure. Each data line in the central area is electrically connected to its corresponding fan-out trace via a switching structure; or, the data lines in the central area include a first data line and a second data line, wherein: the first data line and its corresponding fan-out trace are staggered in the second direction, and the first data line and its corresponding fan-out trace are electrically connected via a switching structure; the second data line and its corresponding fan-out trace are aligned in the second direction, and the first end of the second data line and its corresponding fan-out trace are directly electrically connected; the arrangement order of all second signal lines and second data lines in the first direction is the same as the arrangement order of the data lines in the display area.

[0062] Specifically, all data lines in the display panel can be electrically connected to the corresponding fan-out traces via a cable swapping structure. Alternatively, all data lines in the edge area can be electrically connected to the corresponding fan-out traces via a cable swapping structure, some data lines in the central area can be directly connected to the corresponding fan-out traces, and another portion of the data lines in the central area can be electrically connected to the corresponding fan-out traces via a cable swapping structure.

[0063] The following explanation uses a display panel where some data lines in the central area are directly electrically connected to the corresponding fan-out traces as an example:

[0064] Continue to refer to Figure 3In the central region 200, the data line 110 electrically connected to the second signal line 120 is the first data line 111, and the data line 110 not electrically connected to the second signal line 120 is the second data line 112. The first data line 111 and its corresponding fan-out trace 410 are staggered in the second direction Y, meaning that after the first data line 111 is extended along the second direction Y, it does not intersect with its corresponding fan-out trace 410. The second data line 112 and its corresponding fan-out trace 410 are aligned in the second direction Y, meaning that the second data line 112 intersects with its corresponding fan-out trace 410 along the second direction Y, or the second data line 112 intersects with its corresponding fan-out trace 410 after being extended along the second direction Y.

[0065] exist Figure 3 In the diagram, the intersection of data line 110 and sub-pixel 140 is circular, while the intersection of first signal line 130, second signal line 120, and data line 110 is quadrilateral. Each first signal line 130 has two quadrilateral intersections. Figure 3 It can be seen that the arrangement order of the second signal line 120 connected to the data line 110 in the edge region 300, the second signal line 120 connected to the first data line 111, and the second data line 112 in the first direction X is: S1, S2, S3, S4, S5, S6, S7, S8, S9, S10. From Figure 3 It can also be seen that the data lines 110, 111, and 112 in the edge region 300 and their respective connected sub-pixel columns are arranged in the first direction X as follows: P1, P2, P3, P4, P5, P6, P7, P8, P9, P10. It can be seen that the arrangement order of the sub-pixel columns in the first direction X is the same as the arrangement order of the input terminals that receive the data signals. The arrangement order of the ports connected to the data lines on the driver chip 102 in the non-display area 400 of the display panel is the same as the arrangement order of the sub-pixel columns. Therefore, the display panel provided in this embodiment does not need to perform jumper processing on the fan-out traces 410 in the non-display area 400, thereby saving the space required for jumpers, reducing the space occupied by the fan-out traces 410 in the non-display area 400 in the second direction Y, and reducing the bezel of the display panel.

[0066] Optional, continue to refer to Figure 3 The central region 200 includes two first regions and a second region connected between the two first regions along the first direction X. The data lines of the first regions are configured as first data lines 111, and the data lines of the second regions are configured as second data lines 112.

[0067] Specifically, Figure 3 In the middle, the two first regions are the regions where sub-pixel columns P3 and P4 are located and the regions where sub-pixel columns P7 and P8 are located, respectively.

[0068] Optional, Figure 4 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention, with reference to... Figure 4 Multiple second signal lines 120 include a first extended trace 121 or a second extended trace 122; the first extended trace 121 is on a different layer from the data line 110.

[0069] Specifically, the first extension trace 121 and the data line 110 are on different layers, which allows for more flexible routing of the first extension trace 121.

[0070] For example, the orthographic projection of the first extended trace 121 onto the substrate 101 can cover the data line 110, or it can have a small gap with the data line 110 in the first direction X. This makes it easier to set the position of the first extended trace 121 connected to the data line 110 of the edge region 300 and the first extended trace 121 connected to the first data line 111. It also makes it easier to adjust the arrangement order of the second signal line 120 connected to the data line 110 of the edge region 300, the second signal line 120 connected to the first data line 111, and the second data line 112 in the first direction X. This ensures that the arrangement order of the second signal line 120 connected to the data line 110 of the edge region 300, the second signal line 120 connected to the first data line 111, and the second data line 112 in the first direction X is the same as the arrangement order of the sub-pixel columns they are connected to in the first direction X.

[0071] It should be noted that, in Figure 4 In this embodiment, the intersection of the first signal line 130 and the first extended trace 121 is elliptical, and the intersection of the first signal line 130 and the second extended trace 122 is quadrilateral. In terms of film layer location, the first extended trace 121 and the first signal line 130 can be located on the same side of the data line 110. For example, the first extended trace 121 and the first signal line 130 can both be located on the side of the data line 110 adjacent to the substrate 101, or both can be located on the side of the data line 110 away from the substrate 101. The specific film layer location is not specifically limited in this embodiment.

[0072] It should also be noted that the length of the first signal line 130 can be equal to the length of the scan line electrically connected to the sub-pixel row, and the length of the second signal line 120 can be equal to the length of the data line 110. After the first signal line 130 intersects with the second signal line 120, there can be no break in the first signal line 130 (see reference). Figure 4 It can also have a break (see reference). Figure 5 Similarly, the second signal line 120 can be without a break (see reference). Figure 4 It can also have a break (see reference). Figure 5 (Optional, please refer to further information.) Figure 4The orthographic projection of the first extended trace 121 on the film layer where the first data line 111 is located overlaps with the first data line 111; the orthographic projection of the second extended trace 122 on the film layer where the data line 110 is located is between two adjacent data lines 110. Specifically, the orthographic projection of the first extended trace 121 overlaps with the orthographic projection of the first data line 111, that is, the orthographic projection of the first extended trace 121 on the substrate 101 is located at the data line 110 connected to other second signal lines 120. This arrangement makes the spacing in the first direction X between the first extended trace 121 connected to the first data line 111, the second extended trace 122 connected to the first data line 111, and the second data line 112 relatively uniform, which facilitates its connection with the driver chip.

[0073] It should be noted that the orthographic projection of each second extended trace 122 on the substrate 101 is located between the orthographic projections of two adjacent data lines 110 on the substrate 101. In the first direction X, the distance between the second extended trace 122 and its adjacent data line 110 can be equal. The length of the first extended trace 121 can be less than the length of the data line 110, and the connection point between the first signal line 130 and the first extended trace 121 can be one end of the first extended trace 121. The length of the second extended trace 122 can be equal to or similar to the length of the data line 110.

[0074] Optional, continue to refer to Figure 4 In the second signal line 120 corresponding to the data line 110 in the same edge region 300, the first extended trace 121 and the second extended trace 122 are arranged alternately. Since the spacing between the first extended trace 121 and the second extended trace 122 is small, this arrangement reduces the spacing between adjacent second signal lines 120, thereby reducing the spacing between the fan-out traces 410 electrically connected to the second signal lines 120, and further reducing the size of the wiring area 401 in the first direction X, achieving a narrow bezel design for the display panel. Furthermore, the alternating arrangement of the first extended trace 121 and the second extended trace 122 makes the arrangement of the second signal lines 120 more uniform, and the arrangement of the fan-out traces 410 more uniform, making wiring easier.

[0075] In addition, the first extension trace 121 and the second extension trace 122 can be on different layers, which helps to ensure the electrical distance between the first extension trace 121 and the second extension trace 122 and avoid interference.

[0076] Optional, continue to refer to Figure 4The spacing between two adjacent second signal lines 120 in the first direction X is smaller than the distance between two adjacent data lines 110 in the first direction X. This setting can reduce the spacing between the fan-out traces 410 electrically connected to the second signal lines 120, thereby reducing the size of the non-display area 400 in the first direction X and realizing the narrow bezel design of the display panel.

[0077] Optionally, the first extended trace 121 and the first signal line 130 are set on the same layer.

[0078] Specifically, the first extended trace 121 and the first signal line 130 are on the same layer, which reduces the number of film layers in the display panel and ensures that the display panel has a smaller thickness. In addition, the first extended trace 121 and the first signal line 130 can be made of the same material. With this configuration, the first extended trace 121 and the first signal line 130 can be manufactured in the same process, thereby improving the manufacturing efficiency of the display panel and reducing the manufacturing process cost of the display panel.

[0079] Optionally, the second extension trace 122 and the data line 110 are on different layers.

[0080] For details, please refer to Figure 4 Setting the second extension trace 122 to a different layer from the data line 110 increases the flexibility of the second extension trace 122 in wiring. The second extension trace 122 can be set at any position in the first direction X according to wiring needs, which can reduce wiring difficulty and manufacturing process difficulty.

[0081] Optional, continue to refer to Figure 4 The lengths of the multiple second extension traces 122 are equal; the lengths of the multiple first signal lines 130 are equal. This configuration reduces the manufacturing difficulty of the second extension traces 122 and the first signal lines 130.

[0082] Optional, continue to refer to Figure 4 The display area 100 of the display panel also includes multiple first virtual traces 123 and multiple second virtual traces 124. The first virtual traces 123 extend along the second direction Y and are located between two adjacent data lines 110. The second virtual traces 124 extend along the first direction X and are located between two adjacent rows of sub-pixels. A portion of the multiple first virtual traces 123 is configured as a second signal line 120, and a portion of the multiple second virtual traces 124 is configured as a first signal line 130 of the line switching structure 210. Another portion of the multiple first virtual traces 123 and / or another portion of the multiple second virtual traces 124 are electrically connected to other preset DC voltage traces in the display panel. The other preset DC voltage traces are connected to at least one of a first power signal line, a second power signal line, and an initialization signal line.

[0083] Specifically, by setting a first virtual trace 123 between any two adjacent data lines 110, each data line 110 can correspond to two first virtual traces 123, so that the interference experienced by each data line 110 is basically similar, thereby making the changes in data signals basically similar and ensuring the uniformity of the display panel.

[0084] Similarly, each sub-pixel row is provided with a second virtual trace 124, so that the number of second virtual traces 124 intersecting with each data line 110 is the same, so that the interference on the data signal in the data line 110 is basically similar, thereby making the changes in the data signal basically similar and ensuring the display uniformity of the display panel.

[0085] Of the multiple first virtual traces 123, the one electrically connected to the fan-out trace 410 is the second signal line 120 in the switching structure 210. Of the multiple second virtual traces 124, the one electrically connected to the fan-out trace 410 is the first signal line 130 of the switching structure 210. The first virtual traces 123 and second virtual traces 124 that are not electrically connected to the fan-out trace 410 are electrically connected to other preset DC voltage traces.

[0086] The first power signal line is used to receive the first power signal, the second power signal line is used to receive the second power signal, and the initialization signal line is used to receive the initialization signal. The first power signal and the second power signal are the power signals received by the two ends of the series-connected driving transistor and the light-emitting diode respectively when the light-emitting diode in the sub-pixel emits light. The initialization signal includes the signal in the driving circuit of the sub-pixel that initializes the gate potential of the driving transistor or the anode of the light-emitting diode. By setting the first virtual trace 123 and the second virtual trace 124, which are not electrically connected to the fan-out trace 410, to be electrically connected to the preset DC voltage trace, it is possible for both the first virtual trace 123 and the second virtual trace 124, which are not electrically connected to the fan-out trace 410, to receive the preset DC voltage signal. This ensures that each first virtual trace 123 and each second virtual trace 124 transmits a signal, further ensuring that the interference experienced by each data line 110 of the display panel is similar, and improving the display uniformity of the display panel.

[0087] Optional, Figure 6 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention, with reference to... Figure 6 The dimension of the wiring area 401 along the first direction X is less than or equal to the dimension of the central area 200 along the first direction X. In this embodiment of the invention, the space occupied by the wiring area 401 in the non-display area 400 along both the first direction X and the second direction Y is relatively small, which can reduce the size of the non-display area 400 and the bezel size of the display panel, thereby achieving a narrow bezel design.

[0088] Optional, continue to refer to Figure 6 The wiring area 401 is fan-shaped.

[0089] Specifically, the fan-shaped shape of the wiring area 401 can reduce the area occupied by the wiring area, thereby reducing the area of ​​the non-display area 400 and achieving a narrower bezel design.

[0090] Optional, continue to refer to Figure 6 The routing area 401 includes a first sub-routing area 402 and a second sub-routing area 403 arranged sequentially along the first direction X. The fan-out routing lines 410 in the first sub-routing area 402 and the fan-out routing lines 410 in the second sub-routing area 403 are symmetrical to each other.

[0091] Specifically, the number of fan-out traces 410 in the first sub-routing area 402 is equal to the number of fan-out traces 410 in the second sub-routing area 403. By setting the fan-out traces 410 in the first sub-routing area 402 and the second sub-routing area 403 to be symmetrical, the area occupied by the first sub-routing area 402 and the area occupied by the second sub-routing area 403 can be the same and both are small, further reducing the area of ​​the routing area 401.

[0092] Optional, continue to refer to Figures 3-6 The extended trajectory of the fan-out routing line 410 is a straight line.

[0093] Specifically, setting the extension trajectory of the fan-out trace 410 to a straight line can reduce the area occupied by the fan-out trace 410, and further reduce the area of ​​the trace area 401. For example, when the extension trajectory of the fan-out trace 410 is a straight line, the extension direction of the fan-out trace 410 can be parallel or approximately parallel to the second direction Y.

[0094] Optional, continue to refer to Figure 6 The second signal line 120 and the second data line 112, which are connected to the data line 110, are both connected to the driver chip 102 through the fan-out trace 410.

[0095] Specifically, the driver chip 102 is used to output data signals to the data line 110. The second signal line 120, which is connected to the driver chip 102, can transmit the data signals output by the driver chip 102 to the data line 110 connected to it. The second data line 112 is directly connected to the driver chip 102 through the fan-out trace 410, and the second data line 112 directly obtains the data signals output by the driver chip 102 through the fan-out trace 410.

[0096] This embodiment also provides a display device, which includes the display panel provided in any embodiment of the present invention.

[0097] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0098] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, divided into a display area and a non-display area, characterized in that, The display area includes a central area and an edge area adjacent to the central area along a first direction; the non-display area includes a wiring area, which is adjacent to one side of the display area along a second direction, wherein the first direction and the second direction intersect each other; the display panel includes: Multiple data lines are provided within the display area, and the data lines extend along the second direction and are spaced apart along the first direction; Multiple fan-out traces are disposed within the trace area. These fan-out traces are arranged sequentially at intervals along the first direction and correspond one-to-one with multiple data lines. Each fan-out trace corresponds to and is electrically connected to a data line arranged in the same order. Multiple switching structures are provided at least within the display area, wherein a portion of the switching structures are connected between the data lines in the edge area and the corresponding fan-out traces, and another portion of the switching structures are connected between the data lines in the center area and the corresponding fan-out traces. Each of the aforementioned switching structures includes a second signal line and a first signal line electrically connected to each other; the second signal line extends along a second direction, and the first signal line extends along the first direction; the second signal line is located within the central region; The central region includes two first regions and a second region connected between the two first regions along the first direction, and the data line of the first region is a first data line; The plurality of second signal lines include a first extended trace and a second extended trace, wherein: The first extended trace is on a different layer from the data line, and the orthographic projection of the first extended trace on the film layer where the first data line is located overlaps with the first data line. The orthographic projection of the second extended trace on the film layer containing the data line is located between two adjacent data lines; In the first direction, the distance between the second extended trace and its adjacent data line is equal; The first extended trace and the second extended trace are on different layers.

2. The display panel according to claim 1, characterized in that, All data lines in the edge region are electrically connected to the corresponding fan-out routing lines through the cable switching structure. Each data line in the central region is electrically connected to the corresponding fan-out trace via the switching structure; or, the data lines in the central region include a first data line and a second data line, wherein: the first data line and its corresponding fan-out trace are staggered in the second direction, and the first data line and its corresponding fan-out trace are electrically connected via the switching structure; the second data line and its corresponding fan-out trace are aligned in the second direction; and the first end of the second data line and its corresponding fan-out trace are directly electrically connected.

3. The display panel according to claim 1, characterized in that, The data line in the second area is the second data line.

4. The display panel according to claim 1 or 2, characterized in that, For the same switching structure: the second signal line is electrically connected to the corresponding fan-out trace, and the first signal line is electrically connected to the corresponding data line.

5. The display panel according to claim 4, characterized in that, In the first direction, the arrangement order of each of the second signal lines is the same as the arrangement order of the data lines that are electrically connected to them.

6. The display panel according to claim 4, characterized in that, In the first direction, the arrangement order of each second signal line and the data line not electrically connected to the switching structure is the same as the arrangement order of each second signal line connected to the data line and the data line not electrically connected to the switching structure.

7. The display panel according to claim 1, characterized in that, The first signal line is disposed on a different layer than the data line.

8. The display panel according to claim 1, characterized in that, In the second signal line corresponding to the data line in the same edge region, the first extended trace and the second extended trace are arranged alternately.

9. The display panel according to claim 1, characterized in that, The spacing between two adjacent second signal lines in the first direction is less than the distance between two adjacent data lines in the first direction.

10. The display panel according to claim 1, characterized in that, The first extended trace is disposed on the same layer as the first signal line; The second extended trace is on a different layer than the data line.

11. The display panel according to claim 1, characterized in that, The display area of ​​the display panel also includes multiple first virtual traces and multiple second virtual traces. The first virtual traces extend along the second direction and are located between two adjacent data lines. The second virtual traces extend along the first direction and are located between two adjacent rows of sub-pixels. A portion of the multiple first virtual traces is configured as the second signal line, and a portion of the multiple second virtual traces is configured as the first signal line of the switching structure; Another portion of the first virtual traces and / or another portion of the second virtual traces are electrically connected to other preset DC voltage traces in the display panel, wherein the other preset DC voltage traces include at least one of a first power signal line, a second power signal line, and an initialization signal line.

12. The display panel according to claim 1, characterized in that, The dimension of the wiring area along the first direction is less than or equal to the dimension of the central area along the first direction.

13. The display panel according to claim 1, characterized in that, The extension trajectory of the fan-out routing line is a straight line.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

Images