Shift register and driving method thereof, scan drive circuit and display panel

Abstract

The present invention discloses a shift register and a driving method thereof, a scan drive circuit and a display panel. The shift register includes: a first input module, a second input module, an interlocking module, a first output module and a second output module. The first input module transmits a first level to a first node under the control of a signal connected to the input end, the second input module transmits a second level to a second node under the control of a signal connected to the input end and a clock signal connected to the first clock signal end, the interlocking module controls the level of one of the first node and the second node in response to the level of the other, the first output module transmits the level of a clock signal connected to the second clock signal end to the output end in response to the first level of the first node, and the second output module transmits the level of a power signal connected to the first power signal end to the output end in response to the second level of the second node, so as to achieve reliable and stable output of the scan signal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register and a driving method thereof, a scan driving circuit and a display panel. Background Art

[0002] Display panels typically include a scan driver circuit, which includes a multi-stage shift register. This multi-stage shift register is used to provide scan signals to the pixel circuits of multiple rows of sub-pixels, enabling progressive scanning of the sub-pixels. Therefore, providing a stable and reliable shift register is key to ensuring the display quality of the display panel. Summary of the Invention

[0003] The invention discloses a shift register and a driving method thereof, a scanning driving circuit and a display panel, so as to provide a stable and reliable shift register.

[0004] In a first aspect, the present invention discloses a shift register, comprising:

[0005] a first input module, the first input module being electrically connected to at least the input terminal and the first node, and configured to transmit a first electrical level to the first node under the control of a signal input to the input terminal;

[0006] a second input module, the second input module being electrically connected to at least the input terminal, the second node, and the first clock signal terminal, and configured to transmit the second level of the clock signal received at the first clock signal terminal to the second node under the control of at least a signal received at the input terminal and a clock signal received at the first clock signal terminal;

[0007] An interlocking module, the interlocking module being electrically connected to at least the first node and the second node, the interlocking module being configured to transmit a third level, which is logically opposite to the second level, to the second node in response to at least a first level of the first node, and to transmit a fourth level, which is logically opposite to the first level, to the first node in response to at least a second level of the second node;

[0008] a first output module, the first output module being electrically connected to the second clock signal terminal and the output terminal, and configured to transmit the level of the clock signal connected to the second clock signal terminal to the output terminal in response to the first level of the first node;

[0009] The second output module is electrically connected to the second node, the first power signal terminal and the output terminal. The second output module is used to transmit the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node.

[0010] Optionally, the first input module is used to transmit the first level of the signal connected to the input end to the first node under the control of the signal connected to the input end; or, the first input module is also electrically connected to the second power signal end or the first clock signal end, and the first input module is used to transmit the second level of the clock signal connected to the first clock signal end or the level of the power signal connected to the second power signal end as the first level to the first node under the control of the signal connected to the input end.

[0011] Optionally, the first input module includes a first transistor; the gate and the first pole of the first transistor are electrically connected to the input end, and the second pole of the first transistor is electrically connected to the first node; or, the gate of the first transistor is electrically connected to the input end, the first pole of the first transistor is electrically connected to the second power supply signal end or the first clock signal end, and the second pole of the first transistor is electrically connected to the first node.

[0012] Optionally, the first transistor includes a dual-gate transistor.

[0013] Optionally, the second input module includes a first input unit and a second input unit; the control end of the first input unit is electrically connected to the input end, the first end of the first input unit is electrically connected to the first power signal end or the second clock signal end, and the first input unit is used to transmit the level of the power signal connected to the first power signal end or the clock signal connected to the second clock signal end to the second end of the first input unit under the control of the signal connected to the input end; the second input unit is electrically connected to the second end of the first input unit, the second node and the first clock signal end, and the second input unit is used to transmit the second level of the clock signal connected to the first clock signal end to the second node under the control of the level of the second end of the first input unit and the signal connected to the first clock signal end.

[0014] Optionally, the first input unit includes a second transistor, the second input unit includes a third transistor and a first capacitor; the gate of the second transistor is electrically connected to the input end, the first pole of the second transistor is electrically connected to the first power supply signal end or the second clock signal end, and the second pole of the second transistor is the second end of the first input unit; the gate of the third transistor is electrically connected to the second end of the first input unit, the first pole of the third transistor is electrically connected to the first clock signal end, and the second pole of the third transistor is electrically connected to the second node; the first pole of the first capacitor is electrically connected to the first pole of the third transistor, and the second pole of the first capacitor is electrically connected to the gate of the third transistor.

[0015] Optionally, the second transistor and / or the third transistor includes a dual-gate transistor.

[0016] Optionally, the interlocking module includes a first adjustment unit and a second adjustment unit; the first adjustment unit is electrically connected to at least the first power signal terminal, the first node and the second node, and the first adjustment unit is used to transmit the level of the first power signal terminal as a third level to the second node in response to at least the first level of the first node; the second adjustment unit is electrically connected to at least the first power signal terminal, the first node and the second node, and the second adjustment unit is used to transmit the level of the power signal connected to the first power signal terminal as a fourth level to the first node in response to at least the second level of the second node.

[0017] Optionally, the first adjustment unit includes a fourth transistor, and the second adjustment unit includes a fifth transistor; the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the first power supply signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node; the gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first power supply signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node.

[0018] Optionally, the fourth transistor and / or the fifth transistor includes a dual-gate transistor.

[0019] Optionally, the first output module includes a sixth transistor, the gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the output terminal; the first output module also includes a second capacitor, the first electrode of the second capacitor is electrically connected to the first electrode of the sixth transistor, and the second electrode of the second capacitor is electrically connected to the gate of the sixth transistor; the second output module includes a seventh transistor, the gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first power supply signal terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal; the second output module also includes a third capacitor, the first electrode of the third capacitor is electrically connected to the first electrode of the seventh transistor, and the second electrode of the third capacitor is electrically connected to the gate of the seventh transistor.

[0020] Optionally, a protection module is further included, which is connected between the first node and the first output module. The protection module is used to transmit the first level of the first node to the first output module under the control of the power signal connected to the second power signal terminal.

[0021] Optionally, the protection module includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first node, a gate of the eighth transistor is electrically connected to the second power signal terminal, and a second electrode of the eighth transistor is electrically connected to the first output module.

[0022] Optionally, the first adjustment unit is also electrically connected to the first clock signal terminal, and the first adjustment unit is used to transmit the level of the first power signal terminal as the third level to the second node in response to the first level of the first node and the second level of the first clock signal terminal; the second adjustment unit is also electrically connected to the first clock signal terminal, and the second adjustment unit is used to transmit the level of the power signal connected to the first power signal terminal as the fourth level to the first node in response to the second level of the second node and the second level of the first clock signal terminal.

[0023] Optionally, the first adjustment unit also includes a ninth transistor, and / or the second adjustment unit also includes a tenth transistor; the gate of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the second electrode of the fourth transistor; or, the gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first power supply signal terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the fourth transistor; the gate of the tenth transistor is electrically connected to the second clock signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second electrode of the fifth transistor; or, the gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the first power supply signal terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the fifth transistor.

[0024] Optionally, one of the levels of the power signal connected to the first power signal terminal and the power signal connected to the second power signal terminal is a high level, and the other is a low level; and / or, the first clock signal connected to the first clock signal terminal and the second clock signal connected to the second clock signal terminal have the same frequency and opposite phases; and / or, the logic of the first level and the second level are the same.

[0025] In a second aspect, the present invention discloses a scan driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register comprises any one of the above shift registers.

[0026] In a third aspect, the present invention discloses a display panel, comprising the above scan drive circuit.

[0027] In a fourth aspect, the present invention discloses a shift register driving method for driving the shift register as described in any one of the above items, the driving method comprising:

[0028] In the first stage, the first input module transmits a first level to the first node under the control of a signal input to the input terminal, the interlock module transmits a third level to the second node in response to at least the first level of the first node, and the first output module transmits the level of the clock signal input to the second clock signal terminal to the output terminal in response to the first level of the first node;

[0029] In the second stage, the levels of the first node and the second node remain unchanged, and the first output module transmits the level of the clock signal connected to the second clock signal terminal to the output terminal in response to the first level of the first node;

[0030] In the third stage, the second input module transmits the second level of the clock signal connected to the first clock signal terminal to the second node under the control of at least the signal connected to the input terminal and the clock signal connected to the first clock signal terminal, the interlock module transmits the fourth level to the first node in response to at least the second level of the second node, and the second output module transmits the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node;

[0031] In the fourth stage, the levels of the first node and the second node remain unchanged, and the second output module transmits the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node.

[0032] The shift register and its driving method, scan drive circuit, and display panel disclosed in the present invention include a first input module, a second input module, an interlocking module, a first output module, and a second output module. The first input module is used to transmit a first level to a first node under the control of a signal received at an input terminal. The second input module is used to transmit a second level of a clock signal received at a first clock signal terminal to a second node under the control of at least a signal received at the input terminal and a clock signal received at a first clock signal terminal. The interlocking module is used to transmit a third level, which is logically opposite to the second level, to the second node in response to at least a first level of the first node, and to transmit a fourth level, which is logically opposite to the first level, to the first node in response to at least a second level of the second node. The first output module is used to transmit the level of a clock signal received at a second clock signal terminal to an output terminal in response to the first level of the first node. The second output module is used to transmit the level of a power signal received at a first power signal terminal to an output terminal in response to the second level of the second node. Thus, by alternately outputting the levels of the clock signal received at the second clock signal terminal and the power signal received at the first power signal terminal, reliable and stable output of a scan signal can be achieved, thereby ensuring the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0034] Figure 1 The present invention is a structural diagram of a shift register disclosed in an embodiment of the present invention.

[0035] Figure 2The present invention discloses a schematic diagram of the structure of various modules of a shift register.

[0036] Figure 3 for Figure 2 A timing diagram of the shift register shown.

[0037] Figure 4 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0038] Figure 5 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0039] Figure 6 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0040] Figure 7 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0041] Figure 8 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0042] Figure 9 This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention.

[0043] Figure 10 This is a schematic structural diagram of various modules of another shift register disclosed in an embodiment of the present invention.

[0044] Figure 11 The present invention discloses a flow chart of a shift register driving method.

[0045] Figure 12 The present invention is a schematic structural diagram of a scan drive circuit disclosed in an embodiment of the present invention.

[0046] Figure 13 The figure is a schematic structural diagram of a display panel disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0048] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a shift register, such as Figure 1 As shown, Figure 1 1 is a schematic structural diagram of a shift register disclosed in an embodiment of the present invention. The shift register includes a first input module 101 , a second input module 102 , an interlocking module 103 , a first output module 104 and a second output module 105 .

[0049] The first input module 101 is electrically connected to at least the input terminal IN and the first node N1. The first input module 101 is configured to transmit a first electrical level to the first node N1 under the control of a signal input to the input terminal IN. Specifically, when the level of the signal input to the input terminal IN is the first electrical level, the first input module 101 is turned on and transmits the first electrical level to the first node N1. When the level of the signal input to the input terminal IN is a level that is logically opposite (or has opposite polarity) to the first electrical level, the first input module 101 is turned off and stops transmitting the first electrical level to the first node N1. Optionally, the first electrical level is a low electrical level, and the level that is logically opposite to the first electrical level is a high electrical level, or alternatively, the first electrical level is a high electrical level, and the level that is logically opposite to the first electrical level is a low electrical level.

[0050] The second input module 102 is electrically connected to at least the input terminal IN, the first clock signal terminal CK1, and the second node N2. The second input module 102 is configured to transmit the second level of the clock signal received by the first clock signal terminal CK1 to the second node N2 under the control of at least the signal received by the input terminal IN and the clock signal received by the first clock signal terminal CK1. Specifically, when the level of the signal received by the input terminal IN is a first level, the second input module 102 stops transmitting the level of the clock signal received by the first clock signal terminal CK1 to the second node N2. When the level of the signal received by the input terminal IN is a level that is logically opposite to the first level and the level input by the first clock signal terminal CK1 is a second level, the second input module 102 transmits the second level of the clock signal received by the first clock signal terminal CK1 to the second node N2. Optionally, the second level has the same logic as the first level. Optionally, the second level and the first level can be low levels.

[0051] Interlocking module 103 is electrically connected to at least first node N1 and second node N2, and interlocking module 103 is used for at least responding to the first level of first node N1, and the third level that is logically opposite to the second level is transferred to second node N2, and at least responding to the second level of second node N2, and the fourth level that is logically opposite to the first level is transferred to first node N1.Wherein, the third level is a level that is logically opposite to the second level or has opposite polarity, for example, the third level is a low level, and the second level is a high level, or the third level is a high level, and the second level is a low level.The fourth level is a level that is logically opposite to the first level or has opposite polarity.For example, the fourth level is a low level, and the first level is a high level, or the fourth level is a high level, and the first level is a low level.Interlocking module 103 can transfer the third level to second node N2 and the fourth level to first node N1 in a time-sharing manner.

[0052] The first output module 104 is electrically connected to the second clock signal terminal CK2 and the output terminal OUT. The first output module 104 is configured to transmit the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT in response to a first level of the first node N1. Optionally, the first output module 104 is turned on in response to the first level of the first node N1, transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT, and is turned off in response to a fourth level of the first node N1, ceasing to transmit the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The first level may be the on-level of the first output module 104, and the fourth level may be the off-level of the first output module 104.

[0053] The second output module 105 is electrically connected to the second node N2, the first power signal terminal VGH, and the output terminal OUT. The second output module 105 is configured to transmit the power level of the power signal connected to the first power signal terminal VGH to the output terminal OUT in response to a second level of the second node N2. Optionally, the second output module 105 is turned on in response to the second level of the second node N2, transmitting the power level of the power signal connected to the first power signal terminal VGH to the output terminal OUT. The second output module 105 is turned off in response to a third level of the second node N2, ceasing to transmit the power level of the power signal connected to the first power signal terminal VGH to the output terminal OUT. The second level may be the on-level of the second output module 105, and the third level may be the off-level of the second output module 105. Optionally, the first output module 104 and the second output module 105 may be turned on in a time-sharing manner, rather than simultaneously. Optionally, the power level of the power signal connected to the first power signal terminal VGH may be the logical opposite of the second level.

[0054] Optionally, the first clock signal connected to the first clock signal terminal CK1 and the second clock signal connected to the second clock signal terminal CK2 have the same frequency and opposite phases. Optionally, both the first clock signal and the second clock signal include pulse signals that alternate between high and low levels.

[0055] Optionally, the control end of the first input module 101 is electrically connected to the input end IN, and the second end of the first input module 101 is electrically connected to the first node N1.

[0056] Optionally, the first end of the first output module 104 is electrically connected to the second clock signal end CK2 , the control end of the first output module 104 is electrically connected to the first node N1 , and the second end of the first output module 104 is electrically connected to the output end OUT.

[0057] Optionally, the first end of the second output module 105 is electrically connected to the first power signal end VGH, the control end of the second output module 105 is electrically connected to the second node N2, and the second end of the second output module 105 is electrically connected to the output end OUT.

[0058] In some embodiments of the present invention, Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of various modules of a shift register disclosed in an embodiment of the present invention. Optionally, a first input module 101 is electrically connected to the input terminal IN and the first node N1, and a first end of the first input module 101 is electrically connected to the input terminal IN. The first input module 101 is configured to transmit a first level (e.g., a low level) of the signal received at the input terminal IN to the first node N1 under the control of the signal received at the input terminal IN.

[0059] Optionally, the first input module 101 includes a first transistor T1, a gate and a first electrode of the first transistor T1 are electrically connected to the input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1. Optionally, the first transistor T1 may be a dual-gate transistor.

[0060] Optionally, the second input module 102 includes a first input unit 1020 and a second input unit 1021. The control end of the first input unit 1020 is electrically connected to the input end IN, and the first end of the first input unit 1020 is electrically connected to the first power signal end VGH or the second clock signal end CK2. The first input unit 1020 is configured to transmit the level of the clock signal connected to the first power signal end VGH or the second clock signal end CK2 to the second input unit 1021 under the control of the signal connected to the input end IN. The second input unit 1021 is electrically connected to the second end of the first input unit 1020, the second node N2, and the first clock signal end CK1. The second input unit 1021 is configured to transmit the second level of the clock signal connected to the first clock signal end CK1 to the second node N2 under the control of the level of the second end of the first input unit 1020 and the clock signal connected to the first clock signal end CK1.

[0061] Optionally, the first end of the second input unit 1021 is electrically connected to the first clock signal end CK1, the control end of the second input unit 1021 is electrically connected to the second end of the first input unit 1020, and the second end of the second input unit 1021 is electrically connected to the second node N2.

[0062] The first input unit 1020 is turned on when the level of the signal input to the input terminal IN is at a first level. The first input unit 1020 transmits the level of the power signal input to the first power signal terminal VGH or the level of the clock signal input to the second clock signal terminal CK2 (this level is the off level of the second input unit 1021 and is logically opposite to the second level) to the second input unit 1021 via the second terminal of the first input unit 1020, thereby turning off the second input unit 1021. The first input unit 1020 is turned off when the level of the signal input to the input terminal IN is at a level that is logically opposite to the first level, and stops transmitting the level of the clock signal input to the first power signal terminal VGH or the second clock signal terminal CK2 to the second input unit 1021. The second input unit 1021 is turned on when the level of the clock signal input to the first clock signal terminal CK1 is at a second level (which may be the on level of the second input unit 1021), and transmits the second level of the clock signal input to the first clock signal terminal CK1 to the second node N2.

[0063] Optionally, the first input unit 1021 includes a second transistor T2, wherein a gate of the second transistor T2 is electrically connected to the input terminal IN, a first electrode of the second transistor T2 is electrically connected to the first power signal terminal VGH or the second clock signal terminal CK2, and a second electrode of the second transistor T2 is the second terminal of the first input unit 1020. Optionally, the second transistor T2 may be a dual-gate transistor.

[0064] Optionally, the second input unit 1021 includes a third transistor T3 and a first capacitor C1. The gate of the third transistor T3 is electrically connected to the second end of the first input unit 1020. The first electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1. The second electrode of the third transistor T3 is electrically connected to the second node N2. The first electrode of the first capacitor C1 is electrically connected to the first electrode of the third transistor T3. The second electrode of the first capacitor C1 is electrically connected to the gate of the third transistor T3. Optionally, the third transistor T3 can be a dual-gate transistor.

[0065] Optionally, the interlock module 103 includes a first regulating unit 1030 and a second regulating unit 1031. The first regulating unit 1030 is electrically connected to at least the first power signal terminal VGH, the first node N1, and the second node N2. The first regulating unit 1030 is responsive to at least the first level of the first node N1 and transmits the level of the power signal connected to the first power signal terminal VGH to the second node N2 as a third level. The second regulating unit 1031 is electrically connected to at least the first power signal terminal VGH, the first node N1, and the second node N2. The second regulating unit 1031 is responsive to at least the second level of the second node N2 and transmits the level of the power signal connected to the first power signal terminal VGH to the first node N1 as a fourth level.

[0066] The first regulating unit 1030 is turned on in response to at least a first level at the first node N1, and transmits the level of the power signal connected to the first power signal terminal VGH as the third level to the second node N2. The first regulating unit 1030 is turned off in response to at least a fourth level at the first node N1, and stops transmitting the level of the power signal connected to the first power signal terminal VGH as the third level to the second node N2. The first level may be a turn-on level of the first regulating unit 1030, and the fourth level may be a turn-off level of the first regulating unit 1030.

[0067] The second regulating unit 1031 is turned on in response to at least the second level of the second node N2, and transmits the level of the power signal connected to the first power signal terminal VGH as the fourth level to the first node N1. The second regulating unit 1031 is turned off in response to at least the third level of the second node N2, and stops transmitting the level of the power signal connected to the first power signal terminal VGH as the fourth level to the first node N1. The second level may be the on-level of the second regulating unit 1031, and the third level may be the off-level of the second regulating unit 1031.

[0068] Optionally, the first regulating unit 1030 includes a fourth transistor T4, wherein a gate of the fourth transistor T4 is electrically connected to the first node N1, a first electrode of the fourth transistor T4 is electrically connected to the first power signal terminal VGH, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. Optionally, the fourth transistor T4 can be a dual-gate transistor.

[0069] Optionally, the second regulating unit 1031 includes a fifth transistor T5, wherein a gate of the fifth transistor T5 is electrically connected to the second node N2, a first electrode of the fifth transistor T5 is electrically connected to the first power signal terminal VGH, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1. Optionally, the fifth transistor T5 can be a dual-gate transistor.

[0070] Optionally, the first output module 104 includes a sixth transistor T6 , a gate of the sixth transistor T6 is electrically connected to the first node N1 , a first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2 , and a second electrode of the sixth transistor T6 is electrically connected to the output terminal OUT.

[0071] Optionally, the first output module 104 further includes a second capacitor C2 , a first electrode of the second capacitor C2 is electrically connected to the second electrode of the sixth transistor T6 , and a second electrode of the second capacitor C2 is electrically connected to the gate of the sixth transistor T6 .

[0072] Optionally, the second output module 105 includes a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the second node N2, a first electrode of the seventh transistor T7 is electrically connected to the first power signal terminal VGH, and a second electrode of the seventh transistor T7 is electrically connected to the output terminal OUT.

[0073] Optionally, the second output module 105 further includes a third capacitor C3 , a first electrode of the third capacitor C3 is electrically connected to the first electrode of the seventh transistor T7 , and a second electrode of the third capacitor C3 is electrically connected to the gate of the seventh transistor T7 .

[0074] It is understandable that Figure 2 In the description, only the first transistor T1 to the seventh transistor T7 are PMOS transistors as an example. The present invention is not limited to this. In other embodiments, the first transistor T1 to the seventh transistor T7 may also be NMOS transistors. Optionally, some of the first transistor T1 to the seventh transistor T7 may be NMOS transistors, and the rest may be PMOS transistors. The difference between an NMOS transistor and a PMOS transistor is that a PMOS transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, while an NMOS transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.

[0075] The working phases of the shift register within one frame of display image include a first phase t1, a second phase t2, a third phase t3 and a fourth phase t4.

[0076] Optional, such as Figure 3 As shown, Figure 3 for Figure 2A timing diagram of the shift register shown in the figure, in the first stage t1, the level of the clock signal connected to the first clock signal terminal CK1 is the second level (such as a low level), the level of the clock signal connected to the second clock signal terminal CK2 is a level logically opposite to the second level (such as a high level), and the level of the signal connected to the input terminal IN is the first level (such as a low level).

[0077] In the first stage t1, the first input module 101 is turned on under the control of the first level of the signal connected to the input terminal IN, and transmits the first level to the first node N1. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the signal connected to the input terminal IN and the clock signal connected to the first clock signal terminal CK1. The interlock module 103 transmits a third level that is logically opposite to the second level to the second node N2 in response to at least the first level of the first node N1. The first output module 104 transmits the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT in response to the first level of the first node N1. The second output module 105 is turned off in response to the third level of the second node N2, and stops transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0078] like Figure 2 As shown, under the control of the signal level connected to the input terminal IN being at a first level (e.g., a low level), the first input module 101 (e.g., the first transistor T1) is turned on, and the first input unit 1020 (e.g., the second transistor T2) is turned on. The turned-on first input module 101 (e.g., the first transistor T1) transmits the signal level connected to the input terminal IN at the first level (e.g., a low level) to the first node N1. The turned-on first input unit 1020 (e.g., the second transistor T2) transmits the level of the clock signal connected to the first power supply signal terminal VGH or the second clock signal terminal CK2 (a level logically opposite to the second level, e.g., a high level) to the second terminal of the first input unit 1020. After the second input unit 1021 (e.g., the gate of the third transistor T3) receives the level (e.g., a high level) of the second terminal of the first input unit 1020, the second input unit 1021 (e.g., the third transistor T3) is turned off, stopping the transmission of the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2.

[0079] The first regulating unit 1030 (e.g., the fourth transistor T4) is turned on in response to the first level (e.g., a low level) of the first node N1, and transmits the level of the power signal connected to the first power signal terminal VGH (e.g., a high level) as the third level to the second node N2, causing the second output module 105 (e.g., the seventh transistor T7) to be turned off in response to the third level (e.g., a high level) of the second node N2, and stop transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT. The second regulating unit 1031 (e.g., the fifth transistor T5) is turned off in response to the third level (e.g., a high level) of the second node N2, and stop transmitting the level of the power signal connected to the first power signal terminal VGH as the fourth level to the first node N1, so that the first node N1 remains at the first level (e.g., a low level). This causes the first output module 104 (e.g., the sixth transistor T6) to be turned on in response to the first level (e.g., a low level) of the first node N1, and transmit the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT.

[0080] Optional, such as Figure 3 As shown, in the second stage t2, the level of the clock signal connected to the first clock signal terminal CK1 is a level logically opposite to the second level (such as a high level), the level of the clock signal connected to the second clock signal terminal CK2 changes from a level logically opposite to the second level (such as a high level) to a second level (such as a low level), and then from the second level (such as a low level) to a level logically opposite to the second level (such as a high level), and the level of the signal connected to the input terminal IN is a level logically opposite to the first level (such as a high level).

[0081] In the second stage t2, the first input module 101 stops transmitting the level to the first node N1 under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the signal connected to the input terminal IN and the clock signal connected to the first clock signal terminal CK1. The interlock module 103 transmits a third level logically opposite to the second level to the second node N2 in response to at least the first level of the first node N1. The levels of the first node N1 and the second node N2 remain unchanged. The first output module 104 transmits the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT in response to the first level of the first node N1. The second output module 105 is turned off in response to the third level of the second node N2 and stops transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0082] like Figure 2As shown, under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level (such as a high level), the first input module 101 (such as the first transistor T1) is turned off and stops transmitting the level to the first node N1, the first input unit 1020 (such as the second transistor T2) is turned off and stops transmitting the third level (such as a high level) of the clock signal connected to the first power supply signal terminal VGH or the second clock signal terminal CK2 to the second end of the first input unit 1020, the level of the second end of the first input unit 1020 (such as the gate of the third transistor T3) remains unchanged, and the second input unit 1021 (such as the third transistor T3) remains turned off and continues to stop transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2. The first regulating unit 1030 (such as the fourth transistor T4) remains turned on and continuously transmits the level of the power signal connected to the first power signal terminal VGH (such as a high level) as the third level to the second node N2. The second regulating unit 1031 (such as the fifth transistor T5) remains turned off, so that the levels of the first node N1 and the second node N2 remain unchanged, so that the second output module 105 (such as the seventh transistor T7) remains turned off and continuously stops transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT, so that the first output module 104 (such as the sixth transistor T6) remains turned on and continuously transmits the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT.

[0083] Optional, such as Figure 3 As shown, in the third stage t3, the level of the clock signal connected to the first clock signal terminal CK1 is the second level (such as a low level), the level of the clock signal connected to the second clock signal terminal CK2 is a level logically opposite to the second level (such as a high level), and the level of the signal connected to the input terminal IN is a level logically opposite to the first level (such as a high level).

[0084] In the third stage t3, the first input module 101 stops transmitting the level to the first node N1 under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level. The second input module 102 transmits the second level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the signal connected to the input terminal IN and the clock signal connected to the first clock signal terminal CK1. The interlock module 103 transmits the fourth level logically opposite to the first level to the first node N1 in response to at least the second level of the second node N2. The first output module 104 is turned off in response to the fourth level of the first node N1 and stops transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module 105 transmits the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT in response to the second level of the second node N2.

[0085] like Figure 2 As shown, under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level (such as a high level), the first input module 101 (such as the first transistor T1) is turned off and stops transmitting the level to the first node N1. The first input unit 1020 (such as the second transistor T2) is turned off and stops transmitting the level of the clock signal connected to the first power supply signal terminal VGH or the second clock signal terminal CK2 (such as a high level) to the second end of the first input unit 1020. After the level of the clock signal connected to the first clock signal terminal CK1 changes from a level logically opposite to the second level (such as a high level) to a second level (such as a low level), under the action of the first capacitor C1, the level of the second end of the first input unit 1020 (such as the gate of the third transistor T3) is pulled down, so that the second input unit 1021 (such as the third transistor T3) is turned on, and the level of the clock signal connected to the first clock signal terminal CK1 (which may be the second level, such as a low level at this time) is transmitted to the second node N2. It should be noted that after the level of the second end of the first input unit 1020 (such as the gate of the third transistor T3) is pulled low, the second input unit 1021 (such as the third transistor T3) can be turned on or not fully turned on, as long as the second level (such as a low level) of the clock signal connected to the first clock signal terminal CK1 can be transmitted to the second node N2.

[0086] The second regulating unit 1031 (e.g., the fifth transistor T5) is turned on in response to the second level (e.g., a low level) of the second node N2, and transmits the high level of the power signal connected to the first power signal terminal VGH as the fourth level to the first node N1, causing the first output module 104 (e.g., the sixth transistor T6) to be turned off in response to the fourth level (e.g., a high level) of the first node N1, and to stop transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The first regulating unit 1030 (e.g., the fourth transistor T4) is turned off in response to the fourth level (e.g., a high level) of the first node N1, and to stop transmitting the level of the power signal connected to the first power signal terminal VGH as the third level to the second node N2, causing the second output module 105 (e.g., the seventh transistor T7) to be turned on in response to the second level (e.g., a low level) of the second node N2, and to transmit the high level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0087] Optional, such as Figure 3As shown, in the fourth stage t4, the level of the clock signal connected to the first clock signal terminal CK1 is a level logically opposite to the second level (such as a high level), the level of the clock signal connected to the second clock signal terminal CK2 changes from a level logically opposite to the second level (such as a high level) to the second level (such as a low level), and then changes from the second level (such as a low level) to a level logically opposite to the second level (such as a high level), and the level of the signal connected to the input terminal IN is a level logically opposite to the first level (such as a high level).

[0088] In the fourth stage t4, the first input module 101 stops transmitting the level to the first node N1 under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the clock signal connected to the input terminal IN and the first clock signal terminal CK1. The levels of the first node N1 and the second node N2 remain unchanged. The interlocking module 103 continues to transmit the fourth level logically opposite to the first level to the first node N1 in response to at least the second level of the second node N2. The first output module 104 is turned off in response to the fourth level of the first node N1 and stops transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module transmits the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT in response to the second level of the second node N2.

[0089] like Figure 2As shown, under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level (such as a high level), the first input module 101 (such as the first transistor T1) is turned off, and the first node N1 stops transmitting the level, and the first input unit 1020 (such as the second transistor T2) is turned off, and the third level (such as a high level) of the clock signal connected to the first power supply signal terminal VGH or the second clock signal terminal CK2 is stopped from being transmitted to the second end of the first input unit 1020. After the first clock signal terminal CK1 changes from the second level (such as a low level) to the third level (such as a high level), under the action of the first capacitor C1, the level of the second end of the first input unit 1020 (such as the gate of the third transistor T3) is pulled high, so that the second input unit 1021 (such as the third transistor T3) is turned off and stops transmitting the level to the second node N2. The second regulating unit 1031 (such as the fifth transistor T5) remains turned on and continuously transmits the level of the power signal connected to the first power signal terminal VGH (such as a high level) as the fourth level to the first node N1. The first regulating unit 1030 (such as the fourth transistor T4) remains turned off and continuously stops transmitting the level of the power signal connected to the first power signal terminal VGH as the third level to the second node N2, so that the levels of the first node N1 and the second node N2 remain unchanged, so that the first output module 104 (such as the sixth transistor T6) remains turned off and stops transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT, so that the second output module 105 (such as the seventh transistor T7) remains turned on and continuously transmits the level of the power signal connected to the first power signal terminal VGH (such as a high level) to the output terminal OUT.

[0090] After the fourth stage t4, the shift register repeats the process of the third stage t3 and the fourth stage t4 alternately until the input terminal IN inputs the first level (such as low level) again and enters the first stage t1 again.

[0091] In some embodiments of the present invention, Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of another shift register disclosed in an embodiment of the present invention. The first input module 101 can also be electrically connected to the second power signal terminal VGL or the first clock signal terminal CK1. For example, the first terminal of the first input module 101 is electrically connected to the second power signal terminal VGL or the first clock signal terminal CK1. The first input module 101 is configured to transmit the level of the power signal connected to the second power signal terminal VGL or the second level of the clock signal connected to the first clock signal terminal CK1 as the first level to the first node N1 under the control of the signal connected to the input terminal IN.

[0092] Under the control of the first level of the signal connected to the input terminal IN, the first input module 101 is turned on and transmits the level of the power signal connected to the second power signal terminal VGL or the second level of the clock signal connected to the first clock signal terminal CK1 as the first level to the first node N1. Under the control of the level of the signal connected to the input terminal IN being a level that is logically opposite to the first level, the first input module 101 is turned off and stops transmitting the level of the power signal connected to the second power signal terminal VGL or the level of the clock signal connected to the first clock signal terminal CK1 to the first node N1.

[0093] Optionally, the gate of the first transistor T1 is electrically connected to the input terminal IN, the first electrode of the first transistor T1 is electrically connected to the second power signal terminal VGL or the first clock signal terminal CK1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. Figure 4 Compared to the structure shown, Figure 2 The gate and the first electrode of the first transistor T1 share a common signal, which can reduce the control signal of the first input module 101.

[0094] It can be understood that when the first level of the first node N1 is a low level, the level of the power signal connected to the second power signal terminal VGL and the second level of the clock signal connected to the first clock signal terminal CK1 are low levels; when the first level of the first node N1 is a high level, the level of the power signal connected to the second power signal terminal VGL and the second level of the clock signal connected to the first clock signal terminal CK1 are high levels.

[0095] In some embodiments of the present invention, Figure 5 As shown, Figure 5 This is a structural diagram of another shift register disclosed in an embodiment of the present invention. The shift register may further include a protection module 106, which is connected between the first node N1 and the first output module 104. The protection module 106 is used to transmit the first level of the first node N1 to the first output module 104 under the control of the power signal connected to the second power signal terminal VGL.

[0096] The level of the power signal connected to the second power signal terminal VGL may be the on-level of the protection module 106. The protection module 106 may remain on under the control of the power signal connected to the second power signal terminal VGL. Optionally, one of the levels of the power signal connected to the first power signal terminal VGH and the power signal connected to the second power signal terminal VGL is a high level, and the other is a low level. Optionally, the level of the power signal connected to the first power signal terminal VGH is a high level, and the level of the power signal connected to the second power signal terminal VGL is a low level.

[0097] In some optional examples, such as Figure 6 As shown, Figure 6 This is a structural diagram of another shift register disclosed in an embodiment of the present invention. The protection module 106 includes an eighth transistor T8, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, a gate of the eighth transistor T8 is electrically connected to the second power supply signal terminal VGL, and a second electrode of the eighth transistor T8 is electrically connected to the first output module 104 (such as the gate of the sixth transistor T6).

[0098] Since there is a second capacitor C2 between the gate and the first electrode of the sixth transistor T6, the gate voltage of the sixth transistor T6 is low. The gate of the sixth transistor T6 is electrically connected to the first node N1 through the eighth transistor T8, which can prevent the high level of the first node N1 from damaging the sixth transistor T6.

[0099] Optionally, the interlock module 103 is further electrically connected to the first clock signal terminal CK1. In response to the first level of the first node N1 and the second level of the clock signal connected to the first clock signal terminal CK1, the interlock module 103 transmits the level of the power signal connected to the first power signal terminal VGH or the level of the clock signal connected to the second clock signal terminal CK2 as a third level to the second node N2. In response to the second level of the second node N2 and the second level of the clock signal connected to the first clock signal terminal CK1, the interlock module 103 transmits the level of the power signal connected to the first power signal terminal VGH or the level of the clock signal connected to the second clock signal terminal CK2 as a fourth level to the first node N1.

[0100] Optionally, the first regulating unit 1030 is further electrically connected to the first clock signal terminal CK1. In response to the first level of the first node N1 and the second level of the clock signal connected to the first clock signal terminal CK1, the first regulating unit 1030 transmits the level of the power signal connected to the first power signal terminal VGH or the level of the clock signal connected to the second clock signal terminal CK2 as the third level to the second node N2. The second regulating unit 1031 is further electrically connected to the first clock signal terminal CK1. In response to the second level of the second node N2 and the second level of the clock signal connected to the first clock signal terminal CK1, the second regulating unit 1031 transmits the level of the power signal connected to the first power signal terminal VGH or the level of the clock signal connected to the second clock signal terminal CK2 as the fourth level to the first node N1. Connecting the first regulating unit 1030 and the second regulating unit 1031 to the first power signal terminal VGH provides more reliable operation than connecting them to the second clock signal terminal CK2.

[0101] Of course, the present invention is not limited to this. In other embodiments, Figure 7 As shown, Figure 7This is a schematic structural diagram of another shift register disclosed in an embodiment of the present invention. The first regulating unit 1030 further includes a ninth transistor T9, and / or the second regulating unit 1031 further includes a tenth transistor T10.

[0102] Optionally, the gate of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the second electrode of the fourth transistor T4. Optionally, the first electrode of the fourth transistor T4 is electrically connected to the first power signal terminal VGH or the second clock signal terminal CK2.

[0103] Optional, such as Figure 7 As shown, the gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CK1, the first electrode of the tenth transistor T10 is electrically connected to the first node N1, and the second electrode of the tenth transistor T10 is electrically connected to the second electrode of the fifth transistor T5. Optionally, the first electrode of the fifth transistor T5 is electrically connected to the first power signal terminal VGH or the second clock signal terminal CK2.

[0104] In other embodiments, Figure 8 As shown, Figure 8 This is a structural diagram of another shift register disclosed in an embodiment of the present invention. Optionally, the gate of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply signal terminal VGH or the second clock signal terminal CK2, and the second electrode of the ninth transistor T9 is electrically connected to the first electrode of the fourth transistor T4.

[0105] Optionally, the gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CK1, the first electrode of the tenth transistor T10 is electrically connected to the first power signal terminal VGH or the second clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the first electrode of the fifth transistor T5.

[0106] In the first phase t1, the first regulating unit 1030 is turned on in response to the first level (e.g., a low level) of the first node N1 and the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1. For example, the fourth transistor T4 is turned on in response to the first level (e.g., a low level) of the first node N1, and the ninth transistor T9 is turned on in response to the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1. The power supply signal input to the first power supply signal terminal VGH or the clock signal input to the second clock signal terminal CK2 (which may be a high level in this case) is transmitted as the third level to the second node N2. The second regulating unit 1031 is turned off in response to the third level (e.g., a high level) of the second node N2. For example, the fifth transistor T5 is turned off in response to the third level (e.g., a high level) of the second node N2. Although the tenth transistor T10 is turned on in response to the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1, this does not affect the off state of the second regulating unit 1031.

[0107] In the second stage t2, the first regulating unit 1030 (such as the ninth transistor T9) is turned off in response to the level of the clock signal connected to the first clock signal terminal CK1 being a level logically opposite to the second level, and the second regulating unit 1031 (such as the fifth transistor T5 and the tenth transistor T10) is turned off, so that the levels of the first node N1 and the second node N2 remain unchanged.

[0108] In the third phase t3, the second regulating unit 1031 is turned on. For example, the fifth transistor T5 is turned on in response to the second level (e.g., a low level) of the second node N2. The tenth transistor T10 is turned on in response to the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1. The tenth transistor T10 is turned on in response to the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1. The power signal input to the first power signal terminal VGH or the clock signal input to the second clock signal terminal CK2 (which may be a high level in this case) is transmitted as the fourth level to the first node N1. The first regulating unit 1030 is turned off. For example, the fourth transistor T4 is turned off in response to the fourth level (e.g., a high level) of the first node N1. Although the ninth transistor T9 is turned on in response to the second level (e.g., a low level) of the clock signal input to the first clock signal terminal CK1, this does not affect the off state of the first regulating unit 1030.

[0109] In the fourth phase t4, the first regulating unit 1030 is turned off, for example, the fourth transistor T4 and the ninth transistor T9 are turned off, and the second regulating unit 1031 is turned off, for example, the tenth transistor T10 is turned off, so that the levels of the first node N1 and the second node N2 remain unchanged. The fifth transistor T5 is turned on, but this does not affect the off state of the second regulating unit 1031.

[0110] Based on this, the interlocking module 103 responds to the first level of the first node N1 and the level of the clock signal connected to the first clock signal terminal CK1 (which may be the second level at this time), and transmits the level of the power signal connected to the first power signal terminal VGH (such as a high level) as the third level to the second node N2. In response to the second level of the second node N2 and the level of the clock signal connected to the first clock signal terminal CK1 being the second level, the level of the power signal connected to the first power signal terminal VGH (such as a high level) is transmitted as the fourth level to the first node N1, thereby further improving the stability of the shift register circuit.

[0111] It is understandable that Figure 7 and Figure 8 In the illustrated structure, the interlock module 103 is electrically connected to the first power signal terminal VGH. Compared to being electrically connected to the second clock signal terminal CK2, the interlock module 103 is more stable and will not accidentally pull the first node N1 and the second node N2 low. It should be noted that when the first level and the second level are low, the first adjustment unit 1030 is used to pull the first node N1 to a high level, and the second adjustment unit 1031 is used to pull the second node N2 to a high level. However, the present invention is not limited to this. When the first level and the second level are high, the first adjustment unit 1030 is used to pull the first node N1 to a low level, and the second adjustment unit 1031 is used to pull the second node N2 to a low level. This will not be repeated here.

[0112] In other embodiments, Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of another shift register disclosed in an embodiment of the present invention. The first input module 101 may further include an eleventh transistor T11. The first electrode of the first transistor T1 is electrically connected to the input terminal IN, the second electrode of the first transistor T1 is electrically connected to the first node N1, the gate of the first transistor T1 is electrically connected to the first electrode of the eleventh transistor T11, the second electrode of the eleventh transistor T11 is electrically connected to the second power signal terminal VGL, and the gate of the eleventh transistor T11 is electrically connected to the input terminal IN. Of course, in other embodiments, the first electrode of the first transistor T1 may also be electrically connected to the second power signal terminal VGL or the first clock signal terminal CK1.

[0113] When the level of the signal connected to the input terminal IN is a first level (e.g., a low level), the eleventh transistor T11 is turned on. The turned-on eleventh transistor T11 transmits the level of the power signal connected to the second power signal terminal VGL (e.g., a low level) to the gate of the first transistor T1, controlling the first transistor T1 to turn on, turning on the first input module 101. The turned-on first input module 101 (e.g., the first transistor T1) transmits the first level (e.g., a low level) to the first node N1. When the level of the signal connected to the input terminal IN is a level logically opposite to the first level (e.g., a high level), the eleventh transistor T11 is turned off. The turned-off eleventh transistor T11 stops transmitting the level of the power signal connected to the second power signal terminal VGL (e.g., a low level) to the gate of the first transistor T1. The first transistor T1 is turned off, turning off the first input module 101. The turned-off first input module 101 (e.g., the first transistor T1) transmits the level of the signal connected to the input terminal IN to the first node N1.

[0114] In other embodiments, Figure 10 As shown, Figure 10 This is a schematic structural diagram of the various modules of another shift register disclosed in an embodiment of the present invention. At least one transistor among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 includes a dual-gate transistor to reduce the impact of leakage current on the transistor, thereby improving the stability of the shift register circuit.

[0115] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a driving method for a shift register, which can be used to drive the shift register provided by any embodiment of the present invention. Figure 11 As shown, Figure 11 This is a flow chart of a shift register driving method disclosed in an embodiment of the present invention. The driving method includes:

[0116] S101: In the first stage, the first input module transmits the first level to the first node under the control of the signal connected to the input end, the interlocking module responds to at least the first level of the first node and transmits the third level that is logically opposite to the second level to the second node, and the first output module responds to the first level of the first node and transmits the level of the clock signal connected to the second clock signal end to the output end.

[0117] Among them, in the first stage t1, the first input module 101 is turned on under the control of the level of the signal connected to the input terminal IN being the first level, and transmits the first level to the first node N1. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the level of the signal connected to the input terminal IN being the first level. The interlock module 103 at least responds to the first level of the first node N1 and transmits the third level that is logically opposite to the second level to the second node N2. The first output module 104 responds to the first level of the first node N1 and transmits the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module 105 is turned off in response to the third level of the second node N2 and stops transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0118] S102: In the second stage, the levels of the first node and the second node remain unchanged, and the first output module transmits the level of the clock signal connected to the second clock signal terminal to the output terminal in response to the first level of the first node.

[0119] In the second stage t2, the first input module 101 is turned off under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level, and stops transmitting the level to the first node N1. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control of the level of the clock signal connected to the first clock signal terminal CK1 being a level logically opposite to the second level. The interlock module 103 at least responds to the first level of the first node N1 and transmits the third level logically opposite to the second level to the second node N2. The levels of the first node N1 and the second node N2 remain unchanged. The first output module 104 is turned on in response to the first level of the first node N1, and transmits the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module 105 is turned off in response to the third level of the second node N2, and stops transmitting the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0120] S103: In the third stage, the second input module transmits the second level to the second node at least under the control of the signal connected to the input end and the clock signal connected to the first clock signal end, the interlocking module transmits the fourth level that is logically opposite to the first level to the first node in response to at least the second level of the second node, and the second output module transmits the level of the power signal connected to the first power signal end to the output end in response to the second level of the second node.

[0121] In the third stage t3, the first input module 101 is shut down under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level, and stops transmitting the level to the first node N1. The second input module 102 transmits the level of the clock signal connected to the first clock signal terminal CK1 (such as the second level) to the second node N2 at least under the control of the level of the signal connected to the input terminal IN being a level logically opposite to the first level and the level of the clock signal connected to the first clock signal terminal CK1 being the second level. The interlock module 103 transmits the fourth level logically opposite to the first level to the first node N1 in response to at least the second level of the second node N2. The first output module 104 is shut down in response to the fourth level of the first node N1 and stops transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module 105 transmits the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT in response to the second level of the second node N2.

[0122] S104: In the fourth stage, the levels of the first node and the second node remain unchanged, and the second output module transmits the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node.

[0123] In the fourth stage t4, the first input module 101 is turned off under the control that the level of the signal connected to the input terminal IN is a level logically opposite to the first level, and stops transmitting the level to the first node N1. The second input module 102 stops transmitting the level of the clock signal connected to the first clock signal terminal CK1 to the second node N2 at least under the control that the level of the signal connected to the input terminal IN is a level logically opposite to the first level and the level of the clock signal connected to the first clock signal terminal CK1 is a level logically opposite to the second level. The levels of the first node N1 and the second node N2 remain unchanged. The interlock module 103 continues to transmit a fourth level logically opposite to the first level to the first node N1 in response to at least the second level of the second node N2. The first output module 104 is turned off in response to the fourth level of the first node N1 and stops transmitting the level of the clock signal connected to the second clock signal terminal CK2 to the output terminal OUT. The second output module is turned on in response to the second level of the second node N2, and transmits the level of the power signal connected to the first power signal terminal VGH to the output terminal OUT.

[0124] After the fourth stage t4, the shift register repeats the process of the third stage t3 and the fourth stage t4 alternately until the input terminal IN inputs the first level (such as low level) again and enters the first stage t1 again.

[0125] It is understandable that for shift registers with modules having different structures, the states of the modules are different at the same stage, such as the states of the transistors, but the functions of the modules are the same and will not be described in detail here.

[0126] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a scan driving circuit, such as Figure 12 As shown, Figure 12 Schematic diagram of the structure of a scan driving circuit disclosed in an embodiment of the present invention. The scan driving circuit includes a plurality of cascaded shift registers SR. The shift register SR includes the shift register disclosed in any of the above embodiments.

[0127] Among them, in two adjacent shift registers SR, the output terminal OUT of the previous shift register SR is electrically connected to the input terminal IN of the next shift register SR. In two adjacent shift registers SR, the first clock signal terminal CK1 of the previous shift register SR and the second clock signal terminal CK2 of the next shift register SR are electrically connected to the same clock signal line, and the second clock signal terminal CK2 of the previous shift register SR and the first clock signal terminal CK1 of the next shift register SR are electrically connected to the same clock signal line. The first clock signal terminal CK1 and the second clock signal terminal CK2 of the same shift register SR are electrically connected to different clock signal lines, for example, the first clock signal line CKB1 and the second clock signal line CKB2.

[0128] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a display panel, such as Figure 13 As shown, Figure 13 This is a schematic structural diagram of a display panel disclosed in an embodiment of the present invention. The display panel includes the scan drive circuit disclosed in any of the above embodiments.

[0129] Among them, the display panel includes a display area and a non-display area. In some embodiments, the scan driving circuit is located in the non-display area on one side of the display area. In other embodiments, the scan driving circuit is located in the non-display areas on opposite sides of the display area. It will not be repeated here.

[0130] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a display device comprising a display panel as disclosed in any of the above embodiments. The display device may be a smartphone, wearable product, computer, television, vehicle-mounted display device, or other display device with a display function, and the present invention does not impose any specific limitations thereto.

[0131] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be subject to the appended claims.

Claims

1. A shift register, characterized in that: include: a first input module, the first input module being electrically connected to at least the input terminal and the first node, and configured to transmit a first electrical level to the first node under the control of a signal input to the input terminal; a second input module, the second input module being electrically connected to at least the input terminal, the second node, and the first clock signal terminal, the second input module being configured to transmit a second level of the clock signal received at the first clock signal terminal to the second node under the control of at least a signal received at the input terminal and a clock signal received at the first clock signal terminal; an interlocking module, the interlocking module being electrically connected to at least the first node and the second node, the interlocking module being configured to transmit a third level, which is logically opposite to the second level, to the second node in response to at least a first level of the first node, and to transmit a fourth level, which is logically opposite to the first level, to the first node in response to at least a second level of the second node; a first output module, the first output module being electrically connected to the second clock signal terminal and the output terminal, and the first output module being configured to transmit the level of the clock signal connected to the second clock signal terminal to the output terminal in response to the first level of the first node; a second output module, the second output module being electrically connected to the second node, the first power signal terminal, and the output terminal, and configured to transmit the power signal level connected to the first power signal terminal to the output terminal in response to a second level of the second node; The interlocking module includes a first adjustment unit and a second adjustment unit; The first regulating unit is electrically connected to at least the first power signal terminal, the first node and the second node; The second regulating unit is electrically connected to at least the first power signal terminal, the first node and the second node; The first regulating unit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the first node, The second regulating unit includes a fifth transistor, the gate of the fifth transistor is electrically connected to the second node, The first regulating unit is further electrically connected to the first clock signal terminal, and is configured to transmit the level of the power signal connected to the first power signal terminal or the level of the clock signal connected to the second clock signal terminal as a third level to the second node in response to the first level of the first node and the second level of the clock signal connected to the first clock signal terminal; The second regulating unit is further electrically connected to the first clock signal terminal, and is configured to transmit the level of the power signal connected to the first power signal terminal or the level of the clock signal connected to the second clock signal terminal as a fourth level to the first node in response to the second level of the second node and the second level of the clock signal connected to the first clock signal terminal; The first regulating unit further includes a ninth transistor, and the second regulating unit further includes a tenth transistor; The gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the second node, the second electrode of the ninth transistor is electrically connected to the second electrode of the fourth transistor; the first electrode of the fourth transistor is electrically connected to the first power signal terminal or the second clock signal terminal; Alternatively, the gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first power signal terminal or the second clock signal terminal, the second electrode of the ninth transistor is electrically connected to the first electrode of the fourth transistor; and the second electrode of the fourth transistor is electrically connected to the second node; The gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, the second electrode of the tenth transistor is electrically connected to the second electrode of the fifth transistor; the first electrode of the fifth transistor is electrically connected to the first power signal terminal or the second clock signal terminal; Alternatively, the gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the first power supply signal terminal or the second clock signal terminal, the second electrode of the tenth transistor is electrically connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is electrically connected to the first node.

2. The shift register according to claim 1, wherein: The first input module is configured to transmit a first level of the signal input to the first node under the control of the signal input to the input terminal; Alternatively, the first input module is also electrically connected to the second power signal terminal or the first clock signal terminal, and the first input module is used to transmit the second level of the clock signal connected to the first clock signal terminal or the level of the power signal connected to the second power signal terminal as the first level to the first node under the control of the signal connected to the input terminal.

3. The shift register according to claim 1, wherein: The first input module includes a first transistor; The gate and the first electrode of the first transistor are electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the first node; Alternatively, the gate of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the second power signal terminal or the first clock signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

4. The shift register according to claim 3, wherein: The first transistor comprises a dual-gate transistor.

5. The shift register according to claim 1, wherein: The second input module includes a first input unit and a second input unit; The control end of the first input unit is electrically connected to the input end, the first end of the first input unit is electrically connected to the first power signal end or the second clock signal end, and the first input unit is configured to transmit the level of the power signal connected to the first power signal end or the clock signal connected to the second clock signal end to the second end of the first input unit under the control of the signal connected to the input end; The second input unit is electrically connected to the second end of the first input unit, the second node and the first clock signal end. The second input unit is used to transmit the second level of the clock signal connected to the first clock signal end to the second node under the control of the level of the second end of the first input unit and the clock signal connected to the first clock signal end.

6. The shift register according to claim 5, wherein: The first input unit includes a second transistor, a gate of the second transistor is electrically connected to the input terminal, a first electrode of the second transistor is electrically connected to the first power signal terminal or the second clock signal terminal, and a second electrode of the second transistor is the second terminal of the first input unit; The second input unit includes a third transistor and a first capacitor, the gate of the third transistor is electrically connected to the second end of the first input unit, the first electrode of the third transistor is electrically connected to the first clock signal end, and the second electrode of the third transistor is electrically connected to the second node; the first electrode of the first capacitor is electrically connected to the first electrode of the third transistor, and the second electrode of the first capacitor is electrically connected to the gate of the third transistor.

7. The shift register according to claim 6, wherein: The second transistor and / or the third transistor include a dual-gate transistor.

8. The shift register according to claim 1, wherein: The fourth transistor and / or the fifth transistor include a dual-gate transistor.

9. The shift register according to claim 1, wherein: The first output module includes a sixth transistor; a gate of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the output terminal; And / or, the second output module includes a seventh transistor; A gate of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the first power signal terminal, and a second electrode of the seventh transistor is electrically connected to the output terminal.

10. The shift register according to claim 9, wherein: The first output module further includes a second capacitor, a first electrode of the second capacitor is electrically connected to the second electrode of the sixth transistor, and a second electrode of the second capacitor is electrically connected to the gate of the sixth transistor.

11. The shift register according to claim 9, wherein: The second output module further includes a third capacitor, a first electrode of the third capacitor is electrically connected to the first electrode of the seventh transistor, and a second electrode of the third capacitor is electrically connected to the gate of the seventh transistor.

12. The shift register according to claim 1, wherein: It also includes a protection module, which is connected between the first node and the first output module. The protection module is used to transmit the first level of the first node to the first output module under the control of the power signal connected to the second power signal terminal.

13. The shift register according to claim 12, wherein: The protection module includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the first node, a gate of the eighth transistor is electrically connected to the second power signal terminal, and a second electrode of the eighth transistor is electrically connected to the first output module.

14. The shift register according to any one of claims 2 to 7, wherein: One of the power signal level connected to the first power signal terminal and the power signal level connected to the second power signal terminal is a high level, and the other is a low level; And / or, the first clock signal connected to the first clock signal terminal and the second clock signal connected to the second clock signal terminal have the same frequency but opposite phases; And / or, the logic of the first level is the same as that of the second level.

15. A scan driving circuit, characterized in that: The invention comprises a plurality of cascaded shift registers, wherein the shift register comprises the shift register according to any one of claims 1 to 14.

16. A display panel, characterized in that: Includes the scan driving circuit according to claim 15.

17. A shift register driving method, characterized in that: Used to drive the shift register according to any one of claims 1 to 14, the driving method comprising: In the first stage, the first input module transmits a first level to the first node under the control of the signal input to the input terminal, the interlock module transmits a third level that is logically opposite to the second level to the second node in response to at least the first level of the first node, and the first output module transmits the level of the clock signal input to the second clock signal terminal to the output terminal in response to the first level of the first node; In the second stage, the levels of the first node and the second node remain unchanged, and the first output module transmits the level of the clock signal connected to the second clock signal terminal to the output terminal in response to the first level of the first node; In the third stage, the second input module transmits the second level of the clock signal connected to the first clock signal terminal to the second node under the control of at least the clock signals connected to the input terminal and the first clock signal terminal, the interlock module transmits a fourth level that is logically opposite to the first level to the first node in response to at least the second level of the second node, and the second output module transmits the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node; In the fourth stage, the levels of the first node and the second node remain unchanged, and the second output module transmits the level of the power signal connected to the first power signal terminal to the output terminal in response to the second level of the second node.

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