Memory read data stabilization method and apparatus

Abstract

The application discloses a memory data reading stability method and device, which comprises the following steps: after determining a reference trimming module, adjusting the equivalent resistance value of the reference trimming module to the optimal resistance value obtained in advance, connecting the second output end of a sensitive amplifier connected with the reference trimming module with a trimming module to be adjusted, and adjusting the trimming module to be adjusted according to the output signal of the sensitive amplifier, so that the total resistance values of each reference circuit and the first trimming module connected with each reference circuit in series are equal, the size of the reading window is increased, the stability of the read data is improved, and the sensitive amplifier in the memory is multiplexed.

Description

Technical Field

[0001] This invention relates to the field of memory, and in particular to a method and apparatus for stabilizing memory read data. Background Technology

[0002] Some memories typically include multiple sensitive amplifiers, reference circuits, and arrays, such as MRAM (Magnetoresistive Random Access Memory), to achieve parallel data output. Each sensitive amplifier's two inputs are connected to a reference circuit and an array, respectively. When reading data stored in the array, the array bits in the memory are read through the sensitive amplifiers within the memory. For stable data reading from the array, the equivalent resistance values ​​of each reference circuit must fall within a specific range, called the read window. A larger read window results in better read stability and a lower probability of data errors. The size of the read window is related to the difference in the equivalent resistance values ​​of each reference circuit; the read window is largest when the equivalent resistance values ​​of all reference circuits are equal. However, due to manufacturing variations in components such as MOSFETs and resistors in the reference circuits, even using the same type of MOSFET and resistors with the same nominal values, the equivalent resistance values ​​of each reference circuit will still vary, reducing the read window size and decreasing the stability of data reading. Summary of the Invention

[0003] The purpose of this invention is to provide a method and apparatus for stabilizing data reading from a memory, which increases the size of the read window, improves the stability of data reading, and enables the multiplexing of the sensitive amplifier in the memory.

[0004] To address the aforementioned technical problems, this invention provides a method for stabilizing read data in a memory, applied to a memory comprising N sensitive amplifiers, N reference circuits, N first adjustment modules, N arrays, and a MUX circuit, where N is an integer not less than 2. The method for stabilizing read data in the memory includes:

[0005] Upon receiving a control command, any one of the first adjustment modules is determined as the reference adjustment module. The equivalent resistance value of the reference adjustment module is adjusted to the optimal resistance value. The MUX circuit is controlled to connect the first input terminal of the sensitive amplifier corresponding to the reference adjustment module, the reference adjustment module, and the reference circuit corresponding to the reference adjustment module in series and then ground.

[0006] Identify any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted, and control the MUX circuit to connect the second input terminal of the sensitive amplifier corresponding to the reference adjustment module, the adjustment module to be adjusted, and the reference circuit corresponding to the adjustment module to be adjusted in series and then ground it;

[0007] The equivalent resistance value of the adjustment module to be adjusted is adjusted according to the output signal of the sensitive amplifier, so that the equivalent resistance value of the adjustment module to be adjusted and the reference circuit corresponding to the adjustment module in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module in series.

[0008] Determine whether the equivalent resistance value of all the first adjustment modules and the reference circuit corresponding to the first adjustment module connected in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module connected in series. If they are not equal, return to the step of determining any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted.

[0009] Preferably, adjusting the equivalent resistance value of the adjustment module according to the output signal of the sensitive amplifier includes:

[0010] Determine the initial output signal of the sensitive amplifier;

[0011] Adjust the equivalent resistance value of the module to be adjusted until the initial output signal of the sensitive amplifier changes.

[0012] Preferably, the memory further includes N second adjustment modules and N resistors. The two input terminals of the sensitive amplifier are respectively connected to one end of the corresponding second adjustment module and one end of the corresponding resistor. The other end of both the resistor and the second adjustment module is connected to the MUX circuit. Before determining any one of the first adjustment modules as the reference adjustment module upon receiving a control command, the method further includes:

[0013] Identify any one of the unadjusted second adjustment modules as the adjustment module to be adjusted;

[0014] By controlling the MUX circuit, the potentials at both ends of the sensitive amplifier corresponding to the module to be adjusted are made equal;

[0015] Adjust the equivalent resistance value of the module to be adjusted according to the output signal of the sensitive amplifier corresponding to the module to be adjusted, so that the equivalent resistance value of the module to be adjusted is equal to the resistance value of the resistor connected to the sensitive amplifier corresponding to the module to be adjusted.

[0016] Determine whether the equivalent resistance value of all the second adjustment modules is equal to the resistance value of the resistor connected to the sensitive amplifier corresponding to the second adjustment module. If they are not equal, return to the step of determining any one of the unadjusted second adjustment modules as the adjustment module to be adjusted. If they are equal, proceed to the step of determining any one of the first adjustment modules as the reference adjustment module when the control command is received.

[0017] Preferably, the first adjustment module includes multiple resistors and a controllable switch. The multiple resistors are connected in series and connected in series with the first input terminal of the sensitive amplifier connected to the adjustment module and the reference circuit corresponding to the adjustment module. A controllable switch is connected in parallel across each resistor. Adjusting the equivalent resistance value of the adjustment module includes:

[0018] The number of resistors connected to the circuit is controlled by controlling the on / off state of the controllable switch.

[0019] Preferably, the resistor is an MTJ or poly resistor.

[0020] Preferably, the first adjustment module includes multiple parallel-connected MOSFETs, and adjusting the equivalent resistance value of the adjustment module includes:

[0021] The equivalent resistance value of the adjustment module is adjusted by controlling the number of MOS transistors connected to the circuit.

[0022] Preferably, the sensitive amplifier is a current comparator or a voltage comparator.

[0023] Preferably, one of the other unadjusted first adjustment modules is selected as the adjustment module to be adjusted, including:

[0024] The first unadjusted adjustment module that is closest to the reference adjustment module is identified as the adjustment module to be adjusted.

[0025] Adjusting the equivalent resistance value of the adjustment module to be adjusted based on the output signal of the sensitive amplifier, and then further including:

[0026] The module to be adjusted is used as the new benchmark adjustment module.

[0027] The present invention also provides a memory read data stabilization device, including a control module, N sensitive amplifiers, N reference circuits, N first adjustment modules, N arrays and MUX circuits;

[0028] The input terminals of the sensitive amplifiers are all connected to the MUX circuit, and the output terminals are all connected to the control module.

[0029] Each of the reference circuits is connected in series with its corresponding first adjustment module and then connected to the MUX circuit.

[0030] The arrays are all connected to the MUX circuit;

[0031] The control module is also connected to N of the aforementioned sensitive amplifiers and N of the first adjustment modules;

[0032] The control module is used to execute the memory read data stabilization method described above.

[0033] Preferably, the control module is a BIST module.

[0034] This invention provides a method and apparatus for stabilizing read data in a memory. After determining the reference adjustment module, the equivalent resistance value of the reference adjustment module is adjusted to the pre-obtained optimal resistance value. Then, the second output terminal of the sensitive amplifier connected to the reference adjustment module is connected to the adjustment module to be adjusted. The adjustment module to be adjusted is adjusted according to the output signal of the sensitive amplifier, so that the total resistance value of each reference circuit and the first adjustment module connected in series with each reference circuit are equal. This increases the size of the read window, improves the stability of read data, and realizes the multiplexing of the sensitive amplifier in the memory. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart of a memory data read stabilization method provided by the present invention;

[0037] Figure 2 This is a schematic diagram of a memory read data stabilization device provided by the present invention;

[0038] Figure 3 This is a schematic diagram of another memory read data stabilization device provided by the present invention. Detailed Implementation

[0039] The core of this invention is to provide a method and apparatus for stabilizing data reading from a memory, which increases the size of the read window, improves the stability of data reading, and enables the reuse of the sensitive amplifier in the memory.

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Please refer to the details. Figure 1 , Figure 1 A flowchart of a memory data reading stabilization method provided by the present invention.

[0042] A method for stabilizing read data in a memory is disclosed. The memory includes N sensitive amplifiers, N reference circuits, N first trimming modules, N arrays, and a MUX (Multiplexer) circuit. The input terminals of the sensitive amplifiers are all connected to the MUX circuit. Each reference circuit is connected to the MUX circuit in series with its corresponding first trimming module. Each array is connected to the MUX circuit. N is an integer not less than 2. The method for stabilizing read data in the memory includes:

[0043] S1: Upon receiving a control command, determine any one of the first trimming modules as the reference trimming module, adjust the equivalent resistance value of the reference trimming module to the optimal resistance value, and control the MUX circuit to connect the first input terminal of the sensitive amplifier corresponding to the reference trimming module, the reference trimming module, and the reference circuit corresponding to the reference trimming module in series and then ground them. The optimal resistance value is the resistance value of the first trimming module that is predetermined by reading and writing the array to achieve the best read stability.

[0044] When reading data from the array, the accuracy of the data reading is related to the equivalent resistance value of the reference circuit connected to one input terminal of the sensitive amplifier. By performing read and write operations on the array beforehand, the equivalent resistance value of the reference circuit with the best stability when reading data can be obtained based on the stability during data reading. In the prior art, the equivalent resistance value of all reference circuits is directly set to the optimal resistance value during production. However, due to the manufacturing process deviations of various components such as MOSFETs and resistors in the reference circuit, the equivalent resistance values ​​of each reference circuit have deviations. In this embodiment, an additional first adjustment module corresponding to each of the N reference circuits is set. By adjusting the resistance value of the first adjustment module connected in series with the reference circuit, the total equivalent resistance value of the reference circuit and the first adjustment module corresponding to the reference circuit is changed. In this embodiment, one of the N first adjustment modules is first determined as the reference adjustment module, and then the equivalent resistance value of the reference adjustment module is adjusted to the optimal resistance value so that the total equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module is the equivalent resistance value with the best stability when reading data from the array. This is so that, using the reference adjustment module as a benchmark, other first adjustment modules can be adjusted so that the total equivalent resistance of the other first adjustment modules and the reference circuits corresponding to the other first adjustment modules connected in series is the equivalent resistance value that provides the best stability when reading data from the array.

[0045] Furthermore, the memory here can be, but is not limited to, MRAM.

[0046] S2: Determine any one of the other unadjusted first trimming modules as the trimming module to be adjusted, and control the MUX circuit to connect the second input terminal of the sensitive amplifier corresponding to the reference trimming module, the trimming module to be adjusted, and the reference circuit corresponding to the trimming module to be adjusted in series and then ground it.

[0047] In order to adjust other first adjustment modules according to the reference adjustment module, so that the total equivalent resistance value of the other first adjustment modules and the reference circuit corresponding to the other first adjustment modules in series is equal to the total equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module in series, in this embodiment, other unadjusted first adjustment modules are first identified as adjustment modules to be adjusted. Other unadjusted first adjustment modules refer to first adjustment modules whose equivalent resistance value has not been adjusted to the optimal resistance value, other than the reference adjustment module. After determining the adjustment modules to be adjusted, the control MUX circuit connects the second input terminal of the sensitive amplifier corresponding to the reference adjustment module, the adjustment module to be adjusted, and the reference circuit corresponding to the adjustment module to be adjusted in series and then grounds them, so that the adjustment module to be adjusted and the reference adjustment module are respectively connected to the two ends of the sensitive amplifier corresponding to the reference adjustment module.

[0048] S3: Adjust the equivalent resistance value of the adjustment module to be adjusted according to the output signal of the sensitive amplifier so that the equivalent resistance value of the adjustment module to be adjusted and the reference circuit corresponding to the adjustment module in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module in series.

[0049] In this embodiment, the built-in sensitive amplifier in the memory is used as a comparator. One input of the sensitive amplifier is connected to the reference tuning module and the corresponding reference circuit, and the other input is connected to the tuning module to be tuned and the corresponding reference circuit. The equivalent resistance value of the tuning module to be tuned is adjusted according to the output signal of the sensitive amplifier. For example, before adjusting the tuning module to be tuned, the output signal of the sensitive amplifier is 0. When the resistance value of the tuning module to be tuned is adjusted so that the output signal of the sensitive amplifier becomes 1, it is considered that the total equivalent resistance value of the reference tuning module and the corresponding reference circuit connected in series is equal to the total equivalent resistance value of the tuning module and the corresponding reference circuit connected in series.

[0050] S4: Determine whether the equivalent resistance value of all first adjustment modules and the reference circuit corresponding to the first adjustment module connected in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module connected in series. If they are not equal, return to the step of determining any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted.

[0051] After adjusting the adjustment module, it is necessary to determine whether the equivalent resistance value of all first adjustment modules and the reference circuit corresponding to the first adjustment module connected in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module connected in series. In other words, it is necessary to determine whether the adjustment of all first adjustment modules has been completed so that the total equivalent resistance value of all first adjustment modules and the reference circuit corresponding to the first adjustment module connected in series is equal. If the judgment result is that the equivalent resistance value of all first adjustment modules and the corresponding reference circuits connected in series is equal to the equivalent resistance value of the reference adjustment module and the corresponding reference circuits connected in series, then it means that all first adjustment modules have been adjusted and the test is over. If the judgment result is that the equivalent resistance value of some first adjustment modules and the corresponding reference circuits connected in series is not equal to the equivalent resistance value of the reference adjustment module and the corresponding reference circuits connected in series, then it means that some first adjustment modules have not been adjusted. Therefore, it is necessary to return to the step of determining any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted in order to complete the adjustment of all first adjustment modules.

[0052] In summary, in this embodiment, after determining the reference adjustment module, the equivalent resistance value of the reference adjustment module is adjusted to the pre-obtained optimal resistance value. Then, the second output terminal of the sensitive amplifier connected to the reference adjustment module is connected to the adjustment module to be adjusted. The adjustment module to be adjusted is adjusted according to the output signal of the sensitive amplifier, so that the total resistance value of each reference circuit and the first adjustment module connected in series with each reference circuit are equal. This increases the size of the read window, improves the stability of data reading, and realizes the multiplexing of the sensitive amplifier in the memory.

[0053] Based on the above embodiments:

[0054] As a preferred embodiment, adjusting the equivalent resistance value of the adjustment module to be adjusted based on the output signal of the sensitive amplifier includes:

[0055] Determine the initial output signal of the sensitive amplifier;

[0056] Adjust the equivalent resistance value of the module to be adjusted until the initial output signal of the sensitive amplifier changes.

[0057] Since the output signal of the sensitive amplifier changes when the equivalent resistance values ​​at the two input terminals change from unequal to equal, in this embodiment, at the moment when the output signal of the sensitive amplifier changes, it is determined that the total equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module connected in series is exactly equal to the total equivalent resistance value of the adjustment module to be adjusted and the reference circuit corresponding to the adjustment module to be adjusted connected in series.

[0058] Specifically, first, determine the initial output signal of the sensitive amplifier, for example, whether the initial output signal is 0 or 1, so that changes in the sensitive amplifier's output signal can be determined based on the initial output signal. Then, adjust the equivalent resistance value of the module to be adjusted until the sensitive amplifier's output signal changes. For example, if the initial output signal of the sensitive amplifier is 0, adjust the equivalent resistance value of the module to be adjusted until the sensitive amplifier's output signal becomes 1. This method achieves simple and accurate adjustment of the equivalent resistance value of the module to be adjusted.

[0059] Please refer to the details. Figure 3 , Figure 3 This is a schematic diagram of another memory read data stabilization device provided by the present invention.

[0060] In a preferred embodiment, the memory further includes N second adjustment modules 31 and N resistors 32. The two input terminals of the sensitive amplifier 21 are respectively connected to one end of the corresponding second adjustment module 31 and one end of the corresponding resistor 32. The other ends of both the resistors 32 and the second adjustment modules 31 are connected to the MUX circuit 25. Before determining any first adjustment module 23 as the reference adjustment module upon receiving a control command, the memory further includes:

[0061] Select any one of the unadjusted second adjustment modules 31 as the adjustment module to be adjusted;

[0062] By controlling the MUX circuit 25, the potentials at both ends of the sensitive amplifier 21 corresponding to the module to be adjusted are made equal;

[0063] Adjust the equivalent resistance value of the module to be adjusted according to the output signal of the sensitive amplifier 21 corresponding to the module to be adjusted, so that the equivalent resistance value of the module to be adjusted is equal to the resistance value of the resistor 32 connected to the sensitive amplifier 21 corresponding to the module to be adjusted.

[0064] Determine whether the equivalent resistance value of all second adjustment modules 31 is equal to the resistance value of the resistor 32 connected to the sensitive amplifier 21 corresponding to the second adjustment module 31. If they are not equal, return to the step of determining any one of the unadjusted second adjustment modules 31 as the adjustment module to be adjusted. If they are equal, proceed to the step of determining any one of the first adjustment modules 23 as the reference adjustment module when the control command is received.

[0065] Considering that process variations between the MOS transistors used to build the sensitive amplifier 21 can affect its comparison performance, the total equivalent resistance of the reference adjustment module and the corresponding reference circuit 22 connected in series cannot be exactly equal to the total equivalent resistance of the module to be adjusted and the corresponding reference circuit 22 connected in series when the output signal of the sensitive amplifier 21 changes. To address this technical problem, in this embodiment, N second adjustment modules 31 and N resistors 32 are also provided in the memory. By adjusting the equivalent resistance of the second adjustment module 31 corresponding to each sensitive amplifier 21, the resistance values ​​of the second adjustment module 31 and resistor 32 connected to the two input terminals of each sensitive amplifier 21 are made equal. This ensures that regardless of which first adjustment module 23 is used as the reference adjustment module, the error introduced by the sensitive amplifier 21 itself will not affect the comparison performance, improving the comparison accuracy of the sensitive amplifier 21 and making the results after adjusting each first adjustment module 23 more accurate.

[0066] In a preferred embodiment, the first adjustment module 23 includes multiple resistors and a controllable switch. The multiple resistors are connected in series and connected in series with the first input terminal of the sensitive amplifier 21 connected to the adjustment module and the reference circuit 22 corresponding to the adjustment module. A controllable switch is connected in parallel across each resistor. Adjusting the equivalent resistance value of the adjustment module includes:

[0067] The number of resistors connected to the circuit is controlled by controlling the on / off state of a controllable switch.

[0068] To facilitate adjustment of the equivalent resistance value of the first adjustment module 23, in this embodiment, each first adjustment module 23 includes multiple resistors and controllable switches, with a controllable switch connected in parallel across each resistor. When the controllable switch across a resistor receives a control command and is closed, the resistor connected in parallel with the closed controllable switch is short-circuited and not connected to the circuit. When the controllable switch across a resistor receives a control command and is open, the resistor connected in parallel with the open controllable switch is connected to the circuit. Therefore, the equivalent resistance value of the first adjustment module 23 is equal to the total resistance value after connecting all resistors connected in parallel with the open controllable switches in series. Adjustment of the equivalent resistance value of the first adjustment module 23 is achieved by controlling each controllable switch, and the implementation method is simple.

[0069] It should also be noted that the controllable switch here can be, but is not limited to, a MOSFET.

[0070] As a preferred embodiment, the resistor is an MTJ (Magnetic Tunnel Junction) or a poly resistor.

[0071] MTJs typically consist of three basic layers: a ferromagnetic layer, an insulating tunneling layer, and a fixed layer. When the magnetic moments of the ferromagnetic and fixed layers are opposite, the memory exhibits a high-resistivity state; when their magnetic moments are equal, the memory exhibits a low-resistivity state. MTJs offer advantages such as high resistivity, low power consumption, and stable performance. Poly resistors also possess advantages such as small resistance deviation and controllable temperature coefficients.

[0072] In a preferred embodiment, the first adjustment module 23 includes multiple parallel-connected MOSFETs, and adjusting the equivalent resistance value of the adjustment module to be adjusted includes:

[0073] The equivalent resistance value of the module to be adjusted is adjusted by controlling the number of MOSFETs connected to the circuit.

[0074] In order to facilitate the adjustment of the equivalent resistance value of the first adjustment module 23, in this embodiment, each first adjustment module 23 includes multiple parallel MOS transistors, which realizes the adjustment of the equivalent resistance value of the first adjustment module 23 and the circuit design is simple.

[0075] In a preferred embodiment, the sensitive amplifier 21 is a current comparator or a voltage comparator.

[0076] In this embodiment, the sensitive amplifier 21 is a current comparator or a voltage comparator. When the sensitive amplifier 21 is a current comparator, the total resistance of each reference circuit 22 and the first adjustment module 23 connected in series with each reference circuit 22 is compared by comparing the current nodes between each reference circuit 22. When the sensitive amplifier 21 is a voltage comparator, the total resistance of each reference circuit 22 and the first adjustment module 23 connected in series with each reference circuit 22 is compared by comparing the voltage nodes between each reference circuit 22. This can meet the different needs of users under different circuit structures and different application scenarios.

[0077] As a preferred embodiment, one of the other unadjusted first adjustment modules 23 is identified as the adjustment module to be adjusted, including:

[0078] The first unadjusted adjustment module 23, which is closest to the reference adjustment module, is identified as the adjustment module to be adjusted.

[0079] Adjusting the equivalent resistance value of the module to be adjusted based on the output signal of the sensitive amplifier 21, and then including:

[0080] The module to be adjusted is used as the new benchmark adjustment module.

[0081] Considering the large number of array 24 modules, after determining the reference adjustment module, a large number of first adjustment modules 23 need to be compared with the reference adjustment module. When the distance between the adjustment module to be adjusted and the reference adjustment module is large, excessively long circuits will result in excessive line resistance, thus affecting the comparison result of the sensitive amplifier 21. To solve this problem, in this embodiment, the first adjustment module 23 closest to the reference adjustment module that has not been adjusted is selected as the adjustment module to be adjusted. After adjusting the equivalent resistance value of the adjustment module to be adjusted according to the output signal of the sensitive amplifier 21, the adjustment module to be adjusted is then used as a new reference adjustment module. Then, the first adjustment module 23 closest to the new reference adjustment module that has not been adjusted is selected as the adjustment module to be adjusted. Adjusting each first adjustment module 23 in this way ensures that the adjustment module to be adjusted compared with the reference adjustment module each time is the closest to the reference adjustment module, minimizing the impact of line resistance on the comparison result of the sensitive amplifier 21, making the calibration result more accurate, and improving read stability.

[0082] Please refer to the details. Figure 2 , Figure 2 This is a schematic diagram of a memory data reading stabilization device provided by the present invention.

[0083] The present invention also provides a memory read data stabilization device, including a control module 26, N sensitive amplifiers 21, N reference circuits 22, N first adjustment modules 23, N arrays 24 and MUX circuit 25;

[0084] The input terminals of the sensitive amplifier 21 are all connected to the MUX circuit 25, and the output terminals are all connected to the control module 26;

[0085] Each of the reference circuits 22 is connected in series with its corresponding first trimming module 23 and then connected to the MUX circuit 25.

[0086] Array 24 is connected to MUX circuit 25;

[0087] The control module 26 is also connected to N sensitive amplifiers 21 and N first adjustment modules 23;

[0088] The control module 26 is used to execute the memory read data stabilization method as described above.

[0089] In a preferred embodiment, the control module 26 is a BIST module.

[0090] For details regarding the memory read data stabilization device, please refer to the above embodiments; further details will not be repeated here.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0092] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for stabilizing data reads from a memory, characterized in that, Applied to a memory, the memory includes N sensitive amplifiers, N reference circuits, N first trimming modules, N arrays and MUX circuits, where N is an integer not less than 2. The memory read data stabilization method includes: Upon receiving a control command, any one of the first adjustment modules is determined as the reference adjustment module. The equivalent resistance value of the reference adjustment module is adjusted to the optimal resistance value. The MUX circuit is controlled to connect the first input terminal of the sensitive amplifier corresponding to the reference adjustment module, the reference adjustment module, and the reference circuit corresponding to the reference adjustment module in series and then ground. Identify any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted, and control the MUX circuit to connect the second input terminal of the sensitive amplifier corresponding to the reference adjustment module, the adjustment module to be adjusted, and the reference circuit corresponding to the adjustment module to be adjusted in series and then ground it; The equivalent resistance value of the adjustment module to be adjusted is adjusted according to the output signal of the sensitive amplifier, so that the equivalent resistance value of the adjustment module to be adjusted and the reference circuit corresponding to the adjustment module in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module in series. Determine whether the equivalent resistance value of all the first adjustment modules and the reference circuit corresponding to the first adjustment module connected in series is equal to the equivalent resistance value of the reference adjustment module and the reference circuit corresponding to the reference adjustment module connected in series. If they are not equal, return to the step of determining any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted.

2. The memory read data stabilization method as described in claim 1, characterized in that, Adjusting the equivalent resistance value of the module to be adjusted based on the output signal of the sensitive amplifier includes: Determine the initial output signal of the sensitive amplifier; Adjust the equivalent resistance value of the module to be adjusted until the initial output signal of the sensitive amplifier changes.

3. The memory read data stabilization method as described in claim 1, characterized in that, The memory further includes N second adjustment modules and N resistors. The two input terminals of the sensitive amplifier are respectively connected to one end of the corresponding second adjustment module and one end of the corresponding resistor. The other end of both the resistor and the second adjustment module is connected to the MUX circuit. Before determining any one of the first adjustment modules as the reference adjustment module upon receiving a control command, the system further includes: Identify any one of the unadjusted second adjustment modules as the adjustment module to be adjusted; By controlling the MUX circuit, the potentials at both ends of the sensitive amplifier corresponding to the module to be adjusted are made equal; Adjust the equivalent resistance value of the module to be adjusted according to the output signal of the sensitive amplifier corresponding to the module to be adjusted, so that the equivalent resistance value of the module to be adjusted is equal to the resistance value of the resistor connected to the sensitive amplifier corresponding to the module to be adjusted. Determine whether the equivalent resistance value of all the second adjustment modules is equal to the resistance value of the resistor connected to the sensitive amplifier corresponding to the second adjustment module. If they are not equal, return to the step of determining any one of the unadjusted second adjustment modules as the adjustment module to be adjusted. If they are equal, proceed to the step of determining any one of the first adjustment modules as the reference adjustment module when the control command is received.

4. The memory read data stabilization method as described in claim 1, characterized in that, The first adjustment module includes multiple resistors and controllable switches. The resistors are connected in series and then connected in series with the first input terminal of a sensitive amplifier connected to the adjustment module and a reference circuit corresponding to the adjustment module. Each resistor is connected in parallel with a controllable switch. Adjusting the equivalent resistance value of the adjustment module includes: The number of resistors connected to the circuit is controlled by controlling the on / off state of the controllable switch.

5. The memory read data stabilization method as described in claim 4, characterized in that, The resistor is an MTJ or poly resistor.

6. The memory read data stabilization method as described in claim 1, characterized in that, The first adjustment module includes multiple parallel-connected MOSFETs. Adjusting the equivalent resistance value of the adjustment module includes: The equivalent resistance value of the adjustment module is adjusted by controlling the number of MOS transistors connected to the circuit.

7. The memory read data stabilization method as described in claim 1, characterized in that, The sensitive amplifier is a current comparator or a voltage comparator.

8. The memory read data stabilization method according to any one of claims 1 to 7, characterized in that, Identify any one of the other unadjusted first adjustment modules as the adjustment module to be adjusted, including: The first unadjusted adjustment module that is closest to the reference adjustment module is identified as the adjustment module to be adjusted. Adjusting the equivalent resistance value of the adjustment module to be adjusted based on the output signal of the sensitive amplifier, and then further including: The module to be adjusted is used as the new benchmark adjustment module.

9. A memory read data stabilization device, characterized in that, It includes a control module, N sensitive amplifiers, N reference circuits, N first adjustment modules, N arrays and MUX circuits; The input terminals of the sensitive amplifiers are all connected to the MUX circuit, and the output terminals are all connected to the control module. Each of the reference circuits is connected in series with its corresponding first adjustment module and then connected to the MUX circuit. The arrays are all connected to the MUX circuit; The control module is also connected to N of the aforementioned sensitive amplifiers and N of the first adjustment modules; The control module is used to execute the memory read data stabilization method as described in any one of claims 1 to 8.

10. The memory read data stabilization device as described in claim 9, characterized in that, The control module is a BIST module.

Images