A current limiting and voltage stabilizing source circuit

Abstract

The present invention belongs to the technical field of power supply design and discloses a current-limiting and voltage-stabilizing power supply circuit, comprising an overheat protection circuit, an overcurrent protection circuit, a boost circuit, a PMOS transistor V2, an NMOS switch transistor U1, an amplifier U2A, resistors R24 and R37, a soft-start circuit, a reference voltage generating circuit, and a capacitor C9. The soft-start circuit is used to achieve circuit soft-start, and its output end and the reference voltage generating circuit are connected to the same input end of the amplifier U2A. The boost circuit is used to boost the input voltage and then supply power to the gate of the PMOS transistor V2. The source of the PMOS transistor V2 is connected to the output end of the amplifier U2A, and the drain is connected to the gate of the NMOS switch transistor U1. The drain of the NMOS switch transistor U1 is connected to the input power supply, and the source is connected to the output end. The source of the NMOS switch transistor U1 is grounded via resistors R24 and R37, and the input end of the resistor R37 is connected to the inverting input end of the amplifier U2A. The present invention is applicable to application scenarios with heavy loads, low ripple, and high heat loss requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of power supply design, and in particular relates to a current-limiting and voltage-stabilizing source circuit. Background Art

[0002] In the prior art, linear power supplies (LDOs) generally use PMOS as the regulator tube. This is because PMOS linear power supplies only need to ensure that the gate voltage of the PMOS tube is lower than the source voltage and the voltage difference is greater than the conduction threshold. This makes the circuit design relatively simple and reduces design costs. For NMOS-type LDOs, on the other hand, the gate voltage must be raised above the source voltage to function properly, which often requires the addition of a boost circuit. Therefore, compared with PMOS-type LDOs, NMOS-type LDOs increase circuit complexity. In addition, traditional linear power supplies all have a large voltage drop, especially under excessive load conditions, resulting in low efficiency, severe heat generation, and large losses.

[0003] Therefore, it is necessary to provide a current limiting and voltage stabilizing source circuit with small voltage drop and better performance. Summary of the Invention

[0004] In order to meet the actual needs of the power supply design field, the present invention overcomes the shortcomings of the existing technology and solves the technical problem of providing a current-limiting and voltage-stabilizing source circuit with small voltage difference and low heat generation, which is suitable for application scenarios with large load, low ripple and high heat loss requirements.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a current limiting and voltage stabilizing source circuit, including an overheating protection circuit, an overcurrent protection circuit, a boost circuit, a PMOS tube V2, an NMOS switch tube U1, an amplifier U2A, a resistor R24, a resistor R37, a soft start circuit, a reference voltage generating circuit, and a capacitor C9;

[0006] The overheat protection circuit is used to generate an overheat signal OTP, the overcurrent protection circuit is used to output an overcurrent protection signal OCP, and the enable signal generating circuit is used to generate a cutoff enable signal according to the enable signal EN output by the main control MCU and the signals OTP and OCP;

[0007] The soft start circuit includes resistors R40, R44, R35, R36, R42, R32, R33, transistors V8, V10, diodes VD2, VD3, the reference voltage generating circuit includes resistor R39, voltage regulator TS3, one end of the resistor R40 is connected to the cutoff enable signal, the other end is connected to the base of the transistor V10, the emitter of the transistor V10 is grounded, the collector is connected to the base of the transistor V8 through the resistor R36, and the emitter of the transistor V8 is connected The positive electrode of the power supply, the collector of the transistor V10 is connected to the positive electrode of the power supply through the resistor R35, the resistor R44 is connected between the base and the emitter of the transistor V10, the anode of the diode VD2 is connected to the collector of the transistor V8, and the cathode is grounded through the diode VD3 and the resistor R42, one end of the resistor R22 is connected to the anode of the diode VD2, and the other end is connected to the emitter of the transistor V9 through the resistor R22, the base of the transistor V9 is grounded through the resistor R42, and the collector is connected to the non-inverting input terminal of the amplifier U2A;

[0008] One end of the resistor R39 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded. One end of the capacitor C9 is connected to the non-inverting input terminal of the amplifier U2A and the control terminal of the voltage regulator TS3, and the other end is grounded. One end of the voltage regulator TS3 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded.

[0009] The boost circuit is used to boost the input voltage and then supply power to the gate of the PMOS transistor V2 under the control of the cutoff enable signal. The source of the PMOS transistor V2 is connected to the output end of the amplifier U2A, and the drain is connected to the gate of the NMOS switch transistor U1. The drain of the NMOS switch transistor U1 is connected to the input power supply, and the source is connected to the output end.

[0010] The source of the NMOS switch U1 is grounded through the resistor R24 ​​and the resistor R37 , and the input end of the resistor R37 is connected to the inverting input end of the amplifier U2A.

[0011] Preferably, the overcurrent protection circuit includes: a current sampling circuit, resistors R5, R6, R10, R19, R20, R28, R23, R25, R28, R31, R22, R27, amplifiers U2B, U2D, diode VD1, transistors V3, V6, V7, capacitors C2, C5;

[0012] The output signal Ifb of the current sampling circuit is connected to the inverting input terminal of the amplifier U2B. The non-inverting input terminal of the amplifier U2B is connected to the positive electrode of the power supply through the resistor R5 and is also grounded through the capacitor C2. The resistors R6 and R10 are connected in series and then connected in parallel with the capacitor C2. The output terminal of the amplifier U2B is connected to the emitter of the transistor V3 through the diode VD2. The base of the transistor V3 is connected to the source of the PMOS tube V2. The collector is connected to the emitter and base of the transistor V6 through the resistors R19 and R20 respectively. The emitter of transistor V6 is connected to the positive pole of the power supply, the collector is connected to the base of transistor V7 through resistor R28, the base of transistor V7 is also grounded through resistor R31, the emitter of transistor V7 is grounded, the collector is connected to the positive pole of the power supply through resistor R23, the collector is also connected to the inverting input terminal of amplifier U2D through resistor R25, the inverting input terminal of amplifier U2D is also grounded through capacitor C5, the non-inverting input terminal is connected to the output terminal through resistor R22, and the output terminal outputs the overcurrent protection signal OCP through resistor R27.

[0013] Preferably, the overcurrent protection circuit also includes: resistors R13, R17, R18 and capacitor C3, one end of the resistor R17 is connected to the non-inverting input terminal of the amplifier U2D, the other end is connected to the positive electrode of the power supply through the resistor R13, and the other end is also grounded through the resistor R18 and capacitor C3 connected in parallel.

[0014] Preferably, the overcurrent protection circuit also includes resistors R26, R29 and a transistor V5. The output end of the amplifier U2D is connected to the base of the transistor V5 through the resistor R26. One end of the resistor R29 is connected to the base of the transistor V5, and the other end is grounded. The emitter of the transistor V5 is grounded, and the collector is used to output an overcurrent signal 4G-Overload to the main control MCU.

[0015] Preferably, the current sampling signal includes a resistor R38, a resistor R41, a resistor R43, a resistor R34, a capacitor C8, and an amplifier U2C. The non-inverting input terminal of the amplifier U2C is connected to the input power supply through the resistor R41, and the non-inverting input terminal is also grounded through the resistor R43 and the resistor R20. The inverting input terminal is connected to the drain of the NMOS switch tube U1 through the resistor R38, and the output terminal is connected to the inverting input terminal through the resistor R34 and the capacitor C8 connected in parallel. The output terminal is also connected to the non-inverting input terminal of the amplifier U2B.

[0016] Preferably, the current-limiting and voltage-stabilizing source circuit further includes resistors R15, R16, R21, and R8, a transistor V4, and a voltage regulator TS1. One end of the resistor R16 is connected to the cutoff enable signal, the other end is connected to the base of the transistor V4, and the other end is also grounded through a resistor R21. The emitter of the transistor V4 is grounded, and the collector is connected to the positive electrode of the power supply output by the boost circuit through a resistor R11. The collector is also connected to the gate of the PMOS tube V2. The resistor R15 is arranged between the gate of the PMOS tube V2 and the output end of the amplifier U2A. After the resistor R8 is connected in parallel with the voltage regulator TS1, one end is connected to the gate of the NMOS switch tube U1, and the other end is connected to the source of the NMOS switch tube U1.

[0017] Preferably, the current-limiting and voltage-stabilizing source circuit further includes a capacitor C6 and a capacitor C7, wherein the capacitor C6 is arranged between the inverting input terminal and the output terminal of the amplifier U2A, and the capacitor C7 is connected in parallel with the resistor R24.

[0018] Preferably, the boost circuit includes a boost chip U14, a resistor R49, a resistor R50, a capacitor C14, an inductor L1, and a Zener diode TS4. Pins IN and EN of the boost chip U14 are connected to the input power supply, pin SW is connected to the input power supply through the inductor L1, and pin SW also outputs the boost voltage through the Zener diode TS4. Pin GND is connected to pin FB through resistor R49, and pin FB is connected to the output end of the Zener diode TS4 through resistor R50. Capacitor C14 is connected in parallel with resistor R50, and is connected to pin GND of the boost chip U14 through resistor R50 and resistor R49 connected in series.

[0019] Preferably, the enable signal generating circuit includes resistors R45, R46, R47, a transistor V11 and a transistor V12, the base of the transistor V11 is connected to the overcurrent protection signal OCP, the base is also grounded through a resistor R46, the emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through a resistor R45; the base of the transistor V12 is connected to the overheating signal OTP, the base is also grounded through a resistor R47, the emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through a resistor R45, and the collectors of the transistors V11 and V12 output cutoff enable signals.

[0020] Preferably, the overheat protection circuit includes a thermistor R14, a voltage regulator TS2, and a transistor V1. One end of the thermistor R14 is connected to the reference end of the voltage regulator TS2, and the other end is grounded. The cathode of the voltage regulator TS2 is grounded, and the anode is connected to the base and emitter of the transistor V1 through resistors R7 and R4. One end of the thermistor R14 is also connected to the positive electrode of the power supply through resistors R3, R9, and R12. The collector of the S transistor V1 outputs an overheat signal OTP through the resistor R1.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The present invention provides a current-limiting and voltage-stabilizing source circuit, the output of which is realized through a voltage-dividing resistor, with small voltage fluctuation and output ripple;

[0023] 2. The present invention can realize large load circuits and be applied to large load scenarios. According to the actual application, the appropriate switch tube can be selected to be applied to large load circuits;

[0024] 3. Low heat loss: Since NMOS tube is used as the switching tube, its voltage drop can be very low. Generally, the output voltage can be stabilized at an input-output of about 200mV, and the ripple is very small. Moreover, the internal resistance of the switching tube is very low. Taking the NMOS tube MQ28N03T1 used as an example, the internal resistance is about 18mΩ. Calculated according to the peak current of 3A, the heat loss is 0.2V*18mR*3A=0.0108W, which is almost negligible. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a principle block diagram of a current-limiting and voltage-stabilizing source circuit proposed in an embodiment of the present invention;

[0026] Figure 2 A circuit schematic diagram of a current-limiting and voltage-stabilizing source circuit proposed in an embodiment of the present invention;

[0027] Figure 3 is a circuit schematic diagram of a current sampling circuit in an embodiment of the present invention;

[0028] Figure 4 1 is a circuit diagram of an overheat protection circuit according to an embodiment of the present invention;

[0029] Figure 5 1 is a circuit schematic diagram of an enable signal generating circuit according to an embodiment of the present invention;

[0030] Figure 6 1 is a circuit schematic diagram of a boost circuit in an embodiment of the present invention; DETAILED DESCRIPTION

[0031] In order to make the technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments and drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, embodiment 1 of the present invention provides a current limiting and voltage stabilizing source circuit, including an overheating protection circuit, an overcurrent protection circuit, a boost circuit, a PMOS tube V2, an NMOS switch tube U1, an amplifier U2A, a resistor R24, a resistor R30, a resistor R37, a soft start circuit, a reference voltage generating circuit, and a capacitor C9.

[0033] The overheat protection circuit is used to generate an overheat signal OTP, the overcurrent protection circuit is used to output an overcurrent protection signal OCP, and the enable signal generating circuit is used to generate a cutoff enable signal according to the enable signal EN and signals OTP and OCP output by the main control MCU.

[0034] The main function of the soft start circuit is to prevent the power supply system from failing to start normally due to a heavy load, and is used to achieve soft start of the circuit.

[0035] like Figure 2 As shown, the soft start circuit includes resistors R40, R44, R35, R36, R42, R32, R33, transistors V8, V10, diodes VD2, VD3, and the reference voltage generating circuit includes a resistor R39 and a voltage regulator TS3.

[0036] Specifically, one end of the resistor R40 is connected to the cutoff enable signal, and the other end is connected to the base of the transistor V10. The emitter of the transistor V10 is grounded, the collector is connected to the base of the transistor V8 through the resistor R36, the emitter of the transistor V8 is connected to the positive electrode of the power supply, the collector of the transistor V10 is connected to the positive electrode of the power supply through the resistor R35, the resistor R44 is connected between the base and the emitter of the transistor V10, the anode of the diode VD2 is connected to the collector of the transistor V8, and the cathode is grounded through the diode VD3 and the resistor R42. One end of the resistor R22 is connected to the anode of the diode VD2, and the other end is connected to the emitter of the transistor V9 through the resistor R22. The base of the transistor V9 is grounded through the resistor R42, and the collector is connected to the non-inverting input terminal of the amplifier U2A; one end of the resistor R39 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded. One end of the capacitor C9 is connected to the non-inverting input terminal of the amplifier U2A and the control end of the voltage regulator TS3, and the other end is grounded. One end of the voltage regulator TS3 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded.

[0037] The boost circuit is used to boost the input voltage and then supply power to the gate of the PMOS transistor V2 under the control of the cutoff enable signal. The source of the PMOS transistor V2 is connected to the output of the amplifier U2A, and the drain is connected to the gate of the NMOS switch transistor U1. The drain of the NMOS switch transistor U1 is connected to the input power supply, and the source is connected to the output. The source of the NMOS switch transistor U1 is grounded via resistors R24, R30, and R37. The input of resistor R37 is connected to the inverting input of the amplifier U2A.

[0038] like Figure 2 As shown, in this embodiment, the overcurrent protection circuit includes: a current sampling circuit, resistors R5, R6, R10, R19, R20, R28, R23, R25, R28, R31, R22, R27, amplifiers U2B, U2D, diode VD1, transistors V3, V6, V7, capacitors C2, C5;

[0039] The output signal Ifb of the current sampling circuit is connected to the inverting input terminal of the amplifier U2B. The non-inverting input terminal of the amplifier U2B is connected to the positive electrode of the power supply through the resistor R5 and is also grounded through the capacitor C2. The resistors R6 and R10 are connected in series and then connected in parallel with the capacitor C2. The output terminal of the amplifier U2B is connected to the emitter of the transistor V3 through the diode VD2. The base of the transistor V3 is connected to the source of the PMOS tube V2 (that is, the output terminal of the amplifier U2A). The collector is connected to the emitter of the transistor V6 through the resistors R19 and R20 respectively. The emitter and base are connected, the emitter of the transistor V6 is connected to the positive pole of the power supply, the collector is connected to the base of the transistor V7 through the resistor R28, the base of the transistor V7 is also grounded through the resistor R31, the emitter of the transistor V7 is grounded, the collector is connected to the positive pole of the power supply through the resistor R23, the collector is also connected to the inverting input terminal of the amplifier U2D through the resistor R25, the inverting input terminal of the amplifier U2D is also grounded through the capacitor C5, the non-inverting input terminal is connected to the output terminal through the resistor R22, and the output terminal outputs the overcurrent protection signal OCP through the resistor R27.

[0040] Further, if Figure 2 As shown, the overcurrent protection circuit also includes: resistors R13, R17, R18 and capacitor C3, one end of the resistor R17 is connected to the non-inverting input terminal of the amplifier U2D, the other end is connected to the positive electrode of the power supply through the resistor R13, and the other end is also grounded through the resistor R18 and capacitor C3 connected in parallel.

[0041] Further, if Figure 2 As shown, the overcurrent protection circuit also includes resistors R26, R29 and a transistor V5. The output end of the amplifier U2D is connected to the base of the transistor V5 through the resistor R26. One end of the resistor R29 is connected to the base of the transistor V5, and the other end is grounded. The emitter of the transistor V5 is grounded, and the collector is used to output an overcurrent signal 4G-Overload to the main control MCU.

[0042] like Figure 3 As shown, the current sampling signal includes resistor R38, resistor R41, resistor R43, resistor R34, capacitor C8, and amplifier U2C. The non-inverting input terminal of the amplifier U2C is connected to the input power supply through resistor R41. The non-inverting input terminal is also connected to the resistor R20 through resistor R43 and grounded. The inverting input terminal is connected to the drain of the NMOS switch tube U1 through resistor R38. The output terminal is connected to the inverting input terminal through the parallel connection of resistor R34 and capacitor C8. The output terminal is also connected to the non-inverting input terminal of the amplifier U2B. Furthermore, it also includes a resistor R2, which is arranged between the drain of the NMOS switch tube U1 and the input power supply.

[0043] Further, if Figure 2As shown, the current-limiting and voltage-stabilizing source circuit further includes resistors R15, R16, R21, and R8, a transistor V4, and a voltage regulator TS1. One end of the resistor R16 is connected to the cutoff enable signal, the other end is connected to the base of the transistor V4, and the other end is also grounded through a resistor R21. The emitter of the transistor V4 is grounded, and the collector is connected to the positive electrode of the power supply output by the boost circuit through a resistor R11. The collector is also connected to the gate of the PMOS tube V2. The resistor R15 is arranged between the gate of the PMOS tube V2 and the output end of the amplifier U2A. After the resistor R8 is connected in parallel with the voltage regulator TS1, one end is connected to the gate of the NMOS switch tube U1, and the other end is connected to the source of the NMOS switch tube U1.

[0044] Furthermore, if Figure 2 As shown, the current limiting and voltage stabilizing source circuit further includes a capacitor C6 and a capacitor C7. The capacitor C6 is arranged between the inverting input terminal and the output terminal of the amplifier U2A, and the capacitor C7 is connected in parallel with the resistor R24.

[0045] Furthermore, if Figure 6 As shown, the boost circuit includes a boost chip U14, resistors R49 and R50, capacitor C14, inductor L1, and Zener diode TS4. Pins IN and EN of the boost chip U14 are connected to the input power supply, pin SW is connected to the input power supply through inductor L1, and pin SW also outputs the boosted voltage through Zener diode TS4. Pin GND is connected to pin FB through resistor R49, and pin FB is connected to the output end of Zener diode TS4 through resistor R50. Capacitor C14 is connected in parallel with resistor R50 and connected to pin GND of the boost chip U14 through resistors R50 and R49 in series. Since the embodiment of the present invention uses an NMOS transistor as a switching transistor, the gate voltage of the MOS transistor needs to be higher than the source voltage (output test voltage) to turn on, so it needs to be boosted to provide power to the error amplifier so that its output signal meets the conduction requirement. In this embodiment, the boost chip U14 uses the Nanlin boost chip LN2220 test voltage booster, which has an efficiency of up to 93% and an output voltage of up to 28V.

[0046] Furthermore, if Figure 5As shown, the enable signal generating circuit includes resistors R45, R46, and R47, a transistor V11, and a transistor V12. The base of the transistor V11 is connected to the overcurrent protection signal OCP, the base is further grounded through a resistor R46, the emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through a resistor R45; the base of the transistor V12 is connected to the overheating signal OTP, the base is further grounded through a resistor R47, the emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through a resistor R45. The collectors of the transistors V11 and V12 output cutoff enable signals.

[0047] Furthermore, if Figure 4 As shown, the overheat protection circuit includes a thermistor R14, a voltage regulator TS2, and a transistor V1. One end of the thermistor R14 is connected to the reference end of the voltage regulator TS2, and the other end is grounded. The cathode of the voltage regulator TS2 is grounded, and the anode is connected to the base and emitter of the transistor V1 through resistors R7 and R4. One end of the thermistor R14 is also connected to the positive electrode of the power supply through resistors R3, R9, and R12. The collector of the S transistor V1 outputs an overheat signal OTP through the resistor R1.

[0048] In this embodiment, the voltage regulator TS2 uses the ME431LAXG, which provides a 2.5V reference source. This chip operates with a low current draw of only 35uA, ensuring precise control across various temperature conditions. The NTC (R14) uses a 10kΩ resistor at 25°C with a B constant of 3380K. Based on its temperature-resistance curve, it is estimated that overtemperature protection occurs at approximately 115°C, at which point the NTC impedance is approximately 600Ω. As the temperature rises, the resistance drops further, causing the voltage at the reference terminal of the ME431LAXG chip to exceed 2.5V. This increases the internal conduction current of the ME431LAXG chip, raising the voltage drop across R4 and reducing the cathode voltage across R4. When the voltage difference exceeds the Vbe drop across V1, V1 conducts, causing the OTP signal to go high, which in turn causes V12 to conduct, causing the enable signal to go low and interrupting the output.

[0049] In this embodiment, the soft-start circuit operates as follows: During the startup phase, the main control MCU outputs a high-level enable signal EN. This generates a cutoff enable signal through the enable signal generation circuit, turning on transistor V10, which in turn pulls down the base of transistor V8. To control the amplified current of V8, a 100kΩ resistor R36 is used at the base to limit the current. Diodes VD2 and VD3 are connected in series to limit the current by clamping the voltage, ultimately limiting the current to approximately 1mA, which provides the operating current for Zener diode TS3. The voltage is ultimately stabilized at approximately 2.5V by charging capacitor C9. During the startup phase, the voltage at the positive input of amplifier U2A remains higher than the negative input. Therefore, due to the lack of negative feedback, the output voltage increases until it exceeds the turn-on voltage of PMOS transistor V2 (V2 uses a BSS84 PMOS transistor with a VGS turn-on voltage of approximately -1.6V). At this point, PMOS transistor V2 turns on, and the gate of NMOS transistor U1 becomes the high-level output of amplifier U2A. When the VGS voltage of NMOS transistor U1 is greater than the turn-on voltage (the turn-on voltage of NMOS transistor WNQ28N03T1 is about 2V), NMOS transistor U1 will be turned on and output 4V voltage. At this time, the feedback signal is input to the negative input terminal of amplifier U2A through the output voltage feedback resistor for regulation.

[0050] In the present invention, the overcurrent protection circuit can limit the output current and prevent the NMOS switch tube U1 from overheating. The positive input terminal of the amplifier U2B is used as a reference reference. Taking the positive pole of the power supply as 3.3V, R5=10Ω, R6=130Ω, and R10=10kΩ as an example, the reference voltage can be calculated as (3.3 / (R5+R6+R10))*(R6+R10)=3.2967V. The reverse input terminal of U2B is used as the current sampling signal input terminal, and the signal is input after the voltage drop of the sampling resistor R2 (10mR) is differentially amplified (1 times) by U2C. Note that the amplified signal lift voltage at this time is (3.3 / (R5+R6+R10))*R10=3.2544V. By calculation, it can be concluded that the current limit value is R2*I+3.254=3.297V, I=4.23A. When the current exceeds this value, U2B outputs a low-level signal, transistor V3 turns on, and then transistor V6 turns on, causing the base of transistor V7 to connect to the high-level signal. At this time, transistor V7 turns on, and capacitor C5 discharges through 47k resistor R25. The charging and discharging process of capacitor C5 forms a triangular wave.

[0051] Furthermore, in the present invention, amplifier U2D forms a hysteresis comparator that implements an overcurrent hiccup protection circuit. Its specific operating principle is as follows: the upper and lower threshold voltages at the positive input of the hysteresis comparator are 2.8V and 1.7V, respectively. During normal operation, the charge level of C5 at the reverse input is higher than the voltage at the positive input. At this time, outputting a low-level signal does not trigger overcurrent protection, and a low-level signal with a threshold voltage of 1.7V is output. When a current exceeding 4.23A is generated, C5 rapidly discharges through the conducting V7, causing the voltage at the reverse terminal of the hysteresis comparator to drop rapidly. When it falls below the positive threshold of 1.7V, a high-level signal is output, and the threshold voltage is now 2.8V. Simultaneously, the overcurrent protection (OCP) signal is triggered, turning on V11. This, in turn, pulls the cutoff voltage down, turning off V4. The gate of V2 is pulled up to 9V, turning it off. This gradually reduces the conduction state of U1, lowering the output current. Once the current returns to normal, C5 is recharged, and the circuit outputs a low-level signal until it exceeds the 2.8V positive threshold voltage. At this point, the threshold voltage drops to 1.7V, and the overcurrent protection trigger signal is cut off. As the current continues to increase, the circuit re-enters the hiccup protection mechanism caused by the previous overcurrent protection. In this design, if an overcurrent condition occurs, a signal (4G-Overload) is reported to the main control MCU, which then disconnects the power enable signal and completely shuts down the circuit, protecting the switch from overheating and damage.

[0052] Furthermore, in this embodiment, the voltage regulator TS3 used in the reference voltage generation circuit can be an AS431 or Weimeng ME431 reference voltage chip, which can generate a 2.5V reference voltage with an accuracy of up to 2.5V±0.4% and a minimum operating current of 1mA. During the power-on startup phase, the soft-start circuit charges capacitor C9 to form a voltage stabilization process. After power is cut off, the resistor R39 discharges the capacitor C9 to ensure that there is no charge in the capacitor C9 when the power is next turned on, which plays a soft role.

[0053] In this embodiment, the amplifier U2A acts as an error amplifier to perform voltage regulation. The output feedback resistors R24, R30, and R37 form a voltage divider feedback resistor, and the output signal amplitude is changed by comparing with the reference voltage, thereby adjusting the conduction degree of the switch tube U1.

[0054] In summary, the present invention provides a current-limiting, voltage-stabilizing power supply circuit that utilizes an NMOS transistor as a switching transistor. This circuit exhibits low voltage drop, minimal voltage fluctuation, and minimal output ripple, as well as low heat loss, making it suitable for use in heavy-load circuits. Furthermore, the circuit achieves a soft start by slowly charging the error amplifier's reference voltage during power-up, providing overcurrent and overtemperature protection. This circuit can be widely used in applications requiring low output ripple, excessive load current, or high heat loss requirements. Furthermore, the circuit can be designed directly as a standalone power supply module or, depending on actual product development needs, incorporated into a complete product PCB.

[0055] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the scope of the present invention.

Claims

1. A current limiting and voltage stabilizing source circuit, characterized in that , including overheat protection circuit, overcurrent protection circuit, boost circuit, PMOS tube V2, NMOS switch tube U1, amplifier U2A, resistor R24, resistor R37, soft start circuit, reference voltage generation circuit, capacitor C9 and enable signal generation circuit; The overheat protection circuit is used to generate an overheat signal OTP, the overcurrent protection circuit is used to output an overcurrent protection signal OCP, and the enable signal generating circuit is used to generate a cutoff enable signal according to the enable signal EN output by the main control MCU and the signals OTP and OCP; The soft start circuit includes resistors R40, R44, R35, R36, R42, R32, R33, transistors V8, V10, diodes VD2, VD3, the reference voltage generating circuit includes resistor R39, voltage regulator TS3, one end of the resistor R40 is connected to the cutoff enable signal, the other end is connected to the base of the transistor V10, the emitter of the transistor V10 is grounded, the collector is connected to the base of the transistor V8 through the resistor R36, and the emitter of the transistor V8 is connected The positive electrode of the power supply, the collector of the transistor V10 is connected to the positive electrode of the power supply through the resistor R35, the resistor R44 is connected between the base and the emitter of the transistor V10, the anode of the diode VD2 is connected to the collector of the transistor V8, and the cathode is grounded through the diode VD3 and the resistor R42. One end of the resistor R32 is connected to the anode of the diode VD2, and the other end is connected to the emitter of the transistor V9 through the resistor R33. The base of the transistor V9 is grounded through the resistor R42, and the collector is connected to the non-inverting input terminal of the amplifier U2A; One end of the resistor R39 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded. One end of the capacitor C9 is connected to the non-inverting input terminal of the amplifier U2A and the control terminal of the voltage regulator TS3, and the other end is grounded. One end of the voltage regulator TS3 is connected to the non-inverting input terminal of the amplifier U2A, and the other end is grounded. The boost circuit is used to boost the input voltage and then supply power to the gate of the PMOS transistor V2 under the control of the cutoff enable signal. The source of the PMOS transistor V2 is connected to the output end of the amplifier U2A, and the drain is connected to the gate of the NMOS switch transistor U1. The drain of the NMOS switch transistor U1 is connected to the input power supply, and the source is connected to the output end. The source of the NMOS switch U1 is grounded through the resistor R24 ​​and the resistor R37 , and the input end of the resistor R37 is connected to the inverting input end of the amplifier U2A.

2. A current limiting and voltage stabilizing source circuit according to claim 1, characterized in that ,The overcurrent protection circuit includes: a current sampling circuit, resistors R5, R6, R10, R19, R20, R28, R23, R25, R28, R31, R22, R27, amplifiers U2B, U2D, diode VD1, transistors V3, V6, V7, capacitors C2, C5; The output signal Ifb of the current sampling circuit is connected to the inverting input terminal of the amplifier U2B. The non-inverting input terminal of the amplifier U2B is connected to the positive electrode of the power supply through the resistor R5 and is also grounded through the capacitor C2. The resistors R6 and R10 are connected in series and then connected in parallel with the capacitor C2. The output terminal of the amplifier U2B is connected to the emitter of the transistor V3 through the diode VD1, the base of the transistor V3 is connected to the source of the PMOS tube V2, the collector is connected to the base of the transistor V6 through the resistor R19, and the collector is connected to the transistor V3 through the resistor R20. 6; the emitter of the transistor V6 is connected to the positive electrode of the power supply, the collector is connected to the base of the transistor V7 through the resistor R28, the base of the transistor V7 is also grounded through the resistor R31, the emitter of the transistor V7 is grounded, the collector is connected to the positive electrode of the power supply through the resistor R23, the collector is also connected to the inverting input terminal of the amplifier U2D through the resistor R25, the inverting input terminal of the amplifier U2D is also grounded through the capacitor C5, the non-inverting input terminal is connected to the output terminal through the resistor R22, and the output terminal outputs the overcurrent protection signal OCP through the resistor R27.

3. A current limiting and voltage stabilizing source circuit according to claim 2, characterized in that The overcurrent protection circuit also includes: resistors R13, R17, R18 and capacitor C3. One end of the resistor R17 is connected to the non-inverting input terminal of the amplifier U2D, and the other end is connected to the positive electrode of the power supply through the resistor R13. The other end is also grounded through the resistor R18 and capacitor C3 connected in parallel.

4. A current limiting and voltage stabilizing source circuit according to claim 2, characterized in that The overcurrent protection circuit also includes resistors R26, R29 and transistor V5. The output end of the amplifier U2D is connected to the base of the transistor V5 through the resistor R26. One end of the resistor R29 is connected to the base of the transistor V5, and the other end is grounded. The emitter of the transistor V5 is grounded, and the collector is used to output an overcurrent signal 4G-Overload to the main control MCU.

5. A current limiting and voltage stabilizing source circuit according to claim 2, characterized in that The current sampling circuit includes a resistor R38, a resistor R41, a resistor R43, a resistor R34, a capacitor C8, and an amplifier U2C. The non-inverting input terminal of the amplifier U2C is connected to the input power supply through the resistor R41, and the non-inverting input terminal is also grounded through the resistor R43 and the resistor R10. The inverting input terminal is connected to the drain of the NMOS switch tube U1 through the resistor R38, and the output terminal is connected to the inverting input terminal through the resistor R34 and capacitor C8 connected in parallel. The output terminal is also connected to the inverting input terminal of the amplifier U2B.

6. A current limiting and voltage stabilizing source circuit according to claim 1, characterized in that , also includes resistors R15, R16, R21, R8, transistor V4, and voltage regulator TS1. One end of the resistor R16 is connected to the cutoff enable signal, the other end is connected to the base of the transistor V4, and the other end is also grounded through the resistor R21. The emitter of the transistor V4 is grounded, and the collector is connected to the positive electrode of the power supply output by the boost circuit through the resistor R11. The collector is also connected to the gate of the PMOS tube V2. The resistor R15 is set between the source of the PMOS tube V2 and the output end of the amplifier U2A. After the resistor R8 is connected in parallel with the voltage regulator TS1, one end is connected to the gate of the NMOS switch tube U1, and the other end is connected to the source of the NMOS switch tube U1.

7. A current limiting and voltage stabilizing source circuit according to claim 1, characterized in that , also includes capacitor C6 and capacitor C7, capacitor C6 is set between the inverting input terminal and the output terminal of amplifier U2A, and capacitor C7 is connected in parallel with resistor R24.

8. A current limiting and voltage stabilizing source circuit according to claim 1, characterized in that The boost circuit includes a boost chip U14, a resistor R49, a resistor R50, a capacitor C14, an inductor L1, and a Zener diode TS4. Pins IN and EN of the boost chip U14 are connected to the input power supply, pin SW is connected to the input power supply through the inductor L1, and pin SW also outputs the boost voltage through the Zener diode TS4. Pin GND is connected to pin FB through resistor R49, and pin FB is connected to the output end of the Zener diode TS4 through resistor R50. Capacitor C14 is connected to resistor R50 in parallel, and the resistor R50 and resistor R49 connected in series are connected to pin GND of the boost chip U14.

9. The current limiting and voltage stabilizing source circuit according to claim 1, characterized in that The enable signal generating circuit includes resistors R45, R46, and R47, transistors V11 and V12. The base of the transistor V11 is connected to the overcurrent protection signal OCP, and the base is also grounded through the resistor R46. The emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through the resistor R45; the base of the transistor V12 is connected to the overheating signal OTP, and the base is also grounded through the resistor R47. The emitter is grounded, and the collector is connected to the enable signal EN output by the main control MCU through the resistor R45. The collectors of the transistors V11 and V12 output cutoff enable signals.

10. The current limiting and voltage stabilizing source circuit according to claim 1, characterized in that The overheat protection circuit includes a thermistor R14, a voltage regulator TS2, and a transistor V1. One end of the thermistor R14 is connected to the reference end of the voltage regulator TS2, and the other end is grounded. The anode of the voltage regulator TS2 is grounded, and the cathode is connected to the base of the transistor V1 through the resistor R7, and the cathode is connected to the emitter of the transistor V1 through the resistor R4. One end of the thermistor R14 is also connected to the positive electrode of the power supply through the resistors R3, R9, and R12. The collector of the transistor V1 outputs the overheat signal OTP through the resistor R1.

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