Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a base substrate and a plurality of pixel driving circuits configured to drive a plurality of sub-pixels to emit light. Each pixel driving circuit includes a driving transistor, a compensation transistor configured to provide a compensation voltage signal to a gate of the driving transistor, the compensation transistor including a source, a drain, and a gate, a node connection line in a first signal line layer, a first pad in a second signal line layer located on a side of the first signal line layer distal to the base substrate, a voltage line configured to output a constant voltage signal, and a voltage connection line electrically connecting the first pad and the voltage line. The node connection line connects the gate of the driving transistor and the drain of the compensation transistor.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate including a base substrate and a plurality of pixel driving circuits configured to drive a plurality of sub-pixels to emit light; wherein each pixel driving circuit includes: a driving transistor; a compensation transistor configured to provide a compensation voltage signal to the gate of the driving transistor; the compensation transistor including a source, a drain, and a gate; a node connection line in a first signal line layer; a first pad in a second signal line layer located on a side of the first signal line layer away from the base substrate; a voltage line configured to output a constant voltage signal; and a voltage connection line electrically connecting the first pad to the voltage line; wherein the node connection line connects the gate of the driving transistor and the drain of the compensation transistor; the orthographic projection of the first pad on the base substrate at least partially overlaps with the orthographic projection of the node connection line on the base substrate; and the orthographic projections of the voltage line and the voltage connection line on the base substrate are spaced apart from the orthographic projection of the node connection line on the base substrate.

[0004] Optionally, the first pad, a portion of the voltage connection line, and a portion of the voltage line are part of a closed loop.

[0005] Optionally, the array substrate further includes: a connection layer located on the side of the second signal line layer away from the substrate, the connection layer including a plurality of connection lines; an anode layer located on the side of the connection layer away from the substrate; wherein each pixel driving circuit further includes a second pad in the second signal line layer; the second pad is connected to a corresponding anode through a corresponding connection line among the plurality of connection lines; and the corresponding connection line includes a transparent conductive material.

[0006] Optionally, each pixel driving circuit further includes a first transistor having two gates and an active layer, wherein the orthographic projection of a portion of the active layer onto the substrate does not overlap with the orthographic projection of the two gates of the first transistor onto the substrate; wherein the drain of the first transistor is electrically connected to the gate of the driving transistor; the array substrate further includes a second conductive layer located on the side of the first signal line layer closer to the substrate; wherein the second conductive layer includes a shielding block, the orthographic projection of the shielding block onto the substrate at least partially overlaps with the orthographic projection of the portion onto the substrate.

[0007] Optionally, the array substrate further includes a second conductive layer located on the side of the first signal line layer closer to the substrate; the second conductive layer includes a plurality of second capacitor electrodes, adjacent second capacitor electrodes being connected to each other by a connection portion; and the orthographic projection of the connection portion on the substrate at least partially overlaps with the orthographic projection of the voltage connection line on the substrate.

[0008] Optionally, the length of the node connection line along the first direction is less than the length along the second direction; the length of the voltage line along the first direction is less than the length along the second direction; and the first direction and the second direction intersect each other.

[0009] Optionally, the orthographic projection of the first pad on the substrate covers the orthographic projection of the node connection line on the substrate; and the orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate.

[0010] Optionally, the orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the gate of the compensation transistor on the substrate.

[0011] Optionally, each pixel driving circuit further includes a second pad in the second signal line layer; wherein the second pad is connected to the drain of the fifth transistor and the drain of the sixth transistor, and is electrically connected to the anode of the light-emitting element connected to the corresponding pixel driving circuit; the source of the fifth transistor is electrically connected to the drain of the driving transistor; and the source of the sixth transistor is electrically connected to the voltage line.

[0012] Optionally, the first pad and the second pad span corresponding gate lines among a plurality of gate lines.

[0013] Optionally, the length of the second pad along the first direction is greater than the length of the first pad along the first direction; the length of the second pad along the second direction is greater than the length of the first pad along the second direction; and the second pad at least partially surrounds the first pad.

[0014] Optionally, the orthographic projection of the second pad on the substrate at least partially overlaps with the orthographic projection of the signal line in the first signal line layer on the substrate; and the signal line is configured to transmit continuous direct current.

[0015] Optionally, a portion of the second pad extends in a direction substantially parallel to the extension direction of a corresponding second reset signal line among a plurality of second reset signal lines, each of the plurality of second reset signal lines being configured to provide a reset signal to the gate of the driving transistor; and the orthographic projection of the corresponding second reset signal line on the substrate at least partially overlaps with the orthographic projection of the portion of the second pad on the substrate.

[0016] Optionally, a portion of the second pad extends in a direction substantially parallel to the extension direction of a corresponding voltage supply line among a plurality of voltage supply lines; the orthographic projection of the corresponding voltage supply line on the substrate at least partially overlaps with the orthographic projection of the portion of the second pad on the substrate; and each voltage supply line is configured to provide a driving voltage to a light-emitting element connected to a corresponding pixel driving circuit.

[0017] Optionally, the first pad is configured to receive a reset signal; the first pad is electrically connected to a vertical reset signal line extending in a second direction; the vertical reset signal line is electrically connected to a horizontal reset signal line extending in a first direction; and the horizontal reset signal line is in a second signal line layer.

[0018] Optionally, the array substrate further includes a plurality of reset signal transmission lines in a semiconductor material layer, the semiconductor material layer being located on the side of the first signal line layer closer to the substrate; wherein, a corresponding reset signal transmission line among the plurality of reset signal transmission lines connects the sources of a first transistor and a sixth transistor in a row pixel driving circuit together; the corresponding reset signal transmission line extends along the first direction; and the drain of a corresponding first transistor among the first transistors is electrically connected to the gate of the driving transistor.

[0019] Optionally, the first pad is configured to receive a voltage supply signal; the first pad is connected to a corresponding voltage supply line among a plurality of voltage supply lines in an adjacent pixel driving circuit; and each voltage supply line is configured to provide a driving voltage to a light-emitting element connected to the corresponding pixel driving circuit.

[0020] Optionally, the voltage connection line crosses a corresponding data line among a plurality of data lines in a pixel driving circuit adjacent to a corresponding pixel driving circuit.

[0021] Optionally, the plurality of pixel driving circuits includes at least a first pixel driving circuit and a second pixel driving circuit; the orthographic projections of the first node connection line in the first pixel driving circuit and the second node connection line in the second pixel driving circuit on the substrate overlap with the orthographic projections of the first anode in the first pixel driving circuit and the second anode in the second pixel driving circuit on the substrate at different portions with different percentages; the second node connection line connects the gate of the driving transistor in the second pixel driving circuit and the drain of the compensation transistor in the second pixel driving circuit; the voltage level at the first node is the same as the voltage level at the gate of the driving transistor in the first pixel driving circuit; and the voltage level at the second node is the same as the voltage level at the gate of the driving transistor in the second pixel driving circuit.

[0022] In another aspect, the present invention provides a display device including an array substrate as described herein and an integrated circuit connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] FIG. 3A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0028] FIG. 3B It is shown FIG. 3A A diagram showing the structure of the semiconductor material layer in the array substrate.

[0029] FIG. 3C It is shown FIG. 3A A diagram showing the structure of the first conductive layer in the array substrate.

[0030] FIG. 3D It is shown FIG. 3A A diagram showing the structure of the second conductive layer in the array substrate.

[0031] FIG. 3E It is shown FIG. 3A The diagram shows the structure of the interlayer dielectric layer in the array substrate.

[0032] FIG. 3F It is shown FIG. 3A A diagram showing the structure of the first signal line layer in the array substrate.

[0033] FIG. 3G It is shown FIG. 3A A diagram showing the structure of the passivation layer in the array substrate.

[0034] FIG. 3H It is shown FIG. 3A A diagram showing the structure of the first planarization layer in the array substrate.

[0035] FIG. 3I It is shown FIG. 3A A diagram showing the structure of the second signal line layer in the array substrate.

[0036] FIG. 3J It is shown FIG. 3A A diagram showing the structure of the second planarization layer in the array substrate.

[0037] FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram.

[0038] FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram.

[0039] FIG. 4C It is along FIG. 3A A cross-sectional view of line C-C' in the diagram.

[0040] FIG. 4D It is along FIG. 3A A cross-sectional view of the D-D' line in the diagram.

[0041] FIG. 5A The structures of a first signal line layer and a second signal line layer according to some embodiments of the present disclosure are shown.

[0042] FIG. 5B The structure of the first pad according to some embodiments of the present disclosure is shown.

[0043] FIG. 5C The structure of the second pad according to some embodiments of the present disclosure is shown.

[0044] FIG. 6A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0045] FIG. 6B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0046] FIG. 7A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0047] FIG. 7B It is shown FIG. 7A A diagram showing the structure of the semiconductor material layer in the array substrate.

[0048] FIG. 7C It is shown FIG. 7A A diagram showing the structure of the first conductive layer in the array substrate.

[0049] FIG. 7D It is shown FIG. 7A A diagram showing the structure of the second conductive layer in the array substrate.

[0050] FIG. 7E It is shown FIG. 7A The diagram shows the structure of the interlayer dielectric layer in the array substrate.

[0051] FIG. 7F It is shown FIG. 7A A diagram showing the structure of the first signal line layer in the array substrate.

[0052] FIG. 7G It is shown FIG. 7A A diagram showing the structure of the passivation layer in the array substrate.

[0053] FIG. 7H It is shown FIG. 7A A diagram showing the structure of the first planarization layer in the array substrate.

[0054] FIG. 7I It is shown FIG. 7A A diagram showing the structure of the second signal line layer in the array substrate.

[0055] FIG. 7J It is shown FIG. 7A A diagram showing the structure of the second planarization layer in the array substrate.

[0056] FIG. 8A It is along FIG. 7A A cross-sectional view of the E-E' line in the diagram.

[0057] FIG. 8B It is along FIG. 7A A cross-sectional view of line F-F' in the diagram.

[0058] FIG. 8C It is along FIG. 7A A cross-sectional view of the G-G' line in the diagram.

[0059] FIG. 8D It is along FIG. 7A A cross-sectional view of the H-H' line in the diagram.

[0060] FIG. 9A It shows FIG. 7A The reset signal line network in the array substrate shown.

[0061] FIG. 9B The structures of a first signal line layer and a second signal line layer according to some embodiments of the present disclosure are shown.

[0062] FIG. 10A It shows FIG. 7A The structure of the second pad and the corresponding second reset signal line in the array substrate shown.

[0063] FIG. 10B The structure of the second pad according to some embodiments of the present disclosure is shown.

[0064] FIG. 11A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0065] FIG. 11B It is shown FIG. 11A A diagram showing the structure of the anode connection pad layer in the array substrate.

[0066] FIG. 11C It is shown FIG. 11A A diagram showing the structure of the third planarization layer in the array substrate.

[0067] FIG. 11D It is shown FIG. 11A A diagram showing the structure of the anode layer in the array substrate.

[0068] FIG. 12 It is along FIG. 11A A cross-sectional view of line I-I' in the diagram.

[0069] FIG. 13A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0070] FIG. 13B It is shown FIG. 13A A diagram showing the structure of the semiconductor material layer in the array substrate.

[0071] FIG. 13C It is shown FIG. 13A A diagram showing the structure of the first conductive layer in the array substrate.

[0072] FIG. 13D It is shown FIG. 13A A diagram showing the structure of the second conductive layer in the array substrate.

[0073] FIG. 13E It is shown FIG. 13A The diagram shows the structure of the interlayer dielectric layer in the array substrate.

[0074] FIG. 13F It is shown FIG. 13A A diagram showing the structure of the first signal line layer in the array substrate.

[0075] FIG. 13G It is shown FIG. 13A A diagram showing the structure of the passivation layer in the array substrate.

[0076] FIG. 13H It is shown FIG. 13A A diagram showing the structure of the first planarization layer in the array substrate.

[0077] FIG. 13I It is shown FIG. 13A A diagram showing the structure of the second signal line layer in the array substrate.

[0078] FIG. 13J It is shown FIG. 13A A diagram showing the structure of the second planarization layer in the array substrate.

[0079] FIG. 14A The structure of a semiconductor material layer according to some embodiments of the present disclosure is shown.

[0080] FIG. 14B The structure of the first conductive layer according to some embodiments of the present disclosure is shown.

[0081] FIG. 14CThe structure of the semiconductor material layer and the first conductive layer according to some embodiments of the present disclosure is shown.

[0082] FIG. 14D The structure of the semiconductor material layer and the second conductive layer according to some embodiments of the present disclosure is shown.

[0083] FIG. 14E The structure of the second conductive layer and the second signal line layer according to some embodiments of the present disclosure is shown.

[0084] FIG. 15A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0085] FIG. 15B It is shown FIG. 15A A diagram showing the structure of the semiconductor material layer in the array substrate.

[0086] FIG. 15C It is shown FIG. 15A A diagram showing the structure of the first conductive layer in the array substrate.

[0087] FIG. 15D It is shown FIG. 15A A diagram showing the structure of the second conductive layer in the array substrate.

[0088] FIG. 15E It is shown FIG. 15A The diagram shows the structure of the interlayer dielectric layer in the array substrate.

[0089] FIG. 15F It is shown FIG. 15A A diagram showing the structure of the first signal line layer in the array substrate.

[0090] FIG. 15G It is shown FIG. 15A A diagram showing the structure of the passivation layer in the array substrate.

[0091] FIG. 15H It is shown FIG. 15A A diagram showing the structure of the first planarization layer in the array substrate.

[0092] FIG. 15I It is shown FIG. 15A A diagram showing the structure of the second signal line layer in the array substrate.

[0093] FIG. 15J It is shown FIG. 15A A diagram showing the structure of the second planarization layer in the array substrate.

[0094] FIG. 16A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0095] FIG. 16B It is shown FIG. 16A A diagram showing the structure of the semiconductor material layer in the array substrate.

[0096] FIG. 16C It is shown FIG. 16A A diagram showing the structure of the first conductive layer in the array substrate.

[0097] FIG. 16D It is shown FIG. 16A A diagram showing the structure of the second conductive layer in the array substrate.

[0098] FIG. 16E It is shown FIG. 16A The diagram shows the structure of the interlayer dielectric layer in the array substrate.

[0099] FIG. 16F It is shown FIG. 16A A diagram showing the structure of the first signal line layer in the array substrate.

[0100] FIG. 16G It is shown FIG. 16A A diagram showing the structure of the passivation layer in the array substrate.

[0101] FIG. 16H It is shown FIG. 16A A diagram showing the structure of the first planarization layer in the array substrate.

[0102] FIG. 16I It is shown FIG. 16A A diagram showing the structure of the second signal line layer in the array substrate.

[0103] FIG. 16J It is shown FIG. 16A A diagram showing the structure of the second planarization layer in the array substrate.

[0104] FIG. 17 Show FIG. 16A The structure of the second pad in the array substrate shown.

[0105] FIG. 18A An anode arrangement in an array substrate according to some embodiments of the present disclosure is shown.

[0106] FIG. 18B This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0107] FIG. 19A An anode arrangement in an array substrate according to some embodiments of the present disclosure is shown.

[0108] FIG. 19BThis is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0109] FIG. 20A This is a diagram illustrating the structure of the anode connection pad layer in an array substrate according to some embodiments of the present disclosure.

[0110] FIG. 20B This is a diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure.

[0111] FIG. 20C This is a diagram illustrating the structure of the second conductive layer, the anode connection pad layer, and the anode layer in an array substrate according to some embodiments of the present disclosure.

[0112] FIG. 21A This is a diagram illustrating the structure of the anode connection pad layer in an array substrate according to some embodiments of the present disclosure.

[0113] FIG. 21B This is a diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure.

[0114] FIG. 21C This is a diagram illustrating the structure of the second conductive layer, the anode connection pad layer, and the anode layer in an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0115] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0116] This disclosure particularly provides an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the invention provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. In some embodiments, each pixel driving circuit includes: a node connection line in a first signal line layer; and a first pad in a second signal line layer. Optionally, the node connection line connects a first capacitor electrode in a respective pixel driving circuit to a portion of a semiconductor material layer located between the source of a first transistor and the drain of the driving transistor. Optionally, the orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the node connection line on the substrate.

[0117] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0118] FIG. 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 1 The array substrate comprises an array of sub-pixels Sp. Each sub-pixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple high-voltage supply lines Vdd. Light emission in each sub-pixel is driven by the corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via the corresponding high-voltage supply line of the multiple high-voltage supply lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., VDD signal) and the low-voltage signal (e.g., VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0119] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, S3 represents a corresponding third sub-pixel, and S4 represents a corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, C3 represents a corresponding third sub-pixel of a third color, and C4 represents a corresponding fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0120] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0121] FIG. 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 2AIn some embodiments, each pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a source connected to a corresponding first reset signal line among a plurality of first reset signal lines Vintr, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a source connected to a corresponding data line among a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and the driving transistor Td. The transistor T4 has a gate and a source connected to the drain of the driving transistor Td; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line of a plurality of light-emitting control signal lines em, a source connected to a corresponding voltage supply line of a plurality of voltage supply lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a source connected to the drain of the driving transistor Td and the source of the third transistor T3, and a drain connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to a corresponding reset control signal line of a plurality of reset control signal lines rst, a source connected to a corresponding first reset signal line of a plurality of first reset signal lines Vintr, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0122] FIG. 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 2B In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (optionally, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding gate line of the plurality of gate lines GL twice (optionally, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0123] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the drain of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the source of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0124] As used herein, source or drain refers to one of the first and second terminals of the transistor, which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from source to drain or from drain to source. Thus, depending on the direction of current flowing through the transistor, in one example, the source is configured to receive an input signal and the drain is configured to output an output signal; in another example, the drain is configured to receive an input signal and the source is configured to output an output signal.

[0125] FIG. 3A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 3B It is shown FIG. 3A A diagram showing the structure of the semiconductor material layer in the array substrate. FIG. 3C It is shown FIG. 3A A diagram showing the structure of the first conductive layer in the array substrate. FIG. 3D It is shown FIG. 3A A diagram showing the structure of the second conductive layer in the array substrate. FIG. 3E It is shown FIG. 3A The diagram shows the structure of the interlayer dielectric layer in the array substrate. FIG. 3F It is shown FIG. 3A A diagram showing the structure of the first signal line layer in the array substrate. FIG. 3G It is shown FIG. 3A A diagram showing the structure of the passivation layer in the array substrate.

[0126] FIG. 3H It is shown FIG. 3A A diagram showing the structure of the first planarization layer in the array substrate. FIG. 3I It is shown FIG. 3A A diagram showing the structure of the second signal line layer in the array substrate. FIG. 3J It is shown FIG. 3A A diagram showing the structure of the second planarization layer in the array substrate. FIG. 4A It is along FIG. 3A A cross-sectional view of line A-A' in the diagram.FIG. 4B It is along FIG. 3A A cross-sectional view of line B-B' in the diagram. FIG. 4C It is along FIG. 3A A cross-sectional view of line C-C' in the diagram. FIG. 4D It is along FIG. 3A A cross-sectional view of the D-D' line in the diagram.

[0127] refer to FIG. 3A to FIG. 3J ,as well as FIG. 4A to FIG. 4D In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer CT1 on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer CT2 on the side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD on the side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2, a first planarization layer PLN1 on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, a second signal line layer SL2 on the side of the first planarization layer PLN1 away from the first signal line layer SL1, and a second planarization layer PLN2 on the side of the second signal line layer SL2 away from the first planarization layer PLN1. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of suitable semiconductor materials for manufacturing semiconductor material layers (SMLs) include polycrystalline silicon, amorphous silicon, and metal oxides.

[0128] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3BEach pixel driving circuit is labeled with a number to indicate the region corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number to indicate the components of each transistor in the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td consists of an active layer ACTd, a source Sd, and a drain Dd.

[0129] In some embodiments, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), at least a portion of the sources (S1, S2, S3, S4, S5, S6, and Sd), and at least a portion of the drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), sources (S1, S2, S3, S4, S5, S6 and Sd), and drains (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) in each pixel driving circuit are located on the same layer.

[0130] In some embodiments, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd of transistors T1, T2, T3, T4, T5, T6, and Td in each pixel driving circuit are part of a first overall structure. In another example, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd of transistors T1, T2, T3, T4, T5, T6, and Td in each pixel driving circuit, the sources S1, S2, S3, S4, S5, S6, and Sd, and the drains D1, D2, D3, D4, D5, D6, and Dd are part of the first overall structure.

[0131] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to a portion of the transistor connected to one side of the active layer, and a drain refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a source refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a drain refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0132] In some embodiments, the semiconductor material layer further includes a plurality of reset signal transmission lines VTL. Each of the plurality of reset signal transmission lines VTL connects the source of the first transistor T1 and the source of the sixth transistor T6 together. In one example, as shown... FIG. 3B As shown, each reset signal transmission line connects the source of all first transistors in a row of pixel driving circuits to the source of all sixth transistors. Each reset signal transmission line extends along the first direction DR1.

[0133] Reference FIG. 2A , FIG. 2B , FIG. 3A as well as FIG. 3C In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, and the first capacitor electrode Ce1 are located in the same layer.

[0134] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple gate lines GL and a first capacitor electrode Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed in the same material layer. In another example, multiple gate lines GL and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0135] In some embodiments, in each pixel driving circuit, each of the plurality of gate lines GL includes a first body portion MP1 extending along the extension direction of the respective gate line, and a first gate protrusion GP1, the first gate protrusion GP1 protruding away from the first body portion MP1, for example, along a direction from the corresponding gate line in the plurality of gate lines GL in the respective pixel driving circuit toward the corresponding reset control signal line in the plurality of reset control signal lines rst in the respective pixel driving circuit.

[0136] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the first gate protrusion GP1 is one of the dual gates G3 in the third transistor T3. In some embodiments, reference... FIG. 4A The orthographic projection of the first gate protrusion GP1 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0137] In some embodiments, in each pixel driving circuit, each of the plurality of reset control signal lines rst includes a second body portion MP2 extending along the extension direction of the respective reset control signal line, and a second gate protrusion GP2 protruding away from the second body portion MP2, for example, along a direction from the corresponding reset control signal line in the plurality of reset control signal lines rst in the respective pixel driving circuit toward the corresponding gate line in the plurality of gate lines GL in the respective pixel driving circuit.

[0138] In some embodiments, as described above, the first transistor T1 is a dual-gate transistor. In some embodiments, the second gate protrusion GP2 is one of the dual gates G1 in the first transistor T1. In some embodiments, reference... FIG. 4B The orthographic projection of the second gate protrusion GP2 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT1 of the first transistor T1 on the substrate BS.

[0139] Reference FIG. 2A , FIG. 2B , FIG. 3Aas well as FIG. 3D In some embodiments, the second conductive layer includes an anti-interference block IPB and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB of the present invention can effectively reduce crosstalk, especially vertical crosstalk between the N1 nodes of adjacent data lines. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the second capacitor electrode Ce2 and the anti-interference block IPB are located in the same layer.

[0140] FIG. 3E The text describes vias extending through the interlayer dielectric layer (ILD).

[0141] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3F In some embodiments, the first signal line layer includes multiple voltage supply lines Vdd, node connection lines Cln, initialization connection lines Cli, a first relay electrode RE1, a second relay electrode RE2, and multiple data lines DL. The node connection lines Cln connect the first capacitor electrode Ce1 and the drain of the third transistor T3 in each pixel driving circuit together. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the multiple voltage supply lines Vdd, node connection lines Cln, initialization connection lines Cli, the first relay electrode RE1, the second relay electrode RE2, and the multiple data lines DL are located in the same layer.

[0142] FIG. 3G The image depicts vias extending through the passivation layer PVX.

[0143] FIG. 3H The via extending through the first planarization layer PLN1 is shown.

[0144] Reference FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3IIn some embodiments, the second signal line layer includes a plurality of first reset signal lines Vintr and first pads PAD1 and second pads PAD2 in each pixel driving circuit. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first reset signal lines Vintr, the first pads PAD1, and the second pads PAD2 are located in the same layer.

[0145] The first pad PAD1 is configured to ensure that the first nodes in different pixel driving circuits are located in similar environments. For example... FIG. 2A and FIG. 2B As shown, the first node N1 is connected to the gate of the driving transistor Td, the drain of the first transistor T1, the drain of the third transistor T3, and the first capacitor electrode Ce1 of the storage capacitor Cst.

[0146] The inventors of this disclosure have discovered that, due to the layout in the relevant display panel, such as the anode layout, the first nodes in different pixel driving circuits of the relevant display panel are typically located in different environments. This problem is particularly pronounced in gate-on-array-in-panel (GOP) type display panels. In these GOP type display panels, the first nodes in different pixel driving circuits are typically located in environments with different anode layouts. The inventors of this disclosure have discovered that, by having first pads respectively in the pixel driving circuits, the first nodes below the first pads can be located in highly similar environments. Surprisingly and unexpectedly, the unique structure of the array substrate of this invention significantly improves display uniformity.

[0147] Reference FIG. 3A and FIG. 3I The first pad PAD1 is connected to two adjacent first reset signal lines among a plurality of first reset signal lines Vintr. In one example, the first pad PAD1 is connected to two adjacent first reset signal lines in two rows of pixel driving circuits, respectively.

[0148] Reference FIG. 3A and FIG. 3I In some embodiments, the first pads in the pixel driving circuit and a plurality of first reset signal lines Vintr form an interconnected first reset signal network.

[0149] The second pad, PAD2, is configured to provide parasitic capacitance at the fourth node, N4. For example... FIG. 2A and FIG. 2B As shown, the fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE. The second pad PAD2 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0150] FIG. 3J The vias extending through the second planarization layer PLN2 are described.

[0151] Reference FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3C , FIG. 3D and FIG. 4A In some embodiments, except for the via region H where a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as a plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first via v1 located in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the second capacitor electrode Ce2 is located on the side of the gate insulating layer IN away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the drain D3 of the third transistor, such as... FIG. 4A As shown.

[0152] refer to FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3D , FIG. 4B and FIG. 4DIn some embodiments, the anti-interference block IPB and the second capacitor electrode Ce2 are located on the same layer. Each of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB via a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines Vdd on the substrate BS.

[0153] Reference FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3F and FIG. 4C The initialization connection line Cli is connected to the source S6 of the sixth transistor T6 via a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Each of the multiple first reset signal lines Vintr is connected to the initialization connection line Cli via a sixth via v6 extending through the first planarization layer PLN1. Initialization signals are provided from each of the first reset signal lines to the source S6 of the sixth transistor T6 via the initialization connection line Cli.

[0154] refer to FIG. 4B Each of the multiple voltage supply lines Vdd is connected to the second capacitor electrode Ce2 via an eighth via v8 extending through the interlayer dielectric layer ILD. (Reference) FIG. 4B In some embodiments, the orthographic projection of each voltage supply line on the substrate BS at least partially overlaps with the orthographic projection of the second pad PAD2 on the substrate BS.

[0155] FIG. 5A The structures of a first signal line layer and a second signal line layer according to some embodiments of the present disclosure are shown. For example... FIG. 4A , FIG. 4D and FIG. 5AAs shown, in some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the node connection line Cln in the corresponding pixel driving circuit onto the substrate BS. In some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 onto the substrate BS. In some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the first gate protrusion GP1 of the corresponding gate line in the plurality of gate lines GL onto the substrate BS. As described above, the inventors of this disclosure have found that by having first pads respectively in the pixel driving circuit, the first nodes (including node connection lines Cln) respectively below the first pads can be located in a highly similar environment, thereby significantly improving display uniformity.

[0156] In some embodiments, each pixel driving circuit in the array substrate further includes a voltage line configured to output a constant voltage signal, and a voltage connection line VCL electrically connecting the first pad PAD1 to the voltage line. FIG. 3A to FIG. 3J In the configuration, each of the multiple first reset signal lines in Vintr can be considered as a voltage line configured to output a constant reset voltage signal. The voltage line is electrically connected to the source of the sixth transistor. For example, as... FIG. 2A and FIG. 2B As shown, the source of the sixth transistor T6 is electrically connected to one of the plurality of first reset signal lines Vintr (e.g., a voltage line).

[0157] In some embodiments, the combination of voltage connection line VCL and first pad PAD1 electrically connects a plurality of first reset signal lines Vintr together, thereby forming a reset signal line network. The first pad PAD1 and a portion of voltage connection line VCL form an open loop.

[0158] In some embodiments, each pixel driving circuit includes a driving transistor Td and a compensation transistor (e.g., a third transistor T3), the compensation transistor being configured to provide a compensation voltage signal to the gate of the driving transistor. The compensation transistor includes a source, a drain, and a gate. A node connection line Cln connects the gate of the driving transistor Td and the drain of the compensation transistor (e.g., D3 of the third transistor T3).

[0159] Reference FIG. 3A to FIG. 3J In some embodiments, the orthographic projections of the voltage line and voltage connection line VCL on the substrate are spaced apart from the orthographic projections of the node connection line Cln on the substrate. The orthographic projection of the first pad PAD1 on the substrate at least partially overlaps with the orthographic projection of the node connection line Cln on the substrate. The orthographic projection of the first pad PAD1 on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor (e.g., the third transistor T3) on the substrate, see, for example... FIG. 4A It depicts the orthographic projection of the first pad PAD1 on the substrate BS and the orthographic projection of the active layer ACT3 of the third transistor (compensation transistor) on the substrate BS, which at least partially overlaps.

[0160] refer to FIG. 3A to FIG. 3J In some embodiments, the length of the node connection line Cln along the first direction DR1 is less than its length along the second direction DR2. The length of the voltage line (e.g., each of the plurality of first reset signal lines Vintr) along the first direction DR1 is less than its length along the second direction DR2. The first direction DR1 and the second direction DR2 intersect each other. In some embodiments, the length of the second pad PAD2 along the first direction DR1 is greater than the length of the first pad PAD1 along the first direction DR1; the length of the second pad PAD2 along the second direction DR2 is greater than the length of the first pad PAD1 along the second direction DR2. FIG. 3I As shown, in some embodiments, the second pad PAD2 is at least partially (e.g., at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, or at least 70%) surrounding the first pad PAD1.

[0161] FIG. 5B The structure of a first pad according to some embodiments of this disclosure is shown. (Refer to...) FIG. 5A and FIG. 5B In some embodiments, the first pad includes a first-first pad portion P1-1, a second-first pad portion P1-2, and a third-first pad portion P1-3. The second-first pad portion P1-2 connects the first-first pad portion P1-1 and the third-first pad portion P1-3. The first-first pad portion P1-1 is connected to a first adjacent first reset signal line in a plurality of first reset signal lines Vintr. The third-first pad portion P1-3 is connected to a second adjacent first reset signal line in a plurality of first reset signal lines Vintr.

[0162] In one example, the first pad portion P1-1 has an L-shape. In another example, the second pad portion P1-2 has an L-shape. In yet another example, the third pad portion P1-3 has an L-shape.

[0163] Reference FIG. 3A , FIG. 4D , FIG. 5A and FIG. 5B In some embodiments, the orthographic projection of the second-first pad portion P1-2 on the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in the corresponding pixel driving circuit on the substrate BS.

[0164] Reference FIG. 3A , FIG. 4D , FIG. 5A and FIG. 5B In some embodiments, the orthographic projection of the first-first pad portion P1-1 on the substrate BS at least partially overlaps with the orthographic projection of the first gate protrusion GP1 of the corresponding gate line in the plurality of gate lines GL in the corresponding pixel driving circuit on the substrate BS.

[0165] Reference FIG. 3A , FIG. 4D , FIG. 5A as well as FIG. 5B In some embodiments, the orthographic projection of the third-first pad portion P1-3 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT5 of the fifth transistor T5 on the substrate BS. Optionally, the orthographic projection of the third-first pad portion P1-3 on the substrate BS at least partially overlaps with the orthographic projection of the source S5 of the fifth transistor T5 on the substrate BS. Optionally, the orthographic projection of the third-first pad portion P1-3 on the substrate BS at least partially overlaps with the orthographic projection of the drain D5 of the fifth transistor T5 on the substrate BS. Optionally, the orthographic projection of the third-first pad portion P1-3 on the substrate BS at least partially overlaps with the orthographic projection of the drain Dd of the driving transistor Td on the substrate BS.

[0166] Reference FIG. 5A In some embodiments, the array substrate includes an interconnected first reset signal network consisting of first pads in pixel driving circuits and a plurality of first reset signal lines Vintr. The interconnected first reset signal network in the array substrate includes a plurality of first reset signal lines Vintr extending along a first direction DR1, and a plurality of first pad lines PL1 extending along a second direction DR2. Each first pad line includes a plurality of first pads in a column of pixel driving circuits. Each first pad line intersects with and connects to a plurality of first reset signal lines among the plurality of first reset signal lines Vintr. Each first reset signal line intersects with and connects to a plurality of first pad lines among the plurality of first pad lines PL1.

[0167] As discussed above, and see also FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3I , FIG. 4B , FIG. 5A and FIG. 5B The second pad PAD2 is configured to provide parasitic capacitance at the fourth node N4. In one example, the parasitic capacitance at the fourth node N4 is formed between the second pad PAD2 and a corresponding voltage supply line among the plurality of voltage supply lines Vdd. The orthographic projection of the second pad PAD2 onto the substrate BS at least partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines Vdd onto the substrate BS. The second pad PAD2 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0168] In some embodiments, the second pad PAD2 spans a corresponding gate line among a plurality of gate lines GL. Optionally, the orthographic projection of the second pad PAD2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding light emission control signal line among a plurality of light emission control signal lines em on the substrate BS. Optionally, the orthographic projection of the second pad PAD2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding reset control signal line among a plurality of reset control signal lines rst on the substrate BS.

[0169] refer to FIG. 3A and FIG. 4B The second pad PAD2 is connected to the first relay electrode RE1 in the first signal line layer SL1 via a ninth via v9 extending through the first planarization layer PLN1, and to the second relay electrode RE2 in the first signal line layer SL1 via a tenth via v10 extending through the first planarization layer PLN1. The first relay electrode RE1 is connected to the drain D5 of the fifth transistor T5 via an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second relay electrode RE2 is connected to the drain D6 of the sixth transistor T6 via a twelfth via v12 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In some embodiments, the array substrate further includes an anode connection pad, which is connected to the second pad PAD2 via a via extending through the second planarization layer PLN2. The anode connection pad is connected to the anode.

[0170] In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines VDD onto the substrate BS. In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the anti-interference block IPB onto the substrate BS. In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the second capacitor electrode Ce2 in the corresponding pixel driving circuit onto the substrate BS. In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 in the corresponding pixel driving circuit onto the substrate BS.

[0171] FIG. 5C The structure of the second pad according to some embodiments of this disclosure is shown. Reference FIG. 5C In some embodiments, the second pad includes a first-second pad portion P2-1, a second-second pad portion P2-2, and a third-second pad portion P2-3. The second-second pad portion P2-2 connects the first-second pad portion P2-1 to the third-second pad portion P2-3. (See reference...) FIG. 3A , FIG. 4B and FIG. 5C The third-second pad portion P2-3 is connected to the first relay electrode RE1; the first-second pad portion P2-1 is connected to the second relay electrode RE2. The first-first pad portion P1-1 is connected to a first adjacent first reset signal line among the plurality of first reset signal lines Vintr. The third-first pad portion P1-3 is connected to a second adjacent first reset signal line among the plurality of first reset signal lines Vintr. The orthographic projection of the second-second pad portion P2-2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines VDD on the substrate BS. In one example, the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines VDD on the substrate BS covers the orthographic projection of the second-second pad portion P2-2 on the substrate BS.

[0172] FIG. 6A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) FIG. 6AIn some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a source connected to a corresponding second reset signal line among a plurality of second reset signal lines Vintc, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a source connected to a corresponding data line among a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and a drain connected to the source of the driving transistor Td. The transistor has a gate and a source connected to the drain of the driving transistor Td; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a source connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a source connected to the drain of the driving transistor Td and the source of the third transistor T3, and a drain connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a source connected to a corresponding first reset signal line among a plurality of first reset signal lines Vintr, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0173] FIG. 6B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) FIG. 6B In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding gate line of the plurality of gate lines GL twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0174] FIG. 6A and FIG. 6B The pixel driving circuit in FIG. 2A and FIG. 2B The difference in the pixel driving circuit is that,FIG. 2A and FIG. 2B In the pixel driving circuit, the sources of the first transistor T1 and the sixth transistor T6 are connected to the same reset signal line, while FIG. 6A and FIG. 6B In the pixel driving circuit, the sources of the first transistor T1 and the sixth transistor T6 are connected to different reset signal lines.

[0175] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the drain of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the source of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0176] FIG. 7A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. FIG. 7B It is shown FIG. 7A A diagram showing the structure of the semiconductor material layer in the array substrate. FIG. 7C It is shown FIG. 7A A diagram showing the structure of the first conductive layer in the array substrate. FIG. 7D It is shown Figure 7A A diagram showing the structure of the second conductive layer in the array substrate. Figure 7E It is shown Figure 7A The diagram shows the structure of the interlayer dielectric layer in the array substrate. Figure 7F It is shown Figure 7A A diagram showing the structure of the first signal line layer in the array substrate. Figure 7G It is shown Figure 7A A diagram showing the structure of the passivation layer in the array substrate.

[0177] Figure 7H It is shown Figure 7A A diagram showing the structure of the first planarization layer in the array substrate. Figure 7I It is shown Figure 7A A diagram showing the structure of the second signal line layer in the array substrate. Figure 7J It is shown Figure 7A A diagram showing the structure of the second planarization layer in the array substrate. Figure 8A It is along Figure 7A A cross-sectional view of the E-E' line in the diagram. Figure 8B It is along Figure 7A A cross-sectional view of line F-F' in the diagram. Figure 8C It is along Figure 7A A cross-sectional view of the G-G' line in the diagram. Figure 8D It is along Figure 7A A cross-sectional view of the H-H' line in the diagram.

[0178] See Figure 6A , Figure 6B , Figure 7A and Figure 7B Each pixel driving circuit is labeled with a number to indicate the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number to indicate the components of each transistor in the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd.

[0179] In some embodiments, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), at least a portion of the sources (S1, S2, S3, S4, S5, S6, and Sd), and at least a portion of the drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), sources (S1, S2, S3, S4, S5, S6 and Sd), and drains (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) in each pixel driving circuit are located on the same layer.

[0180] In some embodiments, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd of transistors T1, T2, T3, T4, T5, and Td in each pixel driving circuit are part of a first overall structure. In another example, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd of transistors T1, T2, T3, T4, T5, and Td in each pixel driving circuit, the sources S1, S2, S3, S4, S5, and Sd, and the drains D1, D2, D3, D4, D5, and Dd are part of the first overall structure. Figure 7B As shown, in some embodiments, the active layer ACT6 of transistor T6 in each pixel driving circuit is spaced apart from the first overall structure, which includes the active layers ACT1, ACT2, ACT3, ACT4, ACT5 and ACTd of transistors T1, T2, T3, T4, T5 and Td in each pixel driving circuit.

[0181] In some embodiments, the active layer ACT6, at least a portion of the source S6, and at least a portion of the drain D6 of the transistor T6 in each pixel driving circuit are part of a second overall structure. Optionally, the active layer ACT6, the source S6, and the drain D6 of the transistor T6 in each pixel driving circuit are part of a second overall structure. The second overall structure in each pixel driving circuit is spaced apart from the first overall structure.

[0182] Reference Figure 6A , Figure 6B , Figure 7A as well as Figure 7C In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, and the first capacitor electrode Ce1 are located in the same layer.

[0183] In some embodiments, in each pixel driving circuit, each of the plurality of gate lines GL includes a first body portion MP1 extending along the extension direction of the respective gate line, and a first gate protrusion GP1 protruding away from the first body portion MP1, for example, along a direction from the corresponding gate line in the plurality of gate lines GL in the respective pixel driving circuit toward the corresponding reset control signal line in the plurality of reset control signal lines rst in the respective pixel driving circuit.

[0184] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the first gate protrusion GP1 is one of the dual gates G3 in the third transistor T3. In some embodiments, reference... Figure 8AThe orthographic projection of the first gate protrusion GP1 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0185] Reference Figure 6A , Figure 6B , Figure 7A and Figure 7D In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vintr, an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB can effectively reduce crosstalk, especially vertical crosstalk between the N1 nodes of adjacent data lines.

[0186] Figure 7E The text describes vias extending through the interlayer dielectric layer (ILD).

[0187] Reference Figure 6A , Figure 6B , Figure 7A and Figure 7F In some embodiments, the first signal line layer includes multiple voltage supply lines VDD, node connection lines Cln, initialization connection lines Cli, a first relay electrode RE1, a second relay electrode RE2, multiple second reset signal lines Vintc, and multiple data lines DL. The node connection lines Cln connect the first capacitor electrode Ce1 and the drain of the third transistor T3 in each pixel driving circuit together. Optionally, the multiple voltage supply lines VDD, node connection lines Cln, initialization connection lines Cli, first relay electrode RE1, second relay electrode RE2, multiple second reset signal lines Vintc, and multiple data lines DL are located on the same layer. Each of the multiple second reset signal lines Vintc is configured to provide a reset signal to the gate of the driving transistor.

[0188] Figure 7G The image depicts vias extending through the passivation layer PVX.

[0189] Figure 7H The via extending through the first planarization layer PLN1 is shown.

[0190] Reference Figure 6A , Figure 6B , Figure 7A as well as Figure 7I In some embodiments, the second signal line layer includes a first pad PAD1 and a second pad PAD2 in each pixel driving circuit. Optionally, multiple first reset signal lines Vintr, the first pad PAD1, and the second pad PAD2 are located in the same layer. The first pad PAD1 is configured to ensure that the first nodes in different pixel driving circuits are located in similar environments. Figure 6A and Figure 6BAs shown, the first node N1 is connected to the gate of the driving transistor Td, the drain of the first transistor T1, the drain of the third transistor T3, and the first capacitor electrode Ce1 of the storage capacitor Cst.

[0191] Figure 7J The vias extending through the second planarization layer PLN2 are shown.

[0192] Reference Figure 6A , Figure 6B , Figure 7A , Figure 7C , Figure 7D and Figure 8A In some embodiments, except for the via region H where the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as a plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first via v1 located in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the drain D3 of the third transistor, such as... Figure 8A As shown.

[0193] refer to Figure 6A , Figure 6B , Figure 7A , Figure 7D and Figure 8DIn some embodiments, the anti-interference block IPB and the second capacitor electrode Ce2 are located on the same layer. Each of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB through a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines Vdd on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0194] Figure 9A It shows Figure 7A The reset signal line network in the array substrate shown. See also Figure 9A and Figure 7A The reset signal line network in the array substrate includes a plurality of first reset signal lines Vintr extending along a first direction DR1 and a plurality of second reset signal lines Vintc extending along a second direction DR2. Each first reset signal line crosses a plurality of second reset signal lines. Each second reset signal line crosses a plurality of first reset signal lines. When each first reset signal line crosses a plurality of second reset signal lines, each first reset signal line is not connected to the plurality of second reset signal lines. When each second reset signal line crosses a plurality of first reset signal lines, each second reset signal line is not connected to the plurality of first reset signal lines.

[0195] See Figure 6A , Figure 6B , Figure 7A and Figure 8B Each of the multiple second reset signal lines Vintc is connected to the source S1 of the first transistor T1 through a fourth via V4 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI, thereby providing an initialization signal to the source S1 of the first transistor T1.

[0196] refer to Figure 6A , Figure 6B , Figure 7A , Figure 7F and Figure 8C The initialization connection line Cli is connected to the source S6 of the sixth transistor T6 through a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI; and is connected to the corresponding first reset signal line among the plurality of first reset signal lines Vintr through a sixth via v6 extending through the interlayer dielectric layer ILD and the insulating layer IN; thereby providing an initialization signal to the source S6 of the sixth transistor T6.

[0197] As described above, the inventors of this disclosure have discovered that, due to the layout in the relevant display panels, the first nodes of different pixel driving circuits in the relevant display panels are typically located in different environments. This problem is particularly pronounced in in-panel gate-on-array (GOP) type display panels. In these GOP type display panels, the first nodes in different pixel driving circuits are typically located in environments with different anode layouts. The inventors of this disclosure have discovered that, by having first pads respectively in the pixel driving circuits, the first nodes below the first pads can be located in highly similar environments. Surprisingly and unexpectedly, the unique structure of the array substrate of this invention significantly improves display uniformity.

[0198] In some embodiments, each pixel driving circuit in the array substrate further includes a voltage line configured to output a constant voltage signal, and a voltage connection line VCL electrically connecting the first pad PAD1 to the voltage line. Figures 7A to 7J In this configuration, each of the multiple voltage supply lines Vdd can be considered a voltage line configured to output a constant voltage signal. Optionally, the orthographic projections of the voltage lines and voltage connection lines VCL on the substrate are spaced apart from the orthographic projections of the node connection lines Cln on the substrate.

[0199] Reference Figure 8D The first pad PAD1 is connected to a corresponding voltage supply line among multiple voltage supply lines Vdd in the adjacent pixel driving circuit via a voltage connection line VCL. The voltage connection line VCL is connected to a corresponding voltage supply line among multiple voltage supply lines Vdd in the adjacent pixel driving circuit via a seventh via v7 extending through the first planarization layer PLN1. Each voltage supply line among the multiple voltage supply lines Vdd is connected to the second capacitor electrode Ce2 via an eighth via v8 extending through the interlayer dielectric layer ILD. Figure 9B The structures of a first signal line layer and a second signal line layer according to some embodiments of the present disclosure are shown. For example... Figure 9B and Figure 8A As shown, in some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the node connection line Cln in the corresponding pixel driving circuit onto the substrate BS.

[0200] In some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 onto the substrate BS. In some embodiments, the orthographic projection of the first pad PAD1 in each pixel driving circuit onto the substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the first gate protrusion GP1 of the corresponding gate line in the plurality of gate lines GL onto the substrate BS.

[0201] Reference Figure 7A , Figure 8D and Figure 9B The orthographic projection of the first pad PAD1 on the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in the corresponding pixel driving circuit on the substrate BS, and at least partially overlaps with the orthographic projection of the first gate protrusion GP1 of the corresponding gate line in the plurality of gate lines GL on the substrate BS. The orthographic projection of the voltage connection line VCL on the substrate BS at least partially overlaps with the orthographic projection of the corresponding voltage supply line in the plurality of voltage supply lines Vdd in the adjacent pixel driving circuit on the substrate BS. The voltage connection line VCL crosses the corresponding data line in the plurality of data lines DL in the adjacent pixel driving circuit, and the corresponding data line is in the pixel driving circuit adjacent to the corresponding pixel driving circuit. The adjacent pixel driving circuit and the corresponding pixel driving circuit are in the same row along the first direction DR1.

[0202] The second pad, PAD2, is configured to provide parasitic capacitance at the fourth node, N4. For example... Figure 6A and Figure 6B As shown, the fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE. The second pad PAD2 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0203] Figure 10A It shows Figure 7A The structure of the second pad and the corresponding second reset signal line in the array substrate shown. (Reference) Figure 6A , Figure 6B , Figure 7A , Figure 7I , Figure 8B and Figure 10AThe second pad PAD2 is configured to provide parasitic capacitance at the fourth node N4. In one example, the parasitic capacitance at the fourth node N4 is formed between the second pad PAD2 and a corresponding first reset signal line among a plurality of first reset signal lines Vintr. The orthographic projection of the second pad PAD2 onto the substrate BS at least partially overlaps with the orthographic projection of the corresponding first reset signal line onto the substrate BS. The second pad PAD2 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0204] In some embodiments, the second pad PAD2 spans a corresponding gate line among a plurality of gate lines GL. Optionally, the orthographic projection of the second pad PAD2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding reset control signal line among a plurality of reset control signal lines rst on the substrate BS. Optionally, the orthographic projection of the second pad PAD2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding light emission control signal line among a plurality of light emission control signal lines em on the substrate BS. In one example, the orthographic projection of the second pad PAD2 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding reset control signal line among a plurality of reset control signal lines rst on the substrate BS, and at least partially overlaps with the orthographic projection of the corresponding light emission control signal line among a plurality of light emission control signal lines em on the substrate BS.

[0205] Figure 10B The structure of the second pad according to some embodiments of this disclosure is shown. Reference Figure 10A and Figure 10B In some embodiments, the first pad includes a first-second pad portion P2-1, a second-second pad portion P2-2, and a third-second pad portion P2-3. The second-second pad portion P2-2 connects the first-second pad portion P2-1 to the third-second pad portion P2-3. The first-second pad portion P2-1 and the third-second pad portion P2-3 extend from the second-second pad portion P2-2 to the same side (e.g., to the left). The orthographic projection of the second-second pad portion P2-2 on the substrate at least partially overlaps with the orthographic projection of the corresponding first reset signal line on the substrate. The orthographic projection of the first-second pad portion P2-1 on the substrate at least partially does not overlap with the orthographic projection of the corresponding first reset signal line on the substrate; for example, the orthographic projection of the first-second pad portion P2-1 on the substrate does not completely overlap with the orthographic projection of the corresponding first reset signal line on the substrate. The orthographic projection of the third-second pad portion P2-3 on the substrate does not overlap with the orthographic projection of the corresponding first reset signal line on the substrate at least partially. For example, the orthographic projection of the third-second pad portion P2-3 on the substrate does not overlap with the orthographic projection of the corresponding first reset signal line on the substrate completely.

[0206] refer to Figure 7A and Figure 8B The second pad PAD2 is connected to the first relay electrode RE1 in the first signal line layer SL1 via a ninth via v9 extending through the first planarization layer PLN1, and to the second relay electrode RE2 in the first signal line layer SL1 via a tenth via v10 extending through the first planarization layer PLN1. The first relay electrode RE1 is connected to the drain D5 of the fifth transistor T5 via an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second relay electrode RE2 is connected to the drain D6 of the sixth transistor T6 via a twelfth via v12 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In some embodiments, the anode connection pad is connected to the second pad PAD2 via a via extending through the second planarization layer PLN2. Optionally, the anode connection pad is connected to the anode.

[0207] It is possible Figure 3A or Figure 8A Various suitable anode layouts are implemented in the array substrate shown. Figure 11A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 11B It is shown Figure 11A A diagram showing the structure of the anode connection pad layer in the array substrate. Figure 11C It is shown Figure 11A A diagram showing the structure of the third planarization layer in the array substrate. Figure 11D It is shown Figure 11A A diagram showing the structure of the anode layer in the array substrate. Figure 12 It is along Figure 11A A cross-sectional view of line I-I' in the diagram. Figures 11A to 11D and Figure 12 An exemplary anode layout in an array substrate according to the present disclosure is shown.

[0208] refer to Figures 11A to 11D and Figure 12In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN, and a first signal line layer SL1 located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2. The first planarization layer PLN1 is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2 is located on the side of the first planarization layer SLN1 away from the first signal line layer SL1; the second planarization layer PLN2 is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode bonding pad layer ACPL is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; the third planarization layer PLN3 is located on the side of the anode bonding pad layer ACPL away from the second planarization layer PLN2; and the anode layer ADL is located on the side of the third planarization layer PLN3 away from the anode bonding pad layer ACPL.

[0209] Reference Figure 11A , Figure 11B and Figure 12 In some embodiments, the anode connection pad layer includes anode connection pads (ACPs) in each pixel driving circuit. The anode connection pads (ACPs) connect the anode of the light-emitting element in each pixel driving circuit to a first pad (PAD1) in the corresponding pixel driving circuit. The anode connection pad layer can be fabricated using a variety of suitable conductive materials and a variety of suitable manufacturing methods. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the anode connection pad layer include, but are not limited to, metal oxide materials such as indium tin oxide (ITO), and metallic materials such as aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0210] Figure 11C A via extending through the third planarization layer PLN3 is shown. Figure 11C In the diagram, the corresponding positions of multiple anodes are indicated by dashed lines.

[0211] Reference Figure 11A , Figure 11D and Figure 12 The array substrate also includes an anode layer. Each anode is connected to an anode bonding pad via a corresponding through-hole extending through the third planarization layer PLN3.

[0212] refer to Figure 11A , Figure 11B and Figure 12 In some embodiments, the second pad PAD2 is connected to the first relay electrode RE1 in the first signal line layer SL1 via a ninth via v9 extending through the first planarization layer PLN1, and to the second relay electrode RE2 in the first signal line layer SL1 via a tenth via v10 extending through the first planarization layer PLN1. The first relay electrode RE1 is connected to the drain D5 of the fifth transistor T5 via an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second relay electrode RE2 is connected to the drain D6 of the sixth transistor T6 via a twelfth via v12 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The anode connection pad ACP is connected to the second pad PAD2 via a thirteenth via v13 extending through the second planarization layer PLN2. The anode AD is connected to the anode connection pad ACP via a fourteenth via v14 extending through the third planarization layer PLN3.

[0213] In some embodiments, the array substrate includes a connection layer located on the side of the second signal line layer away from the substrate (e.g., Figure 12 The array substrate also includes an anode layer (ACPL) located on the side of the interconnect layer away from the substrate. The interconnect layer includes multiple interconnects (e.g., anode interconnect pads (ACP)). The array substrate also includes an anode layer (ADL) located on the side of the interconnect layer away from the substrate. The second pad (PAD2) is connected via a corresponding interconnect among the multiple interconnects (e.g., ...). Figure 12 The anode connection pad (ACP) is connected to the corresponding anode (AD). Optionally, each connection line is made of a transparent conductive material such as a transparent metal oxide.

[0214] like Figure 11A As shown, the first nodes in different pixel driving circuits are located in environments with different anode layouts. In the context of this disclosure, each first node may include a portion of a semiconductor material layer between the source of the first transistor and the drain of the driving transistor. (Refer to...) Figure 11AThe first node N1l on the left (in the left pixel driving circuit) and the first node N1r on the right (in the right pixel driving circuit) are located in environments with different anode layouts. For example, the upper part of the first node N1l on the left is completely covered by the left anode, while the lower left corner is not covered; while the upper part of the first node N1r on the right is not covered by the right anode at all, while the lower part is covered. Furthermore, the first node N1l on the left is covered by a larger percentage compared to the first node N1r on the right. Since the first nodes in different pixel driving circuits are located in environments with different anode layouts, the influence of the anode on the first nodes may vary to different degrees without the first pad of this invention, resulting in uneven display. By having first pads respectively in the pixel driving circuits, the first nodes below the respective first pads can be located in an environment with a highly consistent height.

[0215] refer to Figures 3A to 3J , Figures 4A to 4D , Figures 7A to 7J , Figures 8A to 8D , Figures 11A to 11D and Figure 12 In some embodiments, each pixel driving circuit includes a node connection line Cln in a first signal line layer SL1 and a first pad PAD1 in a second signal line layer SL2. The node connection line Cln connects a first capacitor electrode Ce1 in each pixel driving circuit to a portion of a semiconductor material layer SML, which is located between the source S1 of a first transistor T1 and the drain Dd of a driving transistor Td. The orthographic projection of the first pad PAD1 on the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln on the substrate BS. Optionally, the orthographic projection of the first pad PAD1 on the substrate BS covers the orthographic projection of the node connection line Cln on the substrate BS. Optionally, the orthographic projection of the first pad PAD1 on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS. Optionally, the orthographic projection of the first pad PAD1 on the substrate BS at least partially overlaps with the orthographic projection of the first gate protrusion GP1 of a corresponding gate line in a plurality of gate lines GL on the substrate BS.

[0216] In some embodiments, the first pad PAD1 is configured to receive continuous direct current.

[0217] In some embodiments, each pixel driving circuit further includes a second pad PAD2 in the second signal line layer SL2. The second pad PAD2 is connected to the drain D5 of the fifth transistor T5 and the drain D6 of the sixth transistor T6, and is electrically connected to the anode of a light-emitting element, which is connected to the corresponding pixel driving circuit. Optionally, the orthographic projection of the second pad PAD2 onto the substrate BS at least partially overlaps with the orthographic projection of the signal line in the first signal line layer onto the substrate BS. Optionally, the signal line is configured to transmit continuous direct current.

[0218] In some embodiments, the first pad PAD1 and the second pad PAD2 span corresponding gate lines in a plurality of gate lines GL.

[0219] In some embodiments, a portion of the second pad PAD2 extends in a direction substantially parallel to the extension direction of a corresponding second reset signal line among a plurality of second reset signal lines Vintc. Optionally, the orthographic projection of the corresponding second reset signal line on the substrate BS at least partially overlaps with the orthographic projection of a portion of the second pad PAD2 on the substrate BS.

[0220] In some embodiments, a portion of the second pad PAD2 extends in a direction substantially parallel to the extension direction of the respective voltage supply line among the plurality of voltage supply lines VDD. Optionally, the orthographic projection of the respective voltage supply line on the substrate BS at least partially overlaps with the orthographic projection of a portion of the second pad PAD2 on the substrate BS.

[0221] In some embodiments, the second pad PAD2 is connected to the first relay electrode RE1 in the first signal line layer SL1 through the ninth via v9, and to the second relay electrode RE2 in the first signal line layer SL1 through the tenth via v10. Optionally, the first relay electrode RE1 is connected to the drain D5 of the fifth transistor T5 through the eleventh via v11. Optionally, the second relay electrode RE2 is connected to the drain D6 of the sixth transistor T6 through the twelfth via v12.

[0222] In some embodiments, the first pad PAD1 is configured to receive a reset signal. Optionally, the first pad PAD1 is connected to two adjacent first reset signal lines among a plurality of first reset signal lines Vintr in the same layer, thereby forming an interconnected first reset signal network. Optionally, the array substrate further includes a plurality of reset signal transmission lines vtl located in the semiconductor material layer SML. Each of the plurality of reset signal transmission lines vtl connects the sources of a first transistor and a sixth transistor in a row pixel driving circuit together.

[0223] In some embodiments, the first pad PAD1 is configured to receive a voltage supply signal. Optionally, the first pad PAD1 is connected to a corresponding voltage supply line among a plurality of voltage supply lines VDD in an adjacent pixel driving circuit. Optionally, the first pad PAD1 spans a corresponding data line among a plurality of data lines DL.

[0224] In some embodiments, the plurality of pixel driving circuits includes at least a first pixel driving circuit and a second pixel driving circuit. Optionally, the orthographic projections of the first node connection line in the first pixel driving circuit and the second node connection line in the second pixel driving circuit onto the substrate overlap with the orthographic projections of the first anode in the first pixel driving circuit and the second anode in the second pixel driving circuit onto the substrate at different portions with different percentages.

[0225] In some embodiments, each pixel driving circuit includes a driving transistor Td and a compensation transistor (e.g., a third transistor T3), the compensation transistor being configured to provide a compensation voltage signal to the gate of the driving transistor. The compensation transistor includes a source, a drain, and a gate. A node connection line Cln connects the gate of the driving transistor Td in the first pixel driving circuit and the drain of the compensation transistor (e.g., D3 of the third transistor T3) in the first pixel driving circuit. A second node connection line connects the gate of the driving transistor in the second pixel driving circuit and the drain of the compensation transistor in the second pixel driving circuit. The voltage level at the first node N1 is the same as the voltage level at the gate of the driving transistor in the first pixel driving circuit. The voltage level at the second node N2 is the same as the voltage level at the gate of the driving transistor in the second pixel driving circuit.

[0226] Figure 13A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 13A The array substrate shown and Figure 3A The array substrates shown are similar, except that... Figure 13A The structure of the second signal layer in the array substrate shown is similar to Figure 3A The structure of the second signal layer in the array substrate shown is different.

[0227] Figure 13B It is shown Figure 13A A diagram showing the structure of the semiconductor material layer in the array substrate. Figure 13C It is shown Figure 13A A diagram showing the structure of the first conductive layer in the array substrate. Figure 13D It is shown Figure 13A A diagram showing the structure of the second conductive layer in the array substrate. Figure 13E It is shown Figure 13A The diagram shows the structure of the interlayer dielectric layer in the array substrate. Figure 13F It is shown Figure 13A A diagram showing the structure of the first signal line layer in the array substrate. Figure 13G It is shown Figure 13A A diagram showing the structure of the passivation layer in the array substrate. Figure 13H It is shown Figure 13A A diagram showing the structure of the first planarization layer in the array substrate. Figure 13I It is shown Figure 13A A diagram showing the structure of the second signal line layer in the array substrate. Figure 13J It is shown Figure 13A A diagram showing the structure of the second planarization layer in the array substrate. Figure 13A and Figure 13I The first pad PAD1 in the array substrate shown is part of a closed loop; while Figure 3A and Figure 3I The first pad PAD1 in the array substrate shown is part of an open loop.

[0228] In some embodiments, each pixel driving circuit in the array substrate includes: a node connection line Cln in a first signal line layer; and a first pad PAD1 in a second signal line layer, located on the side of the first signal line layer away from the substrate. Each pixel driving circuit in the array substrate also includes a voltage line configured to output a constant voltage signal, and a voltage connection line VCL electrically connecting the first pad PAD1 to the voltage line. Figure 13I In the context of the plurality of first reset signal lines Vintr, each first reset signal line can be considered as a voltage line configured to output a constant reset voltage signal. The voltage line is electrically connected to the source of the sixth transistor. For example, as... Figure 2A and Figure 2B As shown, the source of the sixth transistor T6 is electrically connected to one of the plurality of first reset signal lines Vintr (e.g., a voltage line).

[0229] In some embodiments, the voltage connection line VCL electrically connects multiple first reset signal lines Vintr together to form a reset signal line network. For example... Figure 13I As shown, the first pad PAD1 and a first portion of the voltage connection line VCL form a first closed loop CLP1. The first pad PAD1, a second portion of the voltage connection line VCL, and a portion of the voltage lines (e.g., a corresponding one of the plurality of first reset signal lines Vintr) constitute a portion of the second closed loop CLP2. More specifically, the second closed loop CLP2 includes the first pad PAD1, the second portion of the voltage connection line VCL, the voltage connection line VCL in the adjacent pixel driving circuit, and portions of two adjacent voltage lines (e.g., portions of two adjacent first reset signal lines of the plurality of first reset signal lines Vintr).

[0230] The inventors of this disclosure have discovered, surprisingly and unexpectedly, that by making the first pad PAD1 part of a closed loop, with an array substrate in which the first pad is part of an open loop (see, for example...) Figure 3I In contrast, the first pad PAD1 is configured to better ensure that the first nodes in different pixel drive circuits are located in a similar environment.

[0231] In some embodiments, each pixel driving circuit includes a driving transistor Td and a compensation transistor (e.g., a third transistor T3), the compensation transistor being configured to provide a compensation voltage signal to the gate of the driving transistor. The compensation transistor includes a source, a drain, and a gate. A node connection line Cln connects the gate of the driving transistor Td and the drain of the compensation transistor (e.g., D3 of the third transistor T3).

[0232] Reference Figures 13A to 13J In some embodiments, the orthographic projections of the voltage line and voltage connection line VCL on the substrate and the orthographic projections of the node connection line Cln on the substrate are spaced apart from each other. The orthographic projection of the first pad PAD1 on the substrate at least partially overlaps with the orthographic projection of the node connection line Cln on the substrate. The orthographic projection of the first pad PAD1 on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor (e.g., the third transistor T3) on the substrate, see, for example... Figure 4A It depicts the orthographic projection of the first pad PAD1 on the substrate BS and the orthographic projection of the active layer ACT3 of the third transistor (compensation transistor) on the substrate BS, which at least partially overlaps.

[0233] refer to Figures 13A to 13J In some embodiments, the length of the node connection line Cln along the first direction DR1 is less than its length along the second direction DR2. The length of the voltage line (e.g., each of the plurality of first reset signal lines Vintr) along the first direction DR1 is less than its length along the second direction DR2. The first direction DR1 and the second direction DR2 intersect each other. In some embodiments, the length of the second pad PAD2 along the first direction DR1 is greater than the length of the first pad PAD1 along the first direction DR1; the length of the second pad PAD2 along the second direction DR2 is greater than the length of the first pad PAD1 along the second direction DR2. Figure 13I As shown, in some embodiments, the second pad PAD2 is at least partially (e.g., at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, or at least 70%) surrounding the first pad PAD1.

[0234] Figure 14A The structure of a semiconductor material layer according to some embodiments of the present disclosure is shown. Figure 14B The structure of the first conductive layer according to some embodiments of the present disclosure is shown. Figure 14C The structure of the semiconductor material layer and the first conductive layer according to some embodiments of the present disclosure is shown. (Refer to...) Figures 14A to 14C The active layer ACT1 of the first transistor T1 includes a portion P, and the orthographic projection of the portion P on the substrate does not overlap with the orthographic projection of the two gates (G1-1 and G1-2) of the first transistor T1 on the substrate.

[0235] Figure 14D The structure of the semiconductor material layer and the second conductive layer according to some embodiments of the present disclosure is shown. (Refer to...) Figure 14A and Figure 14D The second conductive layer includes a shielding block (e.g., Figure 14D The anti-interference block IPB shown has at least a portion (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthogonal projection of the shielding block on the substrate overlapping with the orthogonal projection of a portion of P on the substrate.

[0236] refer to Figure 13D The second conductive layer includes a plurality of second capacitor electrodes (one of which is denoted as Ce2). Adjacent second capacitor electrodes among the plurality of second capacitor electrodes are connected to each other by a connection portion CP.

[0237] Figure 14E The structure of the second conductive layer and the second signal line layer according to some embodiments of the present disclosure is shown. (Refer to...) Figure 13D and Figure 14E The voltage connection line VCL crosses the connection portion CP. The orthographic projection of the connection portion CP onto the substrate at least partially overlaps with the orthographic projection of the voltage connection line VCL onto the substrate.

[0238] In some embodiments, reference Figures 13A to 13I The aforementioned reset signal line network includes horizontal and vertical reset signal lines that intersect each other. Each of the plurality of first reset signal lines (Vintr) can be considered a horizontal reset signal line, and the voltage connection line (VCL) can be considered a vertical reset signal line. In some embodiments, a first pad (PAD1) is electrically connected to a vertical reset signal line (e.g., VCL), and the vertical reset signal line is electrically connected to a horizontal reset signal line (e.g., Vintr). The vertical reset signal line extends along a second direction (DR2), and the horizontal reset signal line extends along a first direction (DR1). The horizontal reset signal line is located in a second signal line layer. Optionally, both the horizontal and vertical reset signal lines are located in the second signal line layer.

[0239] Figure 15A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 15B It is shown Figure 15A A diagram showing the structure of the semiconductor material layer in the array substrate. Figure 15C It is shown Figure 15A A diagram showing the structure of the first conductive layer in the array substrate. Figure 15D It is shown Figure 15A A diagram showing the structure of the second conductive layer in the array substrate. Figure 15E It is shown Figure 15A The diagram shows the structure of the interlayer dielectric layer in the array substrate. Figure 15F It is shown Figure 15A A diagram showing the structure of the first signal line layer in the array substrate. Figure 15G It is shown Figure 15A A diagram showing the structure of the passivation layer in the array substrate. Figure 15H It is shown Figure 15A A diagram showing the structure of the first planarization layer in the array substrate. Figure 15I It is shown Figure 15A A diagram showing the structure of the second signal line layer in the array substrate. Figure 15J It is shown Figure 15A A diagram showing the structure of the second planarization layer in the array substrate.

[0240] Figures 15A to 15J The array substrate shown is Figures 7A to 7J The array substrate shown differs in that it includes, for example, a plurality of second voltage signal lines VDD2 in a second signal line layer. Each of the plurality of second voltage signal lines VDD2 is connected to a corresponding one of the plurality of voltage signal lines VDD through a via extending through the first planarization layer. Figures 15A to 15J The structural details and bonding of the array substrate depicted in the figure Figures 7A to 7J , Figures 8A to 8D , Figure 9A , Figure 9B , Figure 10A and Figure 10B The topics discussed are largely similar, except for the specific content discussed below.

[0241] like Figure 15IAs shown, the voltage connection line VCL, the first pad PAD1, and a corresponding one of the plurality of second voltage signal lines VDD2 are part of the overall structure. The first pad PAD1 is connected to a corresponding voltage supply line among the plurality of voltage supply lines Vdd in the adjacent pixel driving circuit via the voltage connection line VCL and a corresponding one of the plurality of second voltage signal lines VDD2. The voltage connection line VCL is connected to a corresponding voltage supply line among the plurality of voltage supply lines Vdd in the adjacent pixel driving circuit via a corresponding one of the plurality of second voltage signal lines VDD2 in the adjacent pixel driving circuit. A corresponding one of the plurality of second voltage signal lines VDD2 in the adjacent pixel driving circuit is connected to a corresponding voltage supply line among the plurality of voltage supply lines Vdd in the adjacent pixel driving circuit via a via (e.g., a seventh via v7) extending through the first planarization layer PLN1. A corresponding voltage supply line of the plurality of voltage supply lines Vdd is connected to the second capacitor electrode Ce2 via an eighth via v8 extending through the interlayer dielectric layer ILD.

[0242] refer to Figure 15I In some embodiments, the second pad PAD2 is a partial loop surrounding at least 75% (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 98%) of the first pad PAD1. The partial loop of the second pad PAD2 is broken at a location between a corresponding second voltage signal line of the plurality of second voltage signal lines VDD2 and the first pad PAD1, and a voltage connection line VCL extends through this opening from the corresponding second voltage signal line of the plurality of second voltage signal lines VDD2 to the first pad PAD1. The inventors of this disclosure have found that by configuring the second pad PAD2 to have a partial loop surrounding at least 75% of the first pad PAD1, it is better ensured that the first nodes in different pixel driving circuits are located in similar environments.

[0243] Figure 16A This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 16B It is shown Figure 16A A diagram showing the structure of the semiconductor material layer in the array substrate. Figure 16C It is shown Figure 16A A diagram showing the structure of the first conductive layer in the array substrate. Figure 16D It is shown Figure 16A A diagram showing the structure of the second conductive layer in the array substrate. Figure 16E It is shown Figure 16A The diagram shows the structure of the interlayer dielectric layer in the array substrate. Figure 16F It is shown Figure 16A A diagram showing the structure of the first signal line layer in the array substrate. Figure 16G It is shown Figure 16A A diagram showing the structure of the passivation layer in the array substrate. Figure 16H It is shown Figure 16A A diagram showing the structure of the first planarization layer in the array substrate. Figure 16I It is shown Figure 16A A diagram showing the structure of the second signal line layer in the array substrate. Figure 16J It is shown Figure 16A A diagram showing the structure of the second planarization layer in the array substrate.

[0244] Figures 16A to 16J The array substrate depicted in the paper and Figures 7A to 7J The array substrate depicted differs in that it includes, for example, a plurality of third reset signal lines Vintc2 in a second signal line layer. A corresponding one of the plurality of third reset signal lines Vintc2 is connected to a corresponding one of the plurality of second reset signal lines Vintc via a via extending through the first planarization layer. Figures 16A to 16J The structural details and bonding of the array substrate depicted in the figure Figures 7A to 7J , Figures 8A to 8D , Figure 9A , Figure 9B , Figure 10A and Figure 10B The topics discussed are largely similar, except for the specific content discussed below.

[0245] like Figure 16I As shown, the voltage connection line VCL, the first pad PAD1, and a corresponding one of the plurality of third reset signal lines Vintc2 are part of the overall structure. The first pad PAD1 is connected to a corresponding second reset signal line in the plurality of second reset signal lines Vintc through the voltage connection line VCL and the corresponding third reset signal line in Vintc2. The voltage connection line VCL is connected to a corresponding second reset signal line in the plurality of second reset signal lines Vintc through the corresponding third reset signal line in Vintc2. The corresponding third reset signal line in Vintc2 is connected to a corresponding second reset signal line in Vintc through vias extending through the first planarization layer. Each second reset signal line in Vintc is configured to provide a reset signal to the gate of the driving transistor. The corresponding second reset signal line in Vintc is connected to the source S1 of the first transistor T1 through a fourth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer, thereby providing an initialization signal to the source S1 of the first transistor T1.

[0246] Figure 17 Show Figure 16A The structure of the second pad in the array substrate shown. (Reference) Figure 17The second pad PAD2 includes a first branch BR1 and a second branch BR2 extending from the body MB of the second pad PAD2. Optionally, the first branch BR1 and the second branch BR2 extend along a second direction DR2. See also Figure 16I and Figure 17 The first branch BR1 and the second branch BR2, respectively, originating from two adjacent pixel driving circuits, at least partially (e.g., at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, or at least 98%) surround the first pad PAD1 on one side away from the respective third reset signal lines in the plurality of third reset signal lines Vintc2. The inventors of this disclosure have discovered that by having the first branch BR1 and the second branch BR2, respectively, originating from two adjacent pixel driving circuits, at least partially surround the first pad PAD1 on one side away from the respective third reset signal lines in the plurality of third reset signal lines Vintc2, it is better ensured that the first nodes in different pixel driving circuits are located in a similar environment.

[0247] Various anode arrangements can be achieved in this array substrate. Figure 18A An anode arrangement in an array substrate according to some embodiments of the present disclosure is shown. Figure 18B This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 18B It shows having Figure 18A The array substrate with the anode arrangement shown. Figure 19A An anode arrangement in an array substrate according to some embodiments of the present disclosure is shown. Figure 19B This is a diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 19B It shows having Figure 19A The array substrate with an anode arrangement is shown in the figure.

[0248] Figure 20A This is a diagram illustrating the structure of the anode connection pad layer in an array substrate according to some embodiments of the present disclosure. Figure 20B This is a diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure. Figure 20C This is a diagram illustrating the structure of the second conductive layer, the anode connection pad layer, and the anode layer in an array substrate according to some embodiments of the present disclosure.

[0249] Figure 21A This is a diagram illustrating the structure of the anode connection pad layer in an array substrate according to some embodiments of the present disclosure. Figure 21B This is a diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure. Figure 21C This is a diagram illustrating the structure of the second conductive layer, the anode connection pad layer, and the anode layer in an array substrate according to some embodiments of the present disclosure.

[0250] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0251] In some embodiments, a gate-on-array (GOA) circuit is disposed in the display area of ​​the display device. In the region corresponding to the GOA circuit, there is no pixel driving circuit, but rather the anode of a light-emitting element. The display area includes a transition region adjacent to the region corresponding to the GOA circuit. The anode in the region corresponding to the GOA circuit is connected to the pixel driving circuit in the transition region. Therefore, the transition region has a higher density of pixel driving circuits compared to the normal display area located on the side of the transition region furthest from the GOA circuit. In the transition region, the relative position between the node connection line and the first node differs from the relative position between the node connection line and the first node in the normal display area.

[0252] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel driving circuits configured to drive light emission in a plurality of sub-pixels. Optionally, forming each pixel driving circuit includes forming node interconnects in a first signal line layer and forming a first pad in a second signal line layer. Optionally, the node interconnects are formed to connect a first capacitor electrode in each pixel driving circuit to a portion of a semiconductor material layer located between the source of a first transistor and the drain of the driving transistor. Optionally, the orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the node interconnects on the substrate.

[0253] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising a substrate and a plurality of pixel driving circuits configured to drive a plurality of sub-pixels to emit light; in, Each pixel driving circuit includes: Drive transistors; A compensation transistor is configured to provide a compensation voltage signal to the gate of the driving transistor; the compensation transistor includes a source, a drain, and a gate. Node connection lines in the first signal line layer; The first pad in the second signal line layer is located on the side of the first signal line layer away from the substrate. Voltage lines, configured to output a constant voltage signal; and A voltage connection line that electrically connects the first pad to the voltage line; The node connection line connects the gate of the driving transistor and the drain of the compensation transistor. The orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the node connection line on the substrate; and The orthographic projections of the voltage lines and voltage connection lines on the substrate are spaced apart from the orthographic projections of the node connection lines on the substrate.

2. The array substrate according to claim 1, wherein, The first pad, a portion of the voltage connection line, and a portion of the voltage line form part of a closed loop.

3. The array substrate according to claim 1, further comprising: A connection layer is located on the side of the second signal line layer away from the substrate, and the connection layer includes a plurality of connection lines; An anode layer is located on the side of the interconnect layer away from the substrate. Each pixel driving circuit further includes a second pad in the second signal line layer; The second pad is connected to the corresponding anode via a corresponding connection line among the plurality of connection lines; and The corresponding connecting lines include a transparent conductive material.

4. The array substrate according to claim 1, wherein, Each pixel driving circuit also includes a first transistor having two gates and an active layer, wherein a portion of the active layer is projected onto the substrate and the two gates of the first transistor are not projected onto the substrate. The drain of the first transistor is electrically connected to the gate of the driving transistor. The array substrate further includes a second conductive layer located on the side of the first signal line layer closer to the substrate. The second conductive layer includes a shielding block, the orthographic projection of which on the substrate overlaps at least partially with the orthographic projection of the portion on the substrate.

5. The array substrate according to claim 1, wherein, The array substrate further includes a second conductive layer located on the side of the first signal line layer closer to the substrate. The second conductive layer includes a plurality of second capacitor electrodes, and adjacent second capacitor electrodes are connected to each other through a connection portion; as well as The orthographic projection of the connection portion on the substrate at least partially overlaps with the orthographic projection of the voltage connection line on the substrate.

6. The array substrate according to claim 1, wherein, The length of the node connection line along the first direction is less than the length along the second direction; The length of the voltage line along the first direction is less than the length along the second direction; as well as The first direction and the second direction intersect each other.

7. The array substrate according to claim 1, wherein, The orthogonal projection of the first pad on the substrate covers the orthogonal projection of the node connection line on the substrate. as well as The orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate.

8. The array substrate according to claim 1, wherein, The orthographic projection of the first pad on the substrate at least partially overlaps with the orthographic projection of the gate of the compensation transistor on the substrate.

9. The array substrate according to any one of claims 1 to 8, wherein, Each pixel driving circuit also includes a second pad in the second signal line layer; The second pad is connected to the drain of the fifth transistor and the drain of the sixth transistor, and is electrically connected to the anode of the light-emitting element connected to the corresponding pixel driving circuit. The source of the fifth transistor is electrically connected to the drain of the driving transistor; and The source of the sixth transistor is electrically connected to the voltage line.

10. The array substrate according to claim 9, wherein, The first pad and the second pad span corresponding gate lines among a plurality of gate lines.

11. The array substrate according to claim 9, wherein, The length of the second pad along the first direction is greater than the length of the first pad along the first direction; The length of the second pad along the second direction is greater than the length of the first pad along the second direction; and The second pad at least partially surrounds the first pad.

12. The array substrate according to claim 11, wherein, The orthographic projection of the second pad on the substrate at least partially overlaps with the orthographic projection of the signal line in the first signal line layer on the substrate; as well as The signal line is configured to transmit continuous direct current.

13. The array substrate according to claim 11, wherein, A portion of the second pad extends in a direction substantially parallel to the extension direction of a corresponding second reset signal line among a plurality of second reset signal lines, each of the plurality of second reset signal lines being configured to provide a reset signal to the gate of the driving transistor; as well as The orthographic projection of the corresponding second reset signal line on the substrate at least partially overlaps with the orthographic projection of the portion of the second pad on the substrate.

14. The array substrate according to claim 11, wherein, A portion of the second pad extends in a direction substantially parallel to the extension direction of the respective voltage supply line among the plurality of voltage supply lines; The orthographic projection of the corresponding voltage supply line on the substrate at least partially overlaps with the orthographic projection of a portion of the second pad on the substrate. as well as Each voltage supply line is configured to provide a driving voltage to the light-emitting element connected to the corresponding pixel driving circuit.

15. The array substrate according to claim 1, wherein, The first pad is configured to receive a reset signal; The first pad is electrically connected to a vertical reset signal line, which extends along a second direction; The vertical reset signal line is electrically connected to the horizontal reset signal line, and the horizontal reset signal line extends along a first direction. as well as The horizontal reset signal line is in the second signal line layer.

16. The array substrate of claim 15, further comprising a plurality of reset signal transmission lines in a semiconductor material layer, the semiconductor material layer being located on the side of the first signal line layer closer to the substrate; in, The corresponding reset signal transmission line in the plurality of reset signal transmission lines connects the sources of the first transistor and the sixth transistor in the row pixel driving circuit together. The corresponding reset signal transmission line extends along the first direction; as well as The drain of a corresponding first transistor in the first transistor is electrically connected to the gate of the driving transistor.

17. The array substrate according to claim 1, wherein, The first pad is configured to receive a voltage supply signal; The first pad is connected to a corresponding voltage supply line among multiple voltage supply lines in the adjacent pixel driving circuit; as well as Each voltage supply line is configured to provide a driving voltage to the light-emitting element connected to the corresponding pixel driving circuit.

18. The array substrate according to claim 1, wherein, The voltage connection line crosses a corresponding data line among multiple data lines, which are in a pixel driving circuit adjacent to the corresponding pixel driving circuit.

19. The array substrate according to claim 1, wherein, The plurality of pixel driving circuits include at least a first pixel driving circuit and a second pixel driving circuit. The orthographic projections of the first node connection line in the first pixel driving circuit and the second node connection line in the second pixel driving circuit on the substrate overlap with the orthographic projections of the first anode in the first pixel driving circuit and the second anode in the second pixel driving circuit on the substrate at different percentages in different parts. The second node connection line connects the gate of the driving transistor in the second pixel driving circuit to the drain of the compensation transistor in the second pixel driving circuit. The voltage level at the first node is the same as the voltage level at the gate of the driving transistor in the first pixel driving circuit; as well as The voltage level at the second node is the same as the voltage level at the gate of the driving transistor in the second pixel driving circuit.

20. A display device comprising an array substrate according to any one of claims 1 to 19 and an integrated circuit connected to the array substrate.

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