Display panel and display device

Abstract

A display panel, comprising: a substrate (21); a plurality of pixel circuits (D) disposed on the substrate (21), at least one pixel circuit (D) comprising a driving transistor (T21) and a first switching transistor (T22); the display panel further comprising: an active layer (22) disposed on the substrate (21), the active layer (22) comprising a first active part (A1) and a second active part (A2); the first active part (A1) is used for forming a channel part of the driving transistor (T21), and the second active part (A2) is used for forming a second pole connecting part of the first switching transistor (T22); a first conductive layer (23) disposed on a side of the active layer (22) away from the substrate (21); the first conductive layer (23) comprises a first conductive part (S1), part of the first conductive part (S1) is used for forming a gate electrode of the driving transistor (T21), and another part of the first conductive part (S1) is electrically connected with the second active part (A2); and a channel length (L) of the channel part of the driving transistor (T21) is greater than a channel width (W).

Description

[0001] This application claims priority to application No. CN202111499616.4, filed on December 9, 2021. Each of the above applications is incorporated herein by reference in its entirety for all purposes. Technical Field

[0002] This disclosure relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0003] With the development of technology, people are constantly demanding higher image quality from monitors. For example, there is a current need for monitors that can achieve good display effects at low grayscale levels. In related technologies, the grayscale-brightness variation curve of a monitor can be adjusted based on the HDR10 curve to achieve more detailed brightness segmentation at low grayscale levels. However, even with this, the brightness change corresponding to a single grayscale step at low grayscale levels is still relatively large, which is still insufficient to meet display requirements. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a display panel and a display device.

[0005] According to a first aspect of this disclosure, a display panel is provided, comprising:

[0006] Substrate;

[0007] A plurality of pixel circuits disposed on the substrate, at least one of the pixel circuits including a driving transistor and a first switching transistor;

[0008] The display panel also includes:

[0009] An active layer disposed on the substrate includes a first active portion and a second active portion; the first active portion forms the channel portion of the driving transistor, and the second active portion forms the second electrode connection portion of the first switching transistor; and...

[0010] A first conductive layer is disposed on the side of the active layer away from the substrate.

[0011] Wherein, the first conductive layer includes a first conductive portion, a portion of which is used to form the gate of the driving transistor, and another portion of which is electrically connected to the second active portion; and,

[0012] The channel length of the driving transistor is greater than the channel width.

[0013] According to an embodiment of this disclosure, the display panel further includes: a second conductive layer disposed on the side of the first conductive layer facing away from the substrate;

[0014] The second conductive layer includes a second conductive portion, which is electrically connected to the second active portion and the first conductive portion. The dimension of the second conductive portion in a first direction is smaller than the channel length of the first channel portion, wherein the first direction includes the direction from the first electrode of the driving transistor to the second electrode.

[0015] According to an embodiment of the present disclosure, the first conductive layer further includes a first gate line, which is electrically connected to the gate of the first switching transistor.

[0016] The first conductive portion includes a first side and a second side arranged along the first direction, and the second conductive portion includes a third side and a fourth side arranged along the first direction.

[0017] Wherein, the orthographic projection of the straight line containing the first side on the substrate is located on the side where the orthographic projection of the third side on the substrate is away from the orthographic projection of the fourth side on the substrate, and the orthographic projection of the straight line containing the second side on the substrate is located on the side where the orthographic projection of the third side on the substrate is toward the orthographic projection of the fourth side on the substrate.

[0018] According to an embodiment of this disclosure, the orthographic projection of the straight line containing the second side on the substrate is located on the side where the orthographic projection of the fourth side on the substrate is opposite to the orthographic projection of the third side on the substrate.

[0019] According to embodiments of the present disclosure, at least one pixel circuit further includes a storage capacitor, and the second conductive layer further includes a third conductive portion for forming the storage capacitor, the third conductive portion including a fifth side and a sixth side arranged along the first direction;

[0020] Wherein, the orthographic projection of the fifth side on the substrate is located on the side where the orthographic projection of the sixth side on the substrate is away from the orthographic projection of the second side on the substrate, and the orthographic projection of the sixth side on the substrate is located on the side where the orthographic projection of the first side on the substrate faces the orthographic projection of the second side on the substrate.

[0021] According to embodiments of this disclosure, the second conductive layer further includes a data line and a fourth conductive portion;

[0022] The fourth conductive portion is used to form the first electrode of the first switching transistor, and the orthographic projection of the fourth conductive portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0023] According to an embodiment of the present disclosure, the first conductive layer further includes a first gate line and a second gate line, wherein the first gate line is electrically connected to the gate of the first switching transistor and the second gate line;

[0024] The orthographic projection of the first gate line on the substrate is located on the side of the orthographic projection of the second gate line on the substrate that is close to the orthographic projection of the driving transistor on the substrate;

[0025] The orthographic projection of the third active part on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate.

[0026] According to embodiments of this disclosure, the display panel further includes a plurality of pixel units, and at least one of the pixel units includes a plurality of the pixel circuits;

[0027] In at least one pixel unit, the first poles of the driving transistors of the plurality of pixel circuits are electrically connected to each other.

[0028] According to embodiments of the present disclosure, at least one pixel circuit further includes a second switching transistor;

[0029] In at least one pixel unit, the first poles of the second switching transistors of the plurality of pixel circuits are electrically connected to each other.

[0030] According to embodiments of this disclosure, at least one group of adjacent pixel circuits satisfies the following condition:

[0031] X <Y;

[0032] Wherein, X represents the difference in channel length of the driving transistor in adjacent pixel circuits; and Y represents the difference in channel width of the driving transistor in adjacent pixel circuits.

[0033] According to embodiments of this disclosure, the plurality of pixel circuits includes a first pixel circuit, a second pixel circuit, and a third pixel circuit;

[0034] The first pixel circuit, the second pixel circuit, and the third pixel circuit are electrically connected to light-emitting devices of different colors, and the first pixel circuit is electrically connected to a red light-emitting device.

[0035] The sum of the channel area of ​​the driving transistor in the second pixel circuit and the channel area of ​​the driving transistor in the third pixel circuit is less than the channel area of ​​the driving transistor in the first pixel circuit.

[0036] According to embodiments of this disclosure, a plurality of pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, wherein the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to light-emitting devices of different colors, and the second pixel circuit is electrically connected to a white light-emitting device.

[0037] The aspect ratio of the channel portion of the driving transistor in any of the first pixel circuit, the third pixel circuit, and the fourth pixel circuit is greater than the aspect ratio of the channel portion of the driving transistor in the second pixel circuit.

[0038] According to embodiments of this disclosure, a plurality of pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, wherein the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to light-emitting devices of different colors, and the first pixel circuit is electrically connected to a red light-emitting device.

[0039] The aspect ratio of the driving transistor in any of the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is smaller than that of the driving transistor in the first pixel circuit.

[0040] According to embodiments of this disclosure, the channel lengths of the driving transistors in the plurality of pixel circuits are the same.

[0041] According to embodiments of this disclosure, at least two of the pixel circuits have different channel lengths for their driving transistors.

[0042] According to embodiments of this disclosure, the width-to-length ratio of the channel portion of the driving transistor is greater than or equal to 1 / 5 and less than or equal to 25 / 12.

[0043] According to embodiments of this disclosure, the display panel further includes a gate driving circuit;

[0044] In the gate drive circuit, at least some of the transistors have a channel length less than or equal to their channel width.

[0045] According to an embodiment of this disclosure, the orthographic projection of the portion of the first conductive part that is electrically connected to the second active part on the substrate overlaps with the orthographic projection of the second active part on the substrate.

[0046] According to embodiments of this disclosure, the width of either the first gate line or the second gate line is less than the channel length of the driving transistor.

[0047] According to embodiments of this disclosure, the channel width-to-length ratio of either the first switching transistor or the second switching transistor is greater than the channel width-to-length ratio of the driving transistor.

[0048] According to a second aspect of this disclosure, a display device is provided, which includes the display panel described above. Attached Figure Description

[0049] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0050] Figure 1 The schematic diagram illustrates the equivalent circuit diagram of a pixel circuit in one example;

[0051] Figure 2 A schematic diagram illustrating the HDR10 curve and the Gamma2.2 curve is shown.

[0052] Figure 3 A schematic plan view of the display panel in an embodiment of this disclosure is shown;

[0053] Figure 4a One of the plan views of a pixel circuit in a pixel unit according to an embodiment of the present disclosure is illustrated schematically;

[0054] Figure 4b The equivalent circuit diagram of the pixel circuit in an embodiment of this disclosure is shown schematically;

[0055] Figure 4c The schematic diagram illustrates the driving timing of the pixel circuit in an embodiment of this disclosure;

[0056] Figure 5a The diagram illustrates a second plan view of the pixel circuitry in a pixel unit according to an embodiment of the present disclosure.

[0057] Figure 5b This schematically illustrates the overlay diagram of the various film layers in the display panel in the thickness direction according to an embodiment of the present disclosure;

[0058] Figure 6a A schematic plan view of the active layer in an embodiment of this disclosure is shown.

[0059] Figure 6b A schematic plan view of the first conductive layer in an embodiment of this disclosure is shown.

[0060] Figure 6c A schematic plan view of the second conductive layer in an embodiment of this disclosure is shown.

[0061] Figure 6d A schematic plan view of some of the vias in an embodiment of this disclosure is shown;

[0062] Figure 7a A schematic plan view of the driving transistor and the second conductive portion in an embodiment of this disclosure is shown.

[0063] Figure 7b A schematic plan view of the driving transistor and the third conductive portion in an embodiment of this disclosure is shown;

[0064] Figure 8 The diagram illustrates a third plan view of the pixel circuitry in a pixel unit according to an embodiment of the present disclosure;

[0065] Figure 9 A schematic plan view of the third conductive layer in an embodiment of this disclosure is shown. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0067] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0068] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0069] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0070] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0071] Those skilled in the art will understand that, unless otherwise stated, the term "thickness" in this document refers to the dimension along the surface perpendicular to the display panel on which the various film layers are disposed, i.e., the dimension along the light-emitting direction of the display panel.

[0072] In this article, unless otherwise stated, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "one-step patterning process" refers to the process of forming patterned layers, components, and parts using a single photomask.

[0073] It should be noted that the terms "same layer," "same layer setup," or similar expressions refer to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to pattern this film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0074] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0075] In a pair, the display panel includes multiple pixel units, each pixel unit includes multiple sub-pixels, and each sub-pixel includes a light-emitting device and pixel circuitry for providing drive current to the light-emitting device. Figure 1 The schematic diagram illustrates the equivalent circuit diagram of a pixel circuit in one example, such as... Figure 1As shown, in this example, the pixel circuit may include a first switching transistor T11, a second switching transistor T12, a driving transistor T13, and a storage capacitor C1. The gate of the first switching transistor T11 is electrically connected to the first gate line 11, the first terminal of the first switching transistor T11 is electrically connected to the data line 12, the second terminal of the first switching transistor T11 is electrically connected to the gate of the driving transistor T13, the first terminal of the driving transistor T13 is electrically connected to the first power line 13, the second terminal of the driving transistor T13 is electrically connected to the second plate of the storage capacitor C1, the second terminal of the second switching transistor T12, and the light-emitting device 14, the gate of the second switching transistor T12 is electrically connected to the second gate line 15, and the first terminal of the second switching transistor T12 is electrically connected to the reference signal line 16.

[0076] In this example, the structure of the driving transistor T13 directly affects the driving signal provided to the light-emitting device 14. Therefore, the structural parameters of the driving transistor T13 are quite sensitive. In order to ensure that the light-emitting device 14 can achieve the desired light-emitting effect, the design of the driving transistor T13 is generally quite cautious. It usually adopts a more common design approach, that is, the driving transistor T13 adopts a design approach where the channel length is greater than the channel width.

[0077] To improve the display effect at low grayscale, in this example, the grayscale-brightness change curve of the display panel is adjusted according to the HDR10 curve. In this way, more detailed brightness segmentation can be achieved in the low grayscale range, thereby improving the display effect at low grayscale. Figure 2 The diagram illustrates the grayscale-brightness variation curve before adjustment. Figure 2 The diagram schematically illustrates the HDR10 curve and the Gamma2.2 curve, from... Figure 2 It is evident that, compared to the Gamma 2.2 curve, the HDR10 curve exhibits a smaller brightness variation within a single grayscale step in the lower grayscale range. This results in more detailed brightness segmentation and a certain improvement in grayscale unfolding. However, even so, the brightness variation within a single grayscale step in the lower grayscale range remains significant, still insufficient to meet display requirements.

[0078] In view of this, embodiments of the present disclosure provide a display panel, Figure 3 A schematic plan view of the display panel in an embodiment of this disclosure is shown, such as Figure 3 As shown, the display panel includes a substrate 21 and a plurality of pixel circuits disposed on the substrate 21. The display panel can be divided into a display area AA and a non-display area NA located outside the display area AA. In the display area AA, a plurality of pixel units P are arranged in an array along a first direction and a second direction. The first direction may include the column direction of the display panel, i.e. Figure 3The vertical direction in the image, and the second direction can include the horizontal direction of the display panel, that is... Figure 3 The horizontal direction in the middle.

[0079] Figure 4a This schematically illustrates one of the plan views of the pixel circuitry in a pixel unit according to an embodiment of the present disclosure, such as... Figure 4a As shown, each pixel unit P includes multiple sub-pixels, and the colors of these sub-pixels are different. For example, each pixel unit P includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Alternatively, each pixel unit P may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Each sub-pixel may include a light-emitting device and the aforementioned pixel circuit D. The pixel circuit D is electrically connected to the light-emitting device, thereby providing a driving signal to the light-emitting device to cause it to emit light. For example, the red sub-pixel includes a first pixel circuit Dr, the white sub-pixel includes a second pixel circuit Dw, the blue sub-pixel includes a third pixel circuit Db, and the green sub-pixel includes a fourth pixel circuit Dg.

[0080] Optionally, the light-emitting device may include an organic light-emitting diode (OLED) or a micro LED, and the pixel circuit may provide a driving current to the organic light-emitting device or the micro LED so that the organic light-emitting device or the micro LED emits light.

[0081] In the non-display area NA, a gate drive circuit (GOA) and a data drive chip (IC) are provided. The gate drive circuit (GOA) and the data drive chip (IC) can be electrically connected to the pixel circuit through corresponding gate lines and data lines, thereby providing electrical signals such as scan signals and data voltage signals to the pixel circuit, so that the pixel circuit provides driving signals to the light-emitting device to drive the light-emitting device to emit light.

[0082] Figure 4b The schematic diagram illustrates the equivalent circuit diagram of the pixel circuit in an embodiment of this disclosure, in conjunction with... Figure 4a and Figure 4b As shown, at least one pixel circuit D includes a driving transistor T21 and a first switching transistor T22. In embodiments of this disclosure, the pixel circuit D may adopt a 3T1C structure. For example, the pixel circuit D may also include a second switching transistor T23 and a storage capacitor C2, which will be mentioned below. In other words, the pixel circuit D may be composed of three transistors and a storage capacitor.

[0083] In this embodiment, the display panel further includes a first gate line G1, a third gate line G3, a data line DL, a reference signal line V1, and a first power line V2. The gate of the first switching transistor T22 is electrically connected to the first gate line G1, the first terminal of the first switching transistor T22 is electrically connected to the data line DL, the second terminal of the first switching transistor T22 is electrically connected to the gate of the driving transistor T21, the first terminal of the driving transistor T21 is electrically connected to the first power line V2, the second terminal of the driving transistor T21 is electrically connected to the second plate of the storage capacitor C2, the second terminal of the second switching transistor T23, and the light-emitting device LED, the gate of the second switching transistor T23 is electrically connected to the third gate line G3, and the first terminal of the second switching transistor T23 is electrically connected to the reference signal line V1.

[0084] It should be noted that the transistors used in the embodiments of this disclosure (e.g., driving transistor T21 and first switching transistor T22) may include thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one of the terminals is called the first terminal, and the other is called the second terminal. Furthermore, according to the characteristics of the transistors, they can be divided into N-type and P-type. The following embodiments use an N-type transistor as an example. When an N-type transistor is used, the first terminal is the source of the N-type transistor, and the second terminal is the drain of the N-type transistor. When the gate input is high, the source and drain are turned on; the opposite is true for P-type transistors.

[0085] In the embodiments of this disclosure, an "active level signal" refers to a signal that, when input to the control electrode (i.e., the gate of the transistor), can control the transistor to turn on, and an "inactive level signal" refers to a signal that, when input to the control electrode of the transistor, can control the transistor to turn off. For N-type transistors, a high-level signal is an active level signal, and a low-level signal is an inactive level signal. For P-type transistors, a low-level signal is an active level signal, and a high-level signal is an inactive level signal. Since the embodiments of this disclosure are described using N-type transistors, the following embodiments will use a high-level signal as the active level signal and a low-level signal as the inactive level signal as an example.

[0086] Figure 4c The schematic diagram illustrates the driving timing diagram of the pixel circuit in an embodiment of this disclosure, in conjunction with... Figures 4a to 4c As shown, the operation of the pixel circuit includes at least a data writing stage t1 and a light emission stage t2.

[0087] During the data writing phase t1, valid level signals are provided to the first gate line G1 and the third gate line G3. The first switching transistor T22 and the second switching transistor T23 are turned on. The data line DL inputs a data signal to the gate Vg of the driving transistor T21 through the first switching transistor T22 and stores it in the storage capacitor C2. The reference signal line V1 inputs an initial signal to the second terminal of the driving transistor T21 through the second switching transistor T23.

[0088] During the light-emitting stage t2: the driving transistor T21 is turned on by the storage capacitor C2. The driving transistor T21 generates a driving current I based on its gate-source voltage. This driving current I flows to the LED to drive it to emit light. During this stage, due to the bootstrap effect of the storage capacitor C2, the gate voltage Vg of the driving transistor T21 also rises, thus stabilizing the gate-source voltage of the driving transistor T21. This allows the driving transistor T21 to continuously generate the driving current I to drive the LED to emit light.

[0089] Figure 5a This schematically illustrates a second plan view of the pixel circuitry in a pixel unit according to an embodiment of the present disclosure. Figure 5b This schematically illustrates the overlay diagram of the various film layers in the display panel in the thickness direction according to an embodiment of the present disclosure. Figure 6a A schematic plan view of the active layer in an embodiment of this disclosure is shown. Figure 6b A schematic plan view of the first conductive layer in an embodiment of this disclosure is shown, in conjunction with... Figures 4a to 6b As shown, the display panel further includes: an active layer 22 disposed on a substrate 21, and a first conductive layer 23 disposed on the side of the active layer 22 facing away from the substrate 21. The active layer 22 includes a first active portion A1 and a second active portion A2. The first active portion A1 forms the channel portion of the driving transistor T21, and the second active portion A2 forms the second electrode connection portion of the first switching transistor T22. The first conductive layer 23 includes a first conductive portion S1, a portion of which forms the gate of the driving transistor T21, and another portion of which is electrically connected to the second active portion A2. The second active portion A2 is also electrically connected to the second electrode of the first switching transistor T22, thereby achieving an electrical connection between the gate T21 of the driving transistor and the second electrode of the first switching transistor. Optionally, the first conductive portion S1 may partially overlap with the second active portion A2, resulting in a more compact structure. This will be described in detail below and will not be elaborated upon here.

[0090] In this embodiment, the channel length of the driving transistor T21 is greater than its channel width. As described above, during the light-emitting stage t2, the driving transistor T21 generates a driving current I, which is given by: I = W / 2L × μ × Cox × [(Vgs - Vth)]^2, where W is the channel width of the driving transistor T21, L is the channel length of the driving transistor T21, W / L is the width-to-length ratio of the channel of the driving transistor T21, μ is the mobility, Cox is the capacitance per unit area, Vgs is the gate-source voltage of the driving transistor T21, and Vth is the threshold voltage of the driving transistor T21. In this embodiment, the channel length L of the driving transistor T21 is greater than its channel width W. Compared to the previous example where the channel width W of the driving transistor T21 is greater than its channel length L, the width-to-length ratio W / L of the driving transistor T21 in this embodiment is smaller, resulting in a more subtle change in the driving current I with grayscale, and a better grayscale unfolding effect.

[0091] It should be noted that, in the embodiments of this disclosure, the channel length L can refer to the size of the channel portion of the transistor in the direction from the first pole to the second pole, and correspondingly, the channel width W can refer to the size of the channel portion of the transistor in the direction intersecting the direction of the channel length L.

[0092] The following is combined Figures 4a to 9 The specific structure of the display panel in the embodiments of this disclosure will be further described.

[0093] In some specific embodiments, the display panel further includes a second conductive layer 24 disposed on the side of the first conductive layer 23 facing away from the substrate 21.

[0094] In this embodiment, a first insulating layer 31 is disposed between the first conductive layer 23 and the active layer 22, insulatingly separating the first conductive layer 23 from the active layer 22. The first insulating layer 25 and the first conductive layer 23 can be fabricated using the same mask; in other words, the pattern of the first insulating layer 31 can be the same as the pattern of the first conductive layer 23. For example, a first insulating material layer and a first conductive material layer can be formed first on the side of the active layer 22 away from the substrate 21, and then a mask can be used to pattern the first insulating material layer and the first conductive material layer simultaneously to obtain a first insulating layer 31 and a first conductive layer 23 with the same pattern.

[0095] In this embodiment of the present disclosure, since the first insulating layer 31 and the first conductive layer 23 have the same pattern, no vias are generally provided on the first insulating layer 31. Therefore, in this embodiment of the present disclosure, the connection between the second active part A2 and the first conductive part S1 can be realized through the second conductive part S2.

[0096] Figure 6cA schematic plan view of the second conductive layer in an embodiment of this disclosure is shown, such as... Figure 6c As shown, specifically, the second conductive layer 24 includes a second conductive part S2, which is electrically connected to the second active part A2 and the first conductive part S1, thereby realizing the transfer between the second active part A2 and the first conductive part S1.

[0097] In this embodiment of the present disclosure, a second insulating layer 32 is provided between the first conductive layer 23 and the second conductive layer 24, and between the active layer 22 and the second conductive layer 24, the second insulating layer 32 insulatingly separating the first conductive layer 23, the second conductive layer 24 and the active layer 22.

[0098] Figure 6d A schematic plan view of some of the vias in an embodiment of this disclosure is shown, such as... Figure 6d As shown, a first via V1 penetrating the second insulating layer 32 is provided on the second insulating layer 32. The orthographic projection of the second active part A2 on the substrate 21 overlaps with the orthographic projection of the second conductive part S2 on the substrate 21, and they are electrically connected in the overlapping area through the first via V1. A second via V2 penetrating the second insulating layer 32 is also provided on the second insulating layer 32. The orthographic projection of the first conductive part S1 on the substrate 21 overlaps with the orthographic projection of the second conductive part S2 on the substrate 21, and they are electrically connected in the overlapping area through the second via V2. Optionally, the first via V1 and the second via V2 can be an integral structure.

[0099] Please continue to refer to Figure 5a In this embodiment of the present disclosure, the portions of the second conductive portion S2 electrically connected to the second active portion A2 and the portions of the second conductive portion S2 electrically connected to the first conductive portion S1 are arranged along a first direction. Optionally, the dimension Y of the second conductive portion S2 in the first direction is larger than the dimension X in the second direction. For example, the shape of the second conductive portion S2 can be approximately rectangular, wherein the corners of the rectangle can be right angles or arc corners, which can be determined according to actual needs and are not limited here.

[0100] In this embodiment of the present disclosure, the channel length L of the driving transistor T21 is greater than the dimension Y of the second conductive portion S2 in a first direction, wherein the first direction includes the direction from the first electrode of the driving transistor T21 to the second electrode. By making the channel length L of the driving transistor T21 greater than the dimension Y of the second conductive portion S2 in the first direction, the channel length L of the driving transistor T21 can be made larger, which is beneficial to reducing the aspect ratio of the driving transistor T21.

[0101] In some specific embodiments, the width-to-length ratio of the channel portion of the driving transistor T21 is greater than or equal to 3 / 10 and less than or equal to 25 / 12. This allows the width-to-length ratio of the driving transistor T21 to reach a relatively ideal range. For example, the channel width W of the driving transistor T21 can be set to 6µm to 25µm, including boundary values, and the channel length L of the channel portion of the driving transistor T21 can be set to 12µm or more. For example, such as... Figure 5a As shown, the channel length L of the driving transistor T21 can reach more than 20um, so that the channel of the driving transistor T21 is approximately a long and narrow structure, which can better improve the grayscale unfolding effect.

[0102] In some specific embodiments, the first conductive layer 23 further includes a first gate line G1, which is electrically connected to the gate of the first switching transistor T22. In embodiments of this disclosure, the first gate line G1 extends along a second direction, and the first gate line G1 and the gate of the first switching transistor T22 can be an integral structure.

[0103] Figure 7a A schematic plan view of the driving transistor and the second conductive portion in an embodiment of this disclosure is shown, such as Figure 7a As shown, the first conductive portion S1 includes a first side D1 and a second side D2 arranged along a first direction, and the second conductive portion S2 includes a third side D3 and a fourth side D4 arranged along the first direction. The orthographic projection of the line containing the first side D1 onto the substrate 21 is located on the side where the orthographic projection of the third side D3 onto the substrate 21 is away from the orthographic projection of the fourth side D4 onto the substrate 21. The orthographic projection of the line containing the second side D2 onto the substrate 21 is located on the side where the orthographic projection of the third side D3 onto the substrate 21 faces the orthographic projection of the fourth side D4 onto the substrate 21.

[0104] like Figure 7a As shown, the first side D1 is located above the third side D3. The distance between the first side D1 and the third side D3 can be determined according to actual needs. For example, the pixel circuit D also includes the storage capacitor C2, which will be mentioned below. Figures 5a to 7a As shown, the area above the first side D1 is used to house the storage capacitor C2. The size of this area affects the effective area of ​​the storage capacitor C2, and thus the capacitance of the storage capacitor C2. Therefore, the distance between the first side D1 and the third side D3 should not be too large to avoid affecting the effective area of ​​the storage capacitor C2. It should be noted that the distance between the first side D1 and the third side D3 can refer to the perpendicular distance between them, and the effective area of ​​the storage capacitor C2 can refer to the overlapping area between the two plates of the storage capacitor C2.

[0105] In some specific embodiments, the orthographic projection of the line containing the second side D2 onto the substrate 21 is located on the side where the orthographic projection of the fourth side D4 onto the substrate 21 is opposite to the orthographic projection of the third side D3 onto the substrate 21.

[0106] like Figure 7a As shown, the second side D2 is located below the fourth side D4. The distance between the second side D1 and the fourth side D4 can be determined according to actual needs, for example, by combining... Figure 5a and Figure 7a As shown, the area below the second side D1 is used to set the first gate line G1. The orthographic projection of the fifth active part A5 on the substrate 21 is located between the orthographic projection of the first gate line G1 on the substrate 21 and the orthographic projection of the first conductive part S1 on the substrate 21. Therefore, the distance between the second side D1 and the fourth side D4 should not be too large to avoid affecting the setting of the fifth active part A5 and the first gate line G1. It should be noted that the distance between the first side D1 and the third side D3 can refer to the vertical distance between them.

[0107] In some specific embodiments, at least one pixel circuit D further includes a storage capacitor C2, and the second conductive layer 24 further includes a third conductive portion S3 for forming the storage capacitor C2. Figure 7b A schematic plan view of the driving transistor and the third conductive portion in an embodiment of this disclosure is shown, such as... Figure 7b As shown, the third conductive portion S3 includes a fifth side D5 and a sixth side D6 arranged along the first direction. The orthographic projection of the fifth side D5 onto the substrate 21 is located on the side where the orthographic projection of the sixth side D6 onto the substrate 21 is away from the orthographic projection of the second side D2 onto the substrate 21, and the orthographic projection of the sixth side D6 onto the substrate 21 is located on the side where the orthographic projection of the first side D1 onto the substrate 21 faces the orthographic projection of the second side D2 onto the substrate 21.

[0108] Figure 8 This schematically illustrates a third plan view of the pixel circuitry in a pixel unit according to an embodiment of this disclosure, in conjunction with... Figures 5a to 8 As shown, in some specific embodiments, the first conductive layer 23 further includes a fifth conductive portion S5, and the second conductive layer 24 further includes a fourth conductive portion S4, a sixth conductive portion S6, and a seventh conductive portion S7. The fifth conductive portion S5 is used to form the gate of the first switching transistor T22, the fourth conductive portion S4 is used to form the first electrode of the first switching transistor T22, the sixth conductive portion S6 is used to form the first electrode of the driving transistor T21, and the seventh conductive portion S7 is used to form the second electrode of the driving transistor T21.

[0109] In some specific embodiments, the active layer 22 further includes a third active portion A3, a fourth active portion A4, a fifth active portion A5, and a sixth active portion A6. The third active portion A3 is used to form the first terminal connection portion of the first switching transistor T21, the fourth active portion A4 is used to form the channel portion of the first switching transistor T21, the fifth active portion A5 is used to form the first terminal connection portion of the driving transistor T22, and the sixth active portion A6 is used to form the second terminal connection portion of the driving transistor T22.

[0110] The first active portion A1 is located between the fifth active portion A5 and the sixth active portion A6, and is directly opposite to the portion of the first conductive portion S1 used to form the gate of the driving transistor T21. The orthographic projection of the third active portion A3 on the substrate 21 partially overlaps with the orthographic projection of the fourth conductive portion S4 on the substrate 21, and is electrically connected in the overlapping area through a third via V3 penetrating the second insulating layer 32. The fourth active portion A4 is located between the second active portion A2 and the third active portion A3, and is directly opposite to the fifth conductive portion S5. The orthographic projection of the fifth active portion A5 on the substrate 21 at least partially overlaps with the orthographic projection of the sixth conductive portion S6 on the substrate 21, and is electrically connected in the overlapping area through a fourth via V4 penetrating the second insulating layer 32. The orthographic projection of the sixth active portion A6 on the substrate 21 at least partially overlaps with the orthographic projection of the seventh conductive portion S7 on the substrate 21, and is electrically connected in the overlapping area through a fifth via V5 penetrating the second insulating layer 32.

[0111] In some specific embodiments, the third conductive portion S3 is used to form the first electrode of the storage capacitor C2. Optionally, the active layer 22 further includes a seventh active portion A7, the orthographic projection of the seventh active portion A7 on the substrate 21 overlapping with the orthographic projection of the third conductive portion S3 on the substrate 21. The seventh active portion A7 is used to form the second electrode of the storage capacitor C2.

[0112] Figure 9 A schematic plan view of the third conductive layer in an embodiment of this disclosure is shown, such as Figure 9 As shown, optionally, the display panel further includes a third conductive layer 26 located on the side of the active layer 22 near the substrate 21, the third conductive layer 26 including an eighth conductive portion S8. Combined with... Figures 5a to 9As shown, the orthographic projections of the seventh active portion A7, the third conductive portion S3, and the eighth conductive portion S8 on the substrate 21 partially overlap. The third conductive portion S3 and the eighth conductive portion S8 are electrically connected, and together they form the first electrode of the storage capacitor C2. The first electrode and the second electrode of the storage capacitor C2 are insulated from each other, thereby forming a storage capacitor C2 with a dual-capacitor structure. For example, the second conductive layer 24 also includes an eleventh conductive portion S11, which will be mentioned below. The eleventh conductive portion S11 and the third conductive portion S3 are integrally structured. The orthographic projection of the eighth conductive portion S8 on the substrate 21 partially overlaps with the eleventh conductive portion S11, and they are electrically connected in the overlapping area through a seventh via V7, thereby realizing the electrical connection between the eighth conductive portion S8 and the third conductive portion S3.

[0113] Optionally, a third insulating layer 33 is provided between the third conductive layer 26 and the active layer 22, and the third insulating layer 33 insulates and separates the third conductive layer 26 and the active layer 22.

[0114] In some specific embodiments, the second conductive layer 24 further includes a data line DL and a fourth conductive portion S4, wherein the data line DL extends along a first direction. The fourth conductive portion S4 is used to form the first electrode of the first switching transistor T22, and the orthographic projection of the fourth conductive portion S4 on the substrate 21 overlaps with the orthographic projection of the data line DL on the substrate 21. In embodiments of this disclosure, the details of the fourth conductive portion S4 can be found in the preceding embodiments, and therefore will not be repeated here.

[0115] In some specific embodiments, the first conductive layer 23 further includes a second gate line G2, and the first gate line G1 and the second gate line G2 are electrically connected. The orthographic projection of the first gate line G1 on the substrate 21 is located on the side of the orthographic projection of the second gate line G2 on the substrate 21 that is close to the orthographic projection of the first conductive portion S1 on the substrate 21. The orthographic projection of the fourth conductive portion S4 on the substrate 21 is located between the orthographic projections of the first gate line G1 and the second gate line G2 on the substrate 21.

[0116] In this embodiment, both the first gate line G1 and the second gate line G2 extend along a second direction, and the first gate line G1 and the second gate line G2 can be electrically connected through a first connecting line Q1 extending along a first direction. Optionally, the first gate line G1, the second gate line G2, and the first connecting line Q1 can be arranged in the same layer, that is, the first gate line G1, the second gate line G2, and the first connecting line Q1 can be formed through the same patterning process. Using the above method allows the first gate line G1 and the second gate line G2 to be connected in parallel, thereby reducing the resistance on the first gate line G1 and improving transmission efficiency.

[0117] In some specific embodiments, the width of either the first gate line G1 or the second gate line G2 is smaller than the channel length of the driving transistor T21. Since the first gate line G1 and the second gate line G2 are set to be relatively wide to ensure low resistance, when the channel length of the driving transistor T21 is greater than the width of either the first gate line G1 or the second gate line G2, the driving transistor T21 can also have a smaller aspect ratio, thereby improving the grayscale unfolding effect.

[0118] In some specific embodiments, the display panel further includes a plurality of pixel units P, and at least one pixel unit P includes a plurality of pixel circuits D. In the at least one pixel unit P, the first terminals of the driving transistors T21 of the plurality of pixel circuits D are electrically connected to each other, thereby saving the number of first power lines V2, which is beneficial for increasing pixel density.

[0119] Optionally, the third conductive layer 26 includes a second connection line Q2, in which the first poles of the driving transistors T21 of multiple pixel circuits D are electrically connected through the second connection line Q2 in a pixel unit P.

[0120] Optionally, the first conductive layer 23 further includes a third connecting line Q3. The second connecting line Q2 extends along a second direction, and the third connecting line Q3 extends along a first direction. In a pixel unit P, the first electrode of the driving transistor T21 of one of the pixel circuits D is formed integrally with the first power line V2. The first power line V2 is electrically connected to the second connecting line Q2. For example, the orthographic projection of the first power line V2 on the substrate 21 overlaps with the orthographic projection of the second connecting line Q2 on the substrate 21, and they are electrically connected through vias in the overlapping area. In the pixel unit P, the first electrodes of the driving transistors T21 of other pixel circuits D are electrically connected to the second connecting line Q2 through the third connecting line Q3, thereby realizing that the first electrodes of the driving transistors T21 of multiple pixel circuits D in a pixel unit P are electrically connected to each other. The orthographic projection of the third connecting line Q3 on the substrate 21 overlaps with the orthographic projection of the second connecting line Q2 on the substrate 21, and they are electrically connected through vias in the overlapping area.

[0121] In some specific embodiments, at least one pixel circuit D further includes a second switching transistor T23.

[0122] In some specific embodiments, the channel width-to-length ratio of either the first switching transistor T22 or the second switching transistor T23 is greater than the channel width-to-length ratio of the driving transistor T21.

[0123] In this embodiment of the disclosure, since the first switching transistor T22 and the second switching transistor only need to function as switches, having a larger aspect ratio relative to the driving transistor T21 is beneficial for reducing power consumption.

[0124] In at least one pixel unit P, the first poles of the second switching transistors T23 of multiple pixel circuits D are electrically connected to each other.

[0125] In this embodiment, the active layer 22 further includes an eighth active portion A8, a ninth active portion A9, and a tenth active portion A10. The first conductive layer 23 further includes a ninth conductive portion S9, and the second conductive layer 24 further includes a tenth conductive portion S10 and an eleventh conductive portion S11. The eighth active portion A8 forms the channel portion of the second switching transistor, the ninth active portion A9 forms the first electrode connection portion of the second switching transistor, and the tenth active portion A10 forms the second electrode connection portion of the second switching transistor. The ninth conductive portion S9 forms the gate of the second switching transistor T23, the tenth conductive portion S10 forms the first electrode of the second switching transistor T23, and the eleventh conductive portion S11 forms the second electrode of the second switching transistor T23.

[0126] The ninth active portion A9 and the tenth active portion A10 are arranged along a first direction, and the eighth active portion A8 is located between the ninth active portion A9 and the tenth active portion A10, and is directly opposite the ninth conductive portion S9. The orthographic projection of the ninth active portion A9 on the substrate 21 overlaps with the orthographic projection of the tenth conductive portion S10 on the substrate 21, and is electrically connected in the overlapping area through a sixth via V6. The tenth active portion A10 partially overlaps with the eleventh conductive portion S11, and is electrically connected in the overlapping area through a seventh via V7.

[0127] In this embodiment, the orthographic projection of the eleventh conductive part S11 on the substrate 21 overlaps with the orthographic projection of the eighth conductive part A8 on the substrate 21, and they are electrically connected in the overlapping area through the seventh via V7, thereby realizing the electrical connection between the second electrode of the second switching transistor T23 and the second plate of the storage capacitor C2.

[0128] In some specific embodiments, the second conductive layer 23 further includes a fourth connection line Q4, and the third conductive layer 26 further includes a fifth connection line Q5. In a pixel unit P, the first terminals of the second switching transistors T23 of at least two pixel circuits D are electrically connected through the fourth connection line Q4, and the first terminals of the second switching transistors T23 of at least two pixel circuits D are electrically connected through the fifth connection line Q5.

[0129] For example, in Figure 5aIn this design, a pixel unit P includes a red sub-pixel Pr, a white sub-pixel Pw, a blue sub-pixel Pb, and a green sub-pixel Pg arranged from left to right, along a second direction. The first terminals of the driving transistors T21 for the red and white sub-pixels Pr and Pw are electrically connected via a fifth connection line Q5. The first terminals of the driving transistors T21 for the blue and green sub-pixels Pb and Pg are also electrically connected via a fifth connection line Q5. The first terminals of the driving transistors T21 for the white and blue sub-pixels Pw are electrically connected via a fourth connection line Q4.

[0130] The display panel using the above method can provide a first power line V2 and a reference signal line V1 for each pixel unit P, thereby reducing the number of first power lines V2 and reference signal lines V1, which is beneficial to improving pixel density.

[0131] In some specific embodiments, in a pixel unit P, different sub-pixels have different colors, and the luminous efficiency of the light-emitting devices in different colored sub-pixels is also different. In order to adapt to the luminous efficiency of each color, the width-to-length ratio of the channel portion of the driving transistor T2 of multiple pixel circuits can be different. Since the width-to-length ratio of the channel portion of the driving transistor T2 is related to the driving current I, by configuring the corresponding width-to-length ratio for different sub-pixels, the required driving current I can be provided for different light-emitting devices, thereby adapting to the luminous efficiency of each light-emitting device.

[0132] For example, combining Figure 4a and Figure 5a As shown, in some specific embodiments, at least one pixel unit P contains multiple pixel circuits D, including a first pixel circuit Dr, a second pixel circuit Dw, a third pixel circuit Db, and a fourth pixel circuit Dg. The first pixel circuit Dr, the second pixel circuit Dw, the third pixel circuit Db, and the fourth pixel circuit Dg are electrically connected to light-emitting devices of different colors, and the second pixel circuit Dw is electrically connected to a white light-emitting device. The aspect ratio of the driving transistor T21 in any of the first pixel circuits Dr, the third pixel circuit Db, and the fourth pixel circuit Dg is greater than that of the driving transistor in the second pixel circuit Dw. In other words, among the first pixel circuits Dr, the second pixel circuit Dw, the third pixel circuit Db, and the fourth pixel circuit Dg, the driving transistor in the second pixel circuit Dw has the smallest aspect ratio.

[0133] In this way, the width-to-length ratio of the channel portion of the driving transistor T21 in the second pixel circuit Dw can be minimized while ensuring that the second pixel circuit Dw provides the required driving current I for the white light-emitting device.

[0134] For example, combining Figure 4aand Figure 5a , in some specific embodiments, multiple pixel circuits D in at least one pixel unit P include a first pixel circuit Dr, a second pixel circuit Dw, a third pixel circuit Db, and a fourth pixel circuit Dg. Among them, the first pixel circuit Dr, the second pixel circuit Dw, the third pixel circuit Db, and the fourth pixel circuit Dg are electrically connected to light-emitting devices of different colors respectively, and the first pixel circuit Dr is electrically connected to a red light-emitting device. The width-to-length ratio of the driving transistor T21 in any one of the second pixel circuit Dw, the third pixel circuit Db, and the fourth pixel circuit Dg is smaller than the width-to-length ratio of the driving transistor T21 in the first pixel circuit Dr. In other words, among the first pixel circuit Dr, the second pixel circuit Dw, the third pixel circuit Db, and the fourth pixel circuit Dg, the width-to-length ratio of the driving transistor T21 in the first pixel circuit Dr is the largest.

[0135] In this way, on the basis of minimizing the width-to-length ratio of the channel portion of the driving transistor T21 in each pixel circuit D, the first pixel circuit Dr can still provide the required driving current I for the red light-emitting device.

[0136] Optionally, the third pixel circuit Db is electrically connected to a blue light-emitting device, and the fourth pixel circuit Dg is electrically connected to a green light-emitting device. Among the first pixel circuit Dr, the fourth pixel circuit Dg, the third pixel circuit Db, and the second pixel circuit Dw, the width-to-length ratio of the channel portion of the driving transistor T21 can decrease in sequence.

[0137] , in some specific embodiments, multiple pixel circuits D in at least one pixel unit P include a first pixel circuit Dr, a second pixel circuit Dw, and a third pixel circuit Db. Among them, the first pixel circuit Dr, the second pixel circuit Dw, and the third pixel circuit Db are electrically connected to light-emitting devices of different colors respectively, and the first pixel circuit Dr is electrically connected to a red light-emitting device. The sum of the channel areas of the driving transistor T21 in the second pixel circuit Dw and the driving transistor T21 in the third pixel circuit Db is smaller than the channel area of the driving transistor T21 in the first pixel circuit Dr.

[0138] In this way, on the basis of minimizing the width-to-length ratio of the channel portion of the driving transistor T21 in each pixel circuit D, the first pixel circuit Dr can still provide the required driving current I for the red light-emitting device.

[0139] , in some specific embodiments, at least one group of adjacent pixel circuits D satisfies the following condition: X < Y. Where X represents the difference in the channel lengths of the channel portions of the driving transistors T21 in adjacent pixel circuits D; Y represents the difference in the channel widths of the channel portions of the driving transistors T21 in adjacent pixel circuits D.

[0140] In this embodiment of the disclosure, an adjacent set of pixel circuits D can refer to two adjacent pixel circuits D, or multiple adjacent pixel circuits D. Adjacent pixel circuits D can mean that there are no other pixel circuits between two pixel circuits. Optionally, adjacent pixel circuits D can be adjacent in a second direction, depending on actual needs, and are not limited here.

[0141] In this embodiment, a number of devices, such as the seventh active part A7, are distributed along the channel length of the driving transistor T21. Therefore, in this embodiment, when it is necessary to make the driving transistor T21 in different pixel circuits D have different width-to-length ratios, the channel width of the driving transistor T21 can be adjusted by a larger margin, while the channel length of the driving transistor T21 can be adjusted by a smaller margin. This prevents the influence of the width-to-length ratio of the driving transistor T21 on other devices to a greater extent, while also allowing the driving transistor T21 to have a better width-to-length ratio adjustment range.

[0142] In some specific embodiments, the channel length L of the driving transistors T21 of multiple pixel circuits D is the same, thereby simplifying the fabrication process. Optionally, in the embodiments of this disclosure, the width-to-length ratio of the channel of the driving transistor T21 can be adjusted by adjusting the channel width W of the driving transistor T21.

[0143] In some specific embodiments, the channel length L of the driving transistor T21 of at least two pixel circuits D is different. In this way, the corresponding channel length L can be set for the driving transistor T21 of each pixel circuit D according to the actual situation of each pixel circuit D.

[0144] In some specific embodiments, the display panel further includes a gate drive circuit GOA. In this GOA, at least a portion of the transistors have a channel length L less than or equal to a channel width W.

[0145] In this embodiment, the channel length L of the transistor in the gate drive circuit GOA can be set to 4.5µm to 8µm, including the boundary value, and the channel width W of the transistor in the gate drive circuit GOA can be set to 6 to 25µm, including the boundary value. This results in a smaller size of the transistor in the second direction, which is beneficial for achieving a narrow bezel.

[0146] In some specific embodiments, the orthographic projection of the portion where the first conductive part S1 and the second active part A2 are electrically connected on the substrate 21 overlaps with the orthographic projection of the second active part A2 on the substrate 21. This allows for a more compact structure of the pixel circuit D, increases the adjustability of the channel portion of the driving transistor T21, and enables the channel length L and channel width W of the driving transistor T21 to be adjusted within a wider range, thus improving design flexibility.

[0147] This disclosure also provides a display device including the display panel described above.

[0148] In other embodiments of this disclosure, the display device may include a tablet PC, a smartphone, a personal digital assistant (PDA), a portable multimedia player, a game console, or a wristwatch-style electronic device, etc. However, the embodiments of this disclosure are not intended to limit the type of display device. In some exemplary embodiments, the display device can be used not only in large electronic devices such as televisions (TVs) or billboards, but also in medium or small electronic devices such as PCs, laptop computers, car navigation systems, or cameras.

[0149] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display panel, wherein, include: Substrate; A plurality of pixel circuits disposed on the substrate, at least one of the pixel circuits including a driving transistor and a first switching transistor; The display panel also includes: An active layer disposed on the substrate includes a first active portion and a second active portion; the first active portion forms the channel portion of the driving transistor, and the second active portion forms the second electrode connection portion of the first switching transistor; and... A first conductive layer is disposed on the side of the active layer away from the substrate. Wherein, the first conductive layer includes a first conductive portion, a portion of which is used to form the gate of the driving transistor, and another portion of which is electrically connected to the second active portion; and, The channel length of the driving transistor is greater than the channel width. The display panel further includes: a second conductive layer disposed on the side of the first conductive layer opposite to the substrate; The second conductive layer includes a second conductive portion, which is electrically connected to the second active portion and the first conductive portion. The size of the second conductive portion in a first direction is smaller than the channel length of the channel portion of the driving transistor. The first direction includes the direction from the first electrode of the driving transistor to the second electrode.

2. The display panel according to claim 1, wherein, The first conductive layer further includes a first gate line, which is electrically connected to the gate of the first switching transistor; The first conductive portion includes a first side and a second side arranged along the first direction, and the second conductive portion includes a third side and a fourth side arranged along the first direction. Wherein, the orthographic projection of the straight line containing the first side on the substrate is located on the side where the orthographic projection of the third side on the substrate is away from the orthographic projection of the fourth side on the substrate, and the orthographic projection of the straight line containing the second side on the substrate is located on the side where the orthographic projection of the third side on the substrate is toward the orthographic projection of the fourth side on the substrate.

3. The display panel according to claim 2, wherein, The orthographic projection of the straight line containing the second side onto the substrate is located on the side where the orthographic projection of the fourth side onto the substrate is opposite to the orthographic projection of the third side onto the substrate.

4. The display panel according to claim 2, wherein, At least one pixel circuit further includes a storage capacitor, and the second conductive layer further includes a third conductive portion for forming the storage capacitor, the third conductive portion including a fifth side and a sixth side arranged along the first direction; Wherein, the orthographic projection of the fifth side on the substrate is located on the side where the orthographic projection of the sixth side on the substrate is away from the orthographic projection of the second side on the substrate, and the orthographic projection of the sixth side on the substrate is located on the side where the orthographic projection of the first side on the substrate faces the orthographic projection of the second side on the substrate.

5. The display panel according to claim 1, wherein, The second conductive layer also includes data lines and a fourth conductive portion; The fourth conductive portion is used to form the first electrode of the first switching transistor, and the orthographic projection of the fourth conductive portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

6. The display panel according to claim 5, wherein, The first conductive layer further includes a first gate line and a second gate line, wherein the first gate line is electrically connected to the gate of the first switching transistor and the second gate line; The orthographic projection of the first gate line on the substrate is located on the side of the orthographic projection of the second gate line on the substrate that is close to the orthographic projection of the driving transistor on the substrate; The active layer further includes a third active portion, which is used to form the first electrode connection portion of the first switching transistor. The orthographic projection of the third active portion on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate.

7. The display panel according to claim 1, wherein, The display panel further includes a plurality of pixel units, and at least one of the pixel units includes a plurality of the pixel circuits; In at least one pixel unit, the first poles of the driving transistors of the plurality of pixel circuits are electrically connected to each other.

8. The display panel according to claim 7, wherein, At least one pixel circuit also includes a second switching transistor; In at least one pixel unit, the first poles of the second switching transistors of the plurality of pixel circuits are electrically connected to each other.

9. The display panel according to claim 1, wherein, At least one group of adjacent pixel circuits satisfies the following condition: X <Y; Wherein, X represents the difference in channel length of the driving transistor in adjacent pixel circuits; and Y represents the difference in channel width of the driving transistor in adjacent pixel circuits.

10. The display panel according to claim 1, wherein, The multiple pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit; The first pixel circuit, the second pixel circuit, and the third pixel circuit are electrically connected to light-emitting devices of different colors, and the first pixel circuit is electrically connected to a red light-emitting device. The sum of the channel area of ​​the driving transistor in the second pixel circuit and the channel area of ​​the driving transistor in the third pixel circuit is less than the channel area of ​​the driving transistor in the first pixel circuit.

11. The display panel according to claim 1, wherein, The multiple pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, wherein the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to light-emitting devices of different colors, and the second pixel circuit is electrically connected to a white light-emitting device. The aspect ratio of the channel portion of the driving transistor in any of the first pixel circuit, the third pixel circuit, and the fourth pixel circuit is greater than the aspect ratio of the channel portion of the driving transistor in the second pixel circuit.

12. The display panel according to claim 1, wherein, The multiple pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, wherein the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to light-emitting devices of different colors, and the first pixel circuit is electrically connected to a red light-emitting device. The aspect ratio of the driving transistor in any of the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is smaller than that of the driving transistor in the first pixel circuit.

13. The display panel according to any one of claims 1 to 12, wherein, The driving transistors of the plurality of pixel circuits have the same channel length.

14. The display panel according to any one of claims 1 to 12, wherein, At least two of the pixel circuits have different channel lengths for their driving transistors.

15. The display panel according to any one of claims 1 to 12, wherein, The width-to-length ratio of the channel portion of the driving transistor is greater than or equal to 1 / 5 and less than or equal to 25 / 12.

16. The display panel according to any one of claims 1 to 12, wherein, The display panel also includes a gate driving circuit; In the gate drive circuit, at least some of the transistors have a channel length less than or equal to their channel width.

17. The display panel according to any one of claims 1 to 12, wherein, The portion of the first conductive part that is electrically connected to the second active part is disposed with its orthographic projection on the substrate overlapping the orthographic projection of the second active part on the substrate.

18. The display panel according to any one of claims 1 to 12, wherein, The first conductive layer further includes a first gate line and a second gate line, wherein the first gate line is electrically connected to the gate of the first switching transistor and the second gate line; the width of either the first gate line or the second gate line is smaller than the channel length of the driving transistor.

19. The display panel according to any one of claims 1 to 12, wherein, At least one pixel circuit further includes a second switching transistor, wherein the channel width-to-length ratio of either the first switching transistor or the second switching transistor is greater than the channel width-to-length ratio of the driving transistor.

20. A display device, wherein, Includes the display panel as described in any one of claims 1 to 19.

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