Memory controller and method of calibration data reception window

Abstract

A method for calibrating a data receiving window includes: (A) setting a level of a reference voltage at different predetermined values and sampling a data signal to obtain first valid data receiving windows corresponding to the predetermined values respectively; (B) establishing a first eye diagram according to the first valid data receiving windows corresponding to the predetermined values; (C) resetting the level of the reference voltage at the predetermined values in combination with a first offset and sampling the data signal to obtain second valid data receiving windows corresponding to the predetermined values respectively; (D) selectively updating the first eye diagram according to the second valid data receiving windows corresponding to the predetermined values. When a width of the second valid data receiving window corresponding to the predetermined value is greater than a width of the first valid data receiving window, the second valid data receiving window replaces the first valid data receiving window in the first eye diagram.

Description

Technical Field

[0001] This invention relates to a method and related apparatus for calibrating a data receiving window. Background Technology

[0002] During memory access operations (e.g., memory read and write procedures), control signals (e.g., clock pulse signal CLK, address signal ADDR, and command signal CMD) may be transferred from the memory controller (e.g., the central processing unit CPU) to the memory, such as dynamic random access memory (DRAM). The clock pulse signal CLK can serve as the system reference clock pulse (e.g., the data trigger signal DQS, address signal ADDR, and command signal CMD should be aligned with the system reference clock pulse). The command signal CMD can be configured to a first value to initiate a read operation and a second value to initiate a write operation. The address signal ADDR indicates the address from which data is read during a read operation (e.g., a selected memory address in DRAM) and the address to which data is written during a write operation.

[0003] Generally, memory access operations are not synchronized with system control signals (such as clock pulse signal CLK, address signal ADDR, and command signal CMD). Therefore, the input / output data DQ received from dynamic random access memory (DRAM) will not be phase-aligned with any known clock pulse signal in the memory controller. In view of this, during memory access operations, it is necessary to provide the data trigger signal DQS from DRAM along with the data DQ to the memory controller so that a proper timing relationship can be established between the data trigger signal DQS and the data DQ, thereby ensuring successful reception of data DQ from DRAM.

[0004] To establish an appropriate timing relationship between the data trigger signal DQS and the data DQ, the data trigger signal DQS is delayed to sample the data DQ, thus obtaining an effective data reception window. Traditionally, the center of the falling / rising edge of the clock pulse of the data trigger signal DQS is used to sample the data DQ. If the data DQ is not successfully sampled at the center time point, the system provides another delay time to the data trigger signal DQS to sample the data DQ until it is successfully received. The system calculates the effective data reception window based on the successful sampling of the data DQ by the data trigger signal DQS with different delay times.

[0005] However, as data transfer rates increase, the voltage level of the data DQ received by the memory controller from the dynamic random access memory may vary between different bits due to channel interference or other factors, which could significantly reduce the size or range of the effective data reception window.

[0006] To address the aforementioned issues, a method and related apparatus for calibrating the data receiving window are needed to effectively increase the effective data receiving window at the receiver and enhance its tolerance to voltage fluctuations. Summary of the Invention

[0007] The purpose of this invention is to provide a method and related apparatus for calibrating a data receiving window that can effectively increase the effective data receiving window and enhance its tolerance to voltage jitter, so as to solve the problem that the size of the effective data receiving window is greatly reduced as the data transmission rate increases.

[0008] According to one embodiment of the present invention, a memory controller, coupled to a memory device, is used to control access operations of the memory device. The memory controller receives data signals from the memory device through multiple receive pads, and includes a sampling circuit and a calibration circuit. The sampling circuit samples the data signals according to a reference voltage. The calibration circuit performs the following operations: (A) setting the level of the reference voltage to multiple different predetermined values, and controlling the sampling circuit to repeatedly sample the data signals according to the reference voltage to obtain first valid data receiving windows corresponding to the predetermined values; (B) establishing a first eye diagram based on the first valid data receiving windows corresponding to the predetermined values; (C) resetting the level of the reference voltage with a predetermined value combined with a first offset, and controlling the sampling circuit to repeatedly sample the data signals according to the reference voltage to obtain second valid data receiving windows corresponding to the predetermined values; (D) selectively updating the first eye diagram based on the second valid data receiving windows corresponding to the predetermined values, wherein when the width of the second valid data receiving window corresponding to the predetermined value is greater than the width of the first valid data receiving window corresponding to the predetermined value, the second valid data receiving window corresponding to the predetermined value replaces the first valid data receiving window corresponding to the predetermined value in the first eye diagram.

[0009] According to another embodiment of the present invention, a method for calibrating a data receiving window includes the following steps: (A) setting the level of a reference voltage with a plurality of different predetermined values, and repeatedly sampling data signals received from a memory device according to the reference voltage to obtain a first effective data receiving window corresponding to each predetermined value; (B) establishing a first eye diagram according to the first effective data receiving window corresponding to the predetermined value; (C) resetting the level of the reference voltage with a predetermined value combined with a first offset, and repeatedly sampling data signals according to the reference voltage to obtain a second effective data receiving window corresponding to each predetermined value; (D) selectively updating the first eye diagram according to the second effective data receiving window corresponding to the predetermined value, wherein when the width of the second effective data receiving window corresponding to the predetermined value is greater than the width of the first effective data receiving window corresponding to the predetermined value, the second effective data receiving window corresponding to the predetermined value replaces the first effective data receiving window corresponding to the predetermined value in the first eye diagram.

[0010] According to another embodiment of the present invention, a method for calibrating a data receiving window includes the following steps: (A) setting the level of a reference voltage with a plurality of different predetermined values, and repeatedly sampling data signals received from a memory device according to the reference voltage to obtain a first effective data receiving window corresponding to each predetermined value; (B) establishing a first eye diagram according to the first effective data receiving window corresponding to the predetermined value; and (C) generating a second eye diagram according to a tolerance height and the first eye diagram, wherein in the second eye diagram, each predetermined value has a corresponding second effective data receiving window, and the second effective data receiving window corresponding to each predetermined value in the second eye diagram is less than or equal to the first effective data receiving window corresponding to the predetermined value in the first eye diagram. Attached Figure Description

[0011] Figure 1 This is a schematic diagram showing a dynamic random access memory system.

[0012] Figure 2 This is a flowchart illustrating a method for calibrating a data receiving window according to a first embodiment of the present invention.

[0013] Figure 3 This is an example of an eye diagram obtained by combining multiple predetermined values ​​with different offsets.

[0014] Figure 4 This is a flowchart illustrating a method for calibrating a data receiving window according to a second embodiment of the present invention.

[0015] Figures 5A-5C It shows the process of generating a second eye diagram based on the set tolerance height and the first eye diagram corresponding to a bit.

[0016] Figure 6This is a flowchart illustrating a method for calibrating a data receiving window according to a third embodiment of the present invention.

[0017] Figure 7 This is an example of an eye diagram that shows a bit after applying two or more different offsets.

[0018] Figure 8 This is an example of an eye diagram showing multiple bits after applying at least three different offsets. Detailed Implementation

[0019] Figure 1 This is a schematic diagram showing a dynamic random access memory (DRAM) system 10. The DRAM system 10 can be applied to personal computers, laptops, etc. The DRAM system 10 includes a DRAM 10A and a memory controller 10B. The DRAM 10A is a memory device. The memory controller 10B controls the access operations of the DRAM 10A. During a read operation, the memory controller 10B can receive data DQ and a data trigger signal DQS from the DRAM 10A. To increase the effective data reception window at the receiving end and further enhance the voltage jitter tolerance of the effective data reception window to the received data DQ, this invention proposes a method and corresponding hardware for calibrating the data reception window.

[0020] According to one embodiment of the present invention, the memory controller 10B may include a receive pad module 111, which includes a plurality of receive pads, such as receive pads P1 to PN, where N is a positive integer. The memory controller 10B receives data DQ from the dynamic random access memory 10A through the receive pads P1 to PN, wherein the data DQ may be a data signal (hereinafter referred to as data signal DQ) including a plurality of bits, for example, the data signal DQ may include bits DQ1 to DQN, and one of the receive pads P1 to PN may be used to receive one bit of the data signal. In addition, the receive pad module 111 may also include a receive pad VP for receiving a reference voltage Vref. In one embodiment of the present invention, the receive pads P1 to PN may share the reference voltage Vref, that is, the memory controller 10B receives the reference voltage Vref only through the receive pad VP, and this reference voltage Vref is the voltage commonly used when providing sampling bits DQ1 to DQN.

[0021] The memory controller 10B may also include a processing unit 112, a storage unit 113, a calibration circuit 114, a sampling circuit 115, and a voltage adjustment circuit 116. The processing unit 112 may be a microprocessor or an application-specific integrated circuit (ASIC). The storage unit 113 may be any data storage device used to store program code and other data required to control the operation of the dynamic random access memory system 10. The processing unit 112 can read and execute the program code within the storage unit 113. For example, the storage unit 113 may be a subscriber identity module (SIM), read-only memory (ROM), random-access memory (RAM), optical disc read-only memory (CD-ROMs), magnetic tapes, floppy disks, optical data storage devices, etc., and is not limited thereto.

[0022] The sampling circuit 115 is used to sample the data signal DQ based on the reference voltage Vref and the data trigger signal DQS. More specifically, the data trigger signal DQS is used to trigger the sampling circuit 115 to sample each bit DQ1 to DQN in the data signal, and the data trigger signal DQS is delayed according to different delay amounts to obtain the effective data reception window corresponding to each bit. The sampling circuit 115 can repeatedly perform data sampling at different sampling points (or different phases) according to different delays to calculate the effective data reception window, wherein the effective data reception window defines the time interval (or sampling point or phase range) under the predetermined reference voltage Vref that allows the sampling circuit 115 to successfully sample data.

[0023] The calibration circuit 114 controls the sampling circuit 115 to sample the data signal DQ at different reference voltage Vref settings during the calibration procedure to obtain eye diagrams corresponding to each bit. The eye diagrams define the time interval (or sampling point or phase range) and corresponding reference voltage range that allow the sampling circuit 115 to successfully sample data. The calibration circuit 114 can further establish data eyes for the data signal DQ based on the intersection of the eye diagrams corresponding to these bits. The calibration circuit 114 can configure the data eyes to the memory controller 10B or the corresponding processing unit 112, enabling the memory controller 10B to receive the data signal DQ based on the data eyes in subsequent operations.

[0024] In the calibration procedure, the voltage level of the reference voltage Vref can be set by an external circuit and provided to the memory controller 10B via the receiving pad VP after setting. Besides changing the set value of the reference voltage Vref, in embodiments of the present invention, the memory controller 10B can also internally combine the received reference voltage Vref with different offsets to attempt to find an optimal voltage offset that allows each bit DQ1 to DQN to have a larger effective data reception window.

[0025] More specifically, the voltage adjustment circuit 116 is used to adjust the reference voltage Vref corresponding to each receiving pad P1 to PN according to different offsets in response to the control of the calibration circuit 114. The optimal voltage offsets corresponding to different receiving pads P1 to PN or different data bits DQ1 to DQN may not be the same. Therefore, the voltage offsets corresponding to different data bits DQ1 to DQN can be adjusted independently by the voltage adjustment circuit 116. It should be noted that in the embodiments of the present invention, the voltage adjustment circuit 116 is not used to adjust the set value of the reference voltage Vref, but rather to elastically fine-tune the level of the reference voltage Vref locally according to different offsets based on the set value of the reference voltage Vref received from the receiving pad VP. Therefore, in the embodiments of the present invention, even if bits DQ1 to DQN share the same reference voltage Vref, fine-tuning the level of the reference voltage Vref locally under each set value of the reference voltage Vref may have the opportunity to find a larger effective data reception window for each bit, thereby potentially increasing the data eye ultimately established for the data signal.

[0026] It should be noted that the present invention is not limited to placing the calibration circuit 114 and the voltage adjustment circuit 116 inside the memory controller 10B. In some embodiments, the calibration circuit 114 and the voltage adjustment circuit 116 may also be placed outside the memory controller 10B.

[0027] According to a first embodiment of the present invention, below a predetermined set value (hereinafter referred to as the predetermined value), the calibration circuit 114 can further adjust the level of the reference voltage Vref corresponding to each receiving pad P1 to PN according to one or more voltage offsets via the voltage adjustment circuit 116. Furthermore, when determining a valid data receiving window for a bit below this predetermined value, the result of sampling this bit using the predetermined value in combination with the one or more voltage offsets can be additionally considered. In one embodiment of the present invention, the calibration circuit 114 can set the valid data receiving window with the largest width as the valid data receiving window for this bit below the predetermined value, and record the voltage offset (which can be a zero or non-zero value) corresponding to the valid data receiving window with the largest width.

[0028] Figure 2This is a flowchart illustrating a method for calibrating a data receiving window according to a first embodiment of the present invention, which includes the following steps or operations performed by the calibration circuit 114:

[0029] Step / Operation S202: The level of the reference voltage Vref is set to multiple different predetermined values, and the data signal DQ is repeatedly sampled according to the reference voltage Vref to obtain the first effective data reception window corresponding to each of the different predetermined values. As described above, the voltage level of the reference voltage Vref can be sequentially set to the different predetermined values ​​by an external circuit, and provided to the memory controller 10B through the receiving pad VP after setting. For each predetermined value set to the reference voltage Vref (which can be regarded as the voltage level of the reference voltage Vref to be measured), the sampling circuit 115 can repeatedly sample a bit of the data signal DQ at different sampling points in response to a data trigger signal DQS with different delays to calculate the first effective data reception window of that bit under the currently set predetermined value.

[0030] Step / Operation S204: Establish a first eye diagram for the bit based on the first valid data receiving window corresponding to these predetermined values.

[0031] Step / Operation S206: The level of the reference voltage Vref is reset with the different predetermined values, and the level of the reference voltage Vref is adjusted by the voltage adjustment circuit 116 according to the first offset to obtain a result that is approximately equal to or approximates the result of resetting the level of the reference voltage Vref with the different predetermined values ​​combined with the first offset. The data signal DQ is repeatedly sampled according to the reset and adjusted reference voltage Vref to obtain the second effective data reception window corresponding to the different predetermined values ​​under the condition of the first offset. Similarly, for each reference voltage Vref voltage level to be measured, the sampling circuit 115 can repeatedly sample a bit of the data signal DQ at different sampling points in response to a data trigger signal DQS with different delays to calculate the second effective data reception window of that bit under the currently set voltage level.

[0032] Step / Operation S208: Selectively update the first eye diagram based on the second valid data receiving window corresponding to these predetermined values. More specifically, for each predetermined value, the calibration circuit 114 can compare the width of the valid data receiving window obtained under no-offset conditions with the width of the valid data receiving window obtained under conditions combined with a first offset (i.e., the time interval or sampling point / phase range where data can be successfully sampled). If the width of the second valid data receiving window corresponding to a predetermined value is greater than the width of the first valid data receiving window corresponding to this predetermined value, the calibration circuit 114 can replace the first valid data receiving window corresponding to this predetermined value in the first eye diagram with this second valid data receiving window, and record a first offset that makes the valid data receiving window have a larger width as the preferred offset corresponding to this predetermined value.

[0033] In embodiments of the present invention, the calibration circuit 114 can be configured to set the number of offsets to be measured. For example, in one embodiment of the present invention, when more than one offset is applied, Figure 2 The calibration method may also include the following steps / operations:

[0034] The reference voltage Vref level is reset with the different predetermined values, and the voltage adjustment circuit 116 adjusts the reference voltage Vref level according to the second offset to obtain a result that is approximately equal to or approximates the result of resetting the reference voltage Vref level with the different predetermined values ​​combined with the second offset. The data signal DQ is then repeatedly sampled based on the reset and adjusted reference voltage Vref level to obtain the third effective data reception window corresponding to the different predetermined values ​​under the condition of the second offset. It should be noted that the above steps / operations can also be incorporated into step / operation S206.

[0035] In addition, when multiple offsets to be measured are applied, step / operation S208 may also include the following operations:

[0036] The first eye diagram is selectively updated based on these predetermined values ​​combined with different offsets to obtain effective data receiving windows. More specifically, for each predetermined value, the calibration circuit 114 can compare the effective data receiving window obtained under no-offset conditions with the effective data receiving window obtained under conditions combined with different offsets to determine which has a larger width. If the width of the effective data receiving window obtained by combining this predetermined value with any offset is greater than the width of the first effective data receiving window corresponding to this predetermined value under no-voltage offset conditions, the calibration circuit 114 can replace the first effective data receiving window corresponding to this predetermined value in the first eye diagram with the effective data receiving window having the largest width (or, with any effective data receiving window having a width greater than the width of the first effective data receiving window), and record for this predetermined value the offset that makes the effective data receiving window have a larger width as the preferred offset corresponding to this predetermined value.

[0037] In an embodiment of the present invention, the calibration circuit 114 may repeatedly perform steps / operations S202 to S208 on each bit of the data signal DQ during the calibration procedure to establish a first eye diagram corresponding to each bit. Furthermore, the calibration circuit 114 may further establish a data eye for the data signal DQ based on the intersection of the first eye diagrams corresponding to multiple bits of the data signal DQ, enabling the memory controller 10B to receive the data signal DQ based on the data eye in subsequent operations.

[0038] Figure 3 This is an example of an eye diagram obtained by combining multiple predetermined values ​​with different offsets. Figure 3 The voltage value is represented by a percentage, where the maximum amplitude of the reference voltage Vref is assumed to be Y. The X% shown in the figure and below means that the voltage value is Y*X%.

[0039] exist Figure 3The image shows three eye diagrams corresponding to the three bits DQ1, DQ2, and DQN. For ease of comparison, the eye diagram on the left is the one obtained when the reference voltage Vref is not offset; the eye diagram in the center is the one obtained when the reference voltage Vref is combined with a +1% offset; and the eye diagram on the right is the one obtained when the reference voltage Vref is combined with a -1% offset. Therefore, the three eye diagrams corresponding to each bit are marked with Ori, +1, and -1 respectively for distinction. The double arrows and the corresponding bold marking Vref = 34.5% in each eye diagram represent the effective data reception window obtained under the conditions of no offset, +1% offset, and -1% offset when the level of the reference voltage Vref (i.e., the aforementioned predetermined value) is set to Y*34.5%. In addition, the figure also shows other voltage value settings, such as Vref = 35.5% and Vref = 36.5%, which means that the calibration circuit 114 will also use other level settings of the reference voltage Vref in combination with different offsets to find the corresponding valid data receiving window for each bit in the calibration procedure.

[0040] Assuming that calibration circuit 114 plans to apply two additional offsets (+1 and -1) for testing during the calibration procedure, after obtaining the effective data reception window corresponding to each offset, calibration circuit 114 compares the widths of the effective data reception window obtained under three conditions: no offset, a +1% offset, and a -1% offset, and takes the maximum value. Figure 3 In the example shown, with Vref = 34.5%, the effective data reception window obtained by bit DQ1 with an offset of +1% has a maximum width of 10, so it is labeled Max_Width = 10(+1), where 10 represents the number of sampling points or phases of successfully sampled data. The effective data reception window obtained by bit DQ2 without applying an offset has a maximum width of 11, so it is labeled Max_Width = 11(Ori). The effective data reception window obtained by bit DQN with an offset of -1% has a maximum width of 9, so it is labeled Max_Width = 9(-1).

[0041] Next, the calibration circuit 114 further intersects the effective data reception windows with the maximum width obtained after applying one or more offset operations at the setting of Vref = 34.5% for bits DQ1 to DQN, to find the effective data reception window in the data eye of the data signal DQ relative to the setting of Vref = 34.5%. The intersection operation here finds the range that can cover all effective data reception windows with the maximum width for bits DQ1 to DQN. Assuming the effective data reception window width in the data eye relative to the setting of Vref = 34.5% is 9, the calibration circuit 114 records information such as this width, range, and the optimal offset corresponding to each bit under this setting, for example... Figure 3 The diagram on the right shows Vref = 34.5% => (+1, Ori, ..., -1). The calibration circuit 114 can repeatedly perform the above operation with other levels of the reference voltage Vref combined with different offsets to establish a complete data eye for the data signal DQ. Compared to establishing a data eye based solely on the voltage level set according to the reference voltage Vref without applying an offset, the data eye established according to the above process has a larger effective data reception window.

[0042] According to one embodiment of the present invention, in order to enhance the tolerance of the effective data reception window to voltage jitter, the duration is extended. Figure 2 As shown in the process, after performing step / operation S204 and before step / operation S208, calibration circuit 114 also generates a second eye diagram based on the tolerance height (or eye height) and the first eye diagram. In the second eye diagram, these predetermined values ​​each have a corresponding fourth effective data receiving window, and the fourth effective data receiving window corresponding to each predetermined value in the second eye diagram is less than or equal to the first effective data receiving window corresponding to that predetermined value in the first eye diagram.

[0043] More specifically, the calibration circuit 114 can select one predetermined value from these predetermined values, and select one or more other predetermined values ​​close to the selected predetermined value from these predetermined values ​​according to a set tolerance height. Furthermore, based on the intersection of the selected predetermined value and the first valid data reception windows corresponding to the one or more other predetermined values ​​in the first eye diagram, it determines the fourth valid data reception window corresponding to the selected predetermined value in the second eye diagram. Additionally, according to an embodiment of the invention, after generating the second eye diagram, the calibration circuit 114 can replace the first eye diagram with the content of the second eye diagram and continue executing step / operation S208. It should be noted that in embodiments applying the tolerance height, the calibration circuit 114 can also generate another eye diagram in the same manner based on the eye diagram obtained below the tolerance height and the applied offset in the operation of applying the offset (e.g., step / operation S206) to obtain better tolerance for voltage jitter.

[0044] Figure 4 This is a flowchart illustrating a method for calibrating a data receiving window according to a second embodiment of the present invention, which includes the following steps or operations performed by the calibration circuit 114:

[0045] Step / Operation S402: The level of the reference voltage Vref is set to multiple different predetermined values, and the data signal DQ is repeatedly sampled according to the reference voltage Vref to obtain the first effective data reception window corresponding to each of the different predetermined values. As described above, the voltage level of the reference voltage Vref can be sequentially set to the different predetermined values ​​by an external circuit, and after setting, it is provided to the memory controller 10B through the receiving pad VP. For each predetermined value set to the reference voltage Vref, the sampling circuit 115 can repeatedly sample a bit of the data signal DQ at different sampling points in response to a data trigger signal DQS with different delays to calculate the first effective data reception window of that bit under the currently set predetermined value.

[0046] Step / Operation S404: Establish a first eye diagram for the bit based on the first valid data receiving window corresponding to these predetermined values.

[0047] Step / Operation S406: Generate a second eye diagram based on the tolerance height and the first eye diagram. In the second eye diagram, these predetermined values ​​each have a corresponding second valid data receiving window, and the second valid data receiving window corresponding to each predetermined value in the second eye diagram is less than or equal to the first valid data receiving window corresponding to that predetermined value in the first eye diagram.

[0048] In embodiments of the present invention, the calibration circuit 114 may repeatedly perform steps / operations S402 to S406 on each bit of the data signal DQ during the calibration procedure to establish a second eye diagram corresponding to each bit. Furthermore, the calibration circuit 114 may further establish a data eye for the data signal DQ based on the intersection of the second eye diagrams corresponding to multiple bits of the data signal DQ, enabling the memory controller 10B to receive the data signal DQ based on the data eye in subsequent operations.

[0049] Figures 5A-5C It shows the process of generating a second eye diagram based on the first eye diagram corresponding to a set tolerance height and a bit (e.g., DQ1). Figures 5A-5C The left side of the image shows the first eye diagram corresponding to bit DQ1. The vertical axis represents the percentage of each predetermined value used to set the reference voltage Vref, and the numbers on the horizontal axis represent the sampling point or phase index value. The column marked with "1" in the image indicates that the data content of bit DQ1 can be successfully or correctly sampled at the corresponding sampling point or phase according to the corresponding predetermined value.

[0050] Assuming the current tolerance height is set to 3 and the voltage resolution is 1%, then this means that for a predetermined value (e.g., Figure 5A Given Vref = 34.5%, the calibration circuit 114 can select two predetermined values ​​adjacent to this predetermined value (e.g., two other predetermined values ​​Vref = 35.5% and Vref = 33.5%), and select the intersection of the effective data reception windows corresponding to these three predetermined values ​​(e.g., ...). Figure 5A The three data reception windows enclosed by the box on the left cover the sampling points or phase range, determining the effective data reception window corresponding to the predetermined value of 34.5% in the second eye diagram (e.g., Figure 5A The right side shows the valid data receiving window corresponding to the predetermined value of 34.5%.

[0051] The calibration circuit 114 sequentially selects different predetermined values ​​to perform the above operation, for example... Figure 5B The above operation is performed with Vref = 35.5% as shown to obtain the effective data reception window after considering the tolerance height for different predetermined values, and to establish the second eye diagram accordingly. Figure 5C The eye diagram shown on the right. Compared to Figure 5C The first-glance image on the left is shown in Figure 5C The second eye diagram on the right has better tolerance for voltage jitter. For example, with a reference voltage Vref = 34.5%, even if a 1% voltage jitter occurs, the sampling bit DQ1 can still obtain the correct data content within the sampling point or phase interval 8 to 21.

[0052] According to one embodiment of the present invention, in order to further increase the effective data reception window and extend... Figure 4 The calibration circuit 114 may also perform the following steps or operations (not shown below) in the process described. Figure 4 ):

[0053] Step / Operation S408: The reference voltage level is reset and adjusted using different predetermined values ​​used in step / operation S402 as described above, combined with at least one offset. The data signal DQ is repeatedly sampled based on the reference voltage Vref after the level is reset and adjusted, so as to obtain the third effective data receiving window corresponding to different predetermined values ​​under the condition of offset.

[0054] Step / Operation S410: Establish a third eye diagram based on the third valid data receiving window corresponding to these predetermined values.

[0055] Step / Operation S412: Selectively update the second eye based on the tolerance height and the third eye.

[0056] Step / operation S412 may also include the following steps or operations (not shown below) Figure 4 ):

[0057] Step / Operation S412-1: Select a predetermined value, and select one or more other predetermined values ​​that are close to the selected predetermined value according to the tolerance height.

[0058] Step / Operation S412-2: Determine the fourth valid data receiving window corresponding to the selected predetermined value based on the intersection of the selected predetermined value in the third eye diagram and the third valid data receiving window corresponding to one or more other predetermined values.

[0059] Step / Operation S412-3: Compare the width of the fourth valid data receiving window with the width of the second valid data receiving window corresponding to the selected predetermined value in the second eye diagram, and when the width of the fourth valid data receiving window is greater than the width of the second valid data receiving window, replace the second valid data receiving window corresponding to the selected predetermined value in the second eye diagram with the fourth valid data receiving window.

[0060] According to one embodiment of the present invention, when multiple offsets to be measured are applied, the calibration circuit 114 can repeatedly execute steps / operations S408 to S412 with different offsets to obtain the third eye diagram corresponding to the application of multiple different offsets, and selectively update the second eye diagram according to the tolerance height and the third eye diagram.

[0061] Figure 6 This is a flowchart illustrating a method for calibrating a data receiving window according to a third embodiment of the present invention, which includes the following steps or operations performed by the calibration circuit 114:

[0062] Step / Operation S602: Determine the tolerance height (or eye height).

[0063] Step / Operation S604: Establish the first eye diagram and the second eye diagram corresponding to each bit without applying an offset (e.g., disabling the voltage adjustment circuit 116). Step / Operation S604 may further include the following steps or operations:

[0064] Step / Operation S604-1: Set the level of the reference voltage Vref to a predetermined value, and sample each bit of the data signal DQ according to the reference voltage Vref to obtain the effective data reception window corresponding to each bit relative to this predetermined value.

[0065] Step / Operation S604-2: Re-execute step / operation S604-1 using different predetermined values ​​to obtain the valid data receiving window corresponding to each bit relative to the different predetermined values, and establish the first eye diagram corresponding to each bit.

[0066] Step / Operation S604-3: As in step / operation S406 above, generate the second eye diagram corresponding to each bit based on the tolerance height and the first eye diagram.

[0067] Step / Operation S606: Establish the third eye diagram corresponding to each bit under the condition of applying a first offset (e.g., enabling the voltage adjustment circuit 116 and setting the first offset, e.g., setting offset = +1%), and selectively update the second eye diagram according to the tolerance height and the third eye diagram. Step / Operation S606 may also include the following steps or operations:

[0068] Step / Operation S606-1: Set the level of the reference voltage Vref to a predetermined value, and sample each bit of the data signal DQ based on the reference voltage Vref to obtain the effective data reception window corresponding to each bit relative to this predetermined value. It should be noted that in S606-1, the voltage adjustment circuit 116 further adjusts the level of the reference voltage Vref based on the currently set first offset to obtain a result that is approximately equal to or approximates the result of resetting the level of the reference voltage Vref using the predetermined value combined with the first offset, and samples each bit of the data signal DQ based on the reset and adjusted reference voltage Vref level.

[0069] Step / Operation S606-2: Re-execute step / operation S606-1 using different predetermined values ​​to obtain the effective data receiving window corresponding to each bit relative to different predetermined values ​​and under the condition of applying the first offset, and establish the third eye diagram corresponding to each bit.

[0070] Step / Operation S606-3: As in step / operation S412 above, selectively update the second eye diagram based on the tolerance height and the third eye diagram. It should be noted that in S606, if the valid data receiving window corresponding to any predetermined value in the second eye diagram is updated, the calibration circuit 114 will further record the corresponding first offset for these predetermined values(s).

[0071] Step / Operation S608: Under the condition of applying the second offset (e.g., enabling the voltage adjustment circuit 116 and setting the second offset, for example, setting offset = -1%), establish the fourth eye diagram corresponding to each bit, and selectively update the second eye diagram according to the tolerance height and the fourth eye diagram. The detailed operation of step / operation S608 is similar to S606-1 to S606-3 of S606, and will not be described again.

[0072] Figure 6The example given is that the number of offsets to be measured is set to 2. If the number of offsets to be measured is set to 1, the calibration circuit 114 may not perform step / operation S608. If the number of offsets to be measured is set to 3 or more, the calibration circuit 114 may perform one or more steps / operations similar to S606 / S608 before performing the final step / operation S610.

[0073] Step / Operation S610: Establish a data eye for the data signal DQ based on the intersection of the second eye diagrams corresponding to each bit of the data signal DQ, and take the predetermined value that maximizes the width of the effective data reception window as the optimal reference voltage Vref setting value.

[0074] Figure 7 This is an example of an eye diagram obtained after step / operation S608 is completed (e.g., after applying two or more different offsets). In the second eye diagram, the effective data reception windows corresponding to different offsets are distinguished by different screen backgrounds. Since the second eye diagram is the result of selectively updating according to different offsets while considering the tolerance height, the updated second eye diagram may include one or more effective data reception windows corresponding to different offsets. Note that for easy differentiation of different screen backgrounds, Figure 7 The marker "1" used to indicate a successful sampling result will be removed.

[0075] Figure 8 This is an example of a second eye diagram showing multiple bits after applying at least three different offsets; it can also be an example of the final eye diagram for each bit. Figure 8 The eye diagram on the left is the final eye diagram corresponding to DQ1. Figure 8 The eye diagram in the middle is the final eye diagram corresponding to DQ2. Figure 8 The eye diagram on the right is the final eye diagram corresponding to the DQN, and different mesh bases represent different offsets. Similarly, to easily distinguish different mesh bases, Figure 8 The marker "1" used to indicate a successful sampling result is removed. In an embodiment of the invention, the calibration circuit 114 may take the intersection of these eye diagrams as the data eye of the data signal DQ, and take a predetermined value that maximizes the width of the effective data reception window, for example, 34.5% in this example, as the optimal reference voltage Vref setting. Under the setting of reference voltage Vref = 34.5%, the preferred offsets corresponding to bits DQ1, DQ2, and DQN can be different offsets, for example, -1%, +1%, and 0.

[0076] In summary, the method and related apparatus for calibrating the data receiving window proposed in this invention can effectively increase the effective data receiving window of the receiving end and enhance the tolerance of the effective data receiving window to voltage jitter.

[0077] The above description is only a preferred embodiment of the present invention. Any modifications or variations made according to the claims of the present invention are within the scope of the present invention.

[0078] Figure Labels

[0079] 10: Dynamic Random Access Memory System

[0080] 10A: Dynamic Random Access Memory

[0081] 10B: Memory controller

[0082] 111: Receive pad module

[0083] 112: Processing Unit

[0084] 113: Storage unit

[0085] 114: Calibration Circuit

[0086] 115: Sampling Circuit

[0087] 116: Voltage Regulation Circuit

[0088] P1, P2, PN, VP: Receiving pads

Claims

1. A memory controller coupled to a memory device for controlling access operations of the memory device, wherein the memory controller receives data signals from the memory device via a plurality of receive pads, and the memory controller includes: A sampling circuit is used to sample the data signal based on a reference voltage; The calibration circuit is used to perform the following operations: (A) The level of the reference voltage is set with multiple different predetermined values, and the sampling circuit is controlled to repeatedly sample the data signal according to the reference voltage to obtain the first effective data receiving window corresponding to each predetermined value; (B) Establish a first eye diagram based on the first valid data receiving window corresponding to the predetermined value; (C) The level of the reference voltage is reset by combining the predetermined value with the first offset, and the sampling circuit is controlled to repeatedly sample the data signal according to the reference voltage to obtain the second effective data receiving window corresponding to the predetermined value respectively; (D) The first eye diagram is selectively updated according to the second valid data receiving window corresponding to the predetermined value, wherein when the width of the second valid data receiving window corresponding to the predetermined value is greater than the width of the first valid data receiving window corresponding to the predetermined value, the first valid data receiving window corresponding to the predetermined value in the first eye diagram is replaced by the second valid data receiving window corresponding to the predetermined value.

2. The memory controller of claim 1, wherein the calibration circuit further performs the following operations before performing operation (D): (E) The level of the reference voltage is reset using the predetermined value in combination with the second offset, and the sampling circuit is controlled to repeatedly sample the data signal according to the reference voltage to obtain the third valid data receiving window corresponding to the predetermined value. Furthermore, when the calibration circuit performs operation (D), it selectively updates the first eye diagram according to the third valid data receiving window corresponding to the predetermined value. When the width of the second valid data receiving window or the third valid data receiving window corresponding to the predetermined value is greater than the width of the first valid data receiving window corresponding to the predetermined value, the first valid data receiving window corresponding to the predetermined value in the first eye diagram is replaced by the one with the larger width between the second valid data receiving window and the third valid data receiving window corresponding to the predetermined value.

3. The memory controller of claim 1, wherein the calibration circuit further performs the following operations: (F) Generate a second eye diagram based on the tolerance height and the first eye diagram. In the second eye diagram, each predetermined value has a corresponding fourth effective data receiving window, and the fourth effective data receiving window corresponding to each predetermined value in the second eye diagram is less than or equal to the first effective data receiving window corresponding to the predetermined value in the first eye diagram.

4. The memory controller of claim 3, wherein operation (F) further comprises: (F-1) Select a predetermined value from the predetermined values, and select one or more other predetermined values ​​that are close to the selected predetermined value from the predetermined values ​​according to the tolerance height; as well as (F-2) Determine the fourth valid data receiving window in the second eye diagram corresponding to the selected predetermined value based on the intersection of the first valid data receiving window corresponding to the selected predetermined value in the first eye diagram and the one or more other predetermined values.

5. The memory controller according to claim 1, wherein the data signal includes a plurality of bits, each receiving pad is used to receive one bit of the data signal, the sampling circuit is used to repeatedly sample the bit according to the reference voltage, and the calibration circuit repeatedly performs operations (A)-(D) on the bit in a calibration procedure to establish the first eye diagram corresponding to the bit respectively.

6. The memory controller of claim 5, wherein the calibration circuit further establishes a data eye for the data signal based on the intersection of the first eye diagrams corresponding to the bits.

7. A method for calibrating a data receiving window, comprising the following steps: (A) The level of the reference voltage is set with multiple different predetermined values, and the data signal received from the memory device is repeatedly sampled according to the reference voltage to obtain the first effective data receiving window corresponding to each of the predetermined values; (B) Establish a first eye diagram based on the first valid data receiving window corresponding to the predetermined value; (C) The level of the reference voltage is reset by combining the predetermined value with the first offset, and the data signal is repeatedly sampled according to the reference voltage to obtain the second effective data receiving window corresponding to the predetermined value respectively; (D) The first eye diagram is selectively updated according to the second valid data receiving window corresponding to the predetermined value, wherein when the width of the second valid data receiving window corresponding to the predetermined value is greater than the width of the first valid data receiving window corresponding to the predetermined value, the first valid data receiving window corresponding to the predetermined value in the first eye diagram is replaced by the second valid data receiving window corresponding to the predetermined value.

8. A method for calibrating a data receiving window, comprising the following steps: (A) The level of the reference voltage is set with multiple different predetermined values, and the data signal received from the memory device is repeatedly sampled according to the reference voltage to obtain the first effective data receiving window corresponding to each of the predetermined values; (B) Establish a first eye diagram based on the first valid data receiving window corresponding to the predetermined value; as well as (C) Generate a second eye diagram based on the tolerance height and the first eye diagram. In the second eye diagram, each predetermined value has a corresponding second effective data receiving window, and the second effective data receiving window corresponding to each predetermined value in the second eye diagram is less than or equal to the first effective data receiving window corresponding to the predetermined value in the first eye diagram.

9. The method of claim 8, wherein step (C) further comprises: (C-1) Select a predetermined value from the predetermined values, and select one or more other predetermined values ​​that are close to the selected predetermined value from the predetermined values ​​according to the tolerance height; as well as (C-2) Determine the second valid data receiving window in the second eye diagram corresponding to the selected predetermined value based on the intersection of the first valid data receiving window corresponding to the selected predetermined value in the first eye diagram and the first valid data receiving window corresponding to the one or more other predetermined values.

10. The method of claim 8, further comprising: (D) The level of the reference voltage is reset by combining the predetermined value with the first offset, and the data signal is repeatedly sampled according to the reference voltage to obtain the third effective data receiving window corresponding to the predetermined value respectively; (E) Establish a third eye diagram based on the third valid data receiving window corresponding to the predetermined value; and (F) The second eye map is selectively updated based on the tolerance height and the third eye map.

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