Driving circuit, driving method, driving module and display device

Abstract

The application provides a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a pull-up node control circuit, a pull-down node control circuit, an output circuit, an output reset circuit and an output noise reduction circuit. The output circuit controls the communication between a first driving signal output end and a first output clock signal end and the communication between a second driving signal output end and a second output clock signal end under the control of the potential of the pull-up node. The output reset circuit controls the communication between the first driving signal output end and a first voltage end and the communication between the second driving signal output end and the first voltage end under the control of the potential of the pull-down node. The output noise reduction circuit controls the communication between the first driving signal output end and a second voltage end and the communication between the second driving signal output end and the second voltage end under the control of a first control voltage. The application is beneficial to the realization of narrow frame and low power consumption.

Description

[0001] Cross-references to related applications

[0002] This invention claims priority to Chinese invention patent application number 202210454672.4, filed on April 24, 2022. Technical Field

[0003] This invention relates to the field of display technology, and in particular to a driving circuit, driving method, driving module, and display device. Background Technology

[0004] The display industry is developing rapidly and showing a trend of diversification. As the performance of display products continues to improve, products are pursuing increasingly higher quality. In recent years, keywords such as "narrow bezel" and "low power consumption" have been frequently mentioned. However, due to the difficulty in breaking through hard indicators such as materials, processes, and equipment capabilities, the industry is seeking breakthroughs in product substrate design. Summary of the Invention

[0005] The main objective of this invention is to provide a driving circuit, driving method, driving module, and display device to solve the problem that existing driving circuits cannot reduce the number of transistors used, which is not conducive to achieving narrow bezels and low power consumption.

[0006] This invention provides a driving circuit, which includes a pull-up node control circuit, a pull-down node control circuit, an output circuit, an output reset circuit, and an output noise reduction circuit.

[0007] The pull-up node control circuit is electrically connected to the pull-up node and is used to control the potential of the pull-up node;

[0008] The pull-down node control circuit is electrically connected to the pull-down node and is used to control the potential of the pull-down node;

[0009] The output circuit is electrically connected to the pull-up node, the first drive signal output terminal, the second drive signal output terminal, the first output clock signal terminal, and the second output clock signal terminal, respectively, and is used to control the connection between the first drive signal output terminal and the first output clock signal terminal, and control the connection between the second drive signal output terminal and the second output clock signal terminal, under the control of the potential of the pull-up node.

[0010] The output reset circuit is electrically connected to the pull-down node, the first drive signal output terminal, the second drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the first drive signal output terminal and the first voltage terminal and the connection between the second drive signal output terminal and the first voltage terminal under the control of the potential of the pull-down node.

[0011] The output noise reduction circuit is electrically connected to the first control voltage terminal, the first drive signal output terminal, the second drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the first drive signal output terminal and the second voltage terminal under the control of the first control voltage provided by the first control voltage terminal, and to control the connection between the second drive signal output terminal and the second voltage terminal.

[0012] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first energy storage circuit and a second energy storage circuit;

[0013] The first terminal of the first energy storage circuit is electrically connected to the pull-up node, and the second terminal of the first energy storage circuit is electrically connected to the first drive signal output terminal.

[0014] The first end of the second energy storage circuit is electrically connected to the pull-up node, and the second end of the second energy storage circuit is electrically connected to the second drive signal output terminal.

[0015] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit;

[0016] The first terminal of the third energy storage circuit is electrically connected to the pull-up node, and the second terminal of the third energy storage circuit is electrically connected to the pull-up control terminal.

[0017] The pull-up control terminal is electrically connected to the first drive signal output terminal of the adjacent lower-level drive circuit.

[0018] Optionally, the output noise reduction circuit includes a first transistor and a second transistor;

[0019] The control electrode of the first transistor is electrically connected to the first control voltage terminal, the first electrode of the first transistor is electrically connected to the first drive signal output terminal, and the second electrode of the first transistor is electrically connected to the second voltage terminal.

[0020] The control electrode of the second transistor is electrically connected to the first control voltage terminal, the first electrode of the second transistor is electrically connected to the second drive signal output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0021] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0022] The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal of the first capacitor is electrically connected to the first drive signal output terminal.

[0023] The first end of the second capacitor is electrically connected to the pull-up node, and the second end of the second capacitor is electrically connected to the second drive signal output terminal.

[0024] Optionally, the third energy storage circuit includes a third capacitor;

[0025] The first end of the third capacitor is electrically connected to the pull-up node, and the second end of the third capacitor is electrically connected to the pull-up control terminal.

[0026] Optionally, the output circuit includes a third transistor and a fourth transistor;

[0027] The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the first output clock signal terminal, and the second electrode of the third transistor is electrically connected to the first drive signal output terminal.

[0028] The control electrode of the fourth transistor is electrically connected to the pull-up node, the first electrode of the fourth transistor is electrically connected to the second output clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal.

[0029] Optionally, the output reset circuit includes a fifth transistor and a sixth transistor;

[0030] The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the first drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0031] The control electrode of the sixth transistor is electrically connected to the pull-down node, the first electrode of the sixth transistor is electrically connected to the second drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0032] Optionally, the pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively, for controlling the potential of the pull-down control node under the control of the second control voltage provided by the second control voltage terminal and the potential of the pull-up node, controlling the connection between the pull-down node and the second control voltage terminal under the control of the potential of the pull-down control node, and controlling the connection between the pull-down node and the third voltage terminal under the control of the potential of the pull-up node.

[0033] Optionally, the pull-up node control circuit is electrically connected to the first control terminal, the second control terminal, the first input voltage terminal, the second input voltage terminal, the pull-down node, the pull-up node, and the fourth voltage terminal, respectively. It is used to control the connection between the pull-up node and the first input voltage terminal under the control of the first control signal provided by the first control terminal, control the connection between the pull-up node and the second input voltage terminal under the control of the second control signal provided by the second control terminal, and control the connection between the pull-up node and the fourth voltage terminal under the control of the potential of the pull-down node.

[0034] Optionally, the pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0035] The control electrode and the first electrode of the seventh transistor are both electrically connected to the second control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the pull-down control node;

[0036] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the pull-down control node, and the second electrode of the eighth transistor is electrically connected to the third voltage terminal.

[0037] The control electrode of the ninth transistor is electrically connected to the pull-down control node, the first electrode of the ninth transistor is electrically connected to the second control voltage terminal, and the second electrode of the ninth transistor is electrically connected to the pull-down node.

[0038] The control electrode of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage terminal.

[0039] Optionally, the pull-up node control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0040] The control electrode of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the first input voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the pull-up node.

[0041] The control electrode of the twelfth transistor is electrically connected to the second control terminal, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the second input voltage terminal.

[0042] The control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the fourth voltage terminal.

[0043] Optionally, the driving circuit described in at least one embodiment of the present invention includes a pull-up node noise reduction circuit;

[0044] The pull-up node noise reduction circuit is electrically connected to the pull-up node, the frame start terminal, and the fourth voltage terminal, respectively, and is used to control the connection between the pull-up node and the fourth voltage terminal under the control of the frame start signal provided by the frame start terminal.

[0045] The present invention also provides a driving method applied to the above-described driving circuit, the driving method comprising:

[0046] The pull-up node control circuit controls the potential of the pull-up node;

[0047] The pull-down node control circuit controls the potential of the pull-down node;

[0048] Under the control of the potential of the pull-up node, the output circuit controls the output of the first output clock signal provided by the first output clock signal terminal to the first drive signal output terminal. Under the control of the potential of the pull-up node, the output circuit controls the output of the second output clock signal provided by the second output clock signal terminal to the second drive signal output terminal.

[0049] Under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal provided by the first voltage terminal to the first drive signal output terminal, and under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal to the second drive signal output terminal.

[0050] Under the control of the first control voltage provided by the first control voltage terminal, the output noise reduction circuit controls the connection between the first drive signal output terminal and the second voltage terminal. Under the control of the first control voltage, the output noise reduction circuit controls the connection between the second drive signal output terminal and the second voltage terminal.

[0051] Optionally, the pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively; the driving method further includes:

[0052] The pull-down node control circuit controls the potential of the pull-down control node under the control of the second control voltage provided at the second control voltage terminal and the potential of the pull-up node. Under the control of the potential of the pull-down control node, the pull-down node control circuit controls the connection between the pull-down node and the second control voltage terminal, and under the control of the potential of the pull-up node, controls the connection between the pull-down node and the third voltage terminal.

[0053] Optionally, the first control voltage is inverted compared to the second control voltage; a blank time period is provided between two adjacent display cycles, the blank time period including a frame reset phase; the driving method further includes:

[0054] During the frame reset phase, the output noise reduction circuit, under the control of the first control voltage, controls the connection between the first drive signal output terminal and the second voltage terminal, and the output noise reduction circuit, under the control of the first control voltage, controls the connection between the second drive signal output terminal and the second voltage terminal.

[0055] During the display cycle, the pull-down node control circuit, under the control of the potential of the second control voltage, controls the writing of the second control voltage into the pull-down control node.

[0056] The present invention also provides a driving module, including A driving units, where A equals 1 or 2; the driving unit includes multiple levels of the above-mentioned driving circuits.

[0057] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to eight output clock signal lines;

[0058] The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1.

[0059] The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal;

[0060] The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit.

[0061] The first control terminal of the first-stage drive circuit of the second drive unit is connected to the second start signal.

[0062] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to twelve output clock signal lines;

[0063] The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the first driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1.

[0064] The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal;

[0065] The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the first drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit.

[0066] The first control terminal of the first-stage drive circuit of the second drive unit is connected to the second start signal.

[0067] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to sixteen output clock signal lines;

[0068] The second control terminal of the d-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (d+2)-th stage drive circuit included in the first drive unit, and the first control terminal of the e-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (e-2)-th stage drive circuit included in the first drive unit; d is a positive integer, and e is an integer greater than 2;

[0069] The first control terminal of the first stage driving circuit of the first driving unit is connected to a first start signal; the first control terminal of the second stage driving circuit of the first driving unit is connected to a third start signal.

[0070] The second control terminal of the d-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the d+2-th stage drive circuit included in the second drive unit, and the first control terminal of the e-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the e-2-th stage drive circuit included in the second drive unit.

[0071] The first control terminal of the first-stage drive circuit of the second drive unit is connected to a second start signal, and the first control terminal of the second-stage drive circuit of the second drive unit is connected to a fourth start signal.

[0072] Optionally, the pull-up control terminal of the b-th stage drive circuit included in the first drive unit is electrically connected to the first drive signal output terminal of the b+1-th stage drive circuit included in the first drive unit.

[0073] This invention also provides a display device including the driving module described above.

[0074] The driving circuit, driving method, driving module, and display device described in the embodiments of the present invention can provide two driving signals through a single-stage driving circuit while reducing the number of transistors used. The dual drives share pull-up and pull-down nodes, which can achieve narrow bezels and low power consumption. Attached Figure Description

[0075] Figure 1 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0076] Figure 2 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0077] Figure 3 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0078] Figure 4 A schematic diagram of the fall time of the first driving signal and the fall time of the second driving signal when the driving circuit described in at least one embodiment of the present invention does not employ a third energy storage circuit;

[0079] Figure 5 This is a schematic diagram showing the fall time of the first driving signal and the fall time of the second driving signal when the driving circuit described in at least one embodiment of the present invention employs a third energy storage circuit and the capacitance value of the capacitor included in the third energy storage circuit is 750fF.

[0080] Figure 6 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0081] Figure 7 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0082] Figure 8 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0083] Figure 9 This invention is as follows Figure 8 The timing diagram of the driving circuit shown is shown below;

[0084] Figure 10 This invention is as follows Figure 8 Simulation waveforms of relevant signals during operation of at least one embodiment of the driving circuit shown;

[0085] Figure 11 This invention is as follows Figure 8 Simulation waveforms of relevant signals during operation of at least one embodiment of the driving circuit shown;

[0086] Figure 12 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0087] Figure 13 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0088] Figure 14 It is a schematic diagram of the connection relationship between the first-stage driving circuit G11 and the second-stage driving circuit G12 included in the first driving unit, and a schematic diagram of the connection relationship between the first-stage driving circuit G21 and the second-stage driving circuit G22 included in the second driving unit.

[0089] Figure 15 yes Figure 14 The timing diagram of each output clock signal, start signal, frame start signal, first input voltage, second input voltage, second control voltage, first control voltage, and low voltage signal provided by the frame start terminal STV0;

[0090] Figure 16 This is a schematic diagram of the cascade relationship of two adjacent driving circuits in the first driving unit when the driving module uses eight output clock signal lines, in at least one embodiment of the present invention.

[0091] Figure 17 This is a schematic diagram of the cascade relationship of two adjacent driving circuits in the first driving unit when the driving module uses eight output clock signal lines, in at least one embodiment of the present invention.

[0092] Figure 18 It is a schematic diagram showing the connection relationship of the first-stage driving circuit G11, the second-stage driving circuit G12, the third-stage driving circuit G13, and the fourth-stage driving circuit G14 included in the first driving unit; and a schematic diagram showing the connection relationship of the first-stage driving circuit G21, the second-stage driving circuit G22, the third-stage driving circuit G23, and the fourth-stage driving circuit G24 included in the second driving unit.

[0093] Figure 19 yes Figure 18The timing diagram of each output clock signal, start signal, frame start signal, first input voltage, second input voltage, second control voltage, first control voltage, and low voltage signal provided by the frame start terminal STV0;

[0094] Figure 20 It is a schematic diagram showing the connection relationship of the first-stage driving circuit G11, the second-stage driving circuit G12, and the third-stage driving circuit G13 included in the first driving unit, and a schematic diagram showing the connection relationship of the first-stage driving circuit G21, the second-stage driving circuit G22, and the third-stage driving circuit G23 included in the second driving unit. Detailed Implementation

[0095] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0096] like Figure 1 As shown, the driving circuit described in this embodiment of the invention includes a pull-up node control circuit 11, a pull-down node control circuit 12, an output circuit 13, an output reset circuit 14, and an output noise reduction circuit 15.

[0097] The pull-up node control circuit 11 is electrically connected to the pull-up node PU and is used to control the potential of the pull-up node PU;

[0098] The pull-down node control circuit 12 is electrically connected to the pull-down node PD and is used to control the potential of the pull-down node PD;

[0099] The output circuit 13 is electrically connected to the pull-up node PU, the first drive signal output terminal ON, the second drive signal output terminal ON+1, the first output clock signal terminal KN, and the second output clock signal terminal KN+1, respectively. It is used to control the connection between the first drive signal output terminal ON and the first output clock signal terminal KN, and to control the connection between the second drive signal output terminal ON+1 and the second output clock signal terminal KN+1, under the control of the potential of the pull-up node PU.

[0100] The output reset circuit 14 is electrically connected to the pull-down node PD, the first drive signal output terminal ON, the second drive signal output terminal ON+1, and the first voltage terminal V1, respectively. It is used to control the connection between the first drive signal output terminal ON and the first voltage terminal V1 under the control of the potential of the pull-down node PD, and to control the connection between the second drive signal output terminal ON+1 and the first voltage terminal.

[0101] The output noise reduction circuit 15 is electrically connected to the first control voltage terminal GCL, the first drive signal output terminal ON, the second drive signal output terminal ON+1, and the second voltage terminal V2, respectively. It is used to control the first drive signal output terminal ON and the second voltage terminal V2 to be connected under the control of the first control voltage provided by the first control voltage terminal GCL, and to control the second drive signal output terminal ON+1 and the second voltage terminal to be connected.

[0102] The driving circuit described in this embodiment of the invention can provide two driving signals through a single-stage driving circuit while reducing the number of transistors used. The dual drives share the pull-up node PU and the pull-down node PD, which can achieve narrow bezels and low power consumption.

[0103] Optionally, both the first voltage terminal and the second voltage terminal can be low voltage terminals. Optionally, the voltage signal provided by the first voltage terminal and the voltage signal provided by the second voltage terminal can be the same, but are not limited thereto.

[0104] When the driving circuit described in this embodiment of the invention is working, the pull-up node control circuit 11 controls the potential of the pull-up node PU, the pull-down node control circuit 12 controls the potential of the pull-down node PD, the output circuit 13, under the control of the potential of the pull-up node PU, controls the first driving signal output terminal ON to output a first driving signal, and controls the second driving signal output terminal ON+1 to output a second driving signal, the output reset circuit 14, under the control of the potential of the pull-down node PD, resets the first driving signal output by the N-level driving signal output terminal ON, and resets the second driving signal output by the N+1-level driving signal output terminal ON+1, the output noise reduction circuit 15, under the control of the first control voltage, reduces the noise of the first driving signal output by the N-level driving signal output terminal ON, and reduces the noise of the second driving signal output by the N+1-level driving signal output terminal ON+1.

[0105] like Figure 2 As shown, in Figure 1 Based on the embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first energy storage circuit 21 and a second energy storage circuit 22;

[0106] The first end of the first energy storage circuit 21 is electrically connected to the pull-up node PU, and the second end of the first energy storage circuit 21 is electrically connected to the first drive signal output terminal ON. The first energy storage circuit 21 is used to store electrical energy.

[0107] The first end of the second energy storage circuit 22 is electrically connected to the pull-up node PU, and the second end of the second energy storage circuit 22 is electrically connected to the second drive signal output terminal ON+1. The second energy storage circuit 22 is used to store electrical energy.

[0108] In at least one embodiment of the present invention, the driving circuit may further include a first energy storage circuit 21 and a second energy storage circuit 22, wherein the first energy storage circuit 21 is disposed between the pull-up node PU and the first driving signal output terminal ON, and the second energy storage circuit 22 is disposed between the pull-up node PU and the second driving signal output terminal ON+1.

[0109] The driving circuit described in at least one embodiment of the present invention further includes a third energy storage circuit;

[0110] The first terminal of the third energy storage circuit is electrically connected to the pull-up node, and the second terminal of the third energy storage circuit is electrically connected to the pull-up control terminal. The third energy storage circuit is used to store electrical energy.

[0111] The pull-up control terminal is electrically connected to the first drive signal output terminal of the adjacent lower-level drive circuit.

[0112] In specific implementation, the first drive signal output terminal of the adjacent lower-level drive circuit can be the first drive signal output terminal of the adjacent next-level drive circuit, or it can be the first drive signal output terminal of the adjacent P-level drive circuit, where P is an integer greater than 1.

[0113] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a third energy storage circuit 30;

[0114] The first end of the third energy storage circuit 30 is electrically connected to the pull-up node PU, and the second end of the third energy storage circuit 30 is electrically connected to the pull-up control terminal. The third energy storage circuit 30 is used to store electrical energy.

[0115] The pull-up control terminal is electrically connected to the first drive signal output terminal ON+2 of the adjacent next-stage drive circuit.

[0116] In at least one embodiment of the driving circuit described in this invention, during operation, since ON and ON+1 share a pull-up node PU, the potential of PU is inconsistent at the rising edge of the first driving signal provided by ON and the rising edge of the second driving signal provided by ON+1, and also inconsistent at the falling edge of the first driving signal provided by ON and the falling edge of the second driving signal provided by ON+1. This results in the rise time of the first driving signal provided by ON being unequal to the rise time of the second driving signal provided by ON+1, and the fall time of the first driving signal provided by ON being unequal to the fall time of the second driving signal provided by ON+1. Since the GOA (Gate On Array) circuit has a precharge time, the rise time has no effect on the actual charging, but the difference in fall time can lead to inconsistent charging rates between adjacent rows of pixel circuits, thereby causing changes in brightness.

[0117] like Figure 4 As shown, when the driving circuit described in at least one embodiment of the present invention does not employ a third energy storage circuit, the fall time of the first driving signal provided by ON can be 1.04μs, and the fall time of the second driving signal provided by ON+1 can be 1.85μs. The fall time of the first driving signal and the fall time of the second driving signal differ by 0.81μs, which poses a risk of malfunction.

[0118] When the driving circuit described in at least one embodiment of the present invention does not employ a third energy storage circuit, the reason why the fall time of the first driving signal is inconsistent with the fall time of the second driving signal is that, when the first driving signal provided by ON is at its falling edge, the potential of PU is pulled down through the first energy storage circuit. After the potential of PU drops, when the second driving signal provided by ON+1 is at its falling edge, the output transistor whose gate is electrically connected to PU is not fully turned on, resulting in a delay in the output of the low-level signal provided by the second output clock signal terminal KN+1, which leads to an increase in the fall time of the second driving signal.

[0119] To address the issue of inconsistent fall times between adjacent row drive signals, a third energy storage circuit 30 is added. The first terminal of the third energy storage circuit 30 is electrically connected to a pull-up node, and the second terminal is electrically connected to the first drive signal output terminal of the adjacent next-level drive circuit. For example, the second terminal of the third energy storage circuit 30 can be electrically connected to the first drive signal output terminal of the adjacent next-level drive circuit. After the potential of the first drive signal provided by ON decreases and the potential of PU is coupled down, ON+2 starts outputting. The third energy storage circuit connects ON+2 to the pull-up node of this stage, allowing the potential of PU to be pulled up again through capacitive coupling. This ensures that when the potential of the second drive signal provided by ON+1 decreases, the potential of PU can be maintained at a relatively high potential, resulting in a smaller delay in the low-level output signal provided by the second output clock signal terminal KN+1, thus reducing the difference between the fall time of the first drive signal provided by ON and the fall time of the second drive signal provided by ON+1.

[0120] like Figure 5 As shown in the simulation, when the capacitance of the capacitor included in the third energy storage circuit is 750fF, the fall time of the first drive signal provided by ON and the fall time of the second drive signal provided by ON+1 are both 1.35μs. This eliminates the difference in fall time between the two consecutive drive signals, thereby avoiding defects. (Reference) Figure 5 The low-level period of the first drive signal provided by ON does not overlap with the high-level period of the signal provided by ON+2. At the point where the low-level period of the first drive signal and the high-level period of the signal provided by ON+2 do not overlap, when the signal provided by ON+2 is a high-voltage signal, the high-voltage signal provided by ON+2 can pull the potential of the pull-up node PU corresponding to ON, and through capacitive coupling, pull the potential of the pull-up node PU high again. (Refer to...) Figure 5 The waveform of the potential of the pull-up node PU is a three-stage rise followed by a falling edge (this falling edge is the pull-down effect of the falling edge of the first drive signal provided by ON on the potential of PU), then a fourth-stage rise (due to the pull-up effect of the signal provided by ON+2), followed by two stages of falling, and finally the potential of PU becomes low.

[0121] In specific implementation, when the third energy storage circuit is not used, the rise time of the first drive signal provided by ON can be 4.06μs, and the rise time of the second drive signal provided by ON+1 can be 1.47μs. When the third energy storage circuit is used, the rise time of the first drive signal provided by ON can be 5.95μs, and the rise time of the second drive signal provided by ON+1 can be 2.3μs.

[0122] When the third energy storage circuit is not used, the fall time of the first drive signal provided by ON can be 1.04μs, and the fall time of the second drive signal provided by ON+1 can be 1.85μs. When the third energy storage circuit is used, the fall time of the first drive signal provided by ON can be 1.35μs, and the fall time of the second drive signal provided by ON+1 can be 1.35μs.

[0123] exist Figure 5 In the diagram, the terminal labeled ON+2 is the second drive signal output terminal of the adjacent next-stage drive circuit.

[0124] Optionally, the output noise reduction circuit includes a first transistor and a second transistor;

[0125] The control electrode of the first transistor is electrically connected to the first control voltage terminal, the first electrode of the first transistor is electrically connected to the first drive signal output terminal, and the second electrode of the first transistor is electrically connected to the second voltage terminal.

[0126] The control electrode of the second transistor is electrically connected to the first control voltage terminal, the first electrode of the second transistor is electrically connected to the second drive signal output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal.

[0127] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0128] The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal of the first capacitor is electrically connected to the first drive signal output terminal.

[0129] The first end of the second capacitor is electrically connected to the pull-up node, and the second end of the second capacitor is electrically connected to the second drive signal output terminal.

[0130] Optionally, the third energy storage circuit includes a third capacitor;

[0131] The first end of the third capacitor is electrically connected to the pull-up node, and the second end of the third capacitor is electrically connected to the pull-up control terminal.

[0132] Optionally, the output circuit includes a third transistor and a fourth transistor;

[0133] The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the first output clock signal terminal, and the second electrode of the third transistor is electrically connected to the first drive signal output terminal.

[0134] The control electrode of the fourth transistor is electrically connected to the pull-up node, the first electrode of the fourth transistor is electrically connected to the second output clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal.

[0135] Optionally, the output reset circuit includes a fifth transistor and a sixth transistor;

[0136] The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the first drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0137] The control electrode of the sixth transistor is electrically connected to the pull-down node, the first electrode of the sixth transistor is electrically connected to the second drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0138] In at least one embodiment of the present invention, the pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively, for controlling the potential of the pull-down control node under the control of the second control voltage provided by the second control voltage terminal and the potential of the pull-up node, controlling the connection between the pull-down node and the second control voltage terminal under the control of the potential of the pull-down control node, and controlling the connection between the pull-down node and the third voltage terminal under the control of the potential of the pull-up node.

[0139] Optionally, the third voltage terminal can be a low voltage terminal, and the first voltage terminal, the second voltage terminal, and the third voltage terminal can be the same voltage terminal, but this is not a limitation.

[0140] When the driving circuit described in at least one embodiment of the present invention is in operation, the pull-down node control circuit controls the potential of the pull-down control node under the control of the second control voltage and the potential of the pull-up node, and controls the potential of the pull-down node under the control of the potential of the pull-down control node and the potential of the pull-up node.

[0141] In at least one embodiment of the present invention, the pull-up node control circuit is electrically connected to a first control terminal, a second control terminal, a first input voltage terminal, a second input voltage terminal, the pull-down node, the pull-up node, and a fourth voltage terminal, respectively. It is used to control the connection between the pull-up node and the first input voltage terminal under the control of a first control signal provided by the first control terminal, control the connection between the pull-up node and the second input voltage terminal under the control of a second control signal provided by the second control terminal, and control the connection between the pull-up node and the fourth voltage terminal under the control of the potential of the pull-down node.

[0142] Optionally, the fourth voltage terminal can be a low voltage terminal, and the first voltage terminal, the second voltage terminal, the third voltage terminal, and the fourth voltage terminal can be the same voltage terminal, but this is not a limitation.

[0143] When the driving circuit described in at least one embodiment of the present invention is in operation, the pull-up node control circuit, under the control of the first control signal, writes the first input voltage provided by the first input voltage terminal into the pull-up node; under the control of the second control circuit, writes the second input voltage provided by the second input voltage terminal into the pull-up node; and under the control of the potential of the pull-down node, resets the potential of the pull-up node.

[0144] like Figure 6 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown,

[0145] The pull-down node control circuit 12 is electrically connected to the second control voltage terminal GCH, the pull-up node PU, the pull-down node PD, the pull-down control node PD_CN, and the third voltage terminal V3, respectively. It is used to control the potential of the pull-down control node PD_CN under the control of the second control voltage provided by the second control voltage terminal GGH and the potential of the pull-up node PU, control the connection between the pull-down node PD and the second control voltage terminal GCH under the control of the potential of the pull-down control node PD_CN, and control the connection between the pull-down node PD and the third voltage terminal V3 under the control of the potential of the pull-up node PU.

[0146] The pull-up node control circuit 11 is electrically connected to the first control terminal I1, the second control terminal R1, the first input voltage terminal VDS, the second input voltage terminal VSD, the pull-down node PD, the pull-up node PU, and the fourth voltage terminal V4, respectively. It is used to control the connection between the pull-up node PU and the first input voltage terminal VDS under the control of the first control signal provided by the first control terminal I1, control the connection between the pull-up node PU and the second input voltage terminal VSD under the control of the second control signal provided by the second control terminal R1, and control the connection between the pull-up node PU and the fourth voltage terminal V4 under the control of the potential of the pull-down node PD.

[0147] Optionally, the pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0148] The control electrode and the first electrode of the seventh transistor are both electrically connected to the second control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the pull-down control node;

[0149] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the pull-down control node, and the second electrode of the eighth transistor is electrically connected to the third voltage terminal.

[0150] The control electrode of the ninth transistor is electrically connected to the pull-down control node, the first electrode of the ninth transistor is electrically connected to the second control voltage terminal, and the second electrode of the ninth transistor is electrically connected to the pull-down node.

[0151] The control electrode of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage terminal.

[0152] Optionally, the pull-up node control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0153] The control electrode of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the first input voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the pull-up node.

[0154] The control electrode of the twelfth transistor is electrically connected to the second control terminal, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the second input voltage terminal.

[0155] The control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the fourth voltage terminal.

[0156] like Figure 7 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a pull-up node noise reduction circuit 41;

[0157] The pull-up node noise reduction circuit 41 is electrically connected to the pull-up node PU, the frame start terminal STV0 and the fourth voltage terminal V4 respectively, and is used to control the connection between the pull-up node PU and the fourth voltage terminal V4 under the control of the frame start signal provided by the frame start terminal STV0.

[0158] The present invention is as follows Figure 4 In at least one embodiment of the driving circuit shown, before the start of a frame time, the pull-up node noise reduction circuit 41 reduces the potential of the pull-up node PU under the control of the frame start signal.

[0159] Optionally, the pull-up node noise reduction circuit includes a fourteenth transistor;

[0160] The control electrode of the fourteenth transistor is electrically connected to the frame start terminal, the first electrode of the fourteenth transistor is electrically connected to the pull-up node, and the second electrode of the fourteenth transistor is electrically connected to the fourth voltage terminal.

[0161] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown,

[0162] The output noise reduction circuit includes a first transistor M1 and a second transistor M2;

[0163] The gate of the first transistor M1 is electrically connected to the first control voltage terminal GCL, the source of the first transistor M1 is electrically connected to the first drive signal output terminal ON, and the drain of the first transistor M1 is electrically connected to the low voltage terminal VGL.

[0164] The gate of the second transistor M2 is electrically connected to the first control voltage terminal GCL, the source of the second transistor M2 is electrically connected to the second drive signal output terminal ON+1, and the drain of the second transistor M2 is electrically connected to the low voltage terminal VGL.

[0165] The first energy storage circuit 21 includes a first capacitor C1, and the second energy storage circuit 22 includes a second capacitor C2;

[0166] The first end of the first capacitor C1 is electrically connected to the pull-up node PU, and the second end of the first capacitor C1 is electrically connected to the first drive signal output terminal ON.

[0167] The first end of the second capacitor C2 is electrically connected to the pull-up node PU, and the second end of the second capacitor C2 is electrically connected to the second drive signal output terminal ON+1.

[0168] The output circuit includes a third transistor M3 and a fourth transistor M4;

[0169] The gate of the third transistor M3 is electrically connected to the pull-up node PU, the source of the third transistor M3 is electrically connected to the first output clock signal terminal KN, and the drain of the third transistor M3 is electrically connected to the first drive signal output terminal ON.

[0170] The gate of the fourth transistor M4 is electrically connected to the pull-up node PU, the source of the fourth transistor M4 is electrically connected to the second output clock signal terminal KN+1, and the drain of the fourth transistor M4 is electrically connected to the second drive signal output terminal ON+1.

[0171] The output reset circuit includes a fifth transistor M5 and a sixth transistor M6;

[0172] The gate of the fifth transistor M5 is electrically connected to the pull-down node PD, the source of the fifth transistor M5 is electrically connected to the first drive signal output terminal ON, and the drain of the fifth transistor M5 is electrically connected to the low voltage terminal VGL.

[0173] The gate of the sixth transistor M6 is electrically connected to the pull-down node PD, the source of the sixth transistor M6 is electrically connected to the second drive signal output terminal ON+1, and the drain of the sixth transistor M6 is electrically connected to the low voltage terminal VGL.

[0174] The pull-down node control circuit 12 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

[0175] The gate and source of the seventh transistor M7 are both electrically connected to the second control voltage terminal GCH, and the drain of the seventh transistor M7 is electrically connected to the pull-down control node PD_CN.

[0176] The gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the source of the eighth transistor M8 is electrically connected to the pull-down control node PD_CN, and the drain of the eighth transistor M8 is electrically connected to the low voltage terminal VGL.

[0177] The gate of the ninth transistor M9 is electrically connected to the pull-down control node PD_CN, the source of the ninth transistor M9 is electrically connected to the second control voltage terminal GCH, and the drain of the ninth transistor M9 is electrically connected to the pull-down node PD.

[0178] The gate of the tenth transistor M10 is electrically connected to the pull-up node PU, the source of the tenth transistor M10 is electrically connected to the pull-down node PD, and the second terminal of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0179] The pull-up node control circuit 11 includes an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13;

[0180] The gate of the eleventh transistor M11 is electrically connected to the first control terminal I1, the source of the eleventh transistor M11 is electrically connected to the first input voltage terminal VDS, and the drain of the eleventh transistor M11 is electrically connected to the pull-up node PU.

[0181] The gate of the twelfth transistor M12 is electrically connected to the second control terminal R1, the source of the twelfth transistor M12 is electrically connected to the pull-up node PU, and the drain of the twelfth transistor M12 is electrically connected to the second input voltage terminal VSD.

[0182] The gate of the thirteenth transistor M13 is electrically connected to the pull-down node PD, the source of the thirteenth transistor M13 is electrically connected to the pull-up node PU, and the drain of the thirteenth transistor M13 is electrically connected to the low voltage terminal VGL.

[0183] The pull-up node noise reduction circuit 41 includes a fourteenth transistor M14;

[0184] The gate of the fourteenth transistor M14 is electrically connected to the frame start terminal STV0, the source of the fourteenth transistor M14 is electrically connected to the pull-up node PU, and the drain of the fourteenth transistor M14 is electrically connected to the low voltage terminal VGL.

[0185] exist Figure 8 In at least one embodiment of the driving circuit shown, all transistors may be n-type transistors, but are not limited thereto.

[0186] The present invention is as follows Figure 8 At least one embodiment of the driving circuit shown adds a second transistor M2, a fourth transistor M4, a sixth transistor M6, and a second capacitor C2 to enable dual driving signal output. The circuit is changed from an 11T1C single-drive circuit to a 14T2C dual-drive circuit, reducing the number of transistors used in the driving circuit that provides two driving signals, and achieving narrow bezels and low power consumption.

[0187] In the present invention as Figure 8 In at least one embodiment of the driving circuit shown, the 11T1C single-stage single-drive circuit is converted into a 14T2C single-stage dual-drive circuit, which reduces the number of transistors used to achieve two-stage drive signal output, effectively reducing the bezel size. The bezel size can be reduced by 1500um, which can be used as an implementation scheme for ultra-narrow bezels in actual product design.

[0188] Furthermore, compared to the 11T1C single-stage drive circuit, the 14T2C single-stage drive circuit uses 8 fewer transistors to achieve two-stage drive signal output, which means it reduces the power consumption of 8 transistors. Through simulation, power consumption can be reduced by 20%.

[0189] It should be noted that this example illustrates a single-stage dual-drive circuit scheme. Optionally, this scheme could also be a single-stage triple-drive or multi-stage drive scheme, that is, adding structures including M4, M6, and C2 as an additional new stage of output to the circuit. This is not limited here.

[0190] In addition, when the drive module including the drive circuit described in at least one embodiment of the present invention is working, the power consumption of the output clock signal lines can be reduced by increasing the number of output clock signal lines used, for example, changing from using 8 output clock signal lines to using 16 output clock signal lines. By reducing the frequency of the output clock signal, the power consumption of the output clock signal lines can be reduced. Through simulation, the power consumption of GOA can be reduced by 35%.

[0191] The present invention is as follows Figure 8 The driving circuit shown is capable of bidirectional scanning. When VDS provides a high voltage signal and VSD provides a low voltage signal, the driving circuit can perform forward scanning. When VSD provides a low voltage signal and VSD provides a high voltage signal, the driving circuit can perform reverse scanning.

[0192] like Figure 9 As shown, the present invention is as follows Figure 8 When at least one embodiment of the driving circuit shown is in operation, and VDS provides a high voltage signal and VSD provides a low voltage signal, the display cycle may include an input phase S1, a first output phase S2, a second output phase S3 and a reset phase S4 set sequentially.

[0193] During the input phase S1, I1 provides a high voltage signal, R1 provides a low voltage signal, M12 is turned off, and M11 is turned on, controlling the connection between the pull-up node PU and VDS. At this time, the potential of PU rises in the first order. M3 and M4 are turned on, but at this time KN and KN+1 both provide low voltage signals, so ON and ON+1 have no output.

[0194] During input phase S1, GCH provides a high voltage signal, M7 and M8 are turned on, PD_CN is at a low voltage, M9 is turned off, M10 is turned on, PD is at a low voltage; M13 and M5 are turned off, and M6 is turned off.

[0195] In the first output stage S2, KN provides a high voltage signal, KN+1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, ON outputs a high voltage signal, ON+1 outputs a low voltage signal, and the potential of PU is raised in two stages.

[0196] In the first output stage S2, GCH provides a high voltage signal, M7 and M8 are turned on, PD_CN is at a low voltage, M9 is turned off, M10 is turned on, PD is at a low voltage; M13 and M5 are turned off, and M6 is turned off.

[0197] In the second output stage S3, KN provides a low voltage signal, KN+1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, ON outputs a low voltage signal, and ON+1 outputs a high voltage signal.

[0198] In the second output stage S3, GCH provides a high voltage signal, M7 and M8 are turned on, PD_CN is at a low voltage, M9 is turned off, M10 is turned on, PD is at a low voltage; M13 and M5 are turned off, and M6 is turned off.

[0199] During the reset phase S4, I1 provides a low voltage signal, R1 provides a high voltage signal, M11 is turned off, and M12 is turned on to pull the potential of PU low; GCH provides a high voltage signal, M7 is turned on, M8 is turned off, the potential of PD_CN is high, M9 is turned on, M10 is turned off, the potential of PD is high; M13 is turned on; M3 and M4 are turned off, M5 and M6 are turned on, and both ON and ON+1 output low voltage signals.

[0200] During the display cycle (which can be one frame), STV0 provides a low voltage signal, and M14 is turned off. Before the start of the display cycle, STV0 provides a high voltage signal, and M14 is turned off, to control the pull-up node PU to connect to a low voltage, so that the potential of the pull-up node PU is low.

[0201] The present invention is as follows Figure 8 In at least one embodiment of the driving circuit shown, when in operation, the first control voltage can be inverted with the second control voltage. During a portion of the blank time period set between two adjacent frames, GCL provides a high voltage signal, GCH provides a low voltage signal, and M1 and M2 are turned on to control both ON and ON+1 to output low voltage signals. During one frame, GCH provides a high voltage signal, GCL provides a low voltage signal, and M1 and M2 are turned off.

[0202] In at least one embodiment of the present invention, the first control voltage is out of phase with the second control voltage, the pulse width of the high level of the first control voltage is the same as the pulse width of the low level of the second control voltage, and the pulse width of the low level of the first control voltage is the same as the pulse width of the high level of the second control voltage.

[0203] Figure 10 This invention is as follows Figure 8 When at least one embodiment of the driving circuit shown is in operation, and the duty cycle of the first output clock signal provided by KN and the duty cycle of the second output clock signal provided by KN+1 are both 25%, the simulated waveforms of the potential of PU, the potential of PD, the first driving signal output by ON, and the second driving signal output by ON+1 are shown.

[0204] like Figure 10As shown, since the duty cycle of the first output clock signal and the duty cycle of the second output clock signal are both 25%, and the high-level time of the first output clock signal and the high-level time of the second output clock signal do not overlap, the potential of PU is a normal two-stage rise. At this time, the first drive signal output by ON and the second drive signal output by ON+1 are normal.

[0205] Figure 11 This invention is as follows Figure 8 When at least one embodiment of the driving circuit shown is in operation, and the duty cycle of the first output clock signal provided by KN and the duty cycle of the second output clock signal provided by KN+1 are both 45%, the simulated waveforms of the potential of PU, the potential of PD, the first driving signal output by ON, and the second driving signal output by ON+1 are shown.

[0206] like Figure 11 As shown, since the duty cycle of the first output clock signal and the duty cycle of the second output clock signal are both 45%, the high-level time of the first output clock signal overlaps with the high-level time of the second output clock signal. Therefore, the potential of the PU experiences a third-order rise. At this time, the first drive signal output by ON and the second drive signal output by ON+1 are normal. (Reference) Figure 11 or Figure 4 , Figure 8 or Figure 13 The first-order rise of PU's potential is caused by: M11 being turned on and VDS inputting a high level, at which point PU's potential is raised in the first order. Next, when M3 is turned on and KN inputs a corresponding high level, PU's potential is coupled through the first capacitor C1, at which point PU's potential is raised in the second order. When M4 is turned on and KN+1 inputs a high level, PU's potential is coupled through the second capacitor C2, at which point PU's potential is raised in the third order. Simultaneously, PU's potential drops in three orders (the rising third order is considered the falling first order). The reason for the drop from the first order to the second order is the falling edge of the signal provided by ON. The reason for the drop from the second order to the third order is the falling edge of the signal provided by ON+1. The reason for the drop from the third order to the low level signal is the low level signal provided by ON+1.

[0207] like Figure 12 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a third energy storage circuit 30;

[0208] The first end of the third energy storage circuit 30 is electrically connected to the pull-up node PU, and the second end of the third energy storage circuit 30 is electrically connected to the pull-up control terminal. The third energy storage circuit 30 is used to store electrical energy.

[0209] The pull-up control terminal is electrically connected to the first drive signal output terminal ON+2 of the adjacent next-stage drive circuit.

[0210] This invention Figure 13 At least one embodiment of the driving circuit shown is related to the present invention. Figure 8 The difference in at least one embodiment of the driving circuit shown is that:

[0211] This invention Figure 13 At least one embodiment of the driving circuit shown further includes a third energy storage circuit 30;

[0212] The third energy storage circuit 30 includes a third capacitor C3;

[0213] The first end of the third capacitor C3 is electrically connected to the pull-up node PU, and the second end of the third capacitor C3 is electrically connected to the first drive signal output terminal ON+2 of the adjacent next-stage drive circuit.

[0214] The driving method described in this embodiment of the invention is applied to the aforementioned driving circuit, and the driving method includes:

[0215] The pull-up node control circuit controls the potential of the pull-up node;

[0216] The pull-down node control circuit controls the potential of the pull-down node;

[0217] Under the control of the potential of the pull-up node, the output circuit controls the output of the first output clock signal provided by the first output clock signal terminal to the first drive signal output terminal. Under the control of the potential of the pull-up node, the output circuit controls the output of the second output clock signal provided by the second output clock signal terminal to the second drive signal output terminal.

[0218] Under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal provided by the first voltage terminal to the first drive signal output terminal, and under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal to the second drive signal output terminal.

[0219] Under the control of the first control voltage provided by the first control voltage terminal, the output noise reduction circuit controls the connection between the first drive signal output terminal and the second voltage terminal. Under the control of the first control voltage, the output noise reduction circuit controls the connection between the second drive signal output terminal and the second voltage terminal.

[0220] In at least one embodiment of the present invention, the pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively; the driving method further includes:

[0221] The pull-down node control circuit controls the potential of the pull-down control node under the control of the second control voltage provided at the second control voltage terminal and the potential of the pull-up node. Under the control of the potential of the pull-down control node, the pull-down node control circuit controls the connection between the pull-down node and the second control voltage terminal, and under the control of the potential of the pull-up node, controls the connection between the pull-down node and the third voltage terminal.

[0222] In at least one embodiment of the present invention, the first control voltage is out of phase with the second control voltage; a blank time period is provided between two adjacent display cycles, the blank time period including a frame reset phase; the driving method further includes:

[0223] During the frame reset phase, the output noise reduction circuit, under the control of the first control voltage, controls the connection between the first drive signal output terminal and the second voltage terminal to reset the first drive signal output by the first drive signal output terminal.

[0224] Under the control of the first control voltage, the output noise reduction circuit controls the connection between the second drive signal output terminal and the second voltage terminal to reset the second drive signal output by the second drive signal output terminal;

[0225] During the display cycle, the pull-down node control circuit, under the control of the potential of the second control voltage, controls the writing of the second control voltage into the pull-down control node.

[0226] In specific implementation, the first control voltage and the second control voltage can be out of phase. At this time, the pulse width of the high level of the first control voltage is the same as the pulse width of the low level of the second control voltage, and the pulse width of the low level of the first control voltage is the same as the pulse width of the high level of the second control voltage.

[0227] In at least one embodiment of the present invention, the display period can be one frame display time, but this is not an example.

[0228] The driving module described in this embodiment of the invention includes A driving units, where A equals 1 or 2; each driving unit includes multiple levels of the aforementioned driving circuits.

[0229] In at least one embodiment of the present invention, when the driving module includes a driving unit, the driving unit may be disposed on the left side of the display area or the right side of the display area;

[0230] When the driving module includes two driving units, the first driving unit can be located on the right side of the display area and the second driving unit can be located on the left side of the display area; or, the first driving unit can be located on the left side of the display area and the second driving unit can be located on the right side of the display area.

[0231] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to eight output clock signal lines;

[0232] The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1.

[0233] The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal;

[0234] The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit.

[0235] The second drive unit includes a first control terminal of a first-stage drive circuit that is connected to a second start signal.

[0236] In specific implementation, when the drive module is electrically connected to eight output clock signal lines, the first drive unit can be electrically connected to the odd-numbered output clock signal line, and the second drive unit can be electrically connected to the even-numbered output clock signal line. The second control terminal of the drive circuit in the first drive unit is electrically connected to the second drive signal output terminal of the adjacent next-level drive circuit in the first drive unit. The first control terminal of the drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the adjacent previous-level drive circuit in the first drive unit. The second control terminal of the drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the adjacent next-level drive circuit included in the second drive unit. The first control terminal of the drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the adjacent previous-level drive circuit included in the second drive unit.

[0237] In at least one embodiment of the present invention, when the driving module is electrically connected to eight output clock signal lines, the second f-1 driving circuit included in the first driving unit is electrically connected to the eighth f-7 output clock signal line and the eighth f-5 output clock signal line respectively, and the second f driving circuit included in the first driving unit is electrically connected to the eighth f-3 output clock signal line and the eighth f-1 output clock signal line respectively.

[0238] The second driving unit includes a 2f-1 driving circuit that is electrically connected to the 8f-6 output clock signal line and the 8f-4 output clock signal line, respectively. The second driving unit also includes a 2f driving circuit that is electrically connected to the 8f-2 output clock signal line and the 8f output clock signal line, respectively.

[0239] Where f is a positive integer.

[0240] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to twelve output clock signal lines;

[0241] The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the first driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1.

[0242] The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal;

[0243] The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the first drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit.

[0244] The second drive unit includes a first control terminal of a first-stage drive circuit that is connected to a second start signal.

[0245] In a specific implementation, when the drive module is electrically connected to the twelve output clock signal lines, the first drive unit can be electrically connected to the odd-numbered output clock signal line, and the second drive unit can be electrically connected to the even-numbered output clock signal line. The second control terminal of the drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the adjacent next-level drive circuit included in the first drive unit, and the first control terminal of the drive circuit included in the first drive unit is electrically connected to the first drive signal output terminal of the adjacent previous-level drive circuit included in the first drive unit. The second control terminal of the drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the adjacent next-level drive circuit included in the second drive unit, and the first control terminal of the drive circuit included in the second drive unit is electrically connected to the first drive signal output terminal of the adjacent previous-level drive circuit included in the second drive unit.

[0246] In at least one embodiment of the present invention, when the driving module is electrically connected to twelve output clock signal lines, the 3f-2 driving circuit included in the first driving unit is electrically connected to the 12f-11 and 12f-9 output clock signal lines respectively, the 3f-1 driving circuit included in the first driving unit is electrically connected to the 12f-7 and 12f-5 output clock signal lines respectively, and the 3f driving circuit included in the first driving unit is electrically connected to the 12f-3 and 12f-1 output clock signal lines respectively.

[0247] The second driving unit includes a 3f-2 driving circuit that is electrically connected to the 12f-10 output clock signal line and the 12f-8 output clock signal line, respectively; the second driving unit includes a 3f-1 driving circuit that is electrically connected to the 12f-6 output clock signal line and the 12f-4 output clock signal line, respectively; and the second driving unit includes a 3f driving circuit that is electrically connected to the 12f-2 output clock signal line and the 12f output clock signal line, respectively.

[0248] Where f is a positive integer.

[0249] Optionally, the drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to sixteen output clock signal lines;

[0250] The second control terminal of the d-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (d+2)-th stage drive circuit included in the first drive unit, and the first control terminal of the e-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (e-2)-th stage drive circuit included in the first drive unit; d is a positive integer, and e is an integer greater than 2;

[0251] The first control terminal of the first stage driving circuit of the first driving unit is connected to a first start signal; the first control terminal of the second stage driving circuit of the first driving unit is connected to a third start signal.

[0252] The second control terminal of the d-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the d+2-th stage drive circuit included in the second drive unit, and the first control terminal of the e-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the e-2-th stage drive circuit included in the second drive unit.

[0253] The first control terminal of the first-stage drive circuit of the second drive unit is connected to a second start signal, and the first control terminal of the second-stage drive circuit of the second drive unit is connected to a fourth start signal.

[0254] In a specific implementation, when the drive module is electrically connected to the sixteen output clock signal lines, the first drive unit can be electrically connected to the odd-numbered output clock signal line, and the second drive unit can be electrically connected to the even-numbered output clock signal line. The second control terminal of the drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the adjacent two-stage drive circuits included in the first drive unit, and the first control terminal of the drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the adjacent two-stage drive circuits included in the first drive unit. The second control terminal of the drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the adjacent two-stage drive circuits included in the second drive unit, and the first control terminal of the drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the adjacent two-stage drive circuits included in the second drive unit.

[0255] In at least one embodiment of the present invention, when the driving module is electrically connected to sixteen output clock signal lines, the 4f-3 driving circuit included in the first driving unit is electrically connected to the 16f-15 and 16f-13 output clock signal lines respectively, the 4f-2 driving circuit included in the first driving unit is electrically connected to the 16f-11 and 16f-9 output clock signal lines respectively, the 4f-1 driving circuit included in the first driving unit is electrically connected to the 16f-7 and 16f-5 output clock signal lines respectively, and the 4f driving circuit included in the first driving unit is electrically connected to the 16f-3 and 16f-2 output clock signal lines respectively.

[0256] The second driving unit includes a 4f-3 driving circuit that is electrically connected to the 16f-14 and 16f-12 output clock signal lines respectively; a 4f-2 driving circuit that is electrically connected to the 16f-10 and 16f-8 output clock signal lines respectively; a 4f-1 driving circuit that is electrically connected to the 16f-6 and 16f-4 output clock signal lines respectively; and a 4f driving circuit that is electrically connected to the 16f-2 and 16f output clock signal lines respectively.

[0257] Where f is a positive integer.

[0258] Optionally, the pull-up control terminal of the b-th stage drive circuit included in the first drive unit can be electrically connected to the first drive signal output terminal of the b+1-th stage drive circuit included in the first drive unit.

[0259] The following description uses the example of a drive module comprising two drive units.

[0260] When the driving module uses eight output clock signal lines: first output clock signal line K1, second output clock signal line K2, third output clock signal line K3, fourth output clock signal line K4, fifth output clock signal line K5, sixth output clock signal line K6, seventh output clock signal line K7 and eighth output clock signal line K8, the driving module may include a first driving unit and a second driving unit, with the first driving unit located on the right side of the display area and the second driving unit located on the left side of the display area;

[0261] Figure 14 This is a schematic diagram showing the connection relationship between the first-stage driving circuit G11 and the second-stage driving circuit G12 included in the first driving unit, and a schematic diagram showing the connection relationship between the first-stage driving circuit G21 and the second-stage driving circuit G22 included in the second driving unit.

[0262] like Figure 14 As shown, G11 is electrically connected to K1 and K3 respectively. The first control terminal of G11 is connected to the first start signal STV1. The second control terminal of G11 is electrically connected to the seventh-level drive signal output terminal O7. The first drive signal output terminal of G11 is electrically connected to the first-level drive signal output terminal O1. The second drive signal output terminal of G11 is electrically connected to the third-level drive signal output terminal O3.

[0263] G12 is electrically connected to K5 and K7 respectively. The first control terminal of G12 is electrically connected to O3. The first drive signal output terminal of G12 is electrically connected to the fifth-level drive signal output terminal O5. The second drive signal output terminal of G12 is electrically connected to the seventh-level drive signal output terminal O7.

[0264] G21 is electrically connected to K2 and K4 respectively. The first control terminal of G21 is connected to the second start signal STV2. The second control terminal of G21 is electrically connected to the eighth-level drive signal output terminal O8. The first drive signal output terminal of G21 is electrically connected to the second-level drive signal output terminal O2. The second drive signal output terminal of G21 is electrically connected to the fourth-level drive signal output terminal O4.

[0265] G22 is electrically connected to K6 and K8 respectively. The first control terminal of G22 is electrically connected to O4. The first drive signal output terminal of G22 is electrically connected to the sixth-level drive signal output terminal O6. The second drive signal output terminal of G22 is electrically connected to the eighth-level drive signal output terminal O8.

[0266] exist Figure 14 In the diagram, the circuit labeled 90 is the control signal generation circuit, which is used to provide the aforementioned output clock signals.

[0267] Figure 15 yes Figure 14The timing diagram of each output clock signal, STV1, STV2, frame start signal provided by frame start terminal STV0, first input voltage provided by VDS, second input voltage provided by VSD, second control voltage provided by GCH, first control voltage provided by GCL, and low voltage signal provided by VGL.

[0268] exist Figure 15 In this context, SM represents the time of frame M, SM+1 represents the time of frame M+1, and B0 represents the blank time period between SM and SM+1, where M is a positive integer. (Reference) Figure 15 The potential of the frame start signal provided by STV0 can be raised both at the end of a frame and before the start of a frame to achieve noise reduction for the PU. Alternatively, the potential of the frame start signal provided by STV0 can be raised once at the end of a frame and before the start of a frame to achieve noise reduction for the PU. No limitation is made here. During the blank period, the potential of the first control voltage provided by GCL is raised at least during the blank period. During the period when the potential of the first control voltage provided by GCL is raised, the potential of the second control voltage provided by GCH is correspondingly lowered to achieve noise reduction for ON and ON+1.

[0269] Figure 16 This is a schematic diagram showing the cascade relationship of two adjacent drive circuits in the first drive unit when the drive module uses eight output clock signal lines.

[0270] exist Figure 16 In the diagram, G11 represents the first-stage driving circuit included in the first driving unit, and G12 represents the second-stage driving circuit included in the first driving unit.

[0271] like Figure 16 As shown, the second control terminal of G11 is electrically connected to the second drive signal output terminal of G12, and the second drive signal output terminal of G11 is electrically connected to the first control terminal of G12.

[0272] exist Figure 16 In the middle, the first drive signal output terminal of G11 is electrically connected to O1, the second drive signal output terminal of G11 is electrically connected to O3, the first output clock signal terminal of G11 is electrically connected to K1, and the second output clock signal terminal of G11 is electrically connected to K3.

[0273] The first drive signal output terminal of G12 is electrically connected to O5, the second drive signal output terminal of G12 is electrically connected to O7, the first output clock signal terminal of G12 is electrically connected to K5, and the second output clock signal terminal of G12 is electrically connected to K7.

[0274] Figure 17This is a schematic diagram showing the cascade relationship of two adjacent drive circuits in the first drive unit when the drive module uses eight output clock signal lines.

[0275] exist Figure 17 In the diagram, G11 represents the first-stage driving circuit included in the first driving unit, and G12 represents the second-stage driving circuit included in the first driving unit.

[0276] like Figure 17 As shown, the second control terminal of G11 is electrically connected to the second drive signal output terminal of G12, and the second drive signal output terminal of G11 is electrically connected to the first control terminal of G12.

[0277] exist Figure 17 In the middle, the first drive signal output terminal of G11 is electrically connected to O1, the second drive signal output terminal of G11 is electrically connected to O3, the first output clock signal terminal of G11 is electrically connected to K1, and the second output clock signal terminal of G11 is electrically connected to K3.

[0278] The first drive signal output terminal of G12 is electrically connected to O5, the second drive signal output terminal of G12 is electrically connected to O7, the first output clock signal terminal of G12 is electrically connected to K5, and the second output clock signal terminal of G12 is electrically connected to K7.

[0279] The pull-up control terminal of G11 is electrically connected to the first drive signal output terminal of G12, that is, the pull-up control terminal of G11 is electrically connected to O5.

[0280] The pull-up control terminal of G12 is electrically connected to the ninth-stage drive signal output terminal O9;

[0281] The first drive unit includes a third-stage drive circuit whose first drive signal output terminal is electrically connected to the ninth-stage drive signal output terminal O9.

[0282] When the driving module uses sixteen output clock signal lines: first output clock signal line K1, second output clock signal line K2, third output clock signal line K3, fourth output clock signal line K4, fifth output clock signal line K5, sixth output clock signal line K6, seventh output clock signal line K7, eighth output clock signal line K8, ninth output clock signal line K9, tenth output clock signal line K10, eleventh output clock signal line K11, twelfth output clock signal line K12, thirteenth output clock signal line K13, fourteenth output clock signal line K14, fifteenth output clock signal line K15 and sixteenth output clock signal line K16, the driving module may include a first driving unit and a second driving unit. The first driving unit is located on the right side of the display area, and the second driving unit is located on the left side of the display area.

[0283] Figure 18 This is a schematic diagram showing the connection relationship of the first-stage driving circuit G11, the second-stage driving circuit G12, the third-stage driving circuit G13, and the fourth-stage driving circuit G14 included in the first driving unit; and a schematic diagram showing the connection relationship of the first-stage driving circuit G21, the second-stage driving circuit G22, the third-stage driving circuit G23, and the fourth-stage driving circuit G24 included in the second driving unit.

[0284] like Figure 18 As shown, G11 is electrically connected to K1 and K3 respectively. The first control terminal of G11 is connected to the first start signal STV1. The second control terminal of G11 is electrically connected to the eleventh-level drive signal output terminal O11. The first drive signal output terminal of G11 is electrically connected to the first-level drive signal output terminal O1. The second drive signal output terminal of G11 is electrically connected to the third-level drive signal output terminal O3.

[0285] G12 is electrically connected to K5 and K7 respectively. The first control terminal of G12 is connected to the third start signal STV3. The second control terminal of G12 is electrically connected to the fifteenth-level drive signal output terminal O15. The first drive signal output terminal of G12 is electrically connected to the fifth-level drive signal output terminal O5. The second drive signal output terminal of G12 is electrically connected to the seventh-level drive signal output terminal O7.

[0286] G13 is electrically connected to K9 and K11 respectively; the first control terminal of G13 is electrically connected to O3; the first drive signal output terminal of G13 is electrically connected to the ninth-level drive signal output terminal O9; and the second drive signal output terminal of G13 is electrically connected to the eleventh-level drive signal output terminal O11.

[0287] G14 is electrically connected to K13 and K17 respectively; the first control terminal of G14 is electrically connected to O7; the first drive signal output terminal of G14 is electrically connected to the thirteenth-level drive signal output terminal O13; and the second drive signal output terminal of G14 is electrically connected to the fifteenth-level drive signal output terminal O15.

[0288] G21 is electrically connected to K2 and K4 respectively. The first control terminal of G21 is connected to the second start signal STV2. The second control terminal of G21 is electrically connected to the eleventh-level drive signal output terminal O12. The first drive signal output terminal of G21 is electrically connected to the second-level drive signal output terminal O2. The second drive signal output terminal of G21 is electrically connected to the fourth-level drive signal output terminal O4.

[0289] G22 is electrically connected to K6 and K8 respectively. The first control terminal of G22 is connected to the fourth start signal STV4. The second control terminal of G22 is electrically connected to the sixteenth-level drive signal output terminal O16. The first drive signal output terminal of G22 is electrically connected to the sixth-level drive signal output terminal O6. The second drive signal output terminal of G22 is electrically connected to the eighth-level drive signal output terminal O8.

[0290] G23 is electrically connected to K10 and K12 respectively. The first control terminal of G23 is electrically connected to O4. The first drive signal output terminal of G23 is electrically connected to the tenth-level drive signal output terminal O10. The second drive signal output terminal of G23 is electrically connected to the twelfth-level drive signal output terminal O12.

[0291] G24 is electrically connected to K14 and K16 respectively. The first control terminal of G24 is electrically connected to O8. The first drive signal output terminal of G24 is electrically connected to the fourteenth-level drive signal output terminal O14. The second drive signal output terminal of G24 is electrically connected to the sixteenth-level drive signal output terminal O16.

[0292] exist Figure 18 In the diagram, the circuit labeled 90 is the control signal generation circuit, which is used to provide the aforementioned output clock signals.

[0293] Figure 19 yes Figure 18 The timing diagram of each output clock signal, STV1, STV2, frame start signal provided by frame start terminal STV0, first input voltage provided by VDS, second input voltage provided by VSD, second control voltage provided by GCH, first control voltage provided by GCL, and low voltage signal provided by VGL.

[0294] exist Figure 19 In the table, SM represents the time of frame M, SM+1 represents the time of frame M+1, and B0 represents the blank time period set between SM and SM+1, where M is a positive integer.

[0295] When the driving module uses twelve output clock signal lines: first output clock signal line K1, second output clock signal line K2, third output clock signal line K3, fourth output clock signal line K4, fifth output clock signal line K5, sixth output clock signal line K6, seventh output clock signal line K7, eighth output clock signal line K8, ninth output clock signal line K9, tenth output clock signal line K10, eleventh output clock signal line K11 and twelfth output clock signal line K12, the driving module may include a first driving unit and a second driving unit. The first driving unit is disposed on the right side of the display area, and the second driving unit is disposed on the left side of the display area.

[0296] Figure 20 It is a schematic diagram showing the connection relationship of the first-stage driving circuit G11, the second-stage driving circuit G12, and the third-stage driving circuit G13 included in the first driving unit, and a schematic diagram showing the connection relationship of the first-stage driving circuit G21, the second-stage driving circuit G22, and the third-stage driving circuit G23 included in the second driving unit.

[0297] like Figure 20 As shown, G11 is electrically connected to K1 and K3 respectively. The first control terminal of G11 is connected to the first start signal STV1. The second control terminal of G11 is electrically connected to the seventh-level drive signal output terminal O7. The first drive signal output terminal of G11 is electrically connected to the first-level drive signal output terminal O1. The second drive signal output terminal of G11 is electrically connected to the third-level drive signal output terminal O3.

[0298] G12 is electrically connected to K5 and K7 respectively. The first control terminal of G12 is electrically connected to O1. The second control terminal of G12 is electrically connected to the eleventh-level drive signal output terminal O11. The first drive signal output terminal of G12 is electrically connected to the fifth-level drive signal output terminal O5. The second drive signal output terminal of G12 is electrically connected to the seventh-level drive signal output terminal O7.

[0299] G13 is electrically connected to K9 and K11 respectively; the first control terminal of G13 is electrically connected to O5; the first drive signal output terminal of G13 is electrically connected to the ninth-level drive signal output terminal O9; and the second drive signal output terminal of G13 is electrically connected to the eleventh-level drive signal output terminal O11.

[0300] G21 is electrically connected to K2 and K4 respectively. The first control terminal of G21 is connected to the second start signal STV2. The second control terminal of G21 is electrically connected to the eighth-level drive signal output terminal O8. The first drive signal output terminal of G21 is electrically connected to the second-level drive signal output terminal O2. The second drive signal output terminal of G21 is electrically connected to the fourth-level drive signal output terminal O4.

[0301] G22 is electrically connected to K6 and K8 respectively. The first control terminal of G22 is electrically connected to O2. The second control terminal of G22 is electrically connected to the eleventh-level drive signal output terminal O12. The first drive signal output terminal of G22 is electrically connected to the sixth-level drive signal output terminal O6. The second drive signal output terminal of G22 is electrically connected to the eighth-level drive signal output terminal O8.

[0302] G23 is electrically connected to K10 and K12 respectively. The first control terminal of G23 is electrically connected to the sixth-level drive signal output terminal O6. The first drive signal output terminal of G23 is electrically connected to the tenth-level drive signal output terminal O10. The second drive signal output terminal of G23 is electrically connected to the twelfth-level drive signal output terminal O12.

[0303] exist Figure 20 In the diagram, the circuit labeled 90 is the control signal generation circuit, which is used to provide the aforementioned output clock signals.

[0304] The display device described in this embodiment of the invention includes the driving module described above.

[0305] In at least one embodiment of the present invention, the display device may be an A-Si (amorphous silicon) display product, but is not limited thereto.

[0306] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0307] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that, It includes a pull-up node control circuit, a pull-down node control circuit, an output circuit, an output reset circuit, and an output noise reduction circuit; The pull-up node control circuit is electrically connected to the pull-up node and is used to control the potential of the pull-up node; The pull-down node control circuit is electrically connected to the pull-down node and is used to control the potential of the pull-down node; The output circuit is electrically connected to the pull-up node, the first drive signal output terminal, the second drive signal output terminal, the first output clock signal terminal, and the second output clock signal terminal, respectively, and is used to control the connection between the first drive signal output terminal and the first output clock signal terminal, and control the connection between the second drive signal output terminal and the second output clock signal terminal, under the control of the potential of the pull-up node. The output reset circuit is electrically connected to the pull-down node, the first drive signal output terminal, the second drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the first drive signal output terminal and the first voltage terminal and the connection between the second drive signal output terminal and the first voltage terminal under the control of the potential of the pull-down node. The output noise reduction circuit is electrically connected to the first control voltage terminal, the first drive signal output terminal, the second drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the first drive signal output terminal and the second voltage terminal under the control of the first control voltage provided by the first control voltage terminal; The output noise reduction circuit includes a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first control voltage terminal, the first electrode of the first transistor is electrically connected to the first drive signal output terminal, and the second electrode of the first transistor is electrically connected to the second voltage terminal. The control electrode of the second transistor is electrically connected to the first control voltage terminal, the first electrode of the second transistor is electrically connected to the second drive signal output terminal, and the second electrode of the second transistor is electrically connected to the second voltage terminal. The output reset circuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the first drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal. The control electrode of the sixth transistor is electrically connected to the pull-down node, the first electrode of the sixth transistor is electrically connected to the second drive signal output terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

2. The driving circuit as described in claim 1, characterized in that, It also includes a first energy storage circuit and a second energy storage circuit; The first terminal of the first energy storage circuit is electrically connected to the pull-up node, and the second terminal of the first energy storage circuit is electrically connected to the first drive signal output terminal. The first end of the second energy storage circuit is electrically connected to the pull-up node, and the second end of the second energy storage circuit is electrically connected to the second drive signal output terminal.

3. The driving circuit as described in claim 1, characterized in that, It also includes a third energy storage circuit; The first terminal of the third energy storage circuit is electrically connected to the pull-up node, and the second terminal of the third energy storage circuit is electrically connected to the pull-up control terminal. The pull-up control terminal is electrically connected to the first drive signal output terminal of the adjacent lower-level drive circuit.

4. The driving circuit as described in claim 2, characterized in that, The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The first terminal of the first capacitor is electrically connected to the pull-up node, and the second terminal of the first capacitor is electrically connected to the first drive signal output terminal. The first end of the second capacitor is electrically connected to the pull-up node, and the second end of the second capacitor is electrically connected to the second drive signal output terminal.

5. The driving circuit as described in claim 3, characterized in that, The third energy storage circuit includes a third capacitor; The first end of the third capacitor is electrically connected to the pull-up node, and the second end of the third capacitor is electrically connected to the pull-up control terminal.

6. The driving circuit as described in claim 1, characterized in that, The output circuit includes a third transistor and a fourth transistor; The control electrode of the third transistor is electrically connected to the pull-up node, the first electrode of the third transistor is electrically connected to the first output clock signal terminal, and the second electrode of the third transistor is electrically connected to the first drive signal output terminal. The control electrode of the fourth transistor is electrically connected to the pull-up node, the first electrode of the fourth transistor is electrically connected to the second output clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal.

7. The driving circuit according to any one of claims 1 to 6, characterized in that, The pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively. It is used to control the potential of the pull-down control node under the control of the second control voltage provided by the second control voltage terminal and the potential of the pull-up node, control the connection between the pull-down node and the second control voltage terminal under the control of the potential of the pull-down control node, and control the connection between the pull-down node and the third voltage terminal under the control of the potential of the pull-up node.

8. The driving circuit according to any one of claims 1 to 6, characterized in that, The pull-up node control circuit is electrically connected to the first control terminal, the second control terminal, the first input voltage terminal, the second input voltage terminal, the pull-down node, the pull-up node, and the fourth voltage terminal, respectively. It is used to control the connection between the pull-up node and the first input voltage terminal under the control of the first control signal provided by the first control terminal, control the connection between the pull-up node and the second input voltage terminal under the control of the second control signal provided by the second control terminal, and control the connection between the pull-up node and the fourth voltage terminal under the control of the potential of the pull-down node.

9. The driving circuit as described in claim 7, characterized in that, The pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The control electrode and the first electrode of the seventh transistor are both electrically connected to the second control voltage terminal, and the second electrode of the seventh transistor is electrically connected to the pull-down control node; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the pull-down control node, and the second electrode of the eighth transistor is electrically connected to the third voltage terminal. The control electrode of the ninth transistor is electrically connected to the pull-down control node, the first electrode of the ninth transistor is electrically connected to the second control voltage terminal, and the second electrode of the ninth transistor is electrically connected to the pull-down node. The control electrode of the tenth transistor is electrically connected to the pull-up node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the third voltage terminal.

10. The driving circuit as described in claim 8, characterized in that, The pull-up node control circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The control electrode of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the first input voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the pull-up node. The control electrode of the twelfth transistor is electrically connected to the second control terminal, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the second input voltage terminal. The control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the fourth voltage terminal.

11. The driving circuit as described in claim 8, characterized in that, Includes pull-up node noise reduction circuitry; The pull-up node noise reduction circuit is electrically connected to the pull-up node, the frame start terminal, and the fourth voltage terminal, respectively, and is used to control the connection between the pull-up node and the fourth voltage terminal under the control of the frame start signal provided by the frame start terminal.

12. A driving method, applied to the driving circuit as described in any one of claims 1 to 11, characterized in that, The driving method includes: The pull-up node control circuit controls the potential of the pull-up node; The pull-down node control circuit controls the potential of the pull-down node; Under the control of the potential of the pull-up node, the output circuit controls the output of the first output clock signal provided by the first output clock signal terminal to the first drive signal output terminal. Under the control of the potential of the pull-up node, the output circuit controls the output of the second output clock signal provided by the second output clock signal terminal to the second drive signal output terminal. Under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal provided by the first voltage terminal to the first drive signal output terminal, and under the control of the potential of the pull-down node, the output reset circuit controls the output of the first voltage signal to the second drive signal output terminal. Under the control of the first control voltage provided by the first control voltage terminal, the output noise reduction circuit controls the connection between the first drive signal output terminal and the second voltage terminal. Under the control of the first control voltage, the output noise reduction circuit controls the connection between the second drive signal output terminal and the second voltage terminal.

13. The driving method as described in claim 12, characterized in that, The pull-down node control circuit is electrically connected to the second control voltage terminal, the pull-up node, the pull-down node, the pull-down control node, and the third voltage terminal, respectively; the driving method further includes: The pull-down node control circuit controls the potential of the pull-down control node under the control of the second control voltage provided at the second control voltage terminal and the potential of the pull-up node. Under the control of the potential of the pull-down control node, the pull-down node control circuit controls the connection between the pull-down node and the second control voltage terminal, and under the control of the potential of the pull-up node, controls the connection between the pull-down node and the third voltage terminal.

14. The driving method as described in claim 13, characterized in that, The first control voltage is inversely phase to the second control voltage; a blank time period is provided between two adjacent display cycles, the blank time period including a frame reset phase; the driving method further includes: During the frame reset phase, the output noise reduction circuit, under the control of the first control voltage, controls the connection between the first drive signal output terminal and the second voltage terminal, and the output noise reduction circuit, under the control of the first control voltage, controls the connection between the second drive signal output terminal and the second voltage terminal. During the display cycle, the pull-down node control circuit, under the control of the potential of the second control voltage, controls the writing of the second control voltage into the pull-down control node.

15. A drive module, characterized in that, It includes A driving units, where A equals 1 or 2; the driving units include multiple levels of driving circuits as described in any one of claims 1 to 11.

16. The drive module as described in claim 15, characterized in that, The drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to eight output clock signal lines. The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1. The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal; The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit. The first control terminal of the first-stage drive circuit of the second drive unit is connected to the second start signal.

17. The drive module as described in claim 15, characterized in that, The drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to twelve output clock signal lines. The second control terminal of the b-th stage driving circuit included in the first driving unit is electrically connected to the second driving signal output terminal of the b+1-th stage driving circuit included in the first driving unit, and the first control terminal of the c-th stage driving circuit included in the first driving unit is electrically connected to the first driving signal output terminal of the c-1-th stage driving circuit included in the first driving unit; b is a positive integer, and c is an integer greater than 1. The first control terminal of the first stage drive circuit included in the first drive unit is connected to the first start signal; The second control terminal of the b-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the b+1-th stage drive circuit included in the second drive unit, and the first control terminal of the c-th stage drive circuit included in the second drive unit is electrically connected to the first drive signal output terminal of the c-1-th stage drive circuit included in the second drive unit. The first control terminal of the first-stage drive circuit of the second drive unit is connected to the second start signal.

18. The drive module as described in claim 15, characterized in that, The drive module includes a first drive unit and a second drive unit; the drive module is electrically connected to sixteen output clock signal lines. The second control terminal of the d-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (d+2)-th stage drive circuit included in the first drive unit, and the first control terminal of the e-th stage drive circuit included in the first drive unit is electrically connected to the second drive signal output terminal of the (e-2)-th stage drive circuit included in the first drive unit; d is a positive integer, and e is an integer greater than 2; The first control terminal of the first stage driving circuit of the first driving unit is connected to a first start signal; the first control terminal of the second stage driving circuit of the first driving unit is connected to a third start signal. The second control terminal of the d-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the d+2-th stage drive circuit included in the second drive unit, and the first control terminal of the e-th stage drive circuit included in the second drive unit is electrically connected to the second drive signal output terminal of the e-2-th stage drive circuit included in the second drive unit. The first control terminal of the first-stage drive circuit of the second drive unit is connected to a second start signal, and the first control terminal of the second-stage drive circuit of the second drive unit is connected to a fourth start signal.

19. The drive module according to any one of claims 16 to 18, characterized in that, The pull-up control terminal of the b-th stage drive circuit included in the first drive unit is electrically connected to the first drive signal output terminal of the b+1-th stage drive circuit included in the first drive unit.

20. A display device, characterized in that, Includes the drive module as described in any one of claims 15 to 19.

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