Semiconductor memory device

Abstract

An embodiment of the present invention provides a semiconductor memory device with improved reliability. The semiconductor memory device includes a memory cell array (17) including a plurality of memory cells (MC), a word line (WL) connected to the plurality of memory cells, a plurality of bit lines (BL) connected to the plurality of memory cells, respectively, a sense amplifier (19) connected to the plurality of bit lines, and a controller (2) capable of performing a write operation including a repeated program cycle including a program operation and a verify operation. The sense amplifier applies any one of a first voltage (VSS), a second voltage (VQPW1) higher than the first voltage, a third voltage (VQPW2) higher than the second voltage, and a fourth voltage (VHSA) higher than the third voltage to the plurality of bit lines, during a period in which a program voltage (VPGM) is applied to the word line in the program operation.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-059354 (filed on March 31, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] NAND (Not AND) type flash memory is known as a semiconductor memory device. Summary of the Invention

[0005] In one embodiment of the present invention, a semiconductor memory device with improved reliability is provided.

[0006] A semiconductor memory device according to an embodiment includes a memory cell transistor, a word line connected to the gate of the memory cell transistor, a bit line connected to one end of the memory cell transistor, and a sense amplifier unit connected to the bit line. The sense amplifier unit has a sensing circuit connected to the bit line and a latching circuit connected to the sensing circuit. The sensing circuit includes: a first transistor, one end connected to a corresponding bit line and the other end connected to a first node; a second transistor, one end connected to the first node and the other end connected to a second node; a third transistor, one end connected to the second node and the other end of which can be applied with a first voltage; a fourth transistor, one end connected to the second node and the other end connected to a third node; a fifth transistor, one end connected to the first node; and a sixth transistor, one end of which can be applied with a second voltage, the other end connected to the other end of the fifth transistor, and its gate connected to the third node; the third node can be connected to the first latching circuit. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the overall configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of the memory cell array included in the semiconductor memory device of the first embodiment.

[0009] Figure 3 This is a block diagram of the data register and sensing amplifier included in the semiconductor memory device of the first embodiment.

[0010] Figure 4 This is a circuit diagram of the sensing amplifier unit included in the semiconductor memory device of the first embodiment.

[0011] Figure 5 This is a circuit diagram of the voltage generation circuit and sensing circuit included in the semiconductor memory device of the first embodiment.

[0012] Figure 6 This is a conceptual diagram illustrating an example of a data storage method in a semiconductor memory device according to the first embodiment.

[0013] Figure 7 This is a timing diagram showing an overview of the write operation in the semiconductor memory device of the first embodiment.

[0014] Figure 8 This is a table showing an example of the programming cycle setting in the semiconductor memory device of the first embodiment.

[0015] Figure 9 This is a threshold voltage distribution diagram showing the relationship between the three verification voltages used in each write state and the three programming operations during the write operation of the semiconductor memory device in the first embodiment.

[0016] Figure 10 This is a conceptual diagram illustrating the changes in the threshold voltage of fast cells and slow cells during a write operation in the semiconductor memory device of the first embodiment.

[0017] Figure 11 This is a timing diagram showing the voltage of the word line WLsel and the voltage of the bit line BL during programming in the semiconductor memory device of the first embodiment.

[0018] Figure 12 This is a table showing an example of the setting of the verification voltage in the semiconductor memory device of the first embodiment.

[0019] Figure 13 This is a graph in the semiconductor memory device of the first embodiment, showing the relationship between the number of programming cycles in the write operation and the VL1 verification operation.

[0020] Figure 14 This is a timing diagram showing various wiring and signals in the programming operation of the semiconductor memory device in the first embodiment.

[0021] Figure 15 This is a diagram illustrating the operation of the voltage generation circuit and the sensing amplifier unit during the programming process in the semiconductor memory device of the first embodiment.

[0022] Figure 16 This is a diagram illustrating the operation of the voltage generation circuit and the sensing amplifier unit during the programming process in the semiconductor memory device of the first embodiment.

[0023] Figure 17This is a diagram illustrating the operation of the voltage generation circuit and the sensing amplifier unit during the programming process in the semiconductor memory device of the first embodiment.

[0024] Figure 18 This is a diagram illustrating the operation of the voltage generation circuit and the sensing amplifier unit during the programming process in the semiconductor memory device of the first embodiment.

[0025] Figure 19 This is a diagram illustrating the operation of the voltage generation circuit and the sensing amplifier unit during the programming process in the semiconductor memory device of the first embodiment.

[0026] Figure 20 This is a flowchart of the write operation in the semiconductor memory device of the first embodiment.

[0027] Figure 21 This is a table showing an example of the setting of the verification voltage in the semiconductor memory device of the first example of the second embodiment.

[0028] Figure 22 This is a graph showing the relationship between the number of programming cycles in the write operation and the VL1 verification operation in the first example of the second embodiment of the semiconductor memory device.

[0029] Figure 23 This is a table showing an example of the setting of the verification voltage in the semiconductor memory device of the second embodiment of the second implementation. Detailed Implementation

[0030] The embodiments will now be described with reference to the accompanying drawings. During the description, constituent elements having substantially the same function and structure will be labeled with the same symbols. Furthermore, the embodiments shown below are merely illustrative of apparatuses and methods for implementing the technical concept of these embodiments, and the technical concept of the embodiments does not specify the material, shape, structure, arrangement, etc., of the constituent parts as described below. Various modifications can be made to the technical concept of the embodiments within the scope of the claims.

[0031] 1. First Implementation Method

[0032] The semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is a NAND flash memory capable of non-volatile data storage. The semiconductor memory device 1 according to the first embodiment will now be described. Furthermore, the semiconductor memory device 1 is not limited to a NAND flash memory. The semiconductor memory device 1 may also be other non-volatile memories.

[0033] 1.1 Composition

[0034] 1.1.1 Overall Structure of Semiconductor Memory Devices

[0035] First, use Figure 1 An example of the overall structure of a semiconductor memory device will be explained. Figure 1 This is a block diagram showing the basic overall structure of a semiconductor memory device. Furthermore, in Figure 1 In the diagram, arrows are used to indicate partial connections between the constituent elements, but the connections between the constituent elements are not limited to this.

[0036] like Figure 1 As shown, the semiconductor memory device 1 is configured to be controllable by an external memory controller 2. For example, the semiconductor memory device 1 and the memory controller 2 transmit and receive signals DQ, and timing signals DQS and DQSn. Signal DQ is, for example, data DAT, address ADD, or instruction CMD. Timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. Timing signal DQSn is the inverted signal of timing signal DQS.

[0037] In addition, the semiconductor memory device 1 receives various control signals from the memory controller 2. Furthermore, the semiconductor memory device 1 sends a ready / busy signal RBn to the memory controller 2. The ready / busy signal RBn is a signal indicating whether the semiconductor memory device 1 is in a busy state (unable to receive instruction CMD from the memory controller 2) or in a ready state (able to receive instruction CMD from the memory controller 2).

[0038] The semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, an address register 12, an instruction register 13, a sequencer 14, a ready / busy circuit 15, a voltage generation circuit 16, a memory cell array 17, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21.

[0039] Input / output circuit 10 is a circuit for input / output signal DQ. Input / output circuit 10 is connected to memory controller 2. In addition, input / output circuit 10 is connected to logic control circuit 11, address register 12, instruction register 13, and data register 20.

[0040] When the input signal DQ is the address ADD, the input / output circuit 10 sends the address ADD to the address register 12. Conversely, when the input signal DQ is the instruction CMD, the input / output circuit 10 sends the instruction CMD to the instruction register 13.

[0041] When the input signal DQ is data DAT, the input / output circuit 10 receives the input signal DQ based on timing signals DQS and DQSn. Then, the input / output circuit 10 sends the data DAT to the data register 20. In addition, the input / output circuit 10 outputs the data DAT together with the timing signals DQS and DQSn to the memory controller 2.

[0042] The logic control circuit 11 is a circuit that performs logic control based on control signals. The logic control circuit 11 is connected to the memory controller 2. Additionally, the logic control circuit 11 is connected to the input / output circuit 10 and the sequencer 14. The logic control circuit 11 receives multiple control signals from the memory controller 2. Based on the received control signals, the logic control circuit 11 controls the input / output circuit 10 and the sequencer 14.

[0043] Address register 12 is a register that temporarily stores the address ADD. Address register 12 is connected to input / output circuit 10, row decoder 18, and column decoder 21. The address ADD contains the row address RA and the column address CA. Address register 12 transmits the row address RA to row decoder 18. In addition, address register 12 transmits the column address CA to column decoder 21.

[0044] Instruction register 13 is a register that temporarily stores the instruction CMD. Instruction register 13 is connected to input / output circuit 10 and sequencer 14. Instruction register 13 transmits the instruction CMD to sequencer 14.

[0045] Sequencer 14 is a circuit (controller) that controls semiconductor memory device 1. Sequencer 14 controls the overall operation of semiconductor memory device 1. Sequencer 14 can function as a controller for semiconductor memory device 1. For example, sequencer 14 controls the ready / busy circuit 15, voltage generation circuit 16, row decoder 18, sense amplifier 19, data register 20, and column decoder 21. For example, sequencer 14 performs write operations, read operations, and erase operations based on instruction CMD.

[0046] The ready / busy circuit 15 is a circuit that sends a ready / busy signal RBn to the memory controller 2.

[0047] The voltage generation circuit 16, based on the control of the sequencer 14, generates voltages for write, read, and erase operations. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 17, the row decoder 18, and the sense amplifier 19, etc. The row decoder 18 and the sense amplifier 19 can apply the voltages supplied by the voltage generation circuit 16 to the memory cell array 17.

[0048] The memory cell array 17 is a collection of multiple memory cell transistors (also abbreviated as "memory cells") arranged in a matrix. The memory cell array 17 contains multiple block BLKs. Figure 1 In the example shown, the memory cell array 17 contains four blocks BLK0, BLK1, BLK2, and BLK3. Furthermore, the number of blocks BLK within the memory cell array 17 is arbitrary. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased at once. That is, a block BLK is a unit of data erasure. The detailed structure of the block BLK will be described below.

[0049] The row decoder 18 is the decoding circuit for the row address RA. Based on the decoding result, the row decoder 18 selects any BLK block within the memory cell array 17. The row decoder 18 applies voltage to the row-direction wiring (hereinafter, word lines and select gate lines) of the selected BLK block.

[0050] Sensing amplifier 19 is a circuit for writing and reading data DAT. Sensing amplifier 19 is connected to memory cell array 17 and data register 20. During a read operation, sensing amplifier 19 reads data DAT from memory cell array 17. During a write operation, sensing amplifier 19 supplies a voltage to memory cell array 17 based on the write data DAT and the threshold voltage of the memory cell transistors. For example, during a write operation, sensing amplifier 19 can generate four voltages based on the write data and the threshold voltage of the memory cell transistors. Furthermore, sensing amplifier 19 can apply any one of the four voltages to the column-direction wiring (hereinafter referred to as bit lines).

[0051] Data register 20 is a register that temporarily stores data DAT. Data register 20 is connected to sense amplifier 19 and column decoder 21. Data register 20 contains multiple latch circuits. Each latch circuit temporarily stores data to be written or read.

[0052] Column decoder 21 is the circuit that decodes column address CA. Column decoder 21 receives column address CA from address register 12. Based on the decoding result of column address CA, column decoder 21 selects the latch circuit in data register 20.

[0053] 1.1.2 Circuit configuration of storage cell array

[0054] Next, refer to Figure 2 An example of the circuit configuration of the storage cell array 17 will be described. Figure 2 This is the circuit diagram of storage cell array 17.

[0055] A block BLK may contain, for example, four string units SU0 to SU3. Furthermore, the number of string units SU contained in a block BLK is arbitrary. A string unit SU may be, for example, a set of multiple NAND strings NS that are selected at once during a write or read operation.

[0056] Next, the internal structure of the serial cell SU will be explained. The serial cell SU contains multiple NAND strings NS. The NAND strings NS are a collection of multiple memory cell transistors connected in series. The multiple NAND strings NS in the serial cell SU are respectively connected to any bit line among the bit lines BL0 to BLm (m is an integer greater than or equal to 1).

[0057] Next, the internal structure of each NAND string (NS) will be explained. Each NAND string (NS) contains multiple storage cell transistors (MC) and selection transistors (ST1 and ST2). Figure 2 In the example shown, the NAND string NS contains eight storage cell transistors MC0 to MC7.

[0058] A memory cell transistor (MC) is a non-volatile memory device that stores data. An MC includes a control gate and a charge storage layer. MCs can be either MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, which uses an insulator for the charge storage layer, or FG (Floating Gate) type, which uses a conductor for the charge storage layer.

[0059] Selector transistors ST1 and ST2 are switching elements. Selector transistors ST1 and ST2 are used to select the serial cell SU when performing various actions.

[0060] The current paths of select transistor ST2, storage cell transistors MC0-MC7, and select transistor ST1 within the NAND string NS are connected in series. The drain of select transistor ST1 is connected to bit line BL. The source of select transistor ST2 is connected to source line SL.

[0061] The control gates of the memory cell transistors MC0 to MC7 in the same BLK are all connected to word lines WL0 to WL7. More specifically, for example, the BLK contains four serial cells SU0 to SU3. Moreover, each serial cell SU contains multiple memory cell transistors MC0. The control gates of the multiple memory cell transistors MC0 in the BLK are all connected to one word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0062] The gates of multiple selection transistors ST1 within a series unit SU are all connected to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within a series unit SU0 are all connected to selection gate line SGD0. The gates of multiple selection transistors ST1 within a series unit SU1 are all connected to selection gate line SGD1. The gates of multiple selection transistors ST1 within a series unit SU2 are all connected to selection gate line SGD2. The gates of multiple selection transistors ST1 within a series unit SU3 are all connected to selection gate line SGD3.

[0063] The gates of the multiple selection transistors ST2 within block BLK are all connected to the selection gate line SGS. Furthermore, similar to the selection gate line SGD, a separate selection gate line SGS can also be provided for each string cell SU.

[0064] Word lines WL0 to WL7, select gate lines SGD0 to SGD3, and select gate line SGS are respectively connected to the line decoder 18.

[0065] Bit lines BL are commonly connected to one NAND string NS of each of the multiple string units SU of each BLK block. Each bit line BL is connected to the sense amplifier 19.

[0066] For example, multiple BLK blocks share a common source line SL.

[0067] A collection of multiple storage cell transistors MC connected to a common word line WL within a single string cell SU is, for example, denoted as a "cell CU". In other words, a cell CU is a collection of multiple storage cell transistors MC that are selected at once during a write or read operation. A page is a unit of data written to (or read from) a cell CU at once. For example, if a storage cell transistor MC stores 1 bit of data, the storage capacity of the cell CU is 1 page. Furthermore, a cell CU may have a storage capacity of 2 pages or more, depending on the number of bits of data stored by the storage cell transistor MC. The following explanation addresses the case where the storage cell transistor MC is a TLC (Triple Level Cell) storing 3 bits of data.

[0068] 1.1.3 Configuration of Data Register and Sensing Amplifier

[0069] Next, refer to Figure 3 An example of the configuration of the data register 20 and the sensing amplifier 19 will be described. Figure 3 This is a block diagram of data register 20 and sensing amplifier 19.

[0070] like Figure 3 As shown, the sensing amplifier 19 includes multiple sensing amplifier units SAU, each configured for each bit line BL.

[0071] Data register 20 includes, for example, multiple latch circuits XDL, each configured for a sense amplifier unit (SAU). The latch circuits XDL temporarily store read and write data. The latch circuits XDL are used to input and output data between the sense amplifier unit (SAU) and the input / output circuit 10. Each latch circuit XDL is connected to its corresponding sense amplifier unit (SAU) via a bus DBUS. Furthermore, multiple sense amplifier units (SAUs) may be connected to a single latch circuit XDL.

[0072] Next, the internal structure of the sense amplifier unit (SAU) will be described. The sense amplifier unit (SAU) includes, for example, a sense circuit (SA) and latch circuits (SDL, ADL, BDL, CDL, DDL, and TDL). The sense circuit (SA) and the latch circuits (SDL, ADL, BDL, CDL, DDL, and TDL) are all connected to the bus (LBUS). In other words, the latch circuit (SA), sense circuit (SA), and latch circuits (SDL, ADL, BDL, CDL, DDL, and TDL) are connected in a manner that allows them to send and receive data.

[0073] When performing a read operation, the sensing circuit SA senses the data that has been read to the corresponding bit line BL and determines whether the read data is "0" or "1". Conversely, when performing a write operation, the sensing circuit SA applies a voltage to the bit line BL based on the data stored in the latch circuit SDL.

[0074] The latch circuits SDL, ADL, BDL, CDL, DDL, and TDL temporarily store read and write data. For example, during a read operation, data can be transferred from the sensing circuit SA to any one of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL. Similarly, during a write operation, data can be transferred from the latch circuit XDL to any one of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL.

[0075] Furthermore, the configuration of the sense amplifier unit (SAU) is not limited to this and can be modified in various ways. For example, the number of latching circuits in the sense amplifier unit (SAU) can be designed based on the number of bits of data stored in one memory cell transistor (MC).

[0076] 1.1.4 Circuit configuration of the sensing amplifier unit

[0077] Next, refer to Figure 4 An example of the circuit configuration of the sense amplifier unit SAU will be explained. Figure 4 This is the circuit diagram of the sensing amplifier unit (SAU). Furthermore, in Figure 4In the example shown, for simplicity, the circuit diagrams of latch circuits ADL, BDL, CDL, DDL, and TDL are omitted. The circuit configurations of latch circuits ADL, BDL, CDL, DDL, and TDL are the same as those of latch circuit SDL. Furthermore, in the following description, one of the source or drain terminals of the transistor is referred to as "one end of the transistor," and the other of the source or drain terminal is referred to as "the other end of the transistor."

[0078] like Figure 4 As shown, the sensing amplifier unit SAU includes a sensing circuit SA, latching circuits SDL, ADL, BDL, CDL, DDL and TDL, a precharge circuit PPC, and a DBUS switching circuit DSC.

[0079] First, the internal structure of the sensing circuit SA will be explained. The sensing circuit SA includes a high-voltage n-channel MOS (Metal Oxide Semiconductor) transistor 30, a low-voltage p-channel MOS transistor 31, low-voltage n-channel MOS transistors 32-45, and a capacitor element 46.

[0080] One end of transistor 30 is connected to bit line BL. The other end of transistor 30 is connected to node ND1. The gate of transistor 30 is connected to node BLS. With bit line BL electrically connected to the sense amplifier unit SAU, a high ("H") voltage is applied to node BLS to turn on transistor 30.

[0081] A voltage VHSA is applied to one end of transistor 31. VHSA is the power supply voltage of the sensing circuit SA. The other end of transistor 31 is connected to node ND2. The gate of transistor 31 is connected to node INV_S. Node INV_S is the node that can store data in the latch circuit SDL. When node INV_S is low (L"), transistor 31 is turned on.

[0082] One end of transistor 32 is connected to node ND2. A ground voltage VSS is applied to the other end of transistor 32. The gate of transistor 32 is connected to node INV_S. When node INV_S is at a "H" level, transistor 32 is in the ON state. Therefore, based on the logic level of node INV_S, one of transistors 31 and 32 is in the ON state, and the other is in the OFF state. In other words, based on the logic level of node INV_S, either voltage VHSA or voltage VSS is applied to node ND2.

[0083] One end of transistor 33 is connected to node ND2. The other end of transistor 33 is connected to node ND3. The gate of transistor 33 is connected to node BLX.

[0084] One end of transistor 34 is connected to node ND1. The other end of transistor 34 is connected to node ND3. The gate of transistor 33 is connected to node BLC. Transistor 34 can function as a clamping transistor that clamps the voltage to be applied to bit line BL based on the voltage applied to node BLC.

[0085] One end of transistor 35 is connected to node ND3. A voltage VSS is applied to the other end of transistor 35. The gate of transistor 35 is connected to node NLO.

[0086] One end of transistor 36 is connected to node ND3. The other end of transistor 36 is connected to node SEN1. The gate of transistor 36 is connected to node XXL.

[0087] One end of transistor 37 is connected to node ND1. The gate of transistor 37 is connected to node APLS. Transistor 37 can function as a clamping transistor that clamps the voltage to be applied to node ND1 based on the voltage applied to node APLS.

[0088] One end of transistor 38 is connected to the other end of transistor 37. A voltage VHSA is applied to the other end of transistor 38. The gate of transistor 37 is connected to node SEN1. When a voltage of level "H" is applied to node SEN1, transistor 38 becomes ON. Alternatively, a voltage different from VHSA can be applied to the other end of transistor 38. For example, a voltage used to control the signal CLKSA can also be applied.

[0089] One end of transistor 39 is connected to node SEN1. The other end of transistor 39 is connected to node SEN2. The gate of transistor 39 is connected to node S2S. For example, the sensing circuit SA can use transistors 40 to 45 to perform operations. For example, when performing operations, the sensing circuit SA can maintain the voltage of node SEN1 unchanged by turning off transistor 39.

[0090] One end of transistor 40 is connected to node SEN2. The other end of transistor 40 is connected to node ND4. The gate of transistor 40 is connected to node BLQ. For example, when a voltage of level "H" is applied to nodes SEN1 and SEN2 from the precharge circuit PPC, transistor 40 becomes turned on.

[0091] One end of transistor 41 is connected to node ND4. The other end of transistor 41 is connected to one end of transistor 42. A signal STB is input to the gate of transistor 41. After the signal STB is activated, the sensing circuit SA determines the data stored in the selected memory cell transistor MC. More specifically, transistor 41 becomes on after receiving the "H" level signal STB. During this time, when transistor 42 is on, the bus LBUS is discharged through transistors 41, 42, and 45. On the other hand, when transistor 42 is off, the bus LBUS is not discharged through transistors 41, 42, and 45. Data ("0" or "1") based on the voltage of the bus LBUS is stored in any of the latch circuits SDL, ADL, BDL, CDL, DDL, and TDL of the shared bus LBUS.

[0092] A voltage VSS is applied to the other end of transistor 42. The gate of transistor 42 is connected to node SEN2. Transistor 42 functions as a sensing transistor to sense the voltage at node SEN2. For example, if the voltage at node SEN2 is above the threshold voltage of transistor 42, transistor 42 is turned on. On the other hand, if the voltage at node SEN2 is below the threshold voltage of transistor 42, transistor 42 is turned off.

[0093] One end of transistor 43 is connected to node SEN2. The other end of transistor 43 is connected to one end of transistor 44. The gate of transistor 43 is connected to node LSL.

[0094] A voltage VSS is applied to the other end of transistor 44. The gate of transistor 44 is connected to the bus LBUS via node ND5.

[0095] One end of transistor 45 is connected to node ND4. The other end of transistor 45 is connected to the bus LBUS via node ND5. The gate of transistor 45 is connected to node LSW. For example, transistor 45 is in the ON state during the period when signal STB is active.

[0096] One electrode of capacitor element 46 is connected to node SEN1. A clock signal CLKSA is input to the other electrode of capacitor element 46.

[0097] Next, the pre-charge circuit PPC will be explained. The pre-charge circuit PPC is the pre-charge circuit for the bus LBUS and node SEN1, etc. The pre-charge circuit PPC includes a low-voltage n-channel MOS transistor 50. A voltage VHLB is applied to one end of transistor 50. Voltage VHLB is the pre-charge voltage. The other end of transistor 50 is connected to node ND4. The gate of transistor 50 is connected to node LPC. For example, when transistors 45 and 50 are in the ON state, the pre-charge circuit PPC charges the bus LBUS with a voltage of "H" level. In addition, when transistors 39, 40, and 50 are in the ON state, the pre-charge circuit PPC charges node SEN1 with a voltage of "H" level.

[0098] Next, the DBUS switching circuit DSC will be described. The DBUS switching circuit DSC connects the sense amplifier unit SAU to the DBUS bus. In other words, the DBUS switching circuit DSC connects the sense amplifier unit SAU to the latch circuit XDL. The DBUS switching circuit DSC includes a low-voltage n-channel MOS transistor 51. One end of transistor 51 is connected to node ND4. The other end of transistor 51 is connected to the DBUS bus. The gate of transistor 51 is connected to node DSW.

[0099] Next, the internal structure of the latch circuit SDL will be explained. The latch circuit SDL includes inverters 60 and 61, and low-voltage n-channel MOS transistors 62 and 63.

[0100] The input node of inverter 60 is connected to node LAT_T. The output node of inverter 60 is connected to node INV_S.

[0101] The input node of inverter 61 is connected to node INV_S. The output node of inverter 61 is connected to node LAT_T.

[0102] One end of transistor 62 is connected to the bus LBUS. The other end of transistor 62 is connected to node INV_S. The gate of transistor 62 is connected to node STI.

[0103] One end of transistor 63 is connected to the bus LBUS. The other end of transistor 63 is connected to node LAT_T. The gate of transistor 63 is connected to node STL.

[0104] The latch circuit SDL stores data in node LAT_T. On the other hand, the latch circuit SDL stores the inverted data of the data stored in node LAT_T in node INV_S.

[0105] For example, multiple sense amplifier units (SAUs) share nodes BLS, BLX, BLC, NLO, XXL, APLS, S2S, BLQ, LSL, LSW, LPC, DSW, STI, and STL. Signals (applied voltages) based on the sequencer 14 are input to nodes BLS, BLX, BLC, NLO, XXL, APLS, S2S, BLQ, LSL, LSW, LPC, DSW, STI, and STL, respectively.

[0106] 1.1.5 Circuit configuration of voltage generation circuit

[0107] Next, refer to Figure 5 An example of the circuit configuration of the voltage generating circuit 16 will be described. Figure 5 This is a circuit diagram of voltage generation circuit 16 and sensing circuit SA. Figure 5 A portion of the voltage generation circuit 16 and a portion of the sensing circuit SA corresponding to nodes XXL, BLX, BLC and APLS are shown. Figure 5 The sensing circuit SA shown is from Figure 4 The sensor circuit SA shown is a partial representation. Therefore, the description of the sensor circuit SA will be omitted in the following explanation.

[0108] like Figure 5 As shown, the voltage generation circuit 16 includes a current source 70, variable resistor circuits 71-73, n-channel MOS transistors 74 and 75, drivers 76-78, and selector circuits 80-83.

[0109] A voltage VX4 is applied to the input terminal of current source 70. Current source 70 supplies a constant current IX4 from its output terminal. The output terminal of current source 70 is connected to node ND11.

[0110] One end of the variable resistor circuit 71 is connected to node ND11. The other end of the variable resistor circuit 71 is connected to node ND12. For example, the resistance value of the variable resistor circuit 71 can be set to r1.

[0111] One end of the variable resistor circuit 72 is connected to node ND12. The other end of the variable resistor circuit 72 is connected to node ND13. For example, the resistance value of the variable resistor circuit 72 can be set to r2.

[0112] One end and gate of transistor 74 are connected to node ND13. The other end of transistor 74 is connected to one end of variable resistor circuit 73. Transistor 74 functions as a diode.

[0113] The other end of the variable resistor circuit 73 is connected to one end of the transistor 75. For example, the resistance value of the variable resistor circuit 73 can be set to r3.

[0114] A voltage VSS is applied to the other end of transistor 75. A signal SW1 is input to the gate of transistor 75. For example, signal SW1 is a signal that controls whether voltages are applied to nodes XXL, BLX, BLC, and APLS.

[0115] Driver 76 is the circuit that drives the voltage at node ND11. For example, driver 76 contains a unity-gain operational amplifier. The voltage at node ND11 is applied to the input terminals of driver 76. For example, neglecting the on-resistance of transistors 74 and 75, the voltage Vnd11 at node ND11 satisfies Vnd11 = IX4・(r1 + r2 + r3) + Vth74. Vth74 is the threshold voltage of transistor 74 connected to the diode.

[0116] Driver 77 is a driving circuit for the voltage at node ND12. For example, driver 77 includes a unity-gain operational amplifier. The voltage at node ND12 is applied to the input terminals of driver 77. For example, neglecting the on-resistance of transistors 74 and 75, the voltage Vnd12 at node ND12 satisfies Vnd12 = IX4・(r2 + r3) + Vth74. Therefore, the voltage Vnd12 applied to the input terminals of driver 77 is lower than the voltage Vnd11 applied to the input terminals of driver 76. In other words, the output voltage of driver 77 is lower than the output voltage of driver 76. The relationship Vnd11 - Vnd12 = IX4・r1 is satisfied. Therefore, by controlling the resistance value r1 of the variable resistor circuit 71, the voltage difference between voltage Vnd11 and voltage Vnd12 can be controlled.

[0117] Driver 78 is a driving circuit for the voltage at node ND13. For example, driver 78 includes a unity-gain operational amplifier. The voltage at node ND13 is applied to the input terminals of driver 78. For example, neglecting the on-resistance of transistors 74 and 75, the voltage Vnd13 at node ND13 satisfies Vnd13 = IX4·r3 + Vth74. Therefore, the voltage Vnd13 applied to the input terminals of driver 78 is lower than the voltage Vnd12 applied to the input terminals of driver 77. In other words, the output voltage of driver 78 is lower than the output voltage of driver 77. The relationship Vnd12 - Vnd13 = IX4·r2 is satisfied. Therefore, by controlling the resistance value r2 of the variable resistor circuit 72, the voltage difference between voltage Vnd12 and voltage Vnd13 can be controlled. Voltages Vnd11, Vnd12, and Vnd13 satisfy the relationship Vnd11 > Vnd12 > Vnd13.

[0118] Selector circuit 80 has a 0th input terminal and a 1st input terminal. Selector circuit 80 electrically connects either the 0th or 1st input terminal to an output terminal based on signal SEL1. The 0th input terminal of selector circuit 80 is connected to the output terminal of driver 76. A voltage VSS is applied to the 1st input terminal of selector circuit 80. The output terminal of selector circuit 80 is connected to node XXL.

[0119] Selector circuit 81 has input terminal 0, input terminal 1, and input terminal 2. Based on signal SEL2, selector circuit 81 electrically connects any one of input terminals 0, 1, and 2 to an output terminal. A voltage VHSA + Vth is applied to input terminal 0 of selector circuit 81. Voltage Vth is the threshold voltage of the low-voltage n-channel MOS transistors 32-45 of sensing circuit SA. Input terminal 1 of selector circuit 81 is connected to the output terminal of driver 77. A voltage VSS is applied to input terminal 2 of selector circuit 81. The output terminal of selector circuit 81 is connected to node BLX.

[0120] Selector circuit 82 has input terminal 0, input terminal 1, and input terminal 2. Based on signal SEL3, selector circuit 82 electrically connects input terminals 0, 1, and 2 to output terminals. A voltage VHSA + Vth is applied to input terminal 0 of selector circuit 82. Input terminal 1 of selector circuit 82 is connected to the output terminal of driver 78. A voltage VSS is applied to input terminal 2 of selector circuit 82. The output terminal of selector circuit 82 is connected to node BLC.

[0121] Selector circuit 83 has a 0th input terminal and a 1st input terminal. Based on signal SEL4, selector circuit 83 electrically connects either the 0th or 1st input terminal to an output terminal. The 0th input terminal of selector circuit 83 is connected to the output terminal of driver 76. A voltage VSS is applied to the 1st input terminal of selector circuit 83. The output terminal of selector circuit 83 is connected to node APLS.

[0122] Signals SEL1 to SEL4 are signals controlled by the sequencer 14.

[0123] 1.2 Data Storage Methods

[0124] Next, refer to Figure 6 Here is an example of a data storage method. Figure 6 This is a conceptual diagram representing an example of how data is stored. Figure 6An example of the threshold voltage distribution, data allocation, and voltage used for data readout of a memory cell transistor MC is shown. In the threshold voltage distribution diagrams referred to below, "NMCs" on the vertical axis represents the number of memory cell transistors MC, and the voltage on the horizontal axis represents the voltage applied to the gate of the memory cell transistor MC.

[0125] like Figure 6 As shown, when one storage cell transistor MC is a TLC storing 3 bits of data, the threshold voltage distribution formed by the multiple storage cell transistors MC contained in the cell unit CU can have 8 states. Hereinafter, these 8 states are referred to in order of threshold voltage from low to high as state "S0", state "S1", state "S2", state "S3", state "S4", state "S5", state "S6" and state "S7".

[0126] When the memory cell transistor MC is in the erase state, the threshold voltage of the memory cell transistor MC is contained in state "S0". When data has been written to the memory cell transistor MC, the threshold voltage of the memory cell transistor MC is contained in any of states "S0" to "S7". Each of states "S0" to "S7" is assigned a different 3-bit data. The data allocation for each of two adjacent states is preferably set so that only 1 bit of data differs. Below is an example of the data allocation for the eight states.

[0127] State "S0": 111 (highest bit / middle bit / lowest bit) data

[0128] Status "S1": "110" data

[0129] Status "S2": Data "100"

[0130] Status "S3": "000" data

[0131] Status "S4": "010" data

[0132] Status "S5": Data "011"

[0133] Status "S6": Data "001"

[0134] Status "S7": Data "101"

[0135] Between adjacent states, a verification voltage for confirming data writing and a read voltage for reading data are set respectively. Specifically, a verification voltage V1 and a read voltage R1 are set between states "S0" and "S1". A verification voltage V2 and a read voltage R2 are set between states "S1" and "S2". A verification voltage V3 and a read voltage R3 are set between states "S2" and "S3". A verification voltage V4 and a read voltage R4 are set between states "S3" and "S4". A verification voltage V5 and a read voltage R5 are set between states "S4" and "S5". A verification voltage V6 and a read voltage R6 are set between states "S5" and "S6". A verification voltage V7 and a read voltage R7 are set between states "S6" and "S7". The verification voltages V1 to V7 are preferably set to be higher than the read voltages R1 to R7, respectively.

[0136] Verification voltages V1 to V7 are associated with states "S1" to "S7", respectively. During the write operation, the semiconductor memory device 1 uses a read operation (hereinafter referred to as the verification operation) to confirm whether the threshold voltage of the memory cell transistor MC, to which certain data is to be stored, exceeds the verification voltage associated with that data. Furthermore, once the sequencer 14 detects that the threshold voltage of the memory cell transistor MC exceeds the verification voltage associated with that data, it completes the data writing to the memory cell transistor MC.

[0137] The read voltage R1 is used to distinguish between state "S0" and state "S1" and above. The read voltage R2 is used to distinguish between state "S1" and below and state "S2" and above. The read voltage R3 is used to distinguish between state "S2" and below and state "S3" and above. The read voltage R4 is used to distinguish between state "S3" and below and state "S4" and above. The read voltage R5 is used to distinguish between state "S4" and below and state "S5" and above. The read voltage R6 is used to distinguish between state "S5" and below and state "S6" and above. The read voltage R7 is used to distinguish between state "S6" and below and state "S7" and above. Additionally, the read path voltage VREAD is set to a voltage higher than the highest state. The memory cell transistor MC with the read path voltage VREAD applied to its gate is always in the ON state, regardless of the data to be stored.

[0138] During the readout operation, the semiconductor memory device 1 uses at least one readout voltage to determine the state of the memory cell transistors MC. For example, the lower page data, which is the lower bit data set, is determined by reading out using readout voltages R1 and R5 respectively. The middle page data, which is the middle bit data set, is determined by reading out using readout voltages R2, R4, and R6 respectively. The upper page data, which is the upper bit data set, is determined by reading out using readout voltages R3 and R7 respectively. Appropriate computational processing is performed during the readout operation of pages using multiple readout voltages.

[0139] Furthermore, when the storage cell transistor MC is TLC (hereinafter referred to as "TLC mode"), the semiconductor memory device 1 can also employ other data allocation methods. Moreover, the semiconductor memory device 1 can also use storage methods other than TLC mode, and can employ all data allocation methods. For example, one storage cell transistor MC can store 2 bits or more of data. The operations described in this specification can be performed regardless of the data storage method or the type of data allocation.

[0140] Additionally, in this specification, the preceding state refers to the state with the lower threshold voltage among adjacent states. For example, the preceding state of state "S2" is state "S1".

[0141] 1.3 Write Action

[0142] Next, the write operation will be explained. In the following description, the word line WL selected in the write operation will be referred to as "word line WLsel". The memory cell transistor MC connected to the word line WLsel will be referred to as "memory cell transistor MCsel".

[0143] 1.3.1 Overview of the write operation

[0144] First, refer to Figure 7 This section provides a summary of the write operation. Figure 7 This is a timing diagram that represents a summary of the write operation. For example... Figure 7 As shown, during the write operation, the semiconductor memory device 1 repeatedly executes the programming loop. Figure 7 This shows the number of programming loops executed during the write operation (hereinafter referred to as loop number) and the voltage change on the word line WLsel (WLsel voltage). Each programming loop includes a programming action (Program) and a verification action (Verify).

[0145] Programming raises the threshold voltage of the memory cell transistors (MCsels). During programming, multiple memory cell transistors (MCsels) connected to the word line WLsel are set as either program-targets or program-inhibits based on the write data stored in their associated sense amplifier unit (SAU). Specifically, memory cell transistors (MCsels) that do not exceed the threshold voltage of the write target state (hereinafter referred to as the "write state") are set as program-targets. Conversely, memory cell transistors (MCsels) that exceed the threshold voltage of the write state are set as program-inhibits.

[0146] During the programming operation, a programming voltage VPGM is applied to the word line WLsel. The programming voltage VPGM is a high voltage that raises the threshold voltage of the memory cell transistor MCsel. The programming voltage VPGM increases, for example, with repeated execution of the programming cycle. That is, the programming voltage VPGM can be increased according to the number of programming cycles executed. The increase magnitude VPGM can be set to any value. When the programming voltage VPGM is applied to the word line WLsel, the threshold voltage of the memory cell transistor MCsel, which is connected to the word line WLsel and to the bit line BL (the target of programming), rises. On the other hand, the rise in the threshold voltage of the memory cell transistor MCsel, which is connected to the word line WLsel and to the bit line BL (which is disabled for programming), is suppressed by a self-boosting technique, etc. After the sequencer 14 finishes the programming operation, a verification operation is performed.

[0147] The verification action is a read operation that confirms whether the threshold voltage of the memory cell transistor MCsel exceeds the threshold voltage of the write state. Within the same programming cycle, the sequencer 14 performs the verification action on the memory cell transistor MCsel that has been set as the programming object and whose write state is consistent with the verification object.

[0148] During the verification process, the sense amplifier unit (SAU) determines whether the threshold voltage of the memory cell transistor (MCsel) exceeds the verification voltage applied to the word line (WLsel) based on the voltage of the bit line (BL). Each sense amplifier unit (SAU) identifies memory cell transistors (MCsels) whose threshold voltage exceeds the verification voltage (i.e., those exceeding the write state threshold voltage) as "verified successfully." Conversely, each sense amplifier unit (SAU) identifies memory cell transistors (MCsels) whose threshold voltage is below the verification voltage (i.e., those not exceeding the write state threshold voltage) as "verified unsuccessfully." Each sense amplifier unit (SAU) stores the verification result of the write state described above into any of its internal latch circuits. After the verification process is completed, the sequencer (14) sets each memory cell transistor (MCsel) as a programming target or disables programming based on the verification result in the current programming cycle, and then begins processing for the next programming cycle.

[0149] Furthermore, after each programming cycle, the semiconductor memory device 1 may perform a detection operation (“Detection”). During the detection operation, the number of successfully verified memory cell transistors (MCsels) is counted for each write state. Moreover, the sequencer 14 determines whether the write operation for each write state is complete based on the count value. In repeated programming cycles, the sequencer 14 will terminate the write operation, for example, once it detects that the number of unverified memory cell transistors (MCsels) in states “S1” to “S7” is lower than a specified number.

[0150] 1.3.2 Specific Examples of Programming Loops

[0151] Next, refer to Figure 8 This section provides specific examples of programming loops. Figure 8 This is a table representing an example of the settings for a programming loop in a write operation. Figure 8 The diagram illustrates the relationship between the number of loops and the write status assigned to that loop as the verification object, with white circles marking the sections where verification actions have been set.

[0152] like Figure 8 As shown, the types and number of write states that are the objects of verification can change as the programming loop progresses. In this example, the sequencer 14 executes a maximum of 19 programming loops. Moreover, in each of the 19 programming loops, the sequencer 14 performs a verification action targeting at least one state.

[0153] Specifically, state "S1" is set as the verification object in programming loops 1-6. State "S2" is set as the verification object in programming loops 2-8. State "S3" is set as the verification object in programming loops 4-10. State "S4" is set as the verification object in programming loops 6-12. State "S5" is set as the verification object in programming loops 8-14. State "S6" is set as the verification object in programming loops 10-16. State "S7" is set as the verification object in programming loops 12-19.

[0154] Furthermore, the number of programming cycles that the semiconductor memory device 1 can execute in a single write operation can be any number of times. Even if the write operation has not been completed in all write states, the sequencer 14 will terminate the write operation based on the fact that the specified number of programming cycles has been executed. The write state that is being verified and associated with the number of cycle cycles can also be set to other values. The sequencer 14 can also omit the programming and verification actions for that write state in subsequent programming cycles based on the result of the detection action.

[0155] 1.3.3 Details of the programming method

[0156] Next, refer to Figure 9 The details of the programming method are explained. Figure 9 This is a threshold voltage distribution diagram showing the relationship between the three verification voltages and three programming conditions that can be used for each write state during the write operation. Figure 9 The example shown illustrates the case where all memory cell transistors MCsel are written from state "S0" to state "S1".

[0157] like Figure 9As shown, for each write state, a first verification low voltage VL1, a second verification low voltage VL2, and a verification high voltage VH are set for the verification action. That is, the verification action includes a verification action using the first verification low voltage VL1 (hereinafter referred to as "VL1 verification action"), a verification action using the second verification low voltage VL2 (hereinafter referred to as "VL2 verification action"), and a verification action using the verification high voltage VH (hereinafter referred to as "VH verification action"). The verification high voltage VH is referenced... Figure 6 The verification voltage is described. Figure 9 In the example shown, VH = V1. The first verification is of the low voltage VL1, the second verification is of the low voltage VL2, and the third verification is of the high voltage VH, which satisfies the relationship VL1 < VL2 < VH.

[0158] The first verification low voltage VL1 is used to distinguish the multiple storage cell transistors MCsel of the cell unit CU according to the storage cell transistors MCsel with relatively large threshold voltage rise (hereinafter referred to as "fast cell") and storage cell transistors MCsel with relatively small threshold voltage rise (hereinafter referred to as "slow cell").

[0159] In a programming loop that executes multiple times for a single write state, sequencer 14 performs one VL1 verification operation. During the VL1 verification operation, sequencer 14 classifies memory cell transistors MCsel whose threshold voltage is below voltage VL1 as slow cells. In other words, it classifies memory cell transistors MCsel whose VL1 verification operation fails as slow cells. On the other hand, during the VL1 verification operation, sequencer 14 classifies memory cell transistors MCsel whose threshold voltage exceeds voltage VL1 as fast cells. In other words, it classifies memory cell transistors MCsel whose VL1 verification operation succeeds as fast cells. Hereinafter, the determination of fast cells and slow cells based on the VL1 verification operation will be referred to as "cell determination".

[0160] The second verification low voltage VL2 is used to determine the magnitude of the difference between the threshold voltage of the storage cell transistor MCsel and the voltage VH.

[0161] In each programming loop, sequencer 14 executes VL2 verification and VH verification actions. Based on the results of the VL2 verification and VH verification actions, sequencer 14 determines the conditions for the programming actions in the next programming loop.

[0162] More specifically, the programming action includes three programming conditions PG0 to PG2, and a programming prohibition condition INH. For example, when the threshold voltage of the memory cell transistor MCsel is below voltage VL2, the sequencer 14 applies programming condition PG0 in the programming action of the next programming cycle. In other words, the programming action applying programming condition PG0 is performed on the memory cell transistor MCsel that fails VL2 verification (hereinafter referred to as "PG0 programming action").

[0163] Furthermore, when the threshold voltage of the storage cell transistor MCsel exceeds voltage VL2 but is below voltage VH, the sequencer 14 applies programming condition PG1 to the slow cell and programming condition PG2 to the fast cell in the programming operation of the next programming cycle. In other words, the programming operation applying programming condition PG1 (hereinafter referred to as the PG1 programming operation) is performed on the slow cell that successfully verifies VL2 but fails VH. On the other hand, the programming operation applying programming condition PG2 (hereinafter referred to as the "PG2 programming operation") is performed on the fast cell that successfully verifies VL2 but fails VH.

[0164] In addition, if the threshold voltage of the storage cell transistor MCsel exceeds the voltage VH, the sequencer 14 sets the storage cell transistor MC to be unprogrammable in the programming operation of the next programming cycle.

[0165] Programming condition PG0 is a programming condition where the threshold voltage variation of the memory cell transistor MC is relatively large. Programming condition PG1 is a programming condition where the threshold voltage variation of the memory cell transistor MC is smaller than that of programming condition PG0. Programming condition PG1 is applicable to slow cells. Programming condition PG2 is a programming condition where the threshold voltage variation of the memory cell transistor MC is smaller than that of programming condition PG0. Programming condition PG2 is applicable to fast cells. For example, in the programming operation of a memory cell transistor MC, if any of the programming conditions PG0, PG1, PG2, and the inability to program is INH are applied, the variation of the threshold voltage of the memory cell transistor MC satisfies the relationship: "Programming condition PG0" > "Programming condition PG1" > "Programming condition PG2" > "Inability to program". For example, if the PG0 programming operation is performed when the threshold voltage of the memory cell transistor MC exceeds voltage VL2 but is below voltage VH, the threshold voltage of the memory cell transistor MC may exceed voltage VH relatively significantly. Therefore, the PG1 programming operation is performed in slow cells, and the PG2 programming operation is performed in fast cells. Furthermore, it is preferable that the difference between the change in threshold voltage of the slow cell caused by the PG1 programming action and the change in threshold voltage of the fast cell caused by the PG2 programming action is small.

[0166] In the last programming action within a series of multiple programming actions performed on a single write state, sequencer 14 applies either programming condition PG1 or programming condition PG2. In other words, the memory cell transistor MCsel that has undergone either PG1 or PG2 programming is set to be unprogrammable in subsequent programming cycles. Sequencer 14 reduces the difference in threshold voltages among the multiple memory cell transistors MCsel by applying programming condition PG1 to slow cells and programming condition PG2 to fast cells.

[0167] Next, refer to Figure 10 An example illustrating the relationship between the threshold voltage of the memory cell transistor MC and programming conditions will be provided. Figure 10 This is a conceptual diagram representing the changes in the threshold voltage of fast and slow cells during a write operation.

[0168] like Figure 10 As shown, for example, when programming is performed on both fast and slow cells under the same programming conditions during a programming operation, the threshold voltage of the fast cell varies more significantly in a single programming operation. Figure 10 In the example shown, if a PG0 programming action is performed once on a fast cell, the threshold voltage of the fast cell rises to a voltage exceeding VL2 but below VH. Then, if a PG2 programming action is subsequently performed on the fast cell, the threshold voltage of the fast cell exceeds VH. In this case, the increase in the threshold voltage of the fast cell is suppressed compared to the first PG0 programming action. Conversely, if a PG0 programming action is performed twice on a slow cell, the threshold voltage of the slow cell rises to a voltage exceeding VL2 but below VH. If, in this state, programming condition PG2 is applied to the next programming action of the slow cell, the change in the threshold voltage of the slow cell becomes smaller than the change in the threshold voltage of the fast cell that has already undergone PG2 programming. Thus, the threshold voltage of the slow cell may not reach VH. Therefore, programming condition PG1, which has a larger change in threshold voltage than programming condition PG2, should be applied to the programming action of the slow cell.

[0169] 1.3.4 Voltage of word lines and bit lines during programming operations

[0170] Next, refer to Figure 11 An example of the voltage of the word line WL and bit line BL in the programming operation will be explained. Figure 11This is a timing diagram showing the voltages of the word line WLsel and the bit line BL during programming operations. Below, the bit line BL connected to the memory cell transistor MCsel, which is the target of the PG0 programming operation, is designated "Bit Line BL_pg0". The bit line BL connected to the memory cell transistor MCsel, which is the target of the PG1 programming operation, is designated "Bit Line BL_pg1". The bit line BL connected to the memory cell transistor MCsel, which is the target of the PG2 programming operation, is designated "Bit Line BL_pg2". The bit line BL connected to the memory cell transistor MCsel that is disabled for programming is designated "Bit Line BL_inh".

[0171] like Figure 11 As shown, at the start of the programming operation, the voltages of the word line WLsel and the bit lines BL_pg0, BL_pg1, BL_pg2, and BL_inh are, for example, voltage VSS. During the period when the programming voltage VPGM is applied to the word line WLsel, voltage VSS is applied to the bit line BL_pg0. Voltage VQPW1 is applied to the bit line BL_pg1. Voltage VQPW2 is applied to the bit line BL_pg2. Voltage VINH is applied to the bit line BL_inh. Voltage VQPW1 is higher than voltage VSS. Voltage VQPW2 is higher than voltage VQPW1. Voltage VSGD is the voltage applied to the select gate line SGD corresponding to the target string cell SU during the period when the programming voltage VPGM is applied to the word line WLsel. Voltage VINH is higher than voltage VQPW2 and voltage VSGD. In other words, during the period when the programming voltage VPGM is applied to the word line WLsel, the sense amplifier 19 applies voltage VSS to the bit line BL_pg0, voltage VQPW1 to the bit line BL_pg1, voltage VQPW2 to the bit line BL_pg2, and voltage VINH to the bit line BL_inh.

[0172] During the period when the programming voltage VPGM is applied to the word line WLsel, the select transistor ST1 in the NAND string NS connected to the bit lines BL_pg0, BL_pg1, or BL_pg2 is turned on. At this time, a voltage VSS is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg0. A voltage VQPW1 is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg1. A voltage VQPW2 is applied to the channel of the memory cell transistor MCsel corresponding to the bit line BL_pg2. Meanwhile, the select transistor ST1 in the NAND string NS connected to BL_inh is turned off. That is, the channel of the memory cell transistor MCsel corresponding to BL_inh is in a floating state.

[0173] As a result, in the memory cell transistor MCsel corresponding to bit line BL_pg0, electrons are injected into the charge storage layer based on the voltage difference between voltage VPGM and voltage VSS, thereby increasing the threshold voltage. In the memory cell transistor MCsel corresponding to bit line BL_pg1, electrons are injected into the charge storage layer based on the voltage difference between voltage VPGM and voltage VQPW1, thereby increasing the threshold voltage. In the memory cell transistor MCsel corresponding to bit line BL_pg2, electrons are injected into the charge storage layer based on the voltage difference between voltage VPGM and voltage VQPW2, thereby increasing the threshold voltage. The voltage difference between the programming voltage VPGM and the channel voltage satisfies the relationship (VPGM - VSS) > (VPGM - VQPW1) > (VPGM - VQPW2). Therefore, the ease with which the threshold voltage rises satisfies the relationship of programming condition PG0 > programming condition PG1 > programming condition PG2. Furthermore, in the memory cell transistor MCsel corresponding to bit line BL_inh, the voltage of the floating channel increases with the increase of the voltage VPGM applied to word line WLsel. Therefore, the rise in threshold voltage is suppressed.

[0174] 1.3.5 Verification of voltage setting

[0175] Next, refer to Figure 12 An example of setting the verification voltage will be explained. Figure 12 This is a table showing an example of the setting of the verification voltage.

[0176] like Figure 12 As shown, using reference Figure 6 The verification voltages described are the verification high voltages VH for each write state. Specifically, the verification high voltage VH for state "S1" is voltage V1. The verification high voltage VH for state "S2" is voltage V2. The verification high voltage VH for state "S3" is voltage V3. The verification high voltage VH for state "S4" is voltage V4. The verification high voltage VH for state "S5" is voltage V5. The verification high voltage VH for state "S6" is voltage V6. The verification high voltage VH for state "S7" is voltage V7.

[0177] Next, the second verification low voltage VL2 for each write state will be explained. In state "S1", the second verification low voltage VL2 is voltage V1L2. Voltage V1L2 is lower than voltage V1. In state "S2", the second verification low voltage VL2 is voltage V2L2. Voltage V2L2 is higher than voltage V1 and lower than voltage V2. In state "S3", the second verification low voltage VL2 is voltage V3L2. Voltage V3L2 is higher than voltage V2 and lower than voltage V3. In state "S4", the second verification low voltage VL2 is voltage V4L2. Voltage V4L2 is higher than voltage V3 and lower than voltage V4. In state "S5", the second verification low voltage VL2 is voltage V5L2. Voltage V5L2 is higher than voltage V4 and lower than voltage V5. In state "S6", the second verification low voltage VL2 is voltage V6L2. Voltage V6L2 is a voltage higher than voltage V5 and lower than voltage V6. The second verification of state "S7" shows a low voltage VL2 of voltage V7L2. Voltage V7L2 is a voltage higher than voltage V6 and lower than voltage V7.

[0178] Next, the first verification low voltage VL1 for each write state will be explained. The first verification low voltage VL1 for state "S1" is voltage V1L1. Voltage V1L1 is lower than voltage V1L2. The verification high voltage VH for state "S(N-1)" (where N is an integer greater than 2, representing the number assigned to the write state), i.e., voltage V(N-1), is used as the first verification low voltage VL1 for states "S2" to "S7". More specifically, the first verification low voltage VL1 for state "S2" is the same voltage V1 as the verification high voltage VH for state "S1". The first verification low voltage VL1 for state "S3" is the same voltage V2 as the verification high voltage VH for state "S2". The first verification low voltage VL1 for state "S4" is the same voltage V3 as the verification high voltage VH for state "S3". The first verification low voltage VL1 for state "S5" is the same voltage V4 as the verification high voltage VH for state "S4". The first verification low voltage VL1 in state "S6" is the same voltage V5 as the verification high voltage VH in state "S5". The first verification low voltage VL1 in state "S7" is the same voltage V6 as the verification high voltage VH in state "S6".

[0179] 1.3.6 Specific example of the timing of executing VL1 verification actions

[0180] Next, refer to Figure 13 This section provides a specific example illustrating the timing of the VL1 verification action. Figure 13 This is a graph showing the relationship between the number of programming loops in the write action and the VL1 verification action. Figure 13 The table above shows the relationship between... Figure 8The same applies. For each write state, the part where the verification action is set is marked with a white circle. Moreover, the programming loop for the write action that is determined by the sequencer 14 to be in the write state is marked with a black circle. Figure 13 The following diagram illustrates the application of two programming conditions PG0 to PG2 and the disabling programming condition INH based on the results of the VL1 verification operation, VL2 verification operation, and VH verification operation. For example, in the table below, the portion indicated by "L" represents the application of programming condition PG0, the portion indicated by "L / H" represents the application of programming condition PG0 or disabling programming condition INH, the portion indicated by the shaded line represents the application of programming condition PG0, programming condition PG1, programming condition PG2, or disabling programming condition INH, and the portion indicated by "H" represents the application of disabling programming condition INH. The setting data used to apply programming condition PG1 or programming condition PG2 is stored in any of the latch circuits ADL, BDL, CDL, DDL, or TDL of each sense amplifier unit (SAU). The case of storing setting data in latch circuit TDL will be explained below.

[0181] like Figure 13 As shown, firstly, in the first programming cycle, data at the "L" level is stored in the latch circuit TDL corresponding to each write state.

[0182] For example, in state "S1", the number of times the programming loop for executing the VL1 verification action is pre-set. Figure 13 In the example shown, in the second programming loop, a VL1 verification operation using the voltage V1L1 corresponding to state "S1" is performed. More specifically, in the second programming loop, sequencer 14 performs a VL1 verification operation using the voltage V1L1 corresponding to state "S1", a VL2 verification operation using the voltage V1L2, a VH verification operation using the voltage V1, a VL2 verification operation using the voltage V2L2 corresponding to state "S2", and a VH verification operation using the voltage V2. Based on the result of the VL1 verification operation using the voltage V1L1 corresponding to state "S1", sequencer 14 updates the data of the latch circuit TDL corresponding to state "S1". As a result, in the latch circuit TDL corresponding to state "S1", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VL1 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S1", the data of the latch circuit TDL corresponding to the slow cell that fails VL1 verification becomes "H".

[0183] In the 5th programming loop, the sequencer 14 executes the verification actions corresponding to states "S1", "S2", and "S3". For example, in the 5th programming loop, the sequencer 14 determines that the write action corresponding to state "S1" has been completed. Furthermore, in this case, the write action corresponding to state "S1" in the 6th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V1 corresponding to state "S1" in the 5th programming loop as the result of the VL1 verification action corresponding to state "S2", and updates the data of the latch circuit TDL corresponding to state "S2". As a result, in the latch circuit TDL corresponding to state "S2", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V1 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S2", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V1 becomes "H".

[0184] In the 7th programming loop, the sequencer 14 performs the verification actions corresponding to states "S2", "S3", and "S4". For example, in the 7th programming loop, the sequencer 14 determines that the write action corresponding to state "S2" has been completed. Furthermore, in this case, the write action corresponding to state "S2" in the 8th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V2 corresponding to state "S2" in the 7th programming loop as the result of the VL1 verification action corresponding to state "S3", and updates the data of the latch circuit TDL corresponding to state "S3". As a result, in the latch circuit TDL corresponding to state "S3", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V2 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S3", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V2 becomes "H".

[0185] In the 9th programming loop, the sequencer 14 performs the verification actions corresponding to states "S3", "S4", and "S5". For example, in the 9th programming loop, the sequencer 14 determines that the write action corresponding to state "S3" has been completed. Furthermore, in this case, the write action corresponding to state "S3" in the 10th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V3 corresponding to state "S3" in the 9th programming loop as the result of the VL1 verification action corresponding to state "S4", and updates the data of the latch circuit TDL corresponding to state "S4". As a result, in the latch circuit TDL corresponding to state "S4", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V3 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S4", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V3 becomes "H".

[0186] In the 11th programming loop, the sequencer 14 performs the verification actions corresponding to states "S4", "S5", and "S6". For example, in the 11th programming loop, the sequencer 14 determines that the write action corresponding to state "S4" has been completed. Furthermore, in this case, the write action corresponding to state "S4" in the 12th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V4 corresponding to state "S4" in the 11th programming loop as the result of the VL1 verification action corresponding to state "S5", and updates the data of the latch circuit TDL corresponding to state "S5". As a result, in the latch circuit TDL corresponding to state "S5", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V4 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S5", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V4 becomes "H".

[0187] In the 13th programming loop, the sequencer 14 executes the verification actions corresponding to states "S5", "S6", and "S7". For example, in the 13th programming loop, the sequencer 14 determines that the write action corresponding to state "S5" has been completed. Furthermore, in this case, the write action corresponding to state "S5" in the 14th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V5 corresponding to state "S5" in the 13th programming loop as the result of the VL1 verification action corresponding to state "S6", and updates the data of the latch circuit TDL corresponding to state "S6". As a result, in the latch circuit TDL corresponding to state "S6", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V5 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S6", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V5 becomes "H".

[0188] In the 15th programming loop, the sequencer 14 performs the verification actions corresponding to states "S6" and "S7". For example, in the 15th programming loop, the sequencer 14 determines that the write action corresponding to state "S6" has been completed. Furthermore, in this case, the write action corresponding to state "S6" in the 16th programming loop can be omitted. The sequencer 14 considers the result of the VH verification action using voltage V6 corresponding to state "S6" in the 15th programming loop as the result of the VL1 verification action corresponding to state "S7", and updates the data of the latch circuit TDL corresponding to state "S7". As a result, in the latch circuit TDL corresponding to state "S7", the data of the latch circuit TDL corresponding to the fast cell that successfully verifies VH using voltage V6 becomes "L". On the other hand, in the latch circuit TDL corresponding to state "S7", the data of the latch circuit TDL corresponding to the slow cell that fails to verify VH using voltage V6 becomes "H".

[0189] 1.3.7 Programming Action Flow

[0190] Next, refer to Figures 14-19 This section illustrates an example of the process of programming actions. Figure 14 It is a timing diagram that represents the various wiring and signals in the programming process. Figures 15-19 This diagram illustrates the operation of the voltage generation circuit 16 and the sensing amplifier unit SAU during the programming process.

[0191] like Figure 14As shown, firstly, at time t1, the line decoder 18 applies voltage VSS to the word line WLsel. The sense amplifier unit SAU performs the first arithmetic operation, updating the data in the latch circuit SDL. The action of updating the data in the latch circuit SDL through the arithmetic operation will also be referred to as "SCAN". In the first arithmetic operation, if programming is disabled, "H" level data is stored in the corresponding latch circuit SDL; if programming is required, "L" level data is stored in the corresponding latch circuit SDL. That is, "H" level data is stored in the latch circuit SDL corresponding to the bit line BL_inh. Additionally, "L" level data is stored in the latch circuit SDL corresponding to the bit lines BL_pg0, BL_pg1, and BL_pg2.

[0192] Based on the "H" level data stored in the latch circuit SDL, node SEN1 is charged to the "H" level. More specifically, for example, in the sensing circuit SA, transistors 39 and 40 are turned on, and a "H" level voltage VHLB is applied to node SEN1 from the pre-charge circuit PCC. Then, transistors 39 and 43 are turned on. In this state, for example, transistor 62 of the latch circuit SDL is turned on. Thus, when the latch circuit SDL stores "L" level data, the voltage of the bus LBUS becomes "H". Conversely, when the latch circuit SDL stores "H" level data, the voltage of the bus LBUS becomes "L". When the bus LBUS is at the "H" level, transistor 44 is turned on, and therefore node SEN1 discharges via transistors 39, 43, and 44. Conversely, when the bus LBUS is at the "L" level, transistor 44 is turned off, and therefore node SEN1 does not discharge. That is, when the latch circuit SDL stores data at the "H" level, node SEN1 becomes the "H" level.

[0193] Sequencer 14 sets signal SEL1 to "1". This selects the first input terminal in the selector circuit 80 of voltage generation circuit 16. As a result, voltage VSS is applied to node XXL.

[0194] Sequencer 14 sets signal SEL2 to "0". Consequently, in selector circuit 81 of voltage generation circuit 16, input terminal 0 is selected. As a result, voltage VHSA + Vth is applied to node BLX.

[0195] Sequencer 14 sets signal SEL3 to "0". Consequently, in selector circuit 82 of voltage generation circuit 16, input terminal 0 is selected. As a result, voltage VHSA + Vth is applied to node BLC.

[0196] Sequencer 14 sets signal SEL4 to "1". This selects the first input terminal in selector circuit 82 of voltage generation circuit 16. As a result, voltage VSS is applied to node APLS.

[0197] Reference Figure 15 and Figure 16 The voltages of bit lines BL_inh, BL_pg0, BL_pg1 and BL_pg2 at time t1 are described.

[0198] like Figure 15 As shown, in the sense amplifier unit SAU connected to the bit line BL_inh, the latch circuit SDL stores data at the "H" level. Therefore, node INV_S becomes the "L" level. As a result, transistor 31 becomes on. VHSA + Vth is applied to the gates of transistors 33 and 34. Therefore, transistors 33 and 34 become on, enabling the transmission of voltage VHSA. In addition, transistor 30 becomes on. As a result, the sense amplifier unit SAU applies voltage VHSA as voltage VINH to the bit line BL_inh via transistors 31, 33, 34, and 30.

[0199] like Figure 16 As shown, in the sense amplifier unit SAU connected to bit lines BL_pg0, BL_pg1, and BL_pg2, the latch circuit SDL stores data at the "L" level. Therefore, node INV_S becomes at the "H" level. As a result, transistor 32 becomes on. Transistors 33, 34, and 30 also become on. Thus, the sense amplifier unit SAU applies voltage VSS to bit lines BL_pg0, BL_pg1, and BL_pg2 via transistors 32, 33, 34, and 30.

[0200] Next, in Figure 14 At time t2, the line decoder 18 applies a voltage VPASS to the word line WLsel. The voltage VPASS is a voltage that makes the corresponding memory cell transistor MC turn on, regardless of the threshold voltage of the memory cell transistor MC.

[0201] Sequencer 14 sets signal SEL2 to "2". This selects the second input terminal in selector circuit 81 of voltage generation circuit 16. As a result, voltage VSS is applied to node BLX.

[0202] Sequencer 14 sets signal SEL3 to "2". This selects the second input terminal in selector circuit 82 of voltage generation circuit 16. As a result, voltage VSS is applied to node BLC.

[0203] like Figure 17As shown, in the sense amplifier unit SAU, transistors 33 and 34 are in the off state. Therefore, the bit line BL_inh is in the floating state.

[0204] Subsequently, in Figure 14 At time t3, the sense amplifier unit SAU performs the second operation, updating the data in the latch circuit SDL. In the second operation, the use of... Figure 13 The described latch circuit TDL performs a logical AND operation between the inverted set data of VQPW1 and VQPW2 stored in the latch circuit TDL and the data stored in the latch circuit SDL. As a result, "H" level data is stored in the latch circuit SDL corresponding to bit lines BL_inh and BL_pg2. Additionally, "L" level data is stored in the latch circuit SDL corresponding to bit lines BL_pg0 and BL_pg1. Similar to time t1, node SEN1 is charged to "H" level based on the "H" level data stored in the latch circuit SDL.

[0205] Next, in Figure 14 At time t4, based on the second operation, the voltage of node SEN1 corresponding to bit line BL_inh becomes "L" level. On the other hand, the voltage of node SEN1 corresponding to bit line BL_pg2 remains unchanged at "H" level.

[0206] Subsequently, in Figure 14 At the indicated time t5, sequencer 14 sets signal SEL2 to "1". Consequently, in selector circuit 81 of voltage generation circuit 16, the first input terminal is selected. As a result, voltage VBLX is applied to node BLX.

[0207] Sequencer 14 sets signal SEL3 to "1". This selects the first input terminal in selector circuit 82 of voltage generation circuit 16. As a result, a voltage VQPW1 + Vth is applied to node BLC.

[0208] Sequencer 14 sets signal SEL4 to "0". Consequently, in selector circuit 83 of voltage generation circuit 16, input terminal 0 is selected. As a result, voltage VQPW2 + Vth is applied to node APLS.

[0209] like Figure 18 As shown, in the voltage generating circuit 16, the resistance values ​​r1 to r3 of the variable resistor circuits 71 to 73 are adjusted so that voltages Vnd11 to Vnd13 become voltage VQPW2 + Vth, voltage VBLX, and voltage VQPW1 + Vth, respectively. Voltages VQPW2 + Vth, VBLX, and VQPW1 + Vth satisfy the relationship "VQPW2 + Vth" > "VBLX" > "VQPW1 + Vth".

[0210] In the sense amplifier unit SAU connected to bit line BL_pg2, transistor 31 is turned on because node INV_S is at the "L" level. Therefore, voltage VHSA is applied to one end of transistor 33. Voltage VBLX is applied to the gate of transistor 33. Consequently, voltage VBLX-Vth is applied to one end of transistor 34. Additionally, transistor 38 is turned on because node SEN1 is at the "H" level. Furthermore, voltage VQPW2+Vth is applied to the gate of transistor 37. Therefore, voltage VQPW2 is applied to the other end of transistor 34. Voltage VQPW1+Vth is applied to the gate of transistor 34. Since voltage VQPW1+Vth is lower than voltages VQPW2 and VBLX-Vth, transistor 34 is turned off. Therefore, the sense amplifier unit SAU applies voltage VQPW2 to bit line BL_pg2.

[0211] Next, in Figure 14 At time t6, the sense amplifier unit SAU performs the third arithmetic operation, updating the data in the latch circuit SDL. In this third arithmetic operation, a logical AND operation is performed between the setting data of VQPW1 and VQPW2 stored in the latch circuit TDL and the data stored in the latch circuit SDL. As a result, "H" level data is stored in the latch circuit SDL corresponding to the bit lines BL_inh, BL_pg1, and BL_pg2.

[0212] like Figure 19 As shown, in the sense amplifier unit SAU connected to bit line BL_pg1, transistor 31 is turned on because node INV_S is at a "L" level. Therefore, a voltage VHSA is applied to one end of transistor 33. Furthermore, a voltage VBLX is applied to the gate of transistor 33. Therefore, a voltage VBLX - Vth is applied to one end of transistor 34. Additionally, transistor 38 is turned off because node SEN1 is at a "L" level. Therefore, no voltage VQPW2 is applied to the other end of transistor 34. Transistor 34 clamps the voltage of bit line BL_pg1 to VQPW1 based on the voltage VQPW1 + Vth applied to its gate. That is, the sense amplifier unit SAU applies a voltage VQPW1 to bit line BL_pg1.

[0213] Subsequently, in Figure 14At time t7, the line decoder 18 applies voltage VPGM to the word line WLsel. During the period from t6 to t7, the programming voltage VPGM is applied to the word line WLsel. During this time, the sense amplifier 19 applies voltage VSS to bit line BL_pg0, voltage VPQW1 to bit line BL_pg1, voltage VQPW2 to bit line BL_pg2, and voltage VINH (=VHSA) to bit line BL_inh. This injects charge based on the channel voltage into the charge storage layer of the memory cell transistor MCsel.

[0214] Then, at time t8, a recovery operation is performed to reset all wiring. Sequencer 14 sets signals SEL1 to SEL4 to "1", "2", "2", and "1" respectively.

[0215] 1.3.8 Write operation process

[0216] Next, refer to Figure 20 Here is an example illustrating the process of a write operation. Figure 20 This is a flowchart of the write operation. In the following description, variable j (j is an integer greater than or equal to 1) is used as the counter value (number of times) for the programming loop. Variable k (k is an integer greater than or equal to 1) is used as the counter value for the programming loop of the VL1 verification operation set to state "S1". Variable j is, for example, a variable controlled by a counter provided by sequencer 14. Variable j carries over as the programming loop is executed repeatedly. Variable k is a pre-set fixed value.

[0217] like Figure 20 As shown, firstly, sequencer 14 sets variable j = 1. In addition, sequencer 14 sets the number of the write state determined by the execution cell to N = 1 (step S10).

[0218] The sequencer 14 executes the programming and verification actions corresponding to the first programming cycle (step S11).

[0219] Sequencer 14 carries over variable j, making j = j + 1 (step S12).

[0220] Sequencer 14 checks whether variable j has reached variable k (step S13).

[0221] If j = k is not satisfied (step S13_No), that is, if the number of programming loops j has not reached the preset variable k, the sequencer 14 enters S11.

[0222] On the other hand, when j = k (step S13_ is), that is, when the number of programming loops j has reached the preset variable k, the sequencer 14 also executes the VL1 verification action corresponding to state "S1" (step S14) in the verification action of the next j-th programming loop.

[0223] Sequencer 14 performs cell determination for state "S(N)" (step S15). More specifically, when N=1, sequencer 14 performs cell determination for state "S1" based on the result of the VL1 verification action. Furthermore, when N≧2, sequencer 14 performs cell determination for state "S(N)" based on the result of the VH verification action for state "S(N-1)".

[0224] Sequencer 14 carries over variable j, making j = j + 1 (step S16).

[0225] Sequencer 14 executes the programming action and verification action corresponding to the j-th programming loop (step S17).

[0226] Sequencer 14 performs a detection action to determine whether the writing action of state "S(N)" has been completed (step S18).

[0227] If the write operation in state "S(N)" has not been completed (step S18_No), sequencer 14 proceeds to S16.

[0228] On the other hand, if the write operation in state "S(N)" is determined to be completed (step S18_Yes), the sequencer 14 confirms whether N has reached the upper limit (the uppermost write state) (step S19). That is, the sequencer 14 confirms whether the write operation in all states has been completed.

[0229] If N does not reach the upper limit (step S19_No), sequencer 14 carries over N, making N = N + 1 (step S20). After that, sequencer 14 proceeds to S15.

[0230] On the other hand, if N has reached its upper limit (step S19_), the sequencer 14 ends the writing operation.

[0231] 1.4 Effects of this implementation method

[0232] The semiconductor memory device employing the above-described embodiment can improve reliability. This effect will now be described in detail.

[0233] In a semiconductor memory device, the threshold voltage of a memory cell transistor (MC) targeted for writing is determined by the increase in threshold voltage caused by the preceding threshold voltage (exceeding the verification voltage of the write state) and the subsequent programming operation. After a write operation, the threshold voltages of multiple memory cell transistors (MCs) exhibit a difference close to a normal distribution. This difference in threshold voltage can arise from differences in the write characteristics of the memory cell transistors (MCs) or the magnitude of the increase in programming voltage. To accelerate the write operation, it is preferable to increase the magnitude of the increase in programming voltage. However, increasing the magnitude of the increase in programming voltage may lead to a widening of the threshold voltage distribution of the memory cell transistors (MCs).

[0234] In contrast, the semiconductor memory device 1 of this embodiment can set three verification voltages (first verification low voltage VL1, second verification low voltage VL2, and verification high voltage VH) for each write state. Voltages VL1, VL2, and VH satisfy the relationship VL1 < VL2 < VH. In the first verification operation using the first verification low voltage VL1, it is possible to distinguish between memory cell transistors MC (fast cells) with a relatively large rise in threshold voltage caused by the programming operation and memory cell transistors MC (slow cells) with a relatively small rise. Furthermore, based on the VL2 verification operation using the second verification low voltage VL2 and the VH verification operation using the verification high voltage VH, different programming conditions can be applied to fast cells and slow cells. This reduces the difference in the rise in threshold voltage between fast cells and slow cells.

[0235] For example, in the next programming operation, semiconductor memory device 1 applies programming condition PG0 to memory cell transistors MC (including both slow and fast cells) that failed the VL2 verification operation. Semiconductor memory device 1 treats the next programming operation as the final programming operation and applies programming condition PG1 to slow cells that succeeded in the VL2 verification operation but failed in the VH verification operation. Semiconductor memory device 1 treats the next programming operation as the final programming operation and applies programming condition PG2 to fast cells that succeeded in the VL2 verification operation but failed in the VH verification operation. Semiconductor memory device 1 sets memory cell transistors MC (including both slow and fast cells) that succeeded in the VH verification operation to be disabled for programming. Then, in the next programming operation, semiconductor memory device 1 applies a disabling programming condition. The voltage of bit line BL is different for each of the programming conditions PG0, PG1, PG2, and disabling programming conditions. The voltage of bit line BL satisfies the relationship BL_pg0 < BL_pg1 < BL_pg2 < BL_inh. Semiconductor memory device 1 can control the rise in the threshold voltage of memory cell transistors MC based on the voltage of bit line BL.

[0236] More specifically, by setting the voltages of bit lines BL_pg1 and BL_pg2 higher than the voltage of bit line L_pg0, the semiconductor memory device 1 enables the threshold voltage rise of memory cell transistors MC (including both slow and fast cells) that have successfully completed VL2 verification but failed VH verification to be less than the threshold voltage rise of memory cell transistors MC that have failed VL2 verification. Furthermore, by setting the voltage of bit line BL_pg1 lower than the voltage of bit line BL_pg2, the semiconductor memory device 1 can reduce the difference between the threshold voltage rise of slow cells and the threshold voltage rise of fast cells during programming operations of memory cell transistors MC that have successfully completed VL2 verification but failed VH verification.

[0237] This reduces the difference in threshold voltages among the transistors MC of the multiple memory cells included in the write state. Furthermore, it reduces the likelihood that the threshold voltage will fall below voltage VH (not reaching voltage VH) during the final programming operation of a slow cell. This improves the reliability of the semiconductor memory device 1.

[0238] Furthermore, by adopting the configuration of this embodiment, the verification high voltage VH of the previous state "S(N-1)" (where N is an integer of 2 or more) can be allocated as the first verification low voltage VL1 of the "S(N)" state. This simplifies the verification process and, consequently, suppresses the degradation of the processing power of the semiconductor memory device 1.

[0239] Furthermore, using the configuration of this embodiment, the sensing amplifier 19 can apply different voltages to the bit lines BL_pg0, BL_pg1, BL_pg2, and BL_inh during programming operations. For example, the sensing amplifier 19 can apply voltage VSS to bit line BL_pg0, voltage VQPW1 to bit line BL_pg1, voltage VQPW2 to bit line BL_pg2, and voltage VHSA to bit line BL_inh.

[0240] Furthermore, by adopting the configuration of this embodiment, in the voltage generation circuit 16, voltages VQPW1+Vth and VQPW2+Vth, corresponding to voltages VQPW1 and VQPW2 respectively, can be generated by voltage division based on multiple variable resistor circuits 71-73 connected in series with a power supply. Therefore, regardless of process differences, the relationship between voltage VQPW1+Vth and VQPW2+Vth can be maintained. As a result, the reliability of the semiconductor memory device 1 can be improved.

[0241] 2. Second Implementation Method

[0242] Next, the second embodiment will be described. In the second embodiment, two examples are shown regarding the setting of the first verification low voltage VL1. The following description will focus on the differences from the first embodiment.

[0243] 2.1 Case 1

[0244] First, let's explain the first example. In this example, we'll explain the case where VL1 verification is not performed in more than one write state, meaning cell determination to distinguish between slow and fast cells is not performed. For example, in states with fewer programming cycles, the difference between the threshold voltage of slow cells and the threshold voltage of fast cells is small. Therefore, in write states with a lower verification high voltage VH, cell determination can be omitted. In write states where cell determination is not performed, PG2 programming is performed on memory cell transistors MCsel with a threshold voltage exceeding voltage VL2 but below voltage VH, using voltage VQPW2.

[0245] First, refer to Figure 21 An example of setting the verification voltage will be explained. Figure 21 This is a table showing an example of the setting of the verification voltage.

[0246] like Figure 21 As shown, for example, in states "S1" to "S3", the first verification low voltage VL1 is not set. That is, in states "S1" to "S3", the sequencer 14 does not perform the VL1 verification operation, i.e., cell determination. In states "S4" to "S7", the sequencer 14 performs cell determination. The setting of other verification voltages is the same as in the first embodiment. Figure 12 Same. Furthermore, for a write state where the first verification low voltage VL1 is not set, there only needs to be one or more.

[0247] Secondly, refer to Figure 22 This section provides a specific example illustrating the timing of the VL1 verification action. Figure 22 This is a graph showing the relationship between the number of programming loops in the write action and the VL1 verification action. Figure 22 The example shown illustrates the application's use Figure 21 The verification voltage settings are explained.

[0248] like Figure 22 As shown, firstly, in the first programming cycle, data at the "L" level is stored in the latch circuit TDL corresponding to each write state. Since cell determination is not performed in states "S1" to "S3", the data in the latch circuit TDL remains unchanged at "L". Therefore, the PG1 programming operation using voltage VQPW1 is not performed. States "S4" to "S7" are the same as those using the first embodiment. Figure 13 The situation described is the same.

[0249] 2.2 Case 2

[0250] Next, the second example will be explained. In the second example, the case where the verification high voltage VH of state "S(N-1)" is not used as the first verification low voltage VL1 will be explained. That is, the case where the voltage VL1 is set one by one in each write state will be explained. For example, in the verification operation of the next programming cycle after the write operation in state "S(N-1)" is determined to be completed, the sequencer 14 performs the VL1 verification operation in states "S2" to "S7".

[0251] First, refer to Figure 23 An example of setting the verification voltage will be explained. Figure 23 This is a table showing an example of the setting of the verification voltage.

[0252] The first verification low voltage VL1 for each write state will be explained. Furthermore, the other verification voltages are the same as those in the first embodiment. Figure 12 same.

[0253] like Figure 23 As shown, the first verification low voltage VL1 in state "S1" is voltage V1L1. Voltage V1L1 is a voltage lower than voltage V1L2.

[0254] In state "S2", the first verification low voltage VL1 is voltage V2L1. Voltage V2L1 is a voltage higher than voltage V1L2 but lower than voltage V2L2. Voltage V2L1 can be a voltage higher or lower than voltage V1.

[0255] The first verification low voltage VL1 in state "S3" is voltage V3L1. Voltage V3L1 is a voltage higher than voltage V2L2 but lower than voltage V3L2. Voltage V3L1 can be a voltage higher or lower than voltage V2.

[0256] The first verification low voltage VL1 in state "S4" is voltage V4L1. Voltage V4L1 is a voltage higher than voltage V3L2 but lower than voltage V4L2. Voltage V4L1 can be a voltage higher or lower than voltage V3.

[0257] The first verification low voltage VL1 in state "S5" is voltage V5L1. Voltage V5L1 is a voltage higher than voltage V4L2 but lower than voltage V5L2. Voltage V5L1 can be a voltage higher or lower than voltage V4.

[0258] The first verification low voltage VL1 in state "S6" is voltage V6L1. Voltage V6L1 is a voltage higher than voltage V5L2 but lower than voltage V6L2. Voltage V6L1 can be a voltage higher or lower than voltage V5.

[0259] The first verification low voltage VL1 in state "S7" is voltage V7L1. Voltage V7L1 is a voltage higher than voltage V6L2 but lower than voltage V7L2. Voltage V7L1 can be a voltage higher or lower than voltage V6.

[0260] 2.3 Effects of this implementation method

[0261] By adopting the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0262] 3. Examples of variations, etc.

[0263] The semiconductor memory device of the embodiment includes: a memory cell array (17) including a plurality of memory cells (MC); word lines (WL) connected to the plurality of memory cells; a plurality of bit lines (BL) respectively connected to the plurality of memory cells; a sense amplifier (19) connected to the plurality of bit lines; and a controller (2) capable of performing a write operation including a repetitive programming cycle, the programming cycle including a programming operation and a verification operation. During the programming operation, the sense amplifier applies a programming voltage (VPGM) to the word lines and applies any one of a first voltage (VSS), a second voltage (VQPW1) higher than the first voltage, a third voltage (VQPW2) higher than the second voltage, and a fourth voltage (VHSA) higher than the third voltage to the plurality of bit lines respectively.

[0264] The aforementioned implementation provides a semiconductor memory device 1 with improved reliability.

[0265] Furthermore, the implementation method is not limited to the implementation method described above, but can be varied in various ways.

[0266] The term "connection" in the embodiments also includes indirect connections where other objects, such as transistors or resistors, are inserted in between.

[0267] In the described embodiment, during the VL1 verification operation, if the threshold voltage of the storage cell transistor is below VL1, it is considered a failure; if it exceeds VL1, it is considered a success. Similarly, during the VL2 verification operation, if the threshold voltage of the storage cell transistor is below VL2, it is considered a failure; if it exceeds VL2, it is considered a success. Furthermore, during the VH verification operation, if the threshold voltage of the storage cell transistor is below VH, it is considered a failure; if it exceeds VH, it is considered a success. However, the method for determining the failure or success of the verification operation is not limited to these. For example, during the VL1 verification operation, it could also be: if the threshold voltage of the storage cell transistor is below VL1, it is considered a failure; if it is above VL1, it is considered a success. Similarly, during the VL2 verification operation, it could also be: if the threshold voltage of the storage cell transistor is below VL2, it is considered a failure; if it is above VL2, it is considered a success. Alternatively, in the VH verification operation, it can be configured such that if the threshold voltage of the storage cell transistor is lower than voltage VH, it is considered a failure; if it is higher than voltage VH, it is considered a success. That is, whether to determine failure or success when the threshold voltage and the determination voltage are equal can be arbitrarily set. However, for the sake of operational stability, it is preferable to determine failure or success when the threshold voltage and the determination voltage are equal.

[0268] The embodiments are merely illustrative, and the scope of the invention is not limited to them.

[0269] [Explanation of Symbols]

[0270] 1 Semiconductor memory device

[0271] 2 Memory Controller

[0272] 10-input / output circuit

[0273] 11 Logic Control Circuit

[0274] 12 address register

[0275] 13 Instruction Register

[0276] 14 Sequencers

[0277] 15 Ready / Busy Circuits

[0278] 16 Voltage Generation Circuit

[0279] 17-cell array

[0280] 18-line decoder

[0281] 19 Sensing Amplifier

[0282] 20 Data Registers

[0283] 21-column decoder

[0284] 30–45, 50, 51, 62, 63, 74, 75 transistors

[0285] 46 capacitor components

[0286] 60, 61 inverters

[0287] 70 Current Source

[0288] 71-73 Variable Resistor Circuits

[0289] 76-78 drives

[0290] 80-83 selector circuit.

Claims

1. A semiconductor memory device comprising: Storage cell transistor; Word lines are connected to the gate of the storage cell transistor; Bit lines are connected to one end of the storage cell transistor; and A sensing amplifier unit is connected to the bit line; The sensing amplifier unit has: Sensing circuitry is connected to the bit line; as well as A latching circuit is connected to the sensing circuit; The sensing circuit includes: The first transistor has one end connected to the corresponding bit line and the other end connected to the first node; The second transistor has one end connected to the first node and the other end connected to the second node; The third transistor has one end connected to the second node and the other end can be supplied with the first voltage; The fourth transistor has one end connected to the second node and the other end connected to the third node; The fifth transistor, one end of which is connected to the first node; and The sixth transistor has one end to which the second voltage can be applied, the other end of which is connected to the other end of the fifth transistor, and its gate is connected to the third node; The third node can be connected to the latching circuit.

2. The semiconductor memory device of claim 1, further comprising a controller capable of performing a write operation including a repetitive programming cycle, the programming cycle including a programming operation and a verification operation; and During the programming operation, while a programming voltage is applied to the word line, the sensing circuit may apply any of the following voltages to the bit line: The third voltage, A fourth voltage higher than the third voltage, A fifth voltage higher than the fourth voltage, or A sixth voltage that is higher than the fifth voltage.

3. The semiconductor memory device according to claim 2, wherein: During the programming operation, while the programming voltage is applied to the word line, The controller operates in the following manner: Turn on the first transistor. A seventh voltage, corresponding to the fourth voltage, is applied to the gate of the second transistor. An eighth voltage, higher than the seventh voltage, is applied to the gate of the third transistor. The fourth transistor is switched off. A ninth voltage, corresponding to the fifth voltage and higher than the seventh voltage, is applied to the gate of the fifth transistor.

4. The semiconductor memory device according to claim 3, wherein: During the programming operation, when the sensing circuit applies the fourth voltage to the bit line, The controller operates in the following manner: Turn on the second transistor. This turns the third transistor on. The sixth voltage is applied as the first voltage to the other end of the third transistor. Set the sixth transistor to the off state; During the programming operation, when the sensing circuit applies the fifth voltage to the bit line, The controller operates in the following manner: Set the second transistor to the off state. The sixth voltage is applied as the first voltage to the other end of the third transistor. The sixth transistor is turned on.

5. The semiconductor memory device according to claim 4, wherein: During the programming operation, when the sensing circuit applies the fifth voltage to the bit line, The controller controls the third transistor in a manner that turns it on.

6. The semiconductor memory device according to claim 3, wherein: During the programming operation, when the sensing circuit applies the third voltage to the bit line, The controller operates in the following manner: Turn on the second transistor. This turns the third transistor on. The third voltage is applied as the first voltage to the other end of the third transistor. Set the sixth transistor to the off state; In the programming operation, when the sensing circuit applies the sixth voltage to the bit line while it is in a floating state, The controller operates in the following manner: Set the second transistor to the off state. The fifth transistor is turned off.

7. The semiconductor memory device according to claim 6, wherein: In the programming operation, when the sensing circuit causes the bit line to become floating, The controller controls the third transistor in a manner that turns it on.

8. The semiconductor memory device according to claim 6, wherein: It also includes a voltage generating circuit that can supply voltage to the sensing circuit. The voltage generating circuit includes: A current source that can supply current to the fourth node; The first variable resistor circuit has one end connected to the fourth node and the other end connected to the fifth node; and The second variable resistor circuit has one end connected to the fifth node and the other end connected to the sixth node; During the period when the programming voltage is applied to the word line in the programming operation, The controller operates in the following manner: The fourth node is electrically connected to the gate of the fifth transistor. The fifth node is electrically connected to the gate of the third transistor. The sixth node is electrically connected to the gate of the second transistor.

9. A semiconductor memory device comprising: Storage cell transistors from the 1st to the 4th; Word lines are connected to the gates of the transistors in the first to fourth memory cells; The first to fourth bit lines are respectively connected to one end of the first to fourth memory cell transistors; The first to fourth sensing amplifier units are respectively connected to the first to fourth bit lines; as well as The controller can perform write actions including a repetitive programming loop, the programming loop including programming actions and verification actions; During the programming operation, while a programming voltage is applied to the word lines, the first to fourth sense amplifier units may apply any of the following voltages to the first to fourth bit lines respectively: First voltage, A second voltage higher than the first voltage, or A third voltage higher than the second voltage. The verification actions include: The first verification action is based on the first verification voltage; as well as The second verification action is based on a second verification voltage that is higher than the first verification voltage. When the first to fourth memory cells are set to the first threshold voltage during the write operation, If in the first verification action of the programming loop in the Nth iteration, where N is a natural number, The threshold voltage of the first storage cell and the threshold voltage of the second storage cell are both determined to be less than the first verification voltage. The threshold voltage of the third storage cell and the threshold voltage of the fourth storage cell are determined to exceed the first verification voltage, and In the second verification action of the programming loop, which is the Pth iteration after the N+1th iteration, where P is a natural number, The threshold voltage of the first storage cell and the threshold voltage of the third storage cell are determined to exceed the second verification voltage. If the threshold voltage of the second storage cell and the threshold voltage of the fourth storage cell are both less than the second verification voltage, then... In any programming action of the programming loop after the (P+1)th iteration, The first sensing amplifier unit applies the second voltage to the first bit line. The second sensing amplifier unit applies the first voltage to the second bit line. The third sensing amplifier unit applies the third voltage to the third bit line. The fourth sensing amplifier unit applies the first voltage to the fourth bit line.

10. The semiconductor memory device of claim 9, further comprising: Fifth storage cell transistor; The 5th bit line is connected to one end of the 5th memory cell transistor; as well as The fifth sensing amplifier unit is connected to the fifth bit line; and The word line is also connected to the gate of the fifth memory cell transistor. During the programming operation, while the programming voltage is applied to the word lines, the first to fifth sense amplifier units may apply any of the following voltages to the first to fifth bit lines: The first voltage, The second voltage, The third voltage, or A fourth voltage that is higher than the third voltage. The verification action also includes a third verification action, which is based on a third verification voltage that is higher than the second verification voltage; When the fifth memory cell is set to the first threshold voltage during the write operation, If in the third verification action of the programming loop after the Pth iteration, If the threshold voltage of the fifth storage cell exceeds the third verification voltage, then... In the programming action of any subsequent programming loop after the (P+1)th iteration, The fifth sensing amplifier unit applies the fourth voltage to the fifth bit line.

11. The semiconductor memory device according to claim 10, wherein: When the first to fifth memory cells are set to the first threshold voltage during the write operation, If in the second verification action and the third verification action of any subsequent programming loop after the Pth time, If the threshold voltage of the first storage cell and the threshold voltage of the third storage cell exceed the second verification voltage but are less than the third verification voltage, then... In the programming action of any subsequent programming loop after the (P+1)th iteration, The first sensing amplifier unit applies the second voltage to the first bit line. The third sensing amplifier unit applies the third voltage to the third bit line.

12. The semiconductor memory device of claim 10, further comprising: The sixth storage cell transistor; The 6th bit line is connected to one end of the transistor in the 6th memory cell; as well as The sixth sensing amplifier unit is connected to the sixth bit line; and The word line is also connected to the gate of the sixth memory cell transistor. During the programming operation, while the programming voltage is applied to the word lines, the first to sixth sense amplifier units may apply any of the following voltages to the first to sixth bit lines: The first voltage, The second voltage, The third voltage, or The fourth voltage, The verification action also includes a fourth verification action based on the third verification voltage. In the case where the sixth memory cell is set to a second threshold voltage that is higher than the first threshold voltage during the write operation, In any of the programming loops after the (P+1)th iteration, The fourth verification action is performed on the sixth memory cell transistor.

13. The semiconductor memory device according to claim 12, wherein: If in the third verification action of the programming loop after the (P+1)th iteration, If the threshold voltage of the first to fourth storage cells exceeds the third verification voltage, then... The fourth verification action is performed on the sixth memory cell transistor.

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