Detection circuit, method and storage device

Abstract

The present disclosure relates to a detection circuit, a method and a storage device, wherein a mode register data processing module is configured to reserve first preset data in a mode register in response to a mode register write enable command; an external data transmission module is configured to write initial data to a storage array according to the first preset data and a preset encoding rule via an internal data transmission module in response to an enable signal, and further configured to read target data from the storage array in response to a read command; and a comparison module is configured to determine whether there is a data transmission abnormality according to a comparison result of comparing the first preset data with the target data, and save the comparison result to a preset position in the mode register. The embodiment can intelligently detect whether there is an abnormality in a data transmission process of a storage array, analyze failed bits in the storage array according to a detection result stored in the mode register, thereby improving utilization efficiency and working reliability of a semiconductor storage chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a detection circuit, method, and memory device. Background Technology

[0002] With the rapid development of semiconductor technology, the density and number of storage cells in the storage cell array of semiconductor storage devices are constantly increasing to meet the market demand for the storage capacity of semiconductor storage devices.

[0003] However, as the density of semiconductor memory devices continues to increase, memory cells exhibit characteristics such as smaller physical size, reduced stored charge, and lower noise immunity. The electromagnetic interactions between memory cells have a greater impact on the memory cells, increasing the likelihood of data loss. Design or manufacturing defects in semiconductor memory chips can increase the number of faulty addresses, affecting the yield or reliability of the semiconductor memory chip.

[0004] If faulty bits in semiconductor memory chips can be detected in a timely manner, it will undoubtedly improve the utilization efficiency and operational reliability of semiconductor memory chips. Summary of the Invention

[0005] This disclosure provides a detection circuit, method, and storage device that can intelligently detect whether there are any abnormalities in the storage array during data transmission and save the detection results to a mode register. This facilitates the analysis of faulty bits in the storage array based on the detection results stored in the mode register, thereby improving the utilization efficiency and operational reliability of the semiconductor memory chip.

[0006] To achieve the above and other objectives, one aspect of this disclosure provides a detection circuit, including a mode register data processing module, an external data transmission module, a comparison module, and an internal data transmission module disposed within a memory array. The mode register data processing module is used to respond to a mode register write enable command and write first preset data into a reserved mode register within the mode register. The external data transmission module is electrically connected to both the reserved mode register and the internal data transmission module, and is used to respond to an enable signal and write initial data to the memory array via the internal data transmission module according to the first preset data and a preset encoding rule, and is also used to respond to a read command and read target data from the memory array. The initial data has a byte length greater than the first preset data's byte length. The comparison module is electrically connected to both the mode register and the external data transmission module, and is used to compare the first preset data with the target data, determine whether a data transmission anomaly exists based on the comparison result, and save the comparison result to a preset location in the mode register. This embodiment can intelligently detect whether an anomaly exists in the memory array during data transmission and save the detection result to a preset location in the mode register, facilitating the analysis of faulty bits in the memory array based on the detection result stored in the mode register, thereby improving the utilization efficiency and operational reliability of the semiconductor memory chip.

[0007] In some embodiments, the comparison module is configured to: generate initial data according to a preset encoding rule based on first preset data, compare the initial data with target data, and determine whether there is a data transmission anomaly based on the comparison result, wherein the number of bytes in the initial data is associated with the number of bytes in the target data. This embodiment generates initial data with the number of bytes in the initial data associated with the number of bytes in the target data according to a preset encoding rule based on the first preset data, so as to facilitate comparison of whether the corresponding number of bytes in the initial data and target data are equal, thereby obtaining a comparison result. Based on the comparison result, it determines whether there is a data transmission anomaly in the storage array, reducing the complexity of obtaining the comparison result while improving the accuracy of the obtained comparison result.

[0008] In some embodiments, the number of bytes in the initial data is equal to the number of bytes in the target data. The comparison module is further configured to compare each bit of the initial data and the target data. If each bit of the initial data and the target data is equal, the data transmission is determined to be normal; otherwise, the data transmission is determined to be abnormal. By setting the number of bytes in the initial data to be equal to the number of bytes in the target data, and comparing each bit of the initial data and the target data, a comparison result is generated. This reduces the complexity of obtaining the comparison result while improving the accuracy of the obtained comparison result.

[0009] In some embodiments, the first preset data has N1 bytes; the initial data has N2 bytes; the external data transmission module includes a preset data transmission module, which includes N2 preset data transmission units; each bit of the first preset data is electrically connected to the input of the internal data transmission module via the corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2, and N3 are all positive integers. This embodiment reduces the complexity of writing initial data to the storage array based on the first preset data, and also reduces the complexity of the comparison module generating initial data based on the first preset data.

[0010] In some embodiments, the enable signal includes a write enable command; the preset data transmission unit includes a first gated inverter, which is configured such that: its input is electrically connected to the corresponding reserved mode register, and its output is electrically connected to the input of the internal data transmission module, or is electrically connected to the input of the internal data transmission module via a general data transmission module; the control terminal receives the write enable command and responds to the write enable command by writing initial data to the storage array via the internal data transmission module according to the received initial data and a preset encoding rule.

[0011] In some embodiments, the data transmitted by the N3 preset data transmission units corresponding to any bit of the first preset data are equal, which reduces the complexity of the circuit structure, thereby reducing the circuit production cost and improving the reliability of the circuit operation.

[0012] In some embodiments, the number of preset data transmission units corresponding to at least two bits of the first preset data is different, so as to improve the richness of the encoding rules.

[0013] In some embodiments, the enable signal further includes a write enable signal; the external data transmission module further includes a first data transmission module, the first data transmission module including a first data transmission unit with the same number of bytes as the target data; the first data transmission unit is configured to: have its input terminal electrically connected to the corresponding data bus, its output terminal electrically connected to the internal data transmission module, or be electrically connected to the internal data transmission module via a preset data transmission module or a general data transmission module, and its control terminal receiving a write enable signal, and responding to the write enable signal by providing corresponding data to the internal data transmission module according to the data provided by the corresponding data bus.

[0014] In some embodiments, the first data transmission unit includes a second gated inverter, which is configured such that: its input terminal is electrically connected to the corresponding data bus, its output terminal is electrically connected to the internal data transmission module, or it is electrically connected to the internal data transmission module via a preset data transmission module or a general data transmission module; and its control terminal receives a write enable signal and, in response to the write enable signal, provides corresponding data to the internal data transmission module according to the data provided by the corresponding data bus.

[0015] In some embodiments, the enable signal further includes a low-power write enable signal; the external data transmission module further includes a second data transmission module, the second data transmission module including a second data transmission unit with the same number of bytes as the target data; the second data transmission unit is configured to: have its input terminal electrically connected to the corresponding low-power data line, and its output terminal electrically connected to the internal data transmission module, or be electrically connected to the internal data transmission module via a preset data transmission module or a general data transmission module; and have its control terminal receive the low-power write enable signal, and respond to the low-power write enable signal by providing corresponding data to the internal data transmission module according to the data provided by the corresponding low-power data line.

[0016] In some embodiments, the second data transmission unit includes a third gated inverter, which is configured such that: its input terminal is electrically connected to the corresponding low-power data line, its output terminal is electrically connected to the internal data transmission module, or it is electrically connected to the internal data transmission module via a preset data transmission module or a general data transmission module; its control terminal receives a low-power write enable signal and is used to respond to the low-power write enable signal and provide corresponding data to the internal data transmission module according to the data provided by the corresponding low-power data line.

[0017] In some embodiments, the general data transmission module includes a first general data transmission module and a second general data transmission module. The first general data transmission module is configured such that: a first input terminal is connected to the output terminal of a preset data transmission module, and an output terminal is connected to the input terminal of an internal data transmission module; the second general data transmission module is configured such that: a first input terminal is connected to the output terminal of the first data transmission module, a second input terminal is connected to the output terminal of a second data transmission module, and an output terminal is connected to the second input terminal of the first general data transmission module.

[0018] In some embodiments, the first general-purpose data transmission module includes a first inverter, and the preset data transmission module is electrically connected to the internal data transmission module via the first inverter; and / or, the second general-purpose data transmission module includes a second inverter, and the first data transmission module is electrically connected to the input terminal of the first inverter via the second inverter.

[0019] In some embodiments, the preset data transmission unit further includes a third inverter, which is configured such that its input is connected to the output of the first gated inverter, the output of the first data transmission unit, and the output of the second data transmission unit, and its output is connected to the input of the internal data transmission module.

[0020] In some embodiments, the first general data transmission module and / or the second general data transmission module are located inside the storage array.

[0021] In some embodiments, the internal data transmission module includes an internal data transmission unit with the same number of bytes as the target data; the internal data transmission unit includes a fourth inverter, which is configured such that: its input is connected to the output of a first gated inverter, the output of a second gated inverter, and the output of a third gated inverter, or connected to the output of the first inverter, or connected to the output of the third inverter, and its output is connected to a storage array.

[0022] In some embodiments, the external data transmission module further includes a read module, which includes a read unit with the same number of bytes as the initial data; the read unit is used to read the target data from the storage array in response to a read command and transmit it to the comparison module.

[0023] In some embodiments, the read unit includes a fourth gated inverter and a fifth gated inverter. The fourth gated inverter is configured such that its input terminal is electrically connected to the storage array and its control terminal receives a read command. The fifth gated inverter is configured such that its input terminal is electrically connected to the output terminal of the fourth gated inverter and its output terminal is electrically connected to the input terminal of the comparison module, and its control terminal receives a read command.

[0024] Another aspect of the present disclosure provides a storage device, including a storage array, a mode register, and a detection circuit as described in any of the embodiments of the present disclosure.

[0025] Another aspect of this disclosure provides a detection method, comprising: controlling a mode register data processing module to write first preset data to a reserved mode register in the mode register in response to a mode register write enable command; controlling an external data transmission module to write initial data to a storage array via an internal data transmission module according to the first preset data and a preset encoding rule in response to an enable signal; and reading target data from the storage array in response to a read command; wherein the number of bytes of the initial data is greater than the number of bytes of the first preset data; comparing the first preset data with the target data, determining whether there is a data transmission anomaly based on the comparison result, and saving the comparison result to a preset position in the mode register.

[0026] In some embodiments, the number of bytes of the first preset data is N1; the number of bytes of the initial data is N2; the external data transmission module includes N2 preset data transmission units; each bit of the first preset data is electrically connected to the input terminal of the internal data transmission module via the corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2 and N3 are all positive integers.

[0027] In some embodiments, the data transmitted by the N3 preset data transmission units corresponding to any one bit of the first preset data are equal; or the number of preset data transmission units corresponding to at least two bits of the first preset data are different.

[0028] In the storage device or detection method described in the above embodiments, the storage array is intelligently detected to detect whether there is an abnormality during data transmission, and the detection result is saved to a preset position in the mode register. This facilitates the analysis of the faulty bits in the storage array based on the detection result stored in the mode register, thereby improving the utilization efficiency and operational reliability of the storage device. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the detection circuit provided in the first embodiment of this disclosure;

[0031] Figure 2 This is a schematic diagram of the detection circuit provided in the second embodiment of this disclosure;

[0032] Figure 3 This is a schematic diagram of the detection circuit provided in the third embodiment of this disclosure;

[0033] Figure 4 This is a schematic diagram of the detection circuit provided in the fourth embodiment of this disclosure;

[0034] Figure 5 This is a schematic diagram of the detection circuit provided in the fifth embodiment of this disclosure;

[0035] Figures 6a-6b for Figure 2 The circuit schematic diagram corresponding to the embodiment shown in the figure;

[0036] Figures 7a-7b for Figure 3 The circuit schematic diagram corresponding to the embodiment shown in the figure;

[0037] Figures 8a-8b for Figure 5 The circuit schematic diagram corresponding to the embodiment shown in the figure;

[0038] Figures 9a-9b for Figure 2 The circuit diagram corresponding to the embodiment shown in the figure;

[0039] Figures 10a-10b for Figure 5 The circuit diagram corresponding to the embodiment shown in the figure;

[0040] Figures 11a-11b for Figure 3The circuit diagram corresponding to the embodiment shown in the figure;

[0041] Figure 12 This is a schematic flowchart of a detection method provided in one embodiment of the present disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10. Mode register data processing module; 20. External data transmission module; 21. Preset data transmission module; 22. First data transmission module; 23. Second data transmission module; 24. General data transmission module; 25. Read module; 241. First general data transmission module; 242. Second general data transmission module; 30. Internal data transmission module; 40. Comparison module; 200. Mode register; 300. Memory array; 211. First preset data transmission unit; 21K. Kth preset data transmission unit; 21N2. N2th preset data transmission unit; 31. First internal data transmission unit; 3m. mth internal data transmission unit; 3N2. N2th internal data transmission unit. Detailed Implementation

[0044] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the specification of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Additionally, certain terms used throughout the specification and following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements with different names but the same function. In the following description and embodiments, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as “comprising, but not limited to…”. Similarly, the term “connection” is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be accomplished through a direct electrical connection or through an indirect electrical connection with other devices and connectors.

[0046] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0047] In Low Power Double Data Rate (LPDDR5) SDRAM, the control command informs the monitoring mode register command MR21 of its location information. After determining that the conditions are met, the monitoring mode register command MR21 enters the Write X command, and then receives the Column Address Strobe (CAS) command. Based on the high and low values ​​of the WXSA (determining the lower 8 bits) and WXSB (determining the higher 8 bits) bits of WRX in the CAS command, it determines whether to write 1 or 0 to the corresponding data at the specified column address. This function allows for writing large amounts of repetitive data, such as all "0"s or all "1"s, into the memory array. However, CAS_Write X is ineffective for writing other preset data into the memory array. This disclosure aims to promptly detect any data transmission anomalies in the memory array after writing preset data during the semiconductor memory chip design process or before mass production, and to identify faulty bits in the memory array, thereby effectively improving the design efficiency, production yield, and reliability of semiconductor memory chips.

[0048] Please see Figure 1In one embodiment of this disclosure, a detection circuit is provided, including a mode register data processing module 10, an external data transmission module 20, a comparison module 40, and an internal data transmission module 30 disposed within a storage array 300. The mode register data processing module 10 is used to respond to the mode register write enable command MRRWrt and write first preset data Data1 into a reserved mode register in the mode register 200. The external data transmission module 20 is electrically connected to both the reserved mode register and the internal data transmission module 30, and is used to respond to an enable signal and write initial data Datain to the storage array 300 via the internal data transmission module 30 according to the first preset data Data1 and a preset encoding rule. It is also used to respond to the read command Rd and read target data Rdata from the storage array 300. The number of bytes in the initial data Datain is greater than the number of bytes in the first preset data Data1. The comparison module 40 is electrically connected to both the mode register 200 and the external data transmission module 20, and is used to compare the first preset data Data1 with the target data Rdata, determine whether there is a data transmission abnormality based on the comparison result CompResult, and save the comparison result CompResult to a preset location in the mode register 200. This embodiment can intelligently detect whether there are any abnormalities in the storage array 300 during data transmission and save the detection results to a preset position in the mode register 200. This facilitates the analysis of the faulty bits in the storage array 300 based on the detection results stored in the mode register 200, thereby improving the utilization efficiency and operational reliability of the semiconductor memory chip.

[0049] As an example, please continue reading Figure 1 The comparison module 40 is configured to: generate initial data Datain according to a preset encoding rule based on the first preset data Data1; compare the initial data Datain with the target data Rdata; and determine whether there is a data transmission anomaly based on the comparison result CompResult. The number of bytes in the initial data Datain is associated with the number of bytes in the target data Rdata. In this embodiment, the initial data Datain, which is generated according to the first preset data Data1 and a preset encoding rule, is associated with the number of bytes in the target data Rdata. This facilitates the comparison of whether the corresponding bits in the initial data Datain and the target data Rdata are equal, thereby obtaining the comparison result CompResult. Based on the comparison result CompResult, it is determined whether there is a data transmission anomaly in the storage array 300. This reduces the complexity of obtaining the comparison result CompResult while improving the accuracy of the obtained comparison result CompResult.

[0050] As an example, please continue reading Figure 1The initial data (Datain) has the same number of bytes as the target data (Rdata). The comparison module 40 is further configured to compare each byte of the initial data (Datain) and the target data (Rdata) bit by bit. If all bytes of the initial data (Datain) and the target data (Rdata) are equal, the data transmission is considered normal; otherwise, the data transmission is considered abnormal. By setting the number of bytes of the initial data (Datain) to be equal to the number of bytes of the target data (Rdata), and comparing each byte of the initial data (Datain) and the target data (Rdata) bit by bit to generate a comparison result (CompResult), the complexity of obtaining the comparison result (CompResult) is reduced while the accuracy of the obtained comparison result (CompResult) is improved.

[0051] As an example, please continue reading Figure 1 LPDDR5 defines 128 8-bit mode registers, some of which are not effectively utilized and are generally reserved as mode registers. By utilizing the reserved mode registers in mode register 200 and the regular mode register write enable command MRRWrt, the function of writing initial data Datain to memory array 300 is completed. The content of the initial data Datain can be changed by setting different encoding rules, realizing the function of writing arbitrary data to memory array 300 without the need for a data strobe clock signal (WCK) or a data clock signal (DQ) and without increasing the complexity of the circuit structure, effectively improving the storage performance of the semiconductor memory device. By utilizing the low-power write function of the enable signal, this embodiment reduces the data transmission power consumption while ensuring the storage capacity of the semiconductor memory device.

[0052] For example, please refer to Figure 2 The first preset data Data1 has N1 bytes; the target data Rdata has N2 bytes; the external data transmission module 20 includes a preset data transmission module 21, which includes N2 preset data transmission units; each bit of the first preset data Data1 is electrically connected to the input terminal of the internal data transmission module 30 via the corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2, and N3 are all positive integers. This embodiment reduces the complexity of writing target data to the storage array 300 based on the initial data.

[0053] As an example, the preset data transmission module can be placed inside or outside the storage array. The embodiments disclosed herein are intended to illustrate the implementation principle and do not specifically limit the specific location of the preset data transmission module.

[0054] As an example, please continue reading Figure 2The enable signal also includes a write enable signal Wrt; the external data transmission module 20 also includes a first data transmission module 22, which includes a first data transmission unit equal to the number of bytes in the initial data Datain, for example, N2; the first data transmission unit is configured such that its input terminal is electrically connected to the corresponding data bus Dbus, its output terminal is electrically connected to the internal data transmission module 30, and its control terminal receives the write enable signal Wrt and, in response to the write enable signal Wrt, provides corresponding data to the internal data transmission module 30 according to the data provided by the corresponding data bus Dbus. In this embodiment, the first data transmission module 22, in response to the write enable signal Wrt, transmits data provided by the data bus Dbus to write data to the storage array with low power consumption, meeting the storage data writing requirements of different application scenarios.

[0055] As an example, please continue reading Figure 2 The enable signal also includes a low-power write enable signal Wrx; the external data transmission module 20 also includes a second data transmission module 23, which includes a second data transmission unit with the same number of bytes as the initial data Datain, for example, N2; the second data transmission unit is configured such that: the input terminal is electrically connected to the corresponding low-power data line WrxSa, the output terminal is electrically connected to the internal data transmission module 30, and the control terminal receives the low-power write enable signal Wrx and responds to it by providing corresponding data to the internal data transmission module 30 according to the data provided by the corresponding low-power data line WrxSa. The low-power data line WrxSa can be electrically connected to the data pad of the memory via other functional elements to receive data from outside the memory via the data pad, or the low-power data line WrxSa can be electrically connected to the mode register to receive data provided by the mode register, thereby realizing the function of using the second data transmission module 23 to respond to the low-power write enable signal Wrx and transmit the data provided by the low-power data line WrxSa according to the specific application scenario.

[0056] As an example, please continue reading Figure 2The external data transmission module 20 also includes a read module 25. The read module 25 includes read units with the same number of bytes as the initial data Datain, for example, N2. The read units are used to read the target data Rdata from the storage array 300 in response to the read command Rd and provide it to the comparison module 40. The comparison module 40 compares the first preset data Data1 with the target data Rdata, determines whether there is a data transmission anomaly based on the comparison result CompResult, and saves the comparison result CompResult to a preset location in the mode register 200. The read module 25 can be electrically connected to the internal data transmission module 30, and read the target data Rdata from the storage array 300 via the read-write conversion module (not shown) in the internal data transmission module 30. In other embodiments of this disclosure, the read module 25 can also be directly electrically connected to the storage array 300, or electrically connected to the storage array 300 via other functional elements.

[0057] For example, please refer to Figure 3 The enable signal also includes a write enable signal Wrt; the external data transmission module 20 also includes a first data transmission module 22, which includes a first data transmission unit equal to the number of bytes in the initial data Datain, for example, N2; the first data transmission unit is configured such that: its input terminal is electrically connected to the corresponding data bus Dbus, its output terminal is electrically connected to the internal data transmission module 30 via a preset data transmission module 21, and its control terminal receives the write enable signal Wrt and, in response to the write enable signal Wrt, provides corresponding data to the internal data transmission module 30 according to the data provided by the corresponding data bus Dbus. In this embodiment, by means of the first data transmission module 22 responding to the write enable signal Wrt, data provided by the data bus Dbus is transmitted to write data to the storage array with low power consumption, meeting the storage data writing requirements of different application scenarios.

[0058] As an example, please continue reading Figure 3The enable signal also includes a low-power write enable signal Wrx; the external data transmission module 20 also includes a second data transmission module 23, which includes a second data transmission unit with the same number of bytes as the initial data Datain, for example, N2; the second data transmission unit is configured such that: the input terminal is electrically connected to the corresponding low-power data line WrxSa, the output terminal is electrically connected to the internal data transmission module 30 via the preset data transmission module 21, and the control terminal receives the low-power write enable signal Wrx and responds to it by providing corresponding data to the internal data transmission module 30 according to the data provided by the corresponding low-power data line WrxSa. The low-power data line WrxSa can be electrically connected to the data pad of the memory via other functional elements to receive data from outside the memory via the data pad, or the low-power data line WrxSa can be electrically connected to the mode register to receive data provided by the mode register, thereby realizing the function of using the second data transmission module 23 to respond to the low-power write enable signal Wrx and transmit the data provided by the low-power data line WrxSa according to the specific application scenario.

[0059] For example, please refer to Figure 4 The enable signal also includes a write enable signal Wrt; the external data transmission module 20 also includes a first data transmission module 22, which includes a first data transmission unit equal to the number of bytes of the initial data Datain, for example, N2; the first data transmission unit is configured such that: its input terminal is electrically connected to the corresponding data bus Dbus, its output terminal is electrically connected to the internal data transmission module 30 via the general data transmission module 24, and its control terminal receives the write enable signal Wrt and, in response to the write enable signal Wrt, provides corresponding data to the internal data transmission module 30 according to the data provided by the corresponding data bus Dbus. In this embodiment, by means of the first data transmission module 22 responding to the write enable signal Wrt, data provided by the data bus Dbus is transmitted to write data to the storage array with low power consumption, meeting the storage data writing requirements of different application scenarios.

[0060] As an example, please continue reading Figure 4The enable signal also includes a low-power write enable signal Wrx; the external data transmission module 20 also includes a second data transmission module 23, which includes a second data transmission unit with the same number of bytes as the initial data Datain, for example, N2; the second data transmission unit is configured such that: the input terminal is electrically connected to the corresponding low-power data line WrxSa, the output terminal is electrically connected to the internal data transmission module 30 via the general data transmission module 24, and the control terminal receives the low-power write enable signal Wrx and responds to it by providing corresponding data to the internal data transmission module 30 according to the data provided by the corresponding low-power data line WrxSa. The low-power data line WrxSa can be electrically connected to the data pad of the memory via other functional elements to receive data from outside the memory via the data pad, or the low-power data line WrxSa can be electrically connected to the mode register to receive data provided by the mode register, thereby realizing the function of using the second data transmission module 23 to respond to the low-power write enable signal Wrx and transmit the data provided by the low-power data line WrxSa according to the specific application scenario.

[0061] For example, please refer to Figure 5 The general data transmission module 24 includes a first general data transmission module 241 and a second general data transmission module 242. The first general data transmission module 241 is configured such that its first input terminal is connected to the output terminal of a preset data transmission module 21, and its output terminal is connected to the input terminal of an internal data transmission module 30. The second general data transmission module 242 is configured such that its first input terminal is connected to the output terminal of the first data transmission module 22, its second input terminal is connected to the output terminal of the second data transmission module 23, and its output terminal is connected to the second input terminal of the first general data transmission module 241. This embodiment facilitates the use of existing functional components within the specific application circuit to achieve the function of writing arbitrary target data to the storage array, reducing circuit costs while being suitable for the actual needs of various application scenarios.

[0062] For example, please refer to Figures 6a-6bThe first preset data Data1 has N1 bytes; the initial data Datain has N2 bytes; the external data transmission module 20 includes N2 preset data transmission units, including the first preset data transmission unit 211, the Kth preset data transmission unit 21K, and the N2nd preset data transmission unit 21N2, where 1 ≤ K ≤ N2; each bit of the first preset data Data1 (Bit<0:7>) is transmitted to the internal data transmission module 30 via the corresponding N3 preset data transmission units, and then transmitted to the storage array 300 via the internal data transmission module 30, that is, the Bits are transmitted... <0> The preset number of data transmission units, the number of transmitted bits <1> The number of preset data transmission units, the number of transmitted bits <2> The number of preset data transmission units, the number of transmitted bits <3> The number of preset data transmission units, the number of transmitted bits <4> The number of preset data transmission units, the number of transmitted bits <5> The number of preset data transmission units, the number of transmitted bits <6> The number of preset data transmission units and the number of transmitted bits <7> The number of preset data transmission units is N3; N3 = N2 / N1; K, N1, N2, and N3 are all positive integers. In this embodiment, by writing initial data into the reserved mode register in the mode register 200, and then setting each bit of the initial data to be transmitted to the internal data transmission module 30 via the preset data transmission unit, and then transmitted to the storage array 300 via the internal data transmission module 30, the encoding relationship between the N3 preset data transmission units corresponding to each bit of the initial data can be set according to the content of the target data. This effectively reduces the complexity of setting the encoding rules and the complexity of writing the initial data to the storage array according to the first preset data Data1.

[0063] As an example, please continue reading Figures 6a-6bThe internal data transmission module includes N2 internal data transmission units, including the first internal data transmission unit, ..., the m-th internal data transmission unit, ... and the N2-th internal data transmission unit, where N3 = N2 / N1; 1 ≤ m ≤ N2. The first data transmission module includes first data transmission units 221, ..., 22j, ..., and 22N2, where 1 ≤ j ≤ N2. The second data transmission module includes second data transmission units 231, ..., 23i, ..., and 23N2, where 1 ≤ i ≤ N2. m, i, j, N1, N2, and N3 are all positive integers. The output terminals of the K-th preset data transmission unit 21K, the first data transmission unit 22j, and the second data transmission unit 23i are all connected to the input terminal of the corresponding m-th internal data transmission unit. This embodiment can set the encoding relationship between the N3 preset data transmission units corresponding to each digit of the initial data according to the content of the target data, effectively reducing the complexity of setting the encoding rules and reducing the complexity of writing the target data to the storage array 300 according to the first preset data Data1.

[0064] As an example, please continue reading Figures 6a-6b The m-th internal data transmission unit may include one or more of a drive unit, a buffer, and a read / write conversion unit. The type and number of electrical components included in the m-th internal data transmission unit can be determined based on the functional components in the actual circuit of the specific application scenario. Those skilled in the art can undoubtedly determine that equivalent / identical modifications made under the inventive concept of this disclosure fall within the protection scope of the embodiments of this disclosure.

[0065] As an example, please continue reading Figures 6a-6b The number of preset data transmission units corresponding to at least two bits of the first preset data is different, so as to improve the richness of the encoding rules.

[0066] For example, please refer to Figures 7a-7bThe output terminals of the first data transmission unit 22j and the second data transmission unit 23i are electrically connected to the input terminal of the m-th internal data transmission unit via the corresponding K-th preset data transmission unit 21K; 1≤K≤N2, 1≤m≤N2, 1≤i≤N2, 1≤j≤N2, where m, i, j, K, N1, N2, and N3 are all positive integers. In this embodiment, by writing initial data into the reserved mode register in the mode register 200, and then setting each bit of the initial data to be transmitted to the internal data transmission module 30 via the preset data transmission unit, and then transmitted to the storage array 300 via the internal data transmission module 30, the encoding relationship between the N3 preset data transmission units corresponding to each bit of the initial data can be set according to the content of the target data, which effectively reduces the complexity of setting the encoding rules and the complexity of writing the initial data to the storage array according to the first preset data Data1.

[0067] For example, please refer to Figures 8a-8b The first general data transmission module 241 includes first general data transmission units 2411, ..., first general data transmission units 241x, ..., and first general data transmission unit 241N2, where 1 ≤ x ≤ N2; the second general data transmission module 242 includes second general data transmission units 2421, ..., second general data transmission units 242y, ..., and second general data transmission unit 242N2, where 1 ≤ y ≤ N2; the output terminals of the first data transmission unit 22j and the second data transmission unit 23i are electrically connected to the input terminal of the first general data transmission unit 241x via the second general data transmission unit 242y; the Kth preset data transmission unit 21K is electrically connected to the input terminal of the mth internal data transmission unit via the first general data transmission unit 241x; 1 ≤ K ≤ N2, 1 ≤ m ≤ N2, 1 ≤ i ≤ N2, 1 ≤ j ≤ N2, 1 ≤ x ≤ N2, 1 ≤ y ≤ N2, where m, i, j, K, x, y, N1, N2 and N3 are all positive integers. In this embodiment, by writing initial data into the reserved mode register in the mode register 200, and then setting each bit of the initial data to be transmitted to the internal data transmission module 30 via a preset data transmission unit, and then to the storage array 300 via the internal data transmission module 30, the encoding relationship between the N3 preset data transmission units corresponding to each bit of the initial data can be set according to the content of the target data. This effectively reduces the complexity of setting the encoding rules and the complexity of writing the initial data to the storage array according to the first preset data Data1.

[0068] For example, please refer to Figures 8a-8bThe first general-purpose data transmission unit 241x may include one or more of a drive unit, a buffer, and a read / write conversion unit. The type and number of electrical components included in the first general-purpose data transmission unit 241x can be determined based on the functional components in the actual circuit of a specific application scenario. Those skilled in the art can undoubtedly determine that equivalent / identical modifications made under the inventive concept of this disclosure all fall within the protection scope of the embodiments of this disclosure.

[0069] For example, please refer to Figures 8a-8b The second general-purpose data transmission unit 242y may include one or more of a drive unit, a buffer, and a read / write conversion unit. The type and number of electrical components included in the first general-purpose data transmission unit 241x can be determined based on the functional components in the actual circuit of a specific application scenario. Those skilled in the art can undoubtedly determine that equivalent / identical modifications made under the inventive concept of this disclosure all fall within the protection scope of the embodiments of this disclosure.

[0070] For example, please refer to Figures 8a-8b The first general-purpose data transmission module and the second general-purpose data transmission module are located inside the storage array. In other embodiments of this disclosure, the first general-purpose data transmission module or the second general-purpose data transmission module is located outside the storage array. This embodiment facilitates the writing of arbitrary target data to the storage array by utilizing existing functional elements within the specific application circuit, reducing circuit costs while being suitable for the practical needs of various application scenarios.

[0071] For example, please refer to Figures 6a-8b The read module 25 includes N2 read units, including read units 251, ..., read units 25p, ... and read unit 25N2. Read unit 25p is electrically connected to the output of the m-th internal data transmission unit and the comparison module 40. It is used to read the target data Rdata from the storage array 300 in response to the read command Rd and provide it to the comparison module 40. 1≤p≤N2, 1≤m≤N2, and m, p, N1, N2, and N3 are all positive integers. In this embodiment, the comparison module 40 compares the first preset data Data1 with the target data Rdata, determines whether there is a data transmission anomaly based on the comparison result CompResult, and saves the comparison result CompResult to a preset position in the mode register 200.

[0072] For example, please refer to Figures 9a-9bThe enable signal includes a write enable command wrxR; the preset data transmission unit includes a first gated inverter inv1, which is configured such that its input is electrically connected to the corresponding reserved mode register, its output is electrically connected to the input of the internal data transmission module, and its control terminal receives the write enable command wrxR. In response to wrxR, the control terminal writes the target data to the storage array 300 via the internal data transmission module according to the received initial data and a preset encoding rule. This embodiment reduces the complexity of writing target data to the storage array 300 based on initial data.

[0073] As an example, please continue reading Figures 9a-9b The first data transmission unit includes a second gated inverter inv2, configured such that its input is electrically connected to the corresponding data bus, its output is electrically connected to the internal data transmission module 30, and its control terminal receives a write enable signal wrt. In response to the write enable signal wrt, inv2 provides corresponding data to the internal data transmission module 30 based on the data provided by the corresponding data bus. The second data transmission unit also includes a third gated inverter inv3, configured such that its input is electrically connected to the corresponding low-power data line wrxSa, its output is electrically connected to the internal data transmission module 30, and its control terminal receives a low-power write enable signal wrx. In response to the low-power write enable signal wrx, ​​inv3 provides corresponding data to the internal data transmission module 30 based on the data provided by the corresponding low-power data line wrxSa. During the period when the low-power write enable signal wrx is high, the third gated inverter inv3 provides corresponding data to the internal data transmission module 30 based on the data provided by the corresponding low-power data line wrxSa, and transmits the data to the memory array 300 via the internal data transmission module 30; during the period when the low-power write enable signal wrx is low, the third gated inverter inv3 is in a high-impedance state. This embodiment achieves low-power data transmission, reducing the complexity of the circuit structure while improving the energy efficiency of the circuit. The low-power data line WrxSa can be electrically connected to the data pads of the memory device via other functional components to receive data from outside the memory via the data pads, or the low-power data line WrxSa can be electrically connected to the mode register to receive data provided by the mode register, thereby enabling the second data transmission module 23 to respond to the low-power write enable signal Wrx and transmit the data provided by the low-power data line WrxSa according to the specific application scenario.

[0074] As an example, please continue reading Figures 9a-9bThe read unit 25p includes a fourth gated inverter inv8 and a fifth gated inverter inv9. The fourth gated inverter inv8 is configured such that its input is electrically connected to the storage array, its control terminal receives the read command Rd, and its output is electrically connected to the input of the m-th internal data transmission unit. The fifth gated inverter inv9 is configured such that its input is electrically connected to the output of the fourth gated inverter inv8, its output is electrically connected to the input of the comparison module 40, and its control terminal receives the read command Rd. The fourth gated inverter inv8 and the fifth gated inverter inv9 are used to read the target data Rdata from the storage array 300 in response to the read command Rd and provide it to the comparison module 40, where 1 ≤ p ≤ N2, 1 ≤ m ≤ N2, and m, p, N1, N2, and N3 are all positive integers. This embodiment facilitates the comparison module 40 in comparing the first preset data Data1 with the target data Rdata, determining whether there is a data transmission anomaly based on the comparison result CompResult, and saving the comparison result CompResult to a preset location in the mode register 200.

[0075] For example, please refer to Figures 10a-10b The first general-purpose data transmission module includes a first inverter inv4, and a first gated inverter inv1 is electrically connected to the internal data transmission module 30 via the first inverter inv4. The second general-purpose data transmission module includes a second inverter inv5, and the outputs of the second gated inverter inv2 and the third gated inverter inv3 are both electrically connected to the input of the first inverter inv4 via the second inverter inv5. This embodiment facilitates the writing of arbitrary target data to the storage array using existing functional components within the specific application circuit, reducing circuit costs while being suitable for the practical needs of various application scenarios.

[0076] For example, please refer to Figures 11a-11b The preset data transmission unit also includes a third inverter inv6, which is configured such that its input is electrically connected to the outputs of the first gated inverter inv1, the second gated inverter inv2, and the third gated inverter inv3, and its output is connected to the input of the internal data transmission module 30. This embodiment facilitates the use of existing functional components within the specific application circuit to achieve the function of writing arbitrary target data to the storage array, reducing circuit costs while being suitable for the actual needs of various application scenarios.

[0077] In one embodiment of this disclosure, a storage device is provided, including a storage array, a mode register, and the detection circuit described in any embodiment of this disclosure. By utilizing a reserved mode register in the mode register and the conventional mode register write enable command MRRWrt, the function of writing initial data to the storage array is achieved. Furthermore, the content of the target data can be changed by setting different encoding rules, enabling the writing of arbitrary data to the storage array without a data strobe clock signal (WCK) or data clock signal (DQ) and without increasing the complexity of the circuit structure, effectively improving the storage performance of the semiconductor storage device. Due to the utilization of the low-power write function of the enable signal, this embodiment reduces data transmission power consumption while ensuring the storage capacity of the semiconductor storage device. Since this embodiment can intelligently detect whether there are abnormalities in the storage array during data transmission and save the detection results to a preset position in the mode register, it is convenient to analyze the faulty bits in the storage array based on the detection results stored in the mode register, thereby improving the utilization efficiency and operational reliability of the semiconductor storage chip.

[0078] As an example, the write enable command and the data strobe clock signal (WCK) can be set to be inverse signals, so that the low-power write function of the write enable command is mutually exclusive during the writing of data to the memory array using the data strobe clock signal.

[0079] Further, please refer to Figure 12 In some embodiments of this disclosure, a detection method is provided, including:

[0080] Step S110: The control mode register data processing module responds to the mode register write enable command and writes the first preset data into the reserved mode register in the mode register.

[0081] Step S120: Control the external data transmission module to respond to the enable signal, write initial data to the storage array via the internal data transmission module according to the first preset data and the preset encoding rules, and respond to the read command to read the target data from the storage array; the number of bytes of the initial data is greater than the number of bytes of the first preset data.

[0082] Step S130: Compare the first preset data with the target data, determine whether there is a data transmission anomaly based on the comparison result, and save the comparison result to a preset location in the mode register.

[0083] Specifically, this embodiment intelligently detects whether there are any anomalies in the memory array during data transmission and saves the detection results to a preset location in the mode register. This facilitates the analysis of faulty bits in the memory array based on the detection results stored in the mode register, thereby improving the utilization efficiency and operational reliability of the semiconductor memory chip. This embodiment can, after writing initial data to a reserved mode register using a mode register write enable command, change the target data to be written to the memory array by altering the preset encoding rules and utilizing the low-power write function of the enable signal. This enables the writing of arbitrary data to the memory array without a data strobe clock signal or a data clock signal. Compared to the traditional write function using the write enable command, which can only write all "0"s or all "1"s to the memory array, this embodiment effectively improves the storage performance of the semiconductor memory device. Due to the utilization of the low-power write function of the enable signal, this embodiment reduces data transmission power consumption while ensuring the storage capacity of the semiconductor memory device.

[0084] As an example, the first preset data has N1 bytes; the initial data has N2 bytes; the external data transmission module includes N2 preset data transmission units; each bit of the first preset data is electrically connected to the input of the internal data transmission module via its corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2, and N3 are all positive integers to reduce the complexity of writing initial data to the storage array based on the initial data. It is possible to set the data transmitted by the N3 preset data transmission units corresponding to any bit of the first preset data to be equal, reducing the complexity of the circuit structure, thereby reducing circuit production costs and improving the reliability of circuit operation.

[0085] As an example, the number of preset data transmission units corresponding to at least two bits of the first preset data is different, in order to increase the richness of the encoding rules and adapt to a variety of different application scenarios.

[0086] The storage device or detection method in the above embodiments intelligently detects whether there are any abnormalities in the storage array during data transmission and saves the detection results to a preset location in the mode register. This facilitates the analysis of faulty bits in the storage array based on the detection results stored in the mode register, thereby improving the utilization efficiency and operational reliability of the semiconductor storage chip. This embodiment can, after writing initial data to a reserved mode register using a mode register write enable command, change the target data to be written to the storage array by altering the preset encoding rules and utilizing the low-power write function of the enable signal. This enables the writing of arbitrary data to the storage array without a data strobe clock signal or a data clock signal. Compared to the traditional write function using the write enable command, which can only write all "0"s or all "1"s to the storage array, this embodiment effectively improves the storage performance of the semiconductor storage device. Due to the utilization of the low-power write function of the enable signal, this embodiment reduces data transmission power consumption while ensuring the storage capacity of the semiconductor storage device.

[0087] For specific limitations on the detection method in the embodiments of this disclosure, please refer to the specific limitations on the detection circuit in the previous embodiments, which will not be repeated here.

[0088] It should be understood that, although Figure 12 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 12 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0089] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this disclosure can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0090] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A detection circuit, characterized in that, It includes a mode register data processing module, an external data transmission module, a comparison module, and an internal data transmission module located within the memory array; The mode register data processing module is used to respond to the mode register write enable command and write the first preset data into the reserved mode register in the mode register. The external data transmission module is electrically connected to both the reserved mode register and the internal data transmission module. It is used to respond to an enable signal, write initial data to the storage array via the internal data transmission module according to the first preset data and a preset encoding rule, and also to respond to a read command to read target data from the storage array. The number of bytes in the initial data is greater than the number of bytes in the first preset data. The comparison module is electrically connected to both the mode register and the external data transmission module. It is used to compare the first preset data with the target data, determine whether there is a data transmission abnormality based on the comparison result, and save the comparison result to a preset position in the mode register.

2. The detection circuit according to claim 1, characterized in that, The comparison module is configured as follows: The initial data is generated according to the first preset data and the preset encoding rules. The initial data is compared with the target data, and the comparison result is used to determine whether there is a data transmission anomaly. The number of bytes in the initial data is related to the number of bytes in the target data.

3. The detection circuit according to claim 2, characterized in that, The number of bytes in the initial data is equal to the number of bytes in the target data; the comparison module is further configured to: Compare each bit of the initial data with the target data. If all bits of the initial data and the target data are equal, the data transmission is considered normal. Conversely, if the data transmission is abnormal, it is determined that the transmission is abnormal.

4. The detection circuit according to any one of claims 1-3, characterized in that, The first preset data has N1 bytes; the initial data has N2 bytes; the external data transmission module includes a preset data transmission module, which includes N2 preset data transmission units. Each bit of the first preset data is electrically connected to the input terminal of the internal data transmission module via the corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2, and N3 are all positive integers.

5. The detection circuit according to claim 4, characterized in that, The enable signal includes a write enable command; the preset data transmission unit includes: The first gated inverter is configured such that its input is electrically connected to the corresponding reserved mode register, its output is electrically connected to the input of the internal data transmission module, or is electrically connected to the input of the internal data transmission module via a general data transmission module. The control terminal receives the write enable command and responds to the write enable command by writing target data to the storage array via the internal data transmission module according to the received initial data and a preset encoding rule.

6. The detection circuit according to claim 5, characterized in that, The data transmitted by the N3 preset data transmission units corresponding to any bit of the first preset data are equal; or The number of preset data transmission units corresponding to at least two bits of the first preset data is different.

7. The detection circuit according to claim 5, characterized in that, The enable signal further includes a write enable signal; the external data transmission module further includes a first data transmission module, the first data transmission module including a first data transmission unit with the same number of bytes as the initial data; The first data transmission unit is configured such that: its input terminal is electrically connected to the corresponding data bus, its output terminal is electrically connected to the internal data transmission module, or it is electrically connected to the internal data transmission module via the preset data transmission module or the general data transmission module; and its control terminal receives the write enable signal and responds to the write enable signal by providing corresponding data to the internal data transmission module according to the data provided by the corresponding data bus.

8. The detection circuit according to claim 7, characterized in that, The first data transmission unit includes: The second gated inverter is configured such that its input terminal is electrically connected to the corresponding data bus, its output terminal is electrically connected to the internal data transmission module, or it is electrically connected to the internal data transmission module via the preset data transmission module or the general data transmission module. The control terminal receives the write enable signal and responds to the write enable signal by providing corresponding data to the internal data transmission module according to the data provided by the corresponding data bus.

9. The detection circuit according to claim 8, characterized in that, The enable signal also includes a low-power write enable signal; the external data transmission module also includes a second data transmission module, the second data transmission module including a second data transmission unit with the same number of bytes as the initial data; The second data transmission unit is configured such that: its input terminal is electrically connected to the corresponding low-power data line, its output terminal is electrically connected to the internal data transmission module, or is electrically connected to the internal data transmission module via the preset data transmission module or a general data transmission module; and its control terminal receives the low-power write enable signal and responds to the low-power write enable signal by providing corresponding data to the internal data transmission module according to the data provided by the corresponding low-power data line.

10. The detection circuit according to claim 9, characterized in that, The second data transmission unit includes: The third gated inverter is configured such that its input terminal is electrically connected to the corresponding low-power data line, its output terminal is electrically connected to the internal data transmission module, or is electrically connected to the internal data transmission module via the preset data transmission module or a general data transmission module. Its control terminal receives a low-power write enable signal and responds to the low-power write enable signal by providing corresponding data to the internal data transmission module based on the data provided by the corresponding low-power data line.

11. The detection circuit according to claim 10, characterized in that, The general data transmission module includes: The first general data transmission module is configured such that: its first input terminal is connected to the output terminal of the preset data transmission module, and its output terminal is connected to the input terminal of the internal data transmission module; The second general-purpose data transmission module is configured such that: a first input terminal is connected to the output terminal of the first data transmission module, a second input terminal is connected to the output terminal of the second data transmission module, and the output terminal is connected to the second input terminal of the first general-purpose data transmission module.

12. The detection circuit according to claim 11, characterized in that, The first general-purpose data transmission module includes a first inverter, and the preset data transmission module is electrically connected to the internal data transmission module via the first inverter; and / or The second general-purpose data transmission module includes a second inverter, and the first data transmission module is electrically connected to the input terminal of the first inverter via the second inverter.

13. The detection circuit according to claim 12, characterized in that, The preset data transmission unit further includes: The third inverter is configured such that its input is connected to the output of the first gated inverter, the output of the first data transmission unit, and the output of the second data transmission unit, and its output is connected to the input of the internal data transmission module.

14. The detection circuit according to claim 11, characterized in that, The first general data transmission module and / or the second general data transmission module are located inside the storage array.

15. The detection circuit according to claim 13, characterized in that, The internal data transmission module includes an internal data transmission unit with the same number of bytes as the target data; The internal data transmission unit includes: The fourth inverter is configured such that its input is connected to the output of the first gated inverter, the output of the second gated inverter, and the output of the third gated inverter, or connected to the output of the first inverter, or connected to the output of the third inverter, and its output is connected to the memory array.

16. The detection circuit according to claim 10, characterized in that, The external data transmission module further includes a read module, which includes a read unit with the same number of bytes as the initial data; The read unit is used to read the target data from the storage array in response to the read command and transmit it to the comparison module.

17. The detection circuit according to claim 16, characterized in that, The read unit includes: The fourth gated inverter is configured such that its input terminal is electrically connected to the memory array, and its control terminal receives the read command. The fifth gated inverter is configured such that its input terminal is electrically connected to the output terminal of the fourth gated inverter, its output terminal is electrically connected to the input terminal of the comparison module, and its control terminal receives the read command.

18. A storage device, characterized in that, include: Storage array; Mode register; as well as The detection circuit according to any one of claims 1-17.

19. A detection method, characterized in that, include: The control mode register data processing module responds to the mode register write enable command and writes the first preset data to the reserved mode register in the mode register. The external data transmission module responds to an enable signal, writes initial data to the storage array via the internal data transmission module according to the first preset data and a preset encoding rule, and reads target data from the storage array in response to a read command; the number of bytes in the initial data is greater than the number of bytes in the first preset data. The first preset data is compared with the target data. Based on the comparison result, it is determined whether there is a data transmission anomaly, and the comparison result is saved to a preset position in the mode register.

20. The method according to claim 19, characterized in that, The first preset data has N1 bytes; the initial data has N2 bytes; the external data transmission module includes N2 preset data transmission units; Each bit of the first preset data is electrically connected to the input terminal of the internal data transmission module via the corresponding N3 preset data transmission units; N3 = N2 / N1; N1, N2, and N3 are all positive integers.

21. The method according to claim 20, characterized in that, The data transmitted by the N3 preset data transmission units corresponding to any bit of the first preset data are equal; or The number of preset data transmission units corresponding to at least two bits of the first preset data is different.

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