Driving circuit, driving method, and display device

Abstract

The present disclosure provides a driving circuit, a driving method and a display device. The driving circuit comprises a plurality of scanning driving circuits and a plurality of row pixel driving circuits; at least one of the scanning driving circuits comprises a driving signal output end, the driving signal output end is electrically connected with at least three adjacent row pixel driving circuits in the plurality of row pixel driving circuits, and is configured to provide a compensation control signal, a data writing control signal and a reset control signal to the at least three row pixel driving circuits respectively. The present disclosure ensures that the size of the display panel frame does not increase, increases the compensation time of each row pixel driving circuit, reduces the risk of display unevenness, and can double the display frame rate under the same compensation time as the existing solution, greatly improving the display quality.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method and display device. Background Technology

[0002] When AMOLED display devices are operating at high frame rates, insufficient charging time may prevent adequate compensation of the threshold voltage of the driving transistors in the pixel circuitry, leading to uneven display. This unevenness is particularly noticeable when displaying low grayscale images. Summary of the Invention

[0003] The main objective of this disclosure is to provide a driving circuit, driving method, and display device to solve the problem in the prior art where insufficient charging time cannot adequately compensate for the threshold voltage of the driving transistors included in the driving circuit of the pixel circuit, resulting in uneven display.

[0004] In one aspect, embodiments of this disclosure provide a driving circuit, including a multi-level scanning driving circuit and a multi-row pixel driving circuit;

[0005] At least one of the scanning drive circuits includes a drive signal output terminal, which is electrically connected to at least three adjacent rows of pixel drive circuits in the multi-row pixel drive circuit, and is configured to provide a compensation control signal, a data write control signal, and a reset control signal to the at least three rows of pixel drive circuits, respectively.

[0006] Optionally, the driving circuit includes an N+2 level scanning driving circuit and an N-row pixel driving circuit; N is an integer greater than 1.

[0007] The driving circuit includes an nth-level scanning driving circuit whose nth-level driving signal output terminal is electrically connected to the (n-2)th row pixel driving circuit, the (n-1)th row pixel driving circuit, and the nth row pixel driving circuit, respectively. The nth-level scanning driving circuit is configured to provide a compensation control signal to the (n-2)th-level pixel driving circuit, a data write control signal to the (n-1)th row pixel driving circuit, and a reset control signal to the nth row pixel driving circuit through the nth-level driving signal output terminal, respectively.

[0008] n is a positive integer, greater than 2, and less than N+1.

[0009] Optionally, the first-stage drive signal output terminal of the first-stage scan drive circuit is electrically connected to the first row pixel drive circuit, and the first-stage scan drive circuit is configured to provide a reset control signal to the first row pixel drive circuit through the first-stage drive signal output terminal.

[0010] The driving circuit includes an N+2 level scanning driving circuit whose N+2 level driving signal output terminal is electrically connected to the Nth row pixel driving circuit. The N+2 level scanning driving circuit is used to provide a compensation control signal to the Nth row pixel driving circuit through the N+2 level driving signal output terminal.

[0011] Optionally, the second-stage drive signal output terminal of the second-stage scan drive circuit included in the drive circuit is electrically connected to the first row pixel drive circuit and the second row pixel drive circuit respectively. The second-stage scan drive circuit is used to provide a data write control signal to the first row pixel drive circuit and a reset control signal to the second row pixel drive circuit through the second-stage drive signal output terminal.

[0012] The driving circuit includes an N+1 level scanning driving circuit whose N+1 level driving signal output terminal is electrically connected to the N-1 row pixel driving circuit and the N row pixel driving circuit, respectively. The N+1 level scanning driving circuit is used to provide compensation control signals to the N-1 row pixel driving circuit and data writing control signals to the N row pixel driving circuit through the N+1 level driving signal output terminal.

[0013] Optionally, the pixel driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first energy storage sub-circuit, and a second energy storage sub-circuit.

[0014] The data writing sub-circuit is electrically connected to the data writing control line, the compensation control line, the data line, and the first terminal of the driving sub-circuit, respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving sub-circuit under the control of the data writing control signal provided by the data writing control line and the compensation control signal provided by the compensation control line;

[0015] The compensation sub-circuit is electrically connected to the compensation control line, the control terminal of the drive sub-circuit, and the second terminal of the drive sub-circuit, respectively, and is used to control the connection between the control terminal of the drive sub-circuit and the second terminal of the drive sub-circuit under the control of the compensation control signal;

[0016] The first energy storage sub-circuit is electrically connected to the first terminal of the driving sub-circuit and is used to store electrical energy.

[0017] The second energy storage sub-circuit is electrically connected to the control terminal of the drive sub-circuit and is used to store electrical energy.

[0018] Optionally, the pixel driving circuit further includes a reset sub-circuit;

[0019] The reset sub-circuit is electrically connected to the data write control line, the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the data write control signal and the reset control signal provided by the reset control line.

[0020] Optionally, the pixel driving circuit further includes a reset sub-circuit;

[0021] The reset sub-circuit is electrically connected to the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the reset control signal provided by the reset control line.

[0022] Optionally, the pixel driving circuit further includes a first light emission control sub-circuit, a second light emission control sub-circuit, and an initialization sub-circuit;

[0023] The first light-emitting control sub-circuit is electrically connected to the light-emitting control line, the power supply voltage line and the first terminal of the driving sub-circuit, respectively, and is used to control the connection between the power supply voltage line and the first terminal of the driving sub-circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0024] The second light-emitting control sub-circuit is electrically connected to the light-emitting control line, the second terminal of the driving sub-circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the second terminal of the driving sub-circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0025] The initialization sub-circuit is electrically connected to the data write control line, the second initial voltage line, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage line into the first electrode of the light-emitting element under the control of the data write control signal.

[0026] Optionally, the data writing sub-circuit includes a first transistor and a second transistor; the compensation sub-circuit includes a third transistor;

[0027] The control electrode of the first transistor is electrically connected to the data write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0028] The control electrode of the second transistor is electrically connected to the compensation control line, and the second electrode of the second transistor is electrically connected to the first terminal of the driving sub-circuit.

[0029] The control electrode of the third transistor is electrically connected to the compensation control line, the first electrode of the third transistor is electrically connected to the control terminal of the driving sub-circuit, and the second electrode of the third transistor is electrically connected to the second terminal of the driving sub-circuit.

[0030] The first energy storage sub-circuit includes a first capacitor;

[0031] The first plate of the first capacitor is electrically connected to the first terminal of the driving sub-circuit, and the second plate of the first capacitor is electrically connected to the power supply voltage line.

[0032] Optionally, the reset sub-circuit includes a fourth transistor and a fifth transistor;

[0033] The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor.

[0034] The control electrode of the fifth transistor is electrically connected to the data write control line, and the second electrode of the fifth transistor is electrically connected to the control terminal of the driving sub-circuit.

[0035] Optionally, the reset sub-circuit includes a fourth transistor;

[0036] The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the control terminal of the driving sub-circuit.

[0037] Optionally, the first light-emitting control sub-circuit includes a sixth transistor, the second light-emitting control sub-circuit includes a seventh transistor, the initialization sub-circuit includes an eighth transistor, the driving sub-circuit includes a driving transistor, and the second energy storage sub-circuit includes a second capacitor.

[0038] The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor.

[0039] The control electrode of the seventh transistor is electrically connected to the light-emitting control line, the first electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element.

[0040] The control electrode of the eighth transistor is electrically connected to the data write control line, the first electrode of the eighth transistor is electrically connected to the second initial voltage line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0041] The first plate of the second capacitor is electrically connected to the control electrode of the driving transistor, and the second plate of the second capacitor is electrically connected to the power supply voltage line.

[0042] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N rows of reset control lines, N rows of data write control lines, and N rows of compensation control lines; the reset control lines, the data write control lines, and the compensation control lines all extend along a first direction;

[0043] The driving circuit includes pixel driving circuits that are electrically connected to the corresponding row reset control line, the corresponding row data write control line and the corresponding row compensation control line, respectively.

[0044] The reset control line, the data write control line, and the compensation control line of each row extend along the first direction to the surrounding area, and in the surrounding area, the nth row reset control line, the (n-1)th row data write control line, and the (n-2)th row compensation control line are electrically connected, and the first row data write control line is electrically connected to the second row reset control line;

[0045] n is a positive integer, greater than 2, and less than N+1; N is an integer greater than 1.

[0046] Optionally, in the surrounding area, the first row of data write control lines is electrically connected to the second row of reset control lines, and the Nth row of data write control lines is electrically connected to the (N-1)th row of compensation control lines.

[0047] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N rows of light-emitting control lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding row of light-emitting control lines;

[0048] Each row of pixel driving circuits includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor.

[0049] The gate of the fourth transistor and the corresponding row reset control line are integrated into one structure; the gate of the eighth transistor and the next row reset control line adjacent to the corresponding row reset control line are integrated into one structure.

[0050] The gate of the first transistor, the gate of the fifth transistor, and the corresponding row data write control line are integrated into one structure;

[0051] The first gate of the third transistor, the second gate of the third transistor, the gate of the second transistor, and the corresponding row compensation control line are integrated into one structure.

[0052] The gate of the sixth transistor, the gate of the seventh transistor, and the corresponding row light-emitting control line are integrated into one structure.

[0053] The gate of the driving transistor is disposed between the corresponding row compensation control line and the corresponding row light emission control line; the gate of the driving transistor is multiplexed as the first plate of the second capacitor; the second plate of the second capacitor is multiplexed as the second plate of the first capacitor; and the drain of the sixth transistor is multiplexed as the first plate of the first capacitor.

[0054] The corresponding row reset control line, the corresponding row data write control line, the corresponding row compensation control line and the corresponding row light emission control line, which are electrically connected to the pixel driving circuit of the same row, are arranged sequentially along the second direction;

[0055] The first direction intersects with the second direction.

[0056] Optionally, the active layers of the fourth transistor, the fifth transistor, the third transistor, the driving transistor, the second transistor, the first transistor, the sixth transistor, the seventh transistor, and the eighth transistor are formed of continuous semiconductor layers.

[0057] The channels of the fourth transistor, the fifth transistor, and the driving transistor are arranged sequentially along the second direction;

[0058] The channels of the first transistor, the second transistor, and the sixth transistor are arranged sequentially along the second direction.

[0059] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes N rows of second initial voltage lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding rows of second initial voltage lines; the second initial voltage lines and the second plate of the second capacitor are located on the same layer;

[0060] The orthographic projection of the corresponding row second initial voltage line on the substrate is located on the side of the corresponding row reset control line on the substrate that is far from the orthographic projection of the corresponding row data write control line on the substrate.

[0061] In a second aspect, embodiments of this disclosure also provide a driving method for driving the aforementioned driving circuit, the driving method comprising:

[0062] The driving circuit includes at least one scanning driving circuit that provides compensation control signals, data write control signals, and reset control signals to at least three adjacent rows of pixel driving circuits through the driving signal output terminal.

[0063] In a third aspect, embodiments of this disclosure also provide a display device including the driving circuit described above.

[0064] Optionally, the display device according to at least one embodiment of this disclosure further includes a display substrate, wherein the pixel driving circuit included in the driving circuit is disposed in the display area of ​​the display substrate, and the scanning driving circuit included in the driving circuit is disposed in the peripheral area of ​​the display substrate.

[0065] The driving circuit, driving method, and display device described in this disclosure partially overlap the driving signals output by adjacent scanning driving circuits through their driving signal output terminals. The driving signal output by this stage is used as the compensation control signal, data writing control signal, and reset control signal provided to at least three adjacent rows of pixel driving circuits. In this way, not only is the size of the display panel bezel not increased, but the compensation time of each row of pixel driving circuits is also increased, reducing the risk of mura (display inhomogeneity). Furthermore, while maintaining the same compensation time as existing solutions, the display frame rate can be doubled, greatly improving the display quality. Attached Figure Description

[0066] Figure 1 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0067] Figure 2 This is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0068] Figure 3 This is a structural diagram of the pixel driving circuit described in an embodiment of this disclosure;

[0069] Figure 4 This is a structural diagram of the pixel driving circuit according to at least one embodiment of the present disclosure;

[0070] Figure 5 This is a structural diagram of the pixel driving circuit according to at least one embodiment of the present disclosure;

[0071] Figure 6 This is a structural diagram of the pixel driving circuit according to at least one embodiment of the present disclosure;

[0072] Figure 7 This is a structural diagram of the pixel driving circuit according to at least one embodiment of the present disclosure;

[0073] Figure 8 This is a circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0074] Figure 9 This is a public announcement. Figure 6 The timing diagram of at least one embodiment of the pixel driving circuit shown is as follows:

[0075] Figure 10 This is a circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure;

[0076] Figure 11 This is a schematic diagram of the connection relationship between multiple rows of control lines electrically connected to each row of pixel driving circuits in the driving circuit described in at least one embodiment of this disclosure;

[0077] Figure 12 Is Figure 8 Based on at least one embodiment of the pixel driving circuit shown, a schematic diagram illustrating the electrodes of each transistor and the plates of each capacitor is provided.

[0078] Figure 13 yes Figure 18 Layout diagram of the active layer in the diagram;

[0079] Figure 14 yes Figure 18 Layout diagram of the first gate metal layer in the middle;

[0080] Figure 15 yes Figure 18 Layout diagram of the second gate metal layer;

[0081] Figure 16 yes Figure 18 Layout diagram of the first source / drain metal layer in the image;

[0082] Figure 17 yes Figure 18 The layout diagram of the second source / drain metal layer in the diagram.

[0083] Figure 18 For corresponding Figure 8 A schematic diagram of the layout of at least one embodiment of the shift register unit shown;

[0084] Figure 19 Is Figure 18 A schematic diagram with vias added based on the above. Detailed Implementation

[0085] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0086] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0087] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0088] The driving circuit described in this embodiment includes a multi-level scanning driving circuit and a multi-row pixel driving circuit;

[0089] At least one of the scanning drive circuits includes a drive signal output terminal, which is electrically connected to at least three adjacent rows of pixel drive circuits in the multi-row pixel drive circuit, and is configured to provide a compensation control signal, a data write control signal, and a reset control signal to the at least three rows of pixel drive circuits, respectively.

[0090] In the driving circuit described in the embodiments of this disclosure, at least one scanning driving circuit is electrically connected to at least three adjacent rows of pixel driving circuits through its driving signal output terminal. The scanning driving circuit is configured to provide a compensation control signal, a data write control signal, and a reset control signal to the at least three rows of pixel driving circuits respectively through the driving signal output terminal.

[0091] The driving circuit described in this embodiment, without adding a GOA (Gate On Array) circuit unit, utilizes the partial overlap between the driving signals output by adjacent scanning driving circuits through their driving signal output terminals. The driving signal output from this stage is used as the compensation control signal, data write control signal, and reset control signal provided to at least three adjacent rows of pixel driving circuits. In this way, not only is the size of the display panel bezel not increased, but the compensation time of each row of pixel driving circuits is also increased, reducing the risk of mura (display unevenness). Furthermore, while maintaining the same compensation time as existing solutions, the display frame rate can be doubled, greatly improving the display quality.

[0092] In at least one embodiment of this disclosure, at least one level of the multi-level scanning driving circuit may include a corresponding level driving signal output terminal. Each of the corresponding level driving signal output terminals may be electrically connected to at least three adjacent rows of pixel driving circuits included in the driving circuit, so as to provide compensation control signals, data writing control signals and reset control signals to the at least three rows of pixel driving circuits respectively.

[0093] In at least one embodiment of this disclosure, the driving circuits output by adjacent row scanning driving circuits through their driving signal output terminals are in a state of overlap for half of the pulses, but this is not a limitation.

[0094] In at least one embodiment of this disclosure, although the pixel driving circuit uses a compensation control signal more than related solutions, no new driving circuit is required. In at least one embodiment of this disclosure, the signals provided by adjacent row scanning driving circuits overlap in half of their pulses, and the scanning driving module needs to use four clock signals to generate the signal.

[0095] Optionally, the scanning driving module includes N+2 levels of scanning driving circuits, and the driving circuit includes N rows of pixel driving circuits; N is an integer greater than 1.

[0096] The driving circuit includes an nth-level scanning driving circuit whose nth-level driving signal output terminal is electrically connected to the (n-1)th row pixel driving circuit, the nth row pixel driving circuit, and the (n-2)th row pixel driving circuit, respectively. The nth-level scanning driving circuit is configured to provide a compensation control signal to the (n-2)th-level pixel driving circuit, a data write control signal to the (n-1)th row pixel driving circuit, and a reset control signal to the nth row pixel driving circuit through the nth-level driving signal output terminal, respectively.

[0097] n is a positive integer, greater than 2, and less than N+1.

[0098] In at least one embodiment of this disclosure, the nth-level scanning driving circuit of the driving circuit can provide compensation control signals, data writing control signals and reset control signals to the three adjacent rows of pixel driving circuits through the nth-level driving signal output terminal.

[0099] In at least one embodiment of this disclosure, the driving circuit includes a first-stage driving signal output terminal of a first-stage scanning driving circuit electrically connected to a first-row pixel driving circuit, wherein the first-stage scanning driving circuit is configured to provide a reset control signal to the first-row pixel driving circuit through the first-stage driving signal output terminal.

[0100] The driving circuit includes an N+2 level scanning driving circuit whose N+2 level driving signal output terminal is electrically connected to the Nth row pixel driving circuit. The N+2 level scanning driving circuit is used to provide a compensation control signal to the Nth row pixel driving circuit through the N+2 level driving signal output terminal.

[0101] In a specific implementation, the first-stage scanning driving circuit of the driving circuit provides a reset control signal to the first row pixel driving circuit through the first-stage driving signal output terminal, and the last-stage scanning driving circuit (that is, the N+2th stage scanning driving circuit of the driving circuit) provides a compensation control signal to the last row pixel driving circuit (that is, the Nth row pixel driving circuit) through the last-stage driving signal output terminal (that is, the N+2th stage driving signal output terminal).

[0102] Optionally, the second-stage drive signal output terminal of the second-stage scan drive circuit included in the drive circuit is electrically connected to the first row pixel drive circuit and the second row pixel drive circuit respectively. The second-stage scan drive circuit is used to provide a data write control signal to the first row pixel drive circuit and a reset control signal to the second row pixel drive circuit through the second-stage drive signal output terminal.

[0103] The scanning circuit includes an N+1 level scanning drive circuit whose N+1 level drive signal output terminal is electrically connected to the N-1 row pixel drive circuit and the N row pixel drive circuit, respectively. The N+1 level scanning drive circuit is used to provide compensation control signals to the N-1 row pixel drive circuit and data writing control signals to the N row pixel drive circuit through the N+1 level drive signal output terminal.

[0104] In at least one embodiment of this disclosure, the nth-level scan driving circuit includes an nth-level driving signal output terminal, through which an nth-level driving signal is output; the first-level scan driving circuit includes a first-level driving signal output terminal, through which a first-level driving signal is output; the second-level scan driving circuit includes a second-level driving signal output terminal, through which a second-level driving signal is output; the (N+1)th-level scan driving circuit includes an (N+1)th-level driving signal output terminal, through which an (N+1)th-level driving signal is output; and the (N+2)th-level scan driving circuit includes an (N+2)th-level driving signal output terminal, through which an (N+2)th-level driving signal is output.

[0105] exist Figure 1 In the diagram, GU1 is the first-level scan drive circuit, GU2 is the second-level scan drive circuit, GU3 is the third-level scan drive circuit, GU4 is the fourth-level scan drive circuit, GU5 is the fifth-level scan drive circuit, GUN-1 is the (N-1)th-level scan drive circuit, GUN is the Nth-level scan drive circuit, GUN+1 is the N+1th-level scan drive circuit, and GN+2 is the N+2th-level scan drive circuit.

[0106] The circuit labeled P0 is the pseudo-pixel driving circuit; P1 is the first row pixel driving circuit; P2 is the second row pixel driving circuit; P3 is the third row pixel driving circuit; P4 is the fourth row pixel driving circuit; P5 is the fifth row pixel driving circuit; PN-1 is the (N-1)th row pixel driving circuit; PN is the Nth row pixel driving circuit; PN-2 is the (N-2)th row pixel driving circuit; and PN-3 is the (N-3)th row pixel driving circuit.

[0107] exist Figure 1 In at least one embodiment of the driving circuit shown, the pseudo-pixel driving circuit P0 is not used to drive the corresponding light-emitting element to emit light, but rather to ensure that the process conditions of the pixel driving circuits in each column disposed in the display area are consistent. Figure 1 In at least one embodiment of the driving circuit shown, the pseudo-pixel driving circuit P0 may not be provided.

[0108] exist Figure 1 At least one embodiment of the driving circuit shown, when in operation,

[0109] GU1 provides a reset control signal to P1 through the first-stage drive signal output terminal O1;

[0110] GU2 provides a data write control signal to P1 and a reset control signal to P2 through the second-stage drive signal output terminal O2;

[0111] GU3 provides a compensation control signal to P1, a data write control signal to P2, and a reset control signal to P3 through the third-stage drive signal output terminal O3;

[0112] GU4 provides a compensation control signal to P2, a data write control signal to P3, and a reset control signal to P4 through the fourth-stage drive signal output terminal O4.

[0113] GU5 provides a compensation control signal to P3, a data write control signal to P4, and a reset control signal to P5 through the fifth-stage drive signal output terminal O5;

[0114] GUN-1 provides a compensation control signal to PN-3, a data write control signal to PN-2, and a reset control signal to PN-1 through the N-1 stage drive signal output terminal ON-1;

[0115] GUN provides a compensation control signal to PN-2, a data write control signal to PN-1, and a reset control signal to PN through the Nth stage drive signal output terminal ON;

[0116] GUN+1 provides a compensation control signal to PN-1 and a data write control signal to PN through the N+1th stage drive signal output terminal ON+1;

[0117] GUN+2 provides a compensation control signal to PN through the N+2 stage drive signal output terminal ON+2.

[0118] exist Figure 1 In at least one embodiment of the driving circuit shown, the first-stage scanning driving circuit GU1 provides a reset control signal to the first-row pixel driving circuit P1 through the first-stage driving signal output terminal O1, and the (N+2)th-stage scanning driving circuit GUN+2 provides a compensation control signal to the Nth-row pixel driving circuit PN through the (N+2)th-stage driving signal output terminal ON+2; the second-stage scanning driving circuit GU2 provides a data write control signal to the first-row pixel driving circuit P1 and a reset control signal to the second-row pixel driving circuit P2 through the second-stage driving signal output terminal O2; the (N+1)th-stage scanning driving circuit GUN+1 provides a data write control signal to the Nth-row pixel driving circuit PN through the (N+1)th-stage driving signal output terminal ON+1 and a compensation control signal to the (N-1)th-row pixel driving circuit PN-1.

[0119] In at least one embodiment of this disclosure, the driving circuit may further include a multi-level light emission control signal generation circuit;

[0120] The multi-level light emission control signal generation circuit is used to generate multi-level light emission control signals and provide the light emission control signals to each row of pixel driving circuits respectively.

[0121] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a multi-level light emission control signal generation circuit;

[0122] exist Figure 2 In the diagram, EU1 represents the first-stage light-emitting control signal generation circuit included in the driving circuit; EU2 represents the second-stage light-emitting control signal generation circuit included in the driving circuit; EU3 represents the third-stage light-emitting control signal generation circuit included in the driving circuit; EU4 represents the fourth-stage light-emitting control signal generation circuit included in the driving circuit; EU5 represents the fifth-stage light-emitting control signal generation circuit included in the driving circuit; EUN-3 represents the (N-3)th-stage light-emitting control signal generation circuit included in the driving circuit; EUN-2 represents the (N-2)th-stage light-emitting control signal generation circuit included in the driving circuit; EUN-1 represents the (N-1)th-stage light-emitting control signal generation circuit included in the driving circuit; and EUN represents the Nth-stage light-emitting control signal generation circuit included in the driving circuit.

[0123] EU1 provides the first-level light emission control signal to P1, EU2 provides the second-level light emission control signal to P2, EU3 provides the third-level light emission control signal to P3, EU4 provides the fourth-level light emission control signal to P4, and EU5 provides the fifth-level light emission control signal to P5; EUN-3 provides the (N-3)th level light emission control signal to PN-3, EUN-2 provides the (N-2)th level light emission control signal to PN-2, EUN-1 provides the (N-1)th level light emission control signal to PN-1, and EUN provides the Nth level light emission control signal to PN.

[0124] like Figure 3 As shown, at least one embodiment of the pixel driving circuit may include a driving sub-circuit 11, a data writing sub-circuit 12, a compensation sub-circuit 13, a first energy storage sub-circuit 14, and a second energy storage sub-circuit 15.

[0125] The data writing sub-circuit 12 is electrically connected to the data writing control line GA1, the compensation control line GA2, the data line DS and the first end of the driving sub-circuit 11, respectively, and is used to write the data voltage Vdata provided by the data line DS into the first end of the driving sub-circuit 11 under the control of the data writing control signal provided by the data writing control line GA1 and the compensation control signal provided by the compensation control line GA2.

[0126] The compensation sub-circuit 13 is electrically connected to the compensation control line GA2, the control terminal of the drive sub-circuit 11, and the second terminal of the drive sub-circuit 11, respectively, and is used to control the connection between the control terminal of the drive sub-circuit 11 and the second terminal of the drive sub-circuit 11 under the control of the compensation control signal.

[0127] The first energy storage sub-circuit 14 is electrically connected to the first terminal of the driving sub-circuit 11 and is used to store electrical energy;

[0128] The second energy storage sub-circuit 15 is electrically connected to the control terminal of the drive sub-circuit 11 and is used to store electrical energy.

[0129] like Figure 3 In at least one embodiment of the pixel driving circuit shown, the display cycle includes a writing phase and a compensation phase that are set sequentially during operation.

[0130] During the writing phase, under the control of the data writing control signal and the compensation control signal, the data writing sub-circuit 12 writes the data voltage Vdata provided by the data line DS to the first terminal of the driving sub-circuit 11 to charge the first energy storage sub-circuit 14; under the control of the compensation control signal, the compensation sub-circuit 13 controls the connection between the control terminal of the driving sub-circuit 11 and the first terminal of the driving sub-circuit 11; the first energy storage sub-circuit 14 maintains the data voltage.

[0131] At the start of the writing phase, the driving sub-circuit 11, under the control of the potential of its control terminal, controls the first terminal of the driving sub-circuit 11 to connect with the second terminal of the driving sub-circuit 11, so as to charge the second energy storage sub-circuit 15 through the data voltage Vdata.

[0132] During the compensation phase, the data writing sub-circuit 12, under the control of the data writing control signal, controls the disconnection between the data line DS and the first terminal of the driving sub-circuit 11, and the compensation sub-circuit 13, under the control of the compensation control signal, controls the connection between the control terminal of the driving sub-circuit 11 and the first terminal of the driving sub-circuit 11.

[0133] like Figure 3 In at least one embodiment of the pixel driving circuit shown, during operation, in the write phase, the data writing sub-circuit 12 controls the writing of data voltage Vdata to the first terminal of the driving sub-circuit 11, and stores the data voltage Vdata in the first energy storage sub-circuit 14. The compensation sub-circuit 13 controls the connection between the control terminal of the driving sub-circuit 11 and the first terminal of the driving sub-circuit 11. At the start of the write phase, under the control of the potential of its control terminal, the driving sub-circuit 11 controls the connection between the first terminal of the driving sub-circuit 11 and the second terminal of the driving sub-circuit 11, so as to charge the second energy storage sub-circuit 15 through the data voltage Vdata, thereby changing the driving sub-circuit 14. The potential of the control terminal of circuit 11; even if the potential of the control terminal of the driving sub-circuit 11 cannot reach Vdata+Vth (Vth is the threshold voltage of the driving transistor in the driving sub-circuit 11) at the end of the writing stage, the second energy storage sub-circuit 15 can still be charged by the data voltage Vdata stored in the first energy storage sub-circuit 14 during the compensation stage. In this way, the charging time of the second energy storage sub-circuit 15 by the data voltage Vdata can be increased in the case of high frequency frames, and the threshold voltage of the driving transistor included in the driving sub-circuit 11 can be fully compensated, thereby improving the display uniformity and improving the image quality problem of uneven display even when displaying low grayscale images.

[0134] In at least one embodiment of this disclosure, the pixel driving circuit may further include a reset sub-circuit;

[0135] The reset sub-circuit is electrically connected to the data write control line, the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the data write control signal and the reset control signal provided by the reset control line.

[0136] like Figure 4 As shown, in Figure 3Based on at least one embodiment of the pixel driving circuit shown, the pixel driving circuit may further include a reset sub-circuit 21;

[0137] The reset sub-circuit 21 is electrically connected to the data write control line GA1, the reset control line R1, the first initial voltage line I1, and the control terminal of the drive sub-circuit 11, respectively, and is used to write the first initial voltage provided by the first initial voltage line I1 into the control terminal of the drive sub-circuit 11 under the control of the data write control signal and the reset control signal provided by the reset control line R1.

[0138] like Figure 4 When at least one embodiment of the pixel driving circuit shown is in operation, the display cycle may include a reset phase set before the write phase;

[0139] During the reset phase, the reset sub-circuit 21, under the control of the data write control signal and the reset control signal, writes the first initial voltage to the control terminal of the drive sub-circuit 11, so that at the start of the write phase, the drive sub-circuit 11 can connect its first terminal to its second terminal.

[0140] In at least one embodiment of this disclosure, the pixel driving circuit may further include a reset sub-circuit;

[0141] The reset sub-circuit is electrically connected to the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the reset control signal provided by the reset control line.

[0142] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the pixel driving circuit shown, the pixel driving circuit may further include a reset sub-circuit 21;

[0143] The reset sub-circuit 21 is electrically connected to the reset control line R1, the first initial voltage line I1, and the control terminal of the drive sub-circuit 11, respectively, and is used to write the first initial voltage provided by the first initial voltage line I1 into the control terminal of the drive sub-circuit 11 under the control of the reset control signal provided by the reset control line R1.

[0144] This disclosure is as follows Figure 5 When at least one embodiment of the pixel driving circuit shown is in operation, the display cycle may include a reset phase set before the write phase;

[0145] During the reset phase, the reset sub-circuit 21, under the control of the reset control signal, writes the first initial voltage to the control terminal of the drive sub-circuit 11, so that at the start of the writing phase, the drive sub-circuit 11 can connect its first terminal to its second terminal.

[0146] In at least one embodiment of this disclosure, the pixel driving circuit may further include a light-emitting element, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and an initialization sub-circuit;

[0147] The first light-emitting control sub-circuit is electrically connected to the light-emitting control line, the power supply voltage line and the first terminal of the driving sub-circuit, respectively, and is used to control the connection between the power supply voltage line and the first terminal of the driving sub-circuit under the control of the light-emitting control signal provided by the light-emitting control line;

[0148] The second light-emitting control sub-circuit is electrically connected to the light-emitting control line, the second terminal of the driving sub-circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the second terminal of the driving sub-circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element

[0149] Electrically connected to the first voltage terminal;

[0150] The initialization sub-circuit is electrically connected to the data write control line, the second initial voltage line, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage line into the first electrode of the light-emitting element under the control of the data write control signal.

[0151] In a specific implementation, the pixel driving circuit may further include a light-emitting element, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and an initialization sub-circuit. The first light-emitting control sub-circuit and the second light-emitting control sub-circuit perform light-emitting control. The initialization sub-circuit is used to write a second initial voltage to the first electrode of the light-emitting element under the control of a lower data write control signal, so that the light-emitting element does not emit light and clears the residual charge on the first electrode of the light-emitting element.

[0152] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the pixel driving circuit shown, the pixel driving circuit may further include a first light emission control sub-circuit 41, a second light emission control sub-circuit 42, and an initialization sub-circuit 43;

[0153] The first light-emitting control sub-circuit 41 is electrically connected to the light-emitting control line E1, the power supply voltage line Vd, and the first end of the driving sub-circuit 11, respectively, and is used to control the power supply voltage line Vd to connect with the first end of the driving sub-circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.

[0154] The second light-emitting control sub-circuit 42 is electrically connected to the light-emitting control line E1, the second end of the driving sub-circuit 11 and the first pole of the light-emitting element E0, respectively, and is used to control the second end of the driving sub-circuit 11 to connect with the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the second pole of the light-emitting element E0 is electrically connected to the first voltage terminal V1.

[0155] The initialization sub-circuit 43 is electrically connected to the data writing control line GA1, the second initial voltage line I2 and the first pole of the light-emitting element E0, respectively, and is used to write the second initial voltage provided by the second initial voltage line I2 into the first pole of the light-emitting element E0 under the control of the data writing control signal.

[0156] The second electrode of the light-emitting element E0 is electrically connected to the first voltage terminal V1.

[0157] In at least one embodiment of this disclosure, the first voltage terminal V1 may be a low voltage terminal or a ground terminal, but is not limited thereto.

[0158] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the pixel driving circuit shown, the pixel driving circuit may further include a first light emission control sub-circuit 41, a second light emission control sub-circuit 42, and an initialization sub-circuit 43;

[0159] The first light-emitting control sub-circuit 41 is electrically connected to the light-emitting control line E1, the power supply voltage line Vd, and the first end of the driving sub-circuit 11, respectively, and is used to control the power supply voltage line Vd to connect with the first end of the driving sub-circuit 11 under the control of the light-emitting control signal provided by the light-emitting control line E1.

[0160] The second light-emitting control sub-circuit 42 is electrically connected to the light-emitting control line E1, the second end of the driving sub-circuit 11 and the first pole of the light-emitting element E0, respectively, and is used to control the second end of the driving sub-circuit 11 to connect with the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the second pole of the light-emitting element E0 is electrically connected to the first voltage terminal V1.

[0161] The initialization sub-circuit 43 is electrically connected to the data writing control line GA1, the second initial voltage line I2 and the first pole of the light-emitting element E0, respectively, and is used to write the second initial voltage provided by the second initial voltage line I2 into the first pole of the light-emitting element E0 under the control of the data writing control signal.

[0162] The second electrode of the light-emitting element E0 is electrically connected to the first voltage terminal V1.

[0163] In at least one embodiment of this disclosure, the first voltage terminal V1 may be a low voltage terminal or a ground terminal, but is not limited thereto.

[0164] Optionally, the data writing sub-circuit includes a first transistor and a second transistor; the compensation sub-circuit includes a third transistor;

[0165] The control electrode of the first transistor is electrically connected to the data write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor.

[0166] The control electrode of the second transistor is electrically connected to the compensation control line, and the second electrode of the second transistor is electrically connected to the first terminal of the driving sub-circuit.

[0167] The control electrode of the third transistor is electrically connected to the compensation control line, the first electrode of the third transistor is electrically connected to the control terminal of the driving sub-circuit, and the second electrode of the third transistor is electrically connected to the second terminal of the driving sub-circuit.

[0168] Optionally, the first energy storage sub-circuit includes a first capacitor;

[0169] The first plate of the first capacitor is electrically connected to the control terminal of the driving sub-circuit, and the second plate of the first capacitor is electrically connected to the power supply voltage line.

[0170] Optionally, the reset sub-circuit includes a fourth transistor and a fifth transistor;

[0171] The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor.

[0172] The control electrode of the fifth transistor is electrically connected to the data write control line, and the second electrode of the fifth transistor is electrically connected to the control terminal of the driving sub-circuit.

[0173] Optionally, the reset sub-circuit includes a fourth transistor;

[0174] The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the control terminal of the driving sub-circuit.

[0175] Optionally, the first light-emitting control sub-circuit includes a sixth transistor, the second light-emitting control sub-circuit includes a seventh transistor, the initialization sub-circuit includes an eighth transistor, the driving sub-circuit includes a driving transistor, and the second energy storage sub-circuit includes a second capacitor.

[0176] The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor.

[0177] The control electrode of the seventh transistor is electrically connected to the light-emitting control line, the first electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element.

[0178] The control electrode of the eighth transistor is electrically connected to the data write control line, the first electrode of the eighth transistor is electrically connected to the second initial voltage line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0179] The first plate of the second capacitor is electrically connected to the control electrode of the driving transistor, and the second plate of the second capacitor is electrically connected to the power supply voltage line.

[0180] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the pixel driving circuit shown, the data writing sub-circuit 12 includes a first transistor T1 and a second transistor T2; the compensation sub-circuit 13 includes a third transistor T3; the driving sub-circuit 11 includes a driving transistor T0; and the light-emitting element is an organic light-emitting diode F1.

[0181] The gate of the first transistor T1 is electrically connected to the data write control line GA1, the source of the first transistor T1 is electrically connected to the data line DS, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2.

[0182] The gate of the second transistor T2 is electrically connected to the compensation control line GA2, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor T0.

[0183] The gate of the third transistor T3 is electrically connected to the compensation control line GA2, the source of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the drain of the third transistor T3 is electrically connected to the drain of the driving transistor T0.

[0184] The first energy storage sub-circuit 14 includes a first capacitor C1;

[0185] The first plate of the first capacitor C1 is electrically connected to the source of the driving transistor T0, and the second plate of the first capacitor C1 is electrically connected to the power supply voltage line Vd.

[0186] The reset sub-circuit 21 includes a fourth transistor T4 and a fifth transistor T5;

[0187] The gate of the fourth transistor T4 is electrically connected to the reset control line R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage line I1, and the drain of the fourth transistor T4 is electrically connected to the source of the fifth transistor T5.

[0188] The gate of the fifth transistor T5 is electrically connected to the data write control line GA1, and the drain of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0.

[0189] The first light-emitting control sub-circuit 41 includes a sixth transistor T6, the second light-emitting control sub-circuit 42 includes a seventh transistor T7, the initialization sub-circuit 43 includes an eighth transistor T8, and the second energy storage sub-circuit 15 includes a second capacitor C2.

[0190] The gate of the sixth transistor T6 is electrically connected to the light-emitting control line E1, the source of the sixth transistor T6 is electrically connected to the power supply voltage line Vd, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor T0.

[0191] The gate of the seventh transistor T7 is electrically connected to the light-emitting control line E1, the source of the seventh transistor T7 is electrically connected to the drain of the driving transistor T0, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode F1; the cathode of the organic light-emitting diode F1 is electrically connected to the low voltage terminal Vs.

[0192] The gate of the eighth transistor T8 is electrically connected to the data write control line GA1, the source of the eighth transistor T8 is electrically connected to the second initial voltage line I2, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode F1.

[0193] The first plate of the second capacitor C2 is electrically connected to the gate of the driving transistor T0, and the second plate of the second capacitor C2 is electrically connected to the power supply voltage line Vd.

[0194] exist Figure 8 In at least one embodiment of the pixel driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0195] exist Figure 8 In at least one embodiment of the pixel driving circuit shown, the first initial voltage line and the second initial voltage line can be the same initial voltage line, which is used to provide an initial voltage, but is not limited thereto.

[0196] exist Figure 8 In at least one embodiment of the pixel driving circuit shown, T3 may be a dual-gate transistor to reduce leakage current, but is not limited thereto.

[0197] exist Figure 8 In at least one embodiment of the pixel driving circuit shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the drain of the driving transistor T0.

[0198] like Figure 9 As shown, this disclosure is as follows Figure 8 In at least one embodiment of the pixel driving circuit shown, the display cycle may include a reset phase t1, a write phase t2, a compensation phase t3, and a light emission phase t4 arranged sequentially; a buffer phase t0 is provided between the compensation phase t3 and the light emission phase t4.

[0199] During the reset phase t1, R1 provides a low voltage signal, GA1 provides a low voltage signal, GA2 provides a high voltage signal, E1 provides a high voltage signal, T6, T7, T3 and T2 are cut off, T4 is turned on, and T8 is turned on, so as to write the initial voltage to the gate of T0 and the anode of F1, so that T0 can be turned on at the beginning of the writing phase t2, and F1 does not emit light, and the residual charge on the anode of F1 is cleared.

[0200] During the write phase t2, R1 provides a high voltage signal, GA1 provides a low voltage signal, GA2 provides a low voltage signal, E1 provides a high voltage signal, T6 and T7 are off, and T3, T1, T8, T2 and T5 are on. DS provides a data voltage Vdata to write the data voltage Vdata to the source of T0, charging C1, and C1 stores the data voltage Vdata; T3 is on.

[0201] At the start of the write phase t2, T0 is turned on to charge C2 with the data voltage Vdata, thereby increasing the potential of the first node N1;

[0202] During the writing phase t2, as the potential of the first node N1 rises, the current flowing through T0 decreases, and the potential of the first node N1 rises more and more slowly. If the writing phase t2 lasts long enough, the potential of the first node N1 will eventually reach Vdata+Vth, where Vth is the threshold voltage of T0. However, since the opening time of each row of grid lines in high-frequency (e.g., 120Hz) display products is short, the potential of the first node N1 has not yet reached Vdata+Vth. The data writing control signal provided by GA1 becomes a high voltage signal, T1 is cut off, and the writing signal from Vdata to the pixel through T1 ends.

[0203] During the writing phase t2, T8 is turned on, and the initial voltage is written to the anode of F1 to eliminate the interface charge of the light-emitting layer.

[0204] At the end of the write phase t2, the potential of the second node N2 reaches the same potential as Vdata, while T0 is still in a certain degree of on state.

[0205] During the compensation phase t3, R1 provides a high voltage signal, GA1 provides a high voltage signal, GA2 provides a low voltage signal, and E1 provides a high voltage signal. T6, T7, T4, T1, T8, and T5 are off, while T2 and T3 are on. C1 has already saved Vdata during the write phase t2. During the compensation phase, since T0 is not off, C1 will continue to charge C2 through T0 and T3. The potential of the first node N1 continues to rise until T0 is off. Since the potential rise of the first node N1 is small during the compensation phase t3, the charge consumption is limited, and C1 can be approximated as a constant voltage source. Therefore, the potential of the first node N1 eventually reaches Vdata + Vth until GA2 provides a high voltage signal, at which point the compensation phase t3 ends.

[0206] During the buffer phase t0, E1 provides a high voltage signal, R1, GA1 and GA2 all provide high voltage signals, and T4, T3, T1, T8, T2 and T5 are all cut off. During the buffer phase t0, the potential of the first node N1 remains unchanged. The duration of the buffer phase t0 is determined by the turn-on time of E1.

[0207] During the light-emitting phase t4, E1 provides a low-voltage signal, while R1, GA1, and GA2 all provide high-voltage signals. T4, T3, T1, T8, T2, and T5 are all off, while T6 and T7 are on, and F1 emits light. The gate-source voltage of T0 is Vgs = Vdata + Vth - Vdz, where Vdz is the voltage value of the power supply signal provided by Vd. The driving current If1 that drives F1 to emit light is equal to K(Vdz - Vdata). 2 , where K is the current coefficient of T0; K is a constant related to the process and design of T0.

[0208] This disclosure is as follows Figure 8 In at least one embodiment of the pixel driving circuit shown, during operation, C2 can be charged by the data voltage Vdata during the writing phase t2 and the compensation phase t3 until T0 is turned off, so as to increase the time for charging C2 by the data voltage Vdata, fully compensate the threshold voltage of the driving transistor T0, and improve the display uniformity.

[0209] like Figure 9 As shown, during the writing phase t2, both the data writing control signal provided by GA1 and the compensation control signal provided by GA2 are low voltage signals.

[0210] like Figure 10 As shown, in Figure 7 Based on at least one embodiment of the pixel driving circuit shown, the data writing sub-circuit 12 includes a first transistor T1 and a second transistor T2; the compensation sub-circuit 13 includes a third transistor T3; the driving sub-circuit 11 includes a driving transistor T0; and the light-emitting element is an organic light-emitting diode F1.

[0211] The gate of the first transistor T1 is electrically connected to the data write control line GA1, the source of the first transistor T1 is electrically connected to the data line DS, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2.

[0212] The gate of the second transistor T2 is electrically connected to the compensation control line GA2, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor T0.

[0213] The gate of the third transistor T3 is electrically connected to the compensation control line GA2, the source of the third transistor T3 is electrically connected to the gate of the driving transistor T0, and the drain of the third transistor T3 is electrically connected to the drain of the driving transistor T0.

[0214] The first energy storage sub-circuit 14 includes a first capacitor C1;

[0215] The first plate of the first capacitor C1 is electrically connected to the source of the driving transistor T0, and the second plate of the first capacitor C1 is electrically connected to the power supply voltage line Vd.

[0216] The reset sub-circuit 21 includes a fourth transistor T4;

[0217] The gate of the fourth transistor T4 is electrically connected to the reset control line R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage line I1, and the drain of the fourth transistor T4 is electrically connected to the gate of the driving transistor T0.

[0218] The first light-emitting control sub-circuit 41 includes a sixth transistor T6, the second light-emitting control sub-circuit 42 includes a seventh transistor T7, the initialization sub-circuit 43 includes an eighth transistor T8, and the second energy storage sub-circuit 15 includes a second capacitor C2.

[0219] The gate of the sixth transistor T6 is electrically connected to the light-emitting control line E1, the source of the sixth transistor T6 is electrically connected to the power supply voltage line Vd, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor T0.

[0220] The gate of the seventh transistor T7 is electrically connected to the light-emitting control line E1, the source of the seventh transistor T7 is electrically connected to the drain of the driving transistor T0, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light-emitting diode F1; the cathode of the organic light-emitting diode F1 is electrically connected to the low voltage terminal Vs.

[0221] The gate of the eighth transistor T8 is electrically connected to the data write control line GA1, the source of the eighth transistor T8 is electrically connected to the second initial voltage line I2, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode F1.

[0222] The first plate of the second capacitor C2 is electrically connected to the gate of the driving transistor T0, and the second plate of the second capacitor C2 is electrically connected to the power supply voltage line Vd.

[0223] exist Figure 10 In at least one embodiment of the pixel driving circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0224] exist Figure 10 In at least one embodiment of the pixel driving circuit shown, the first initial voltage line and the second initial voltage line can be the same initial voltage line, which is used to provide an initial voltage, but is not limited thereto.

[0225] exist Figure 10In at least one embodiment of the pixel driving circuit shown, the first node N1 is electrically connected to the gate of the driving transistor T0, the second node N2 is electrically connected to the source of the driving transistor T0, and the third node N3 is electrically connected to the drain of the driving transistor T0.

[0226] like Figure 9 As shown, this disclosure is as follows Figure 10 In at least one embodiment of the pixel driving circuit shown, the display cycle may include a reset phase t1, a write phase t2, a compensation phase t3, and a light emission phase t4 arranged sequentially; a buffer phase t0 is provided between the compensation phase t3 and the light emission phase t4.

[0227] During the reset phase t1, R1 provides a low voltage signal, GA1 provides a low voltage signal, GA2 provides a high voltage signal, E1 provides a high voltage signal, T6, T7, T3 and T2 are cut off, T4 is turned on, and T8 is turned on, so as to write the initial voltage to the gate of T0 and the anode of F1, so that T0 can be turned on at the beginning of the writing phase t2, and F1 does not emit light, and the residual charge on the anode of F1 is cleared.

[0228] During the writing phase t2, R1 provides a high voltage signal, GA1 provides a low voltage signal, GA2 provides a low voltage signal, E1 provides a high voltage signal, T6 and T7 are off, T3, T1, T8 and T2 are on, DS provides a data voltage Vdata to write the data voltage Vdata to the source of T0, charging C1, and C1 stores the data voltage Vdata; T3 is on.

[0229] At the start of the write phase t2, T0 is turned on to charge C2 with the data voltage Vdata, thereby increasing the potential of the first node N1;

[0230] During the writing phase t2, as the potential of the first node N1 rises, the current flowing through T0 decreases, and the potential of the first node N1 rises more and more slowly. If the writing phase t2 lasts for a certain period of time, the potential of the first node N1 will eventually reach Vdata+Vth, where Vth is the threshold voltage of T0. However, since the opening time of each row of grid lines in high-frequency display products (e.g., 120Hz) is short, the potential of the first node N1 has not yet reached Vdata+Vth. The data writing control signal provided by GA1 becomes a high voltage signal, T1 is cut off, and the writing signal from Vdata to the pixel through T1 ends.

[0231] During the writing phase t2, T8 is turned on, and the initial voltage is written to the anode of F1 to eliminate the interface charge of the light-emitting layer.

[0232] At the end of the write phase t2, the potential of the second node N2 reaches the same potential as Vdata, while T0 is still in a certain degree of on state.

[0233] During the compensation phase t3, R1 provides a high voltage signal, GA1 provides a high voltage signal, GA2 provides a low voltage signal, and E1 provides a high voltage signal. T6, T7, T4, T1, and T8 are off, while T2 and T3 are on. C1 has already saved Vdata during the write phase t2. During the compensation phase, since T0 is not off, C1 will continue to charge C2 through T0 and T3. The potential of the first node N1 continues to rise until T0 is off. Since the potential rise of the first node N1 is small during the compensation phase t3, the charge consumption is limited, and C1 can be approximated as a constant voltage source. Therefore, the potential of the first node N1 eventually reaches Vdata + Vth until GA2 provides a high voltage signal, at which point the compensation phase t3 ends.

[0234] During the buffer phase t0, E1 provides a high voltage signal, R1, GA1 and GA2 all provide high voltage signals, and T4, T3, T1, T8 and T2 are all cut off. During the buffer phase t0, the potential of the first node N1 remains unchanged. The duration of the buffer phase t0 is determined by the turn-on time of E1.

[0235] During the light-emitting phase t4, E1 provides a low-voltage signal, while R1, GA1, and GA2 all provide high-voltage signals. T4, T3, T1, T8, and T2 are all cut off, while T6 and T7 are turned on, and F1 emits light. The gate-source voltage of T0 is Vgs = Vdata + Vth - Vdz, where Vdz is the voltage value of the power supply voltage signal provided by Vd. The driving current If1 that drives F1 to emit light is equal to K(Vdz - Vdata). 2 , where K is the current coefficient of T0; K is a constant related to the process and design of T0.

[0236] This disclosure is as follows Figure 10 In at least one embodiment of the pixel driving circuit shown, during operation, C2 can be charged by the data voltage Vdata during the writing phase t2 and the compensation phase t3 until T0 is turned off, so as to increase the time for charging C2 by the data voltage Vdata, fully compensate the threshold voltage of the driving transistor T0, and improve the display uniformity.

[0237] In at least one embodiment of this disclosure, the driving circuit further includes N rows of reset control lines, N rows of data write control lines, and N rows of compensation control lines; the reset control lines, the data write control lines, and the compensation control lines all extend along a first direction;

[0238] The driving circuit includes pixel driving circuits that are electrically connected to the corresponding row reset control line, the corresponding row data write control line and the corresponding row compensation control line, respectively.

[0239] The reset control line, the data write control line, and the compensation control line of each row extend along a first direction to the surrounding area, and in the surrounding area, the nth row reset control line, the (n-1)th row data write control line, and the (n-2)th row compensation control line are electrically connected;

[0240] n is a positive integer, greater than 2, and less than N+1; N is an integer greater than 1.

[0241] Optionally, the first row of data write control lines is electrically connected to the second row of reset control lines, and the Nth row of data write control lines is electrically connected to the (N-1)th row of compensation control lines.

[0242] In a specific implementation, each row of pixel driving circuits in the driving circuit is electrically connected to a corresponding row reset control line, a corresponding row data write control line, and a corresponding row compensation control line. The pixel driving circuit can be disposed in the display area of ​​the display substrate. Each row reset control line, each row data write control line, and each row compensation control line extends along a first direction and extends to the peripheral area. The nth row reset control line, the (n-1)th row data write control line, and the (n-2)th row compensation control line are electrically connected to each other to receive the nth level driving signal from the nth level scanning driving circuit included in the driving circuit. The first row data write control line is electrically connected to the second row reset control line to receive the second level driving signal from the second level scanning driving circuit included in the driving circuit. The Nth row data write control line is electrically connected to the (N-1)th row compensation control line to receive the (N+1)th level driving signal from the (N+1)th level scanning driving circuit included in the driving circuit.

[0243] like Figure 11 As shown, a multi-row, multi-column pixel driving circuit is provided within the display area 110;

[0244] exist Figure 11 In the diagram, P1 represents the first row of pixel driving circuits, P2 represents the second row of pixel driving circuits, P3 represents the third row of pixel driving circuits, and P4 represents the fourth row of pixel driving circuits; PN-1 represents the (N-1)th row of pixel driving circuits; PN represents the Nth row of pixel driving circuits; and PN-2 represents the (N-2)th row of pixel driving circuits.

[0245] The first row pixel driving circuit P1 is electrically connected to the first row reset control line R11, the first row data write control line GA11, the first row compensation control line GA12 and the first row light emission control line E1 respectively.

[0246] The second row pixel driving circuit P2 is electrically connected to the second row reset control line R21, the second row data write control line GA21, the second row compensation control line GA22, and the second row light emission control line E2, respectively.

[0247] The third row pixel driving circuit P3 is electrically connected to the third row reset control line R31, the third row data write control line GA31, the third row compensation control line GA32 and the third row light emission control line E3 respectively.

[0248] The fourth row pixel driving circuit P4 is electrically connected to the fourth row reset control line R41, the fourth row data write control line GA41, the fourth row compensation control line GA42, and the fourth row light emission control line E4, respectively.

[0249] The pixel driving circuit PN-2 of the N-2 row is electrically connected to the N-2 row reset control line RN-2-1, the N-2 row data write control line GAN-2-1, the N-2 row compensation control line GAN-2-2, and the N-2 row light emission control line EN-2, respectively.

[0250] The pixel driving circuit PN-1 of the N-1 row is electrically connected to the N-1 row reset control line RN-1-1, the N-1 row data write control line GAN-1-1, the N-1 row compensation control line GAN-1-2, and the N-1 row light emission control line EN-1, respectively.

[0251] The Nth row pixel driving circuit PN is electrically connected to the Nth row reset control line RN1, the Nth row data write control line GAN1, the Nth row compensation control line GAN2, and the Nth row light emission control line EN, respectively.

[0252] Each row of control lines extends horizontally and extends to the surrounding area; the surrounding area includes a first side area 121 and a second side area 122;

[0253] exist Figure 11 In at least one embodiment shown, the first direction is horizontal, the first side region 121 is the left side region, and the second side region 122 is the right side region, but is not limited thereto.

[0254] like Figure 11 As shown, in the first side region 121 and the second side region 122, the first row data write control line GA11 is electrically connected to the second row reset control line R21; the second row data write control line GA21, the third row reset control line R31, and the first row compensation control line GA12 are electrically connected; the third row data write control line GA31, the fourth row reset control line R41, and the second row compensation control line GA22 are electrically connected; the fourth row data write control line GA41, the third row compensation control line GA32, and the fifth row reset control line ( Figure 11(Not shown in the image) Electrically connected; the N-1 row data write control line GAN-1-1, the N-1 row reset control line RN1, and the N-2 row compensation control line GAN-2-2 are electrically connected; the N-1 row data write control line GAN1 is electrically connected to the N-1 row compensation control line GAN-1-2.

[0255] In at least one embodiment of this disclosure, the scanning drive circuit may be disposed in the first side region 121 and the second side region 122. In actual operation, the scanning drive circuit may also be disposed in the first side region 121 or the second side region 122, in which case the above control lines are electrically connected to each other in the first side region 121 or the second side region 122.

[0256] The driving circuit described in at least one embodiment of this disclosure may further include N rows of light-emitting control lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding row of light-emitting control lines.

[0257] like Figure 12 As shown, each row of pixel driving circuits may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0258] like Figure 14 As shown, the gate G4 of the fourth transistor T4 is integrated with the corresponding row reset control line R1; the gate G8 of the eighth transistor T8 and the next row reset control line R2 adjacent to the corresponding row reset control line R1 are integrated; the gate G1 of the first transistor T1, the gate G5 of the fifth transistor T5, and the corresponding row data write control line GA1 are integrated; the first gate G31 of the third transistor T3, the second gate G32 of the third transistor T3, the gate G2 of the second transistor T2, and the corresponding row compensation control line GA2 are integrated; the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, and the corresponding row light emission control line E1 are integrated; the gate of the driving transistor T0 is disposed between the corresponding row compensation control line GA2 and the corresponding row light emission control line E1; the gate of the driving transistor T0 is multiplexed as the first plate C2a of the second capacitor C2; as shown Figure 15 As shown, the second plate C2b of the second capacitor C2 is reused as the second plate of the first capacitor C1; Figure 16 As shown, the drain D6 of the sixth transistor is reused as the first plate of the first capacitor C1;

[0259] like Figure 14As shown, the corresponding row reset control line R1, the corresponding row data write control line GA1, the corresponding row compensation control line GA2, and the corresponding row light emission control line E1, which are electrically connected to the pixel driving circuit of the same row, are arranged sequentially along the second direction;

[0260] The first direction intersects with the second direction.

[0261] In a specific implementation, the next row reset control line R2 adjacent to the corresponding row reset control line R1 and the corresponding row data write control line GA1 can extend to the surrounding area. In the surrounding area, the next row reset control line R2 adjacent to the corresponding row reset control line R1 and the corresponding row data write control line GA1 are electrically connected to each other.

[0262] exist Figures 13-19 In at least one embodiment shown, the first direction is horizontal and the second direction is vertical, but this is not a limitation.

[0263] The above layout settings allow for the reasonable arrangement of control lines and transistors in the pixel driving circuit, resulting in a simple and easy layout.

[0264] Optionally, the driving circuit described in at least one embodiment of this disclosure may further include N rows of second initial voltage lines; the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding rows of second initial voltage lines.

[0265] like Figure 15 As shown, the second initial voltage line I2 and the second plate C2b of the second capacitor C2 are located on the same layer;

[0266] The orthographic projection of the corresponding row second initial voltage line I2 on the substrate is located on the side of the corresponding row reset control line R1 on the substrate that is far away from the orthographic projection of the corresponding row data write control line GA1 on the substrate, so as to reasonably arrange the second initial voltage line I2 and facilitate the electrical connection between the source S8 of T8 and the second initial voltage line I2.

[0267] like Figure 12 As shown, in Figure 8 Based on at least one embodiment of the pixel driving circuit shown, the electrodes of each transistor and the plates of each capacitor are indicated.

[0268] exist Figure 12In the diagram, G1 is the gate of T1, S1 is the source of T1, D1 is the drain of T1, G2 is the gate of T2, S2 is the source of T2, D2 is the drain of T2, G3 is the gate of T3, S3 is the source of T3, D3 is the drain of T3, G4 is the gate of T4, S4 is the source of T4, and D4 is the drain of T4. The terminal labeled G5 is the gate of T5, the terminal labeled S5 is the source of T5, the terminal labeled D5 is the drain of T5, the terminal labeled G6 is the gate of T6, the terminal labeled S6 is the source of T6, the terminal labeled D6 is the drain of T6, the terminal labeled G7 is the gate of T7, the terminal labeled S7 is the source of T7, the terminal labeled D7 is the drain of T7, the terminal labeled G8 is the gate of T8, the terminal labeled S8 is the source of T8, and the terminal labeled D8 is the drain of T8.

[0269] The plate labeled C1a is the first plate of C1, the plate labeled C1b is the second plate of C1, the plate labeled C2a is the first plate of C2, and the plate labeled C2b is the second plate of C2.

[0270] exist Figure 13 In the diagram, 10 represents the channel of the first transistor T1, 20 represents the channel of the second transistor T2, 310 represents the first channel portion of the third transistor T3, 320 represents the second channel portion of the third transistor T3, 40 represents the channel of the fourth transistor T4, 50 represents the channel of the fifth transistor T5, 60 represents the channel of the sixth transistor T6, 70 represents the channel of the seventh transistor T7, 80 represents the channel of the eighth transistor T8, and d0 represents the channel of the driving transistor T0.

[0271] like Figure 13 As shown, the active layers of the fourth transistor T4, the fifth transistor T5, the third transistor T3, the driving transistor T0, the second transistor T2, the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are formed from continuous semiconductor layers.

[0272] like Figure 13 As shown, the channels 80 of T8 and 40 of T4 are arranged in the first direction; the channels of T5 and 10 of T1 are arranged in the first direction; the first channel portion 310 of T3 and the channel portion 20 of T2 are arranged in the first direction; and the channels 70 of T7 and T6 are arranged in the first direction.

[0273] The channels 40 of T4, 50 of T5, and d0 of T0 are arranged sequentially along the second direction;

[0274] The channels 10 of T1, 20 of T2, and 60 of T6 are arranged sequentially along the second direction;

[0275] The first direction intersects with the second direction.

[0276] In at least one embodiment of this disclosure, the first direction may be a horizontal direction and the second direction may be a vertical direction, but is not limited thereto.

[0277] like Figure 14 As shown, G1 is the gate of the first transistor T1, G2 is the gate of the second transistor T2, G31 is the first gate of the third transistor T3, G32 is the second gate of the third transistor T3, G4 is the gate of the fourth transistor T4, G5 is the gate of the fifth transistor T5, G6 is the gate of the sixth transistor T6, G7 is the gate of the seventh transistor T7, G8 is the gate of the eighth transistor T8, and C2a is the first plate of the second capacitor C2. The first plate C2a of the second capacitor C2 is multiplexed as the gate of the driving transistor T0.

[0278] like Figure 14 As shown, the reset control line R1, the data write control line GA1, the compensation control line GA2, and the light emission control line E1 all extend along the first direction, but are not limited thereto.

[0279] like Figure 15 As shown, I2 is the second initial voltage line, C2b is the second plate of the second capacitor C2, and the second plate C2b of the second capacitor C2 is reused as the second plate C1b of the first capacitor C1.

[0280] like Figure 15 As shown, the second initial voltage line I2 extends along the first direction, but is not limited thereto.

[0281] like Figures 13-19 As shown, the drain D6 of the sixth transistor T6 is reused as the first plate of the first capacitor C1.

[0282] like Figures 13-19 As shown, the second plate C2b of the second capacitor C2 is electrically connected to the power supply voltage line Vd through a via.

[0283] exist Figure 16In the diagram, S1 is the source of the first transistor T1, S4 is the source of the fourth transistor T4, S8 is the source of the eighth transistor T8, D5 is the drain of the fifth transistor T5, D6 is the drain of the sixth transistor T6, and D7 is the drain of the seventh transistor T7. Figure 14 In the diagram, the line labeled I1 is the first initial voltage line, the line labeled Vd is the power supply voltage line, and the line labeled DS is the data line.

[0284] like Figure 17 As shown, the first initial voltage line I1, the power supply voltage line Vd, and the data line DS all extend along the second direction, but are not limited thereto.

[0285] like Figures 13-19 As shown, S1 is electrically connected to the data line DS through a via, S4 is electrically connected to the first initial voltage line I1 through a via, S8 is electrically connected to the second initial voltage line I2 through a via, D5 is electrically connected to the first plate C2a of C2 through a via, and D6 is electrically connected to the power supply voltage line Vd through a via.

[0286] Figure 18 For corresponding Figure 8 A schematic diagram of the layout of at least one embodiment of the shift register unit shown;

[0287] Figure 13 yes Figure 18 Layout diagram of the active layer in the middle, Figure 14 yes Figure 18 Layout diagram of the first gate metal layer in the middle. Figure 15 yes Figure 18 The layout diagram of the second gate metal layer in the middle, Figure 16 yes Figure 18 Layout diagram of the first source / drain metal layer in the middle. Figure 17 yes Figure 18 The layout diagram of the second source / drain metal layer in the diagram. Figure 19 Is Figure 18 A schematic diagram with vias added based on the above.

[0288] In specific implementation, the display substrate in the display device described in the embodiments of this disclosure may include an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer and a second source / drain metal layer sequentially disposed on a substrate, but is not limited thereto.

[0289] In at least one embodiment of this disclosure, the portion of the active layer located on both sides of the channel of each transistor can be a conductive portion. The conductive portion can serve as a first electrode or a second electrode of each transistor, or the conductive portion can be electrically connected to the first electrode or the second electrode of each transistor. The first electrode can be a source and the second electrode can be a drain; or the first electrode can be a drain and the second electrode can be a source; however, this is not a limitation.

[0290] In at least one embodiment of this disclosure, the drain of the seventh transistor T7 is electrically connected to the anode of an organic light-emitting diode through a via, wherein the anode of the organic light-emitting diode is located on the side of the second source-drain metal layer away from the substrate.

[0291] Figure 10 At least one embodiment of the pixel driving circuit shown is Figure 8 Compared to at least one embodiment of the pixel driving circuit shown, the fifth transistor T5 is reduced. Figure 10 When at least one embodiment of the pixel driving circuit shown is laid out, in Figure 18 In the layout diagram shown, T5 does not need to be included.

[0292] like Figures 13-19 As shown, compared to the layout diagram of the related pixel driving circuit, although the number of transistors in the pixel driving circuit of at least one embodiment of the present disclosure is increased, the actual layout diagram of the pixel driving circuit is still very simple and does not increase the difficulty of layout.

[0293] The driving method described in this disclosure is used to drive the driving circuit described in at least one embodiment of this disclosure. The driving method described in this disclosure may include:

[0294] The driving circuit includes at least one scanning driving circuit that provides compensation control signals, data write control signals, and reset control signals to at least three adjacent rows of pixel driving circuits through the driving signal output terminal.

[0295] The driving method described in this embodiment utilizes the partial overlap between the driving signals output by adjacent scanning driving circuits through their driving signal output terminals. The driving signal output by this stage is used as the compensation control signal, data writing control signal, and reset control signal provided to at least three adjacent rows of pixel driving circuits. In this way, not only is the size of the display panel bezel not increased, but the compensation time of each row of pixel driving circuits is also increased, reducing the risk of mura (display unevenness). Furthermore, while maintaining the same compensation time as existing solutions, the display frame rate can be doubled, greatly improving the display quality.

[0296] The display device described in this disclosure includes the driving circuit described in at least one embodiment of this disclosure.

[0297] In at least one embodiment of this disclosure, the display device may further include a display substrate, the pixel driving circuit included in the driving circuit may be disposed in the display area of ​​the display substrate, and the scanning driving module included in the driving circuit may be disposed in the peripheral area of ​​the display substrate.

[0298] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0299] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, characterized in that, Includes multi-level scanning drive circuit and multi-row pixel drive circuit; At least one level of the scanning driving circuit includes a driving signal output terminal, which is electrically connected to at least three adjacent rows of pixel driving circuits in the multi-row pixel driving circuit, and is configured to provide a compensation control signal, a data write control signal, and a reset control signal to the at least three rows of pixel driving circuits, respectively; The driving circuit includes an N+2 level scanning driving circuit and an N-row pixel driving circuit; N is an integer greater than 1. The driving circuit includes an nth-level scanning driving circuit whose nth-level driving signal output terminal is electrically connected to the (n-2)th row pixel driving circuit, the (n-1)th row pixel driving circuit, and the nth row pixel driving circuit, respectively. The nth-level scanning driving circuit is configured to provide a compensation control signal to the (n-2)th row pixel driving circuit, a data write control signal to the (n-1)th row pixel driving circuit, and a reset control signal to the nth row pixel driving circuit through the nth-level driving signal output terminal, respectively. n is a positive integer, greater than 2, and less than N+1; The driving circuit includes a first-stage scanning driving circuit whose first-stage driving signal output terminal is electrically connected to a first-row pixel driving circuit. The first-stage scanning driving circuit is configured to provide a reset control signal to the first-row pixel driving circuit through its first-stage driving signal output terminal. The driving circuit also includes an (N+2)-stage scanning driving circuit whose N+2-stage driving signal output terminal is electrically connected to an Nth-row pixel driving circuit. The (N+2)-stage scanning driving circuit provides a compensation control signal to the Nth-row pixel driving circuit through its N+2-stage driving signal output terminal. Alternatively, the driving circuit includes a second-stage scanning driving circuit whose second-stage driving signal output terminal is respectively connected to the first... The row pixel driving circuit and the second row pixel driving circuit are electrically connected. The second-level scanning driving circuit is used to provide data write control signals to the first row pixel driving circuit and reset control signals to the second row pixel driving circuit through the second-level driving signal output terminal. The N+1 level driving signal output terminal of the N+1 level scanning driving circuit included in the driving circuit is electrically connected to the N-1 level pixel driving circuit and the Nth row pixel driving circuit, respectively. The N+1 level scanning driving circuit is used to provide compensation control signals to the N-1 level pixel driving circuit and data write control signals to the Nth row pixel driving circuit through the N+1 level driving signal output terminal.

2. The driving circuit as described in claim 1, characterized in that, The pixel driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first energy storage sub-circuit, and a second energy storage sub-circuit. The data writing sub-circuit is electrically connected to the data writing control line, the compensation control line, the data line, and the first terminal of the driving sub-circuit, respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving sub-circuit under the control of the data writing control signal provided by the data writing control line and the compensation control signal provided by the compensation control line; The compensation sub-circuit is electrically connected to the compensation control line, the control terminal of the drive sub-circuit, and the second terminal of the drive sub-circuit, respectively, and is used to control the connection between the control terminal of the drive sub-circuit and the second terminal of the drive sub-circuit under the control of the compensation control signal; The first energy storage sub-circuit is electrically connected to the first terminal of the driving sub-circuit and is used to store electrical energy. The second energy storage sub-circuit is electrically connected to the control terminal of the drive sub-circuit and is used to store electrical energy.

3. The driving circuit as described in claim 2, characterized in that, The pixel driving circuit also includes a reset sub-circuit; The reset sub-circuit is electrically connected to the data write control line, the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the data write control signal and the reset control signal provided by the reset control line.

4. The driving circuit as described in claim 2, characterized in that, The pixel driving circuit also includes a reset sub-circuit; The reset sub-circuit is electrically connected to the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the reset control signal provided by the reset control line.

5. The driving circuit as described in claim 2, characterized in that, The pixel driving circuit further includes a first light emission control sub-circuit, a second light emission control sub-circuit, and an initialization sub-circuit; The first light-emitting control sub-circuit is electrically connected to the light-emitting control line, the power supply voltage line and the first terminal of the driving sub-circuit, respectively, and is used to control the connection between the power supply voltage line and the first terminal of the driving sub-circuit under the control of the light-emitting control signal provided by the light-emitting control line; The second light-emitting control sub-circuit is electrically connected to the light-emitting control line, the second terminal of the driving sub-circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the second terminal of the driving sub-circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The initialization sub-circuit is electrically connected to the data write control line, the second initial voltage line, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage line into the first electrode of the light-emitting element under the control of the data write control signal.

6. The driving circuit according to any one of claims 2 to 5, characterized in that, The data writing sub-circuit includes a first transistor and a second transistor; the compensation sub-circuit includes a third transistor; The control electrode of the first transistor is electrically connected to the data write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the compensation control line, and the second electrode of the second transistor is electrically connected to the first terminal of the driving sub-circuit. The control electrode of the third transistor is electrically connected to the compensation control line, the first electrode of the third transistor is electrically connected to the control terminal of the driving sub-circuit, and the second electrode of the third transistor is electrically connected to the second terminal of the driving sub-circuit. The first energy storage sub-circuit includes a first capacitor; The first plate of the first capacitor is electrically connected to the first terminal of the driving sub-circuit, and the second plate of the first capacitor is electrically connected to the power supply voltage line.

7. The driving circuit as described in claim 3, characterized in that, The reset sub-circuit includes a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor. The control electrode of the fifth transistor is electrically connected to the data write control line, and the second electrode of the fifth transistor is electrically connected to the control terminal of the driving sub-circuit.

8. The driving circuit as described in claim 4, characterized in that, The reset sub-circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the control terminal of the driving sub-circuit.

9. The driving circuit as described in claim 5, characterized in that, The first light-emitting control sub-circuit includes a sixth transistor, the second light-emitting control sub-circuit includes a seventh transistor, the initialization sub-circuit includes an eighth transistor, the driving sub-circuit includes a driving transistor, and the second energy storage sub-circuit includes a second capacitor. The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor. The control electrode of the seventh transistor is electrically connected to the light-emitting control line, the first electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element. The control electrode of the eighth transistor is electrically connected to the data write control line, the first electrode of the eighth transistor is electrically connected to the second initial voltage line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element. The first plate of the second capacitor is electrically connected to the control electrode of the driving transistor, and the second plate of the second capacitor is electrically connected to the power supply voltage line.

10. The driving circuit according to any one of claims 1 to 5, characterized in that, It also includes N rows of reset control lines, N rows of data write control lines, and N rows of compensation control lines; the reset control lines, the data write control lines, and the compensation control lines all extend along a first direction; The driving circuit includes pixel driving circuits that are electrically connected to the corresponding row reset control line, the corresponding row data write control line and the corresponding row compensation control line, respectively. The reset control line, the data write control line, and the compensation control line of each row extend along the first direction to the surrounding area, and in the surrounding area, the nth row reset control line, the (n-1)th row data write control line, and the (n-2)th row compensation control line are electrically connected, and the first row data write control line is electrically connected to the second row reset control line; n is a positive integer, greater than 2, and less than N+1; N is an integer greater than 1.

11. The driving circuit as described in claim 10, characterized in that, In the surrounding area, the first row of data write control lines is electrically connected to the second row of reset control lines, and the Nth row of data write control lines is electrically connected to the (N-1)th row of compensation control lines.

12. The driving circuit as described in claim 10, characterized in that, It also includes N rows of light-emitting control lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding row of light-emitting control lines; Each row of pixel driving circuits includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor. The gate of the fourth transistor and the corresponding row reset control line are integrated into one structure; the gate of the eighth transistor and the next row reset control line adjacent to the corresponding row reset control line are integrated into one structure. The gate of the first transistor, the gate of the fifth transistor, and the corresponding row data write control line are integrated into one structure; The first gate of the third transistor, the second gate of the third transistor, the gate of the second transistor, and the corresponding row compensation control line are integrated into one structure. The gate of the sixth transistor, the gate of the seventh transistor, and the corresponding row light-emitting control line are integrated into one structure. The gate of the driving transistor is disposed between the corresponding row compensation control line and the corresponding row light emission control line; the gate of the driving transistor is multiplexed as the first plate of the second capacitor; the second plate of the second capacitor is multiplexed as the second plate of the first capacitor; and the drain of the sixth transistor is multiplexed as the first plate of the first capacitor. The corresponding row reset control line, the corresponding row data write control line, the corresponding row compensation control line and the corresponding row light emission control line, which are electrically connected to the pixel driving circuit of the same row, are arranged sequentially along the second direction; The first direction intersects with the second direction.

13. The driving circuit as described in claim 12, characterized in that, The active layers of the fourth transistor, the fifth transistor, the third transistor, the driving transistor, the second transistor, the first transistor, the sixth transistor, the seventh transistor, and the eighth transistor are formed from continuous semiconductor layers. The channels of the fourth transistor, the fifth transistor, and the driving transistor are arranged sequentially along the second direction; The channels of the first transistor, the second transistor, and the sixth transistor are arranged sequentially along the second direction.

14. The driving circuit as described in claim 12, characterized in that, It also includes N rows of second initial voltage lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding rows of second initial voltage lines; the second initial voltage lines and the second plate of the second capacitor are located on the same layer; The orthographic projection of the corresponding row second initial voltage line on the substrate is located on the side of the corresponding row reset control line on the substrate that is far from the orthographic projection of the corresponding row data write control line on the substrate.

15. A driving circuit, characterized in that, Includes multi-level scanning drive circuit and multi-row pixel drive circuit; At least one level of the scanning drive circuit includes a drive signal output terminal, which is electrically connected to at least three adjacent rows of pixel drive circuits in the multi-row pixel drive circuit, and is configured to provide a compensation control signal, a data write control signal, and a reset control signal to the at least three rows of pixel drive circuits respectively. The pixel driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first energy storage sub-circuit, and a second energy storage sub-circuit. The data writing sub-circuit is electrically connected to the data writing control line, the compensation control line, the data line, and the first terminal of the driving sub-circuit, respectively, and is used to write the data voltage provided by the data line into the first terminal of the driving sub-circuit under the control of the data writing control signal provided by the data writing control line and the compensation control signal provided by the compensation control line; The compensation sub-circuit is electrically connected to the compensation control line, the control terminal of the drive sub-circuit, and the second terminal of the drive sub-circuit, respectively, and is used to control the connection between the control terminal of the drive sub-circuit and the second terminal of the drive sub-circuit under the control of the compensation control signal; The first energy storage sub-circuit is electrically connected to the first terminal of the driving sub-circuit and is used to store electrical energy. The second energy storage sub-circuit is electrically connected to the control terminal of the drive sub-circuit and is used to store electrical energy.

16. The driving circuit as described in claim 15, wherein, The driving circuit includes an N+2 level scanning driving circuit and an N-row pixel driving circuit; N is an integer greater than 1. The driving circuit includes an nth-level scanning driving circuit whose nth-level driving signal output terminal is electrically connected to the (n-2)th row pixel driving circuit, the (n-1)th row pixel driving circuit, and the nth row pixel driving circuit, respectively. The nth-level scanning driving circuit is configured to provide a compensation control signal to the (n-2)th row pixel driving circuit, a data write control signal to the (n-1)th row pixel driving circuit, and a reset control signal to the nth row pixel driving circuit through the nth-level driving signal output terminal, respectively. n is a positive integer, greater than 2, and less than N+1.

17. The driving circuit as described in claim 15, wherein, The pixel driving circuit also includes a reset sub-circuit; The reset sub-circuit is electrically connected to the data write control line, the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the data write control signal and the reset control signal provided by the reset control line.

18. The driving circuit as claimed in claim 15, wherein, The pixel driving circuit also includes a reset sub-circuit; The reset sub-circuit is electrically connected to the reset control line, the first initial voltage line, and the control terminal of the drive sub-circuit, respectively, and is used to write the first initial voltage provided by the first initial voltage line into the control terminal of the drive sub-circuit under the control of the reset control signal provided by the reset control line.

19. The driving circuit as claimed in claim 15, wherein, The pixel driving circuit further includes a first light emission control sub-circuit, a second light emission control sub-circuit, and an initialization sub-circuit; The first light-emitting control sub-circuit is electrically connected to the light-emitting control line, the power supply voltage line and the first terminal of the driving sub-circuit, respectively, and is used to control the connection between the power supply voltage line and the first terminal of the driving sub-circuit under the control of the light-emitting control signal provided by the light-emitting control line; The second light-emitting control sub-circuit is electrically connected to the light-emitting control line, the second terminal of the driving sub-circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the second terminal of the driving sub-circuit and the first electrode of the light-emitting element under the control of the light-emitting control signal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The initialization sub-circuit is electrically connected to the data write control line, the second initial voltage line, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage line into the first electrode of the light-emitting element under the control of the data write control signal.

20. The driving circuit according to any one of claims 15 to 19, wherein, The data writing sub-circuit includes a first transistor and a second transistor; the compensation sub-circuit includes a third transistor; The control electrode of the first transistor is electrically connected to the data write control line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the compensation control line, and the second electrode of the second transistor is electrically connected to the first terminal of the driving sub-circuit. The control electrode of the third transistor is electrically connected to the compensation control line, the first electrode of the third transistor is electrically connected to the control terminal of the driving sub-circuit, and the second electrode of the third transistor is electrically connected to the second terminal of the driving sub-circuit. The first energy storage sub-circuit includes a first capacitor; The first plate of the first capacitor is electrically connected to the first terminal of the driving sub-circuit, and the second plate of the first capacitor is electrically connected to the power supply voltage line.

21. The driving circuit as claimed in claim 17, wherein, The reset sub-circuit includes a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor. The control electrode of the fifth transistor is electrically connected to the data write control line, and the second electrode of the fifth transistor is electrically connected to the control terminal of the driving sub-circuit.

22. The driving circuit as described in claim 18, wherein, The reset sub-circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the reset control line, the first electrode of the fourth transistor is electrically connected to the first initial voltage line, and the second electrode of the fourth transistor is electrically connected to the control terminal of the driving sub-circuit.

23. The driving circuit as described in claim 19, wherein, The first light-emitting control sub-circuit includes a sixth transistor, the second light-emitting control sub-circuit includes a seventh transistor, the initialization sub-circuit includes an eighth transistor, the driving sub-circuit includes a driving transistor, and the second energy storage sub-circuit includes a second capacitor. The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor. The control electrode of the seventh transistor is electrically connected to the light-emitting control line, the first electrode of the seventh transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element. The control electrode of the eighth transistor is electrically connected to the data write control line, the first electrode of the eighth transistor is electrically connected to the second initial voltage line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element. The first plate of the second capacitor is electrically connected to the control electrode of the driving transistor, and the second plate of the second capacitor is electrically connected to the power supply voltage line.

24. The driving circuit according to any one of claims 15 to 19, wherein, It also includes N rows of reset control lines, N rows of data write control lines, and N rows of compensation control lines; the reset control lines, the data write control lines, and the compensation control lines all extend along a first direction; The driving circuit includes pixel driving circuits that are electrically connected to the corresponding row reset control line, the corresponding row data write control line and the corresponding row compensation control line, respectively. The reset control line, the data write control line, and the compensation control line of each row extend along the first direction to the surrounding area, and in the surrounding area, the nth row reset control line, the (n-1)th row data write control line, and the (n-2)th row compensation control line are electrically connected, and the first row data write control line is electrically connected to the second row reset control line; n is a positive integer, greater than 2, and less than N+1; N is an integer greater than 1.

25. The driving circuit as described in claim 24, wherein, In the surrounding area, the first row of data write control lines is electrically connected to the second row of reset control lines, and the Nth row of data write control lines is electrically connected to the (N-1)th row of compensation control lines.

26. The driving circuit as described in claim 24, wherein, It also includes N rows of light-emitting control lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding row of light-emitting control lines; Each row of pixel driving circuits includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor. The gate of the fourth transistor and the corresponding row reset control line are integrated into one structure; the gate of the eighth transistor and the next row reset control line adjacent to the corresponding row reset control line are integrated into one structure. The gate of the first transistor, the gate of the fifth transistor, and the corresponding row data write control line are integrated into one structure; The first gate of the third transistor, the second gate of the third transistor, the gate of the second transistor, and the corresponding row compensation control line are integrated into one structure. The gate of the sixth transistor, the gate of the seventh transistor, and the corresponding row light-emitting control line are integrated into one structure. The gate of the driving transistor is disposed between the corresponding row compensation control line and the corresponding row light emission control line; the gate of the driving transistor is multiplexed as the first plate of the second capacitor; the second plate of the second capacitor is multiplexed as the second plate of the first capacitor; and the drain of the sixth transistor is multiplexed as the first plate of the first capacitor. The corresponding row reset control line, the corresponding row data write control line, the corresponding row compensation control line and the corresponding row light emission control line, which are electrically connected to the pixel driving circuit of the same row, are arranged sequentially along the second direction; The first direction intersects with the second direction.

27. The driving circuit as claimed in claim 26, wherein, The active layers of the fourth transistor, the fifth transistor, the third transistor, the driving transistor, the second transistor, the first transistor, the sixth transistor, the seventh transistor, and the eighth transistor are formed from continuous semiconductor layers. The channels of the fourth transistor, the fifth transistor, and the driving transistor are arranged sequentially along the second direction; The channels of the first transistor, the second transistor, and the sixth transistor are arranged sequentially along the second direction.

28. The driving circuit as described in claim 26, wherein, It also includes N rows of second initial voltage lines, and the pixel driving circuit included in the driving circuit is also electrically connected to the corresponding rows of second initial voltage lines; the second initial voltage lines and the second plate of the second capacitor are located on the same layer; The orthographic projection of the corresponding row second initial voltage line on the substrate is located on the side of the corresponding row reset control line on the substrate that is far from the orthographic projection of the corresponding row data write control line on the substrate.

29. A driving method for driving a driving circuit as described in any one of claims 1 to 28, characterized in that, The driving method includes: The driving circuit includes at least one scanning driving circuit that provides compensation control signals, data write control signals, and reset control signals to at least three adjacent rows of pixel driving circuits through the driving signal output terminal.

30. A display device, characterized in that, Includes the driving circuit as described in any one of claims 1 to 28.

31. The display device as claimed in claim 30, characterized in that, It also includes a display substrate, wherein the pixel driving circuit included in the driving circuit is disposed in the display area of ​​the display substrate, and the scanning driving circuit included in the driving circuit is disposed in the peripheral area of ​​the display substrate.

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