A data encryption method and device, electronic equipment and storage medium

Abstract

The application discloses a data encryption method and device, electronic equipment and storage medium. The method comprises the following steps: obtaining a plurality of to-be-encrypted data corresponding to multimedia data and an extended key corresponding to an initial key; the extended key is a plurality of sub-keys obtained by performing multi-round key expansion on the initial key; using the extended key, performing multi-round encryption processing on each to-be-encrypted data in the plurality of to-be-encrypted data in a parallel processing mode to obtain sub-ciphertext data corresponding to each to-be-encrypted data; the encryption processing comprises key addition processing, byte substitution processing, row shift processing and column mixing processing; and combining the sub-ciphertext data corresponding to the to-be-encrypted data according to the grouping order of the to-be-encrypted data to obtain target ciphertext data.

Description

Technical Field

[0001] This application relates to the field of information security technology, and in particular to a data encryption method, apparatus, electronic device, and storage medium. Background Technology

[0002] Currently, with the rapid development and widespread application of computer and information technology, the scale of application systems in various industries is expanding rapidly, resulting in an explosive growth in application data. While promoting industry development, the generation and transmission of large amounts of data undoubtedly exposes more application information to the network, leading to a heavy reliance on electronic cryptographic devices for sensitive information and assets. Under this trend, the methods for security analysis of electronic cryptographic devices are increasing, posing a significant challenge to the security of electronic devices. To ensure the security of generated and transmitted data, various industries are researching effective hardware and software implementations of encryption and decryption modules in their application systems. Currently, the Advanced Encryption Standard (AES) algorithm is commonly used to protect the security of sensitive information and assets in electronic devices.

[0003] When encrypting or decrypting high-speed, large-volume, and wide-bit-width data, refer to... Figure 1 As shown, related technologies use general-purpose processors (CPUs) to implement the AES algorithm for data encryption or decryption. However, due to the limited number of CPU cores, there is at least a problem of slow encryption speed when encrypting or decrypting large amounts of data. Summary of the Invention

[0004] This application provides a data encryption method, apparatus, electronic device, and storage medium.

[0005] The technical solution of this application is implemented as follows:

[0006] This application provides a data encryption method, the method comprising:

[0007] Obtain multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to the initial key; the extended key is a plurality of subkeys obtained by performing multiple rounds of key expansion on the initial key;

[0008] Using the extended key, each of the plurality of data to be encrypted is subjected to multiple rounds of encryption processing in parallel processing mode to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing.

[0009] According to the grouping order of the data to be encrypted, the sub-ciphertext data corresponding to the data to be encrypted are combined to obtain the target ciphertext data.

[0010] This application provides a data encryption device, the device comprising:

[0011] The acquisition module is used to acquire multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to the initial key; the extended key is a plurality of subkeys obtained by performing multiple rounds of key expansion on the initial key;

[0012] The processing module is used to perform multiple rounds of encryption processing in parallel processing mode on each of the plurality of data to be encrypted using the extended key, so as to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing;

[0013] The processing module is further configured to combine the sub-ciphertext data corresponding to the data to be encrypted according to the grouping order of the data to be encrypted, so as to obtain the target ciphertext data.

[0014] This application provides an electronic device, the electronic device comprising:

[0015] Memory, used to store executable instructions;

[0016] A parallel processor is used to execute executable instructions stored in the memory to implement the data encryption method described above.

[0017] This application provides a storage medium that stores one or more programs, which can be executed by one or more processors to implement the data encryption method described above.

[0018] This application provides a data encryption method, apparatus, electronic device, and storage medium. It obtains multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to an initial key. The extended key is a set of sub-keys obtained by expanding the initial key through multiple rounds. Using the extended key, multiple rounds of encryption processing are performed on each of the multiple data to be encrypted in parallel processing mode to obtain sub-ciphertext data corresponding to each data to be encrypted. The encryption processing includes key addition, byte substitution, row shifting, and column mixing. The sub-ciphertext data corresponding to the data to be encrypted are combined according to the grouping order of the data to be encrypted to obtain the target ciphertext data. In other words, this application uses the initial key and extended key to perform multiple rounds of parallel encryption processing on each data to be encrypted, achieving parallel processing of large amounts of data. This fully utilizes the hardware computing power of the parallel processor, greatly reducing data encryption time and improving execution efficiency. Simultaneously, the parallel processor has a relatively specialized function and higher security than a general-purpose CPU, improving the security of encrypted data. Finally, the multiple sub-ciphertext data are recombine to obtain the target ciphertext data, enabling efficient encryption during the data encryption process. Furthermore, using a parallel processor releases CPU memory resources and reduces CPU computational pressure. Attached Figure Description

[0019] Figure 1 A structural block diagram of a data encryption method provided for related technical solutions;

[0020] Figure 2 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram illustrating a key expansion process for an initial key, provided in an embodiment of this application.

[0022] Figure 4 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the structure of a key-adding neural network operator provided in an embodiment of this application;

[0024] Figure 6 A schematic diagram illustrating the XOR operation process of key addition in parallel mode, provided as an embodiment of this application;

[0025] Figure 7 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0026] Figure 8 A flowchart illustrating a byte permutation / inverse byte permutation neural network operator provided in this application embodiment;

[0027] Figure 9 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0028] Figure 10 A flowchart illustrating a row shift / reverse shift neural network operator provided in this application embodiment;

[0029] Figure 11 This application provides a schematic diagram illustrating a process of left-row shifting of a third state matrix according to an embodiment of the present application.

[0030] Figure 12 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0031] Figure 13 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0032] Figure 14 A flowchart illustrating a column hybrid / inverse column hybrid neural network operator provided in this application embodiment;

[0033] Figure 15 A flowchart illustrating an optional data encryption method provided in an embodiment of this application;

[0034] Figure 16 A flowchart illustrating an optional data decryption method provided in an embodiment of this application;

[0035] Figure 17 This is a schematic diagram of the structure of a data encryption device provided in an embodiment of this application;

[0036] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0038] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] See Figure 2 , Figure 2 This is a schematic diagram of an implementation flow of the data encryption method provided in this application embodiment. The data encryption method is applied to a parallel processor and includes the following steps:

[0041] Step 201: Obtain multiple data to be encrypted corresponding to the multimedia data, and the extended key corresponding to the initial key.

[0042] Among them, the extended key is a number of subkeys obtained by expanding the initial key through multiple rounds of key expansion.

[0043] In some embodiments, multimedia data includes, but is not limited to, text, images, photographs, sounds, animations, videos, and files, as well as data generated by other interactive functions provided by a computer. Here, multimedia data can be plaintext data.

[0044] In some embodiments, the data to be encrypted is encoded data represented in bytes obtained by a parallel processor encoding multimedia data, and then grouped according to a preset grouping rule. Here, the preset grouping rule can be to group the encoded data into 128 bits or 16 bytes (B). The bit width of the data to be encrypted is 128 bits, and the data to be encrypted can be represented by a 4×4 data matrix, meaning each piece of data in the data to be encrypted is one byte. It should be noted that after obtaining multiple pieces of data to be encrypted corresponding to the multimedia data, parallel computation can be performed based on these.

[0045] In some embodiments, the initial key is a predetermined key, and its length can be 128 bits, 192 bits, or 256 bits. The initial key can be represented as a matrix, with the number of rows in the initial key equal to the number of rows in the data to be encrypted, and the number of columns in the initial key equal to the number of columns in the data to be encrypted. For example, the initial key is 128 bits long and can be represented as a 4×4 key matrix.

[0046] In some embodiments, the extended key is a plurality of subkeys obtained by performing multiple rounds of key expansion on the initial key, and the extended key includes the initial key. Here, the process of obtaining multiple subkeys by performing multiple rounds of key expansion on the initial key, which is a 4×4 key matrix, is combined with... Figure 3 To explain,

[0047] Each column of the initial 4×4 key matrix key[0] is used to form a word, named W[0], W[1], W[2], and W[3] respectively. Then, the array W is expanded into 40 new columns, forming a total of 44 columns of expanded key. (Refer to...) Figure 3 As shown in A, Figure 3 The diagram A illustrates the key expansion process. Key expansion is generated recursively as follows: when i is not a multiple of 4, the i-th column is represented as... When i is a multiple of 4, then the i-th column is represented as follows: Where T is a complex function composed of nonlinear and linear functions. Figure 3 B in the diagram shows the flowchart of the T function. The processing procedure is as follows: A word, such as w, is cyclically shifted left by one byte, transforming the input word [B1, B2, B3, B4] into [B2, B3, B4, B1]. The result after the word loop is then subjected to byte substitution (also known as byte replacement) using an S-box, resulting in the substituted result [S(B2), S(B3), S(B4), S(B1)]. Finally, the substituted result is XORed with the round constant Rcon[j], where j represents the round number and Rcon is defined in GF(2... 8 The modulus m(x) = x8 + x4 + x3 + x + 1 is used to obtain w' after processing by the T function.

[0048] In some embodiments, a parallel processor is a processor with a certain number of core computing units capable of performing data-parallel operations; this number can range from hundreds to thousands. The parallel processor can be a Graphics Processing Unit (GPU) or a neural network processing unit (NPU), and this application does not impose specific limitations on this. Here, a GPU can be understood as a programmable graphics card, originally used in computers for graphics and image processing. In recent years, GPUs have also been applied to large-scale parallel computing. Since a single GPU typically has hundreds of core computing units, it possesses hundreds of times more core computing units than a CPU. GPUs are well-suited for performing highly parallelizable, intensive computing tasks, often resulting in performance improvements of several times over. The NPU employs a "data-driven parallel computing" architecture to process massive amounts of multimedia data such as video and images. The NPU processor has hundreds of core computing units to accelerate neural network operations.

[0049] In practical applications, compared to CPUs, GPUs / NPUs have fewer control logic units but a large number of logic operation units and GPU / NPU threads, making them suitable for efficiently executing batch computing tasks in parallel. Especially for batch computing tasks with fewer bits, where the number of tasks is large and the computational load of each task is small, more logic operation units and GPU / NPU threads can be used in parallel, thereby improving overall computational efficiency.

[0050] Step 202: Using the extended key, perform multiple rounds of encryption processing on each of the multiple data to be encrypted in parallel processing mode to obtain the sub-ciphertext data corresponding to each data to be encrypted.

[0051] The encryption process includes key addition, byte substitution, row shifting, and column mixing.

[0052] In some embodiments, the sub-ciphertext data is the encrypted data obtained by performing key addition, byte substitution, row shifting, and column mixing on the data to be encrypted using an extended key.

[0053] In this embodiment of the application, the parallel processor assigns the extended key and each of the multiple data to be encrypted to multiple logical units of the parallel processor and their corresponding multiple threads for execution. In the parallel processing mode, each thread uses the extended key to perform multiple rounds of key addition, byte substitution, row shifting and column mixing processing on the data to be encrypted to obtain the sub-ciphertext data.

[0054] Step 203: According to the grouping order of the data to be encrypted, combine the sub-ciphertext data corresponding to the data to be encrypted to obtain the target ciphertext data.

[0055] In this embodiment of the application, an extended key is used to perform multiple rounds of encryption processing on each of the multiple data to be encrypted in parallel processing mode. After obtaining the sub-ciphertext data corresponding to each data to be encrypted, the sub-ciphertext data corresponding to the data to be encrypted are combined according to the grouping order of the data to be encrypted to obtain the target ciphertext data.

[0056] This application provides a data encryption method. It obtains multiple data sets to be encrypted corresponding to multimedia data, and an extended key corresponding to an initial key. The extended key is a set of sub-keys obtained by expanding the initial key through multiple rounds. Using the extended key, multiple rounds of encryption processing are performed on each of the multiple data sets to be encrypted in parallel processing mode to obtain sub-ciphertext data corresponding to each data set to be encrypted. The encryption processing includes key addition, byte substitution, row shifting, and column mixing. The sub-ciphertext data corresponding to the data sets to be encrypted are combined according to the grouping order of the data sets to be encrypted to obtain the target ciphertext data. In other words, this application utilizes the initial key and extended key to perform multiple rounds of parallel encryption processing on each data set to be encrypted, achieving parallel processing of large amounts of data. This fully utilizes the hardware computing power of the parallel processor, greatly reducing data encryption time and improving execution efficiency. Simultaneously, the parallel processor has a relatively specialized function and higher security than a general-purpose CPU, improving the security of encrypted data. Finally, the multiple sub-ciphertext data are recombine to obtain the target ciphertext data, enabling efficient encryption during the data encryption process. Furthermore, using a parallel processor releases CPU memory resources and reduces CPU computational pressure.

[0057] In some embodiments, step 202 provided in the above embodiments can be implemented by steps 301 to 303, such as... Figure 4 The diagram shown is a flowchart illustrating the data encryption method provided in an embodiment of this application. Figure 1 and Figure 4 The steps shown are explained below.

[0058] Step 301: Select the nth subkey from the extended key that corresponds to the nth round of encryption.

[0059] Where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing.

[0060] In some embodiments, the recommended total number of encryption rounds varies depending on the length of the initial key. For example, if the key length is 128 bits, the total number of encryption rounds is 10; if the key length is 192 bits, the total number of encryption rounds is 12; and if the key length is 256 bits, the total number of encryption rounds is 14.

[0061] In some embodiments, the extended key includes N+1 subkeys, each of which is used to perform XOR processing on the data to be encrypted.

[0062] Step 302: Obtain the nth intermediate encrypted data after the nth round of encryption processing on the data to be encrypted.

[0063] In some embodiments, the size of the nth intermediate encrypted data is the same as that of the data to be encrypted, that is, the nth intermediate encrypted data is still a 4×4 data matrix.

[0064] In some embodiments, when n is less than N, the (n-1)th intermediate encrypted data is the (n-1)th column of mixed data; when n is equal to N, the (n-1)th intermediate encrypted data is the (n-1)th row of shifted data.

[0065] Step 303: In parallel processing mode, perform synchronous XOR processing on the data in the nth intermediate encrypted data and the key at the corresponding position of the nth subkey to obtain the nth key operation data after the nth round of key addition processing, so as to obtain the subciphertext data.

[0066] In some embodiments, the parallel processor can divide the nth intermediate encrypted data into multiple groups in the form of data blocks, and also divide the nth subkey into multiple groups in the same form of data blocks. Parallel operations can then be performed on each group of data based on this. For example, if the nth intermediate encrypted data is a 4×4 data matrix and the nth subkey is a 4×4 key matrix, during XOR processing, the data groups are used as the operation unit. A single 8-bit data in the nth intermediate encrypted data and a single 8-bit key at the corresponding position of the nth subkey are assigned to the logic unit and its corresponding thread of the parallel processor. Multiple threads synchronously perform XOR operations on the single 8-bit data and the corresponding 8-bit key. Therefore, there will be 16 parallel XOR operations. Then, the data after each XOR operation are combined to obtain the nth key operation data after the nth round of key addition processing, thus obtaining the subciphertext data.

[0067] In a feasible application scenario, the nth intermediate encrypted data is used as the first state matrix, and the nth subkey is used as the round key matrix. The structure of the key addition neural network operator is referenced. Figure 5As shown, the first state matrix and the round key matrix are bitwise XORed to obtain a new first state matrix. Here, the XOR operation process for key addition in parallel mode is described in detail below. Figure 6 As shown, each data (or element) in the first state matrix is ​​synchronously XORed with each key (or element) in the round key matrix to obtain a new first state matrix. It should be noted that the data encryption process includes an initial round key addition, multiple iterative operations in the middle, and a final non-iterative operation. Before the iterative operations, the initial ciphertext is obtained by performing a round key addition on the data to be encrypted using the initial key. Then, the initial ciphertext and the first subkey are used as input data for the first iterative operation to continue subsequent operations.

[0068] As described above, when performing key operations on the nth intermediate encrypted data and the nth subkey, the serial encryption process for all data is improved to a parallel encryption process. This is achieved through multi-threaded parallel execution within the NPU / GPU using multiple arithmetic logic units, effectively leveraging the high efficiency of the NPU / GPU for batch computation tasks with a small number of bits. Furthermore, using NPU / GPU parallel encryption to encrypt and decrypt dynamic data streams in a big data environment fully utilizes the hardware computing power of parallel processors, significantly reducing data encryption time and improving execution efficiency. Additionally, the relatively specialized function of parallel processors provides higher security than general-purpose CPUs, enhancing the security of encrypted data.

[0069] In some embodiments, step 202 provided in the above embodiments can be implemented by steps 401 to 402, such as... Figure 7 The diagram shown is a flowchart illustrating the data encryption method provided in an embodiment of this application. Figure 1 and Figure 7 The steps shown are explained below.

[0070] Step 401: After performing the (n-1)th round of key addition on the data to be encrypted using the extended key to obtain the (n-1)th key operation data, obtain the permutation parameters corresponding to the data in the first permutation data and the (n-1)th key operation data.

[0071] Where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing.

[0072] In some embodiments, the first permutation data is a pre-set table, also known as the S-box.

[0073] In some embodiments, since each data in the (n-1)th key operation data is 1 byte, the permutation parameter corresponding to each data includes the row value as the high 4 bits of the byte and the column value as the low 4 bits.

[0074] It should be noted that when n=1, the (n-1)th key operation data is the initial ciphertext obtained by performing one round of key addition on the data to be encrypted based on the initial key; when n is greater than 1 and less than or equal to N, the (n-1)th key operation data is the intermediate ciphertext data after n-1 rounds of encryption.

[0075] In some embodiments, the parallel processor can divide the (n-1)th key operation data into multiple groups in the form of data blocks, and perform parallel operations on the permutation parameters of each group of data based on this. For example, with the (n-1)th key operation data as a 4×4 data matrix, and with data groups as the operation unit, each group of data is assigned to the logic unit and its corresponding thread of the parallel processor, and multiple threads synchronously obtain the permutation parameters of a single 8-bit data in the (n-1)th key operation data.

[0076] Step 402: In parallel mode, all data in the (n-1)th key operation data are synchronously replaced with the target parameters corresponding to the permutation parameters in the first permutation data to obtain the nth permutation data after the nth round of byte permutation processing, so as to obtain the sub-ciphertext data.

[0077] In this embodiment of the application, the parallel processor, in parallel mode, searches for the target parameter corresponding to the permutation parameter in the first permutation data according to the permutation parameter corresponding to all data in the (n-1)th key operation data, and synchronously replaces all data in the (n-1)th key operation data with the target parameter to obtain the nth permutation data after the nth round of byte permutation processing, and then obtains the sub-ciphertext data.

[0078] For example, when a certain data S1 in the (n-1)th key operation data is 0x12, the permutation parameters of S1 are determined to be 0x01 and 0x02. Based on the permutation parameters, the 0x01 row and 0x02 column of the S-box are searched to obtain the value 0xc9. Then, the original 0x12 in the (n-1)th key operation data is replaced with 0xc9. Here, the (n-1)th key operation data is used as the second state matrix, and the first permutation data is the S-box (SBOX). The structure of the byte permutation neural network operator is referenced... Figure 8 As shown in A, the second state matrix and the S-box undergo vector indexing (gathering) to obtain a new second state matrix. It should be noted that when the (n-1)th key operation data is used as the second state matrix, and the first permutation data is the inverse S-box (INVSBOX), the structure of the inverse byte permutation neural network operator is as follows: Figure 8As shown in B, the second state matrix and the inverse S-box are subjected to vector indexing to obtain a new second state matrix.

[0079] As described above, when performing byte permutation processing based on the (n-1)th key operation data and the first permutation data, the permutation parameters of each data in the (n-1)th key operation data are obtained in parallel, and the target parameter corresponding to each permutation parameter is searched in the first permutation data simultaneously for replacement. This improves the serial encryption processing of all data into a parallel encryption processing form. In the NPU / GPU, multi-threaded parallel execution through multiple arithmetic logic units effectively leverages the high efficiency of the NPU / GPU for batch computing tasks with a small number of bits. Simultaneously, using NPU / GPU parallel encryption processing to encrypt and decrypt dynamic data streams in a big data environment fully utilizes the hardware computing power of parallel processors, greatly reducing data encryption time and improving execution efficiency. Furthermore, the relatively specialized function of parallel processors provides higher security than general-purpose CPUs, enhancing the security of encrypted data.

[0080] In some embodiments, step 202 provided in the above embodiments can be implemented by steps 501 to 502, such as... Figure 9 The diagram shown is a flowchart illustrating the data encryption method provided in an embodiment of this application. Figure 1 and Figure 9 The steps shown are explained below.

[0081] Step 501: After performing the nth round of byte permutation on the data to be encrypted using the extended key to obtain the nth permuted data, obtain the row shift parameter corresponding to the data in the nth permuted data.

[0082] Where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing.

[0083] In some embodiments, the row shift parameter can be understood as the row number of each data in the nth permutation data. For example, if a data in the nth permutation data is in the 0th row of the nth permutation data, then the row shift parameter of that data is 0, that is, the data is shifted left by 0 bytes; if a data in the nth permutation data is in the 1st row of the nth permutation data, then the row shift parameter of that data is 1, that is, the data is shifted left by 1 byte; if a data in the nth permutation data is in the 2nd row of the nth permutation data, then the row shift parameter of that data is 2, that is, the data is shifted left by 2 bytes; if a data in the nth permutation data is in the 3rd row of the nth permutation data, then the row shift parameter of that data is 3, that is, the data is shifted left by 3 bytes.

[0084] It should be noted that a parallel processor can divide the nth permutation data into multiple groups in the form of data blocks, and perform parallel operations to obtain the row shift parameters of each group of data based on this. For example, with the nth permutation data as a 4×4 data matrix, and using data groups as the operation unit, each group of data is assigned to the logic unit and its corresponding thread of the parallel processor, and multiple threads synchronously obtain the row shift parameters of a single 8-bit data in the nth permutation data.

[0085] Step 502: In parallel processing mode, according to the row shift parameters, perform row shift processing on the data in the nth permutation data to obtain the nth row shifted data after the nth round of row shift processing, so as to obtain the sub-ciphertext data.

[0086] In some embodiments, after obtaining the row shift parameters corresponding to the data in the nth permutation data, the parallel processor performs row shift processing on all the data in the nth permutation data in parallel mode according to the row shift parameters corresponding to all the data in the nth permutation data, to obtain the nth row shifted data after the nth round of row shift processing, and then obtains the sub-ciphertext data.

[0087] For example, the nth permutation data is used as the third state matrix, and the process of row shifting the third state matrix according to the row shift parameters is as follows. Figure 10 As shown, Figure 10 The diagram shown in Figure A illustrates the structure of the row shift neural network operator. The third state matrix is ​​subjected to a row-to-left shift (SHIFT) operation. The process of performing this row-to-left shift on the third state matrix is ​​described in [reference needed]. Figure 11 As shown. Figure 10 B in the diagram shows the structure of the inverse shift neural network operator. Performing an inverse shift (INVSHIFT) on the third state matrix is ​​equivalent to performing a row shift on the third state matrix. It should be noted that if the row shift results in a new 16×1 third state matrix, a reshape transformation is performed on this new matrix to transform it into a new 4×4 third state matrix.

[0088] As described above, when performing row shifting on the nth permutation data, the row shift parameters of each data point in the nth permutation data are obtained in parallel, and the data in the nth permutation data are shifted in parallel according to the corresponding row shift parameters. This improves the serial encryption process for all data into a parallel encryption process. In the NPU / GPU, this is executed in parallel by multiple arithmetic logic units and multiple threads, effectively leveraging the high efficiency of the NPU / GPU for batch computing tasks with a small number of bits. Simultaneously, using NPU / GPU parallel encryption processing to encrypt and decrypt dynamic data streams in a big data environment fully utilizes the hardware computing power of parallel processors, greatly reducing data encryption time and improving execution efficiency. Furthermore, the relatively specialized function of parallel processors provides higher security than general-purpose CPUs, enhancing the security of encrypted data.

[0089] In some embodiments, step 202 provided in the above embodiments can be implemented by steps 601 to 604, such as... Figure 12 The diagram shown is a flowchart illustrating the data encryption method provided in an embodiment of this application. Figure 1 and Figure 12 The steps shown are explained below.

[0090] Step 601: After performing the nth round of row shifting on the data to be encrypted using the extended key to obtain the nth row of shifted data, obtain the first multiplication lookup table and the second multiplication lookup table.

[0091] Where 1≤n≤N-1, and n is an integer, N is the total number of rounds of encryption processing, and the first multiplication lookup table is different from the second multiplication lookup table.

[0092] In some embodiments, the multiplication lookup table is GF(2). 8 A matrix multiplication lookup table is a known data matrix used to break down matrix multiplication operations into addition, subtraction, and other operations to speed up the calculation.

[0093] Step 602: In parallel mode, perform a synchronization vector index on the data in the nth row of shifted data based on the first multiplication lookup table to obtain the first index data, and perform a synchronization vector index on the data in the column mixed coefficient data based on the second multiplication lookup table to obtain the coefficient index data.

[0094] In some embodiments, the column mixing coefficient data is a pre-defined matrix used to implement column mixing operations. The column mixing coefficient data can be represented by a 4×4 matrix.

[0095] In some embodiments, since each data in the nth row of shifted data is 1 byte, the high 4 bits of each data in the nth row of shifted data are used as the row index and the low 4 bits as the column index. In parallel mode, the index data of the row index and column index is searched in the first multiplication lookup table, and the data in the nth row of shifted data is replaced with this index data. Similarly, in parallel mode, the high 4 bits of each data in the column mixed coefficient data are used as the row index and the low 4 bits as the column index. In parallel mode, the coefficient index data of the row index and column index is searched in the second multiplication lookup table, and the data in the column mixed coefficient data is replaced with this coefficient index data.

[0096] It should be noted that the first index data is obtained by performing a synchronous vector index on the data in the nth row of the shifted data based on the first multiplication lookup table, and the coefficient index data is obtained by performing a synchronous vector index on the data in the column mixed coefficient data based on the second multiplication lookup table. These can be allocated to different logical units and their corresponding threads, so that multiple threads can execute synchronously, thereby reducing the computation time and speeding up the data encryption.

[0097] Step 603: Perform synchronous type conversion on the data in the nth row of shifted data to obtain the first converted data, and perform synchronous type conversion on the data in the column mixed coefficient data to obtain the coefficient converted data.

[0098] In some embodiments, synchronous type conversion can be understood as converting a data matrix into a Boolean (bool) type matrix. Here, synchronous type conversion is also called cast type conversion. The rule for synchronous type conversion is that if the data in the nth row of shifted data is 0x00, then the data at that position is converted to false; if the data in the nth row of shifted data is not 0x00, then the data at that position is converted to true.

[0099] In this embodiment, the parallel processor can divide the nth row shifted data into multiple groups in the form of data blocks, and perform parallel type conversion on the data type of each group based on this. For example, using the nth row shifted data as a 4×4 data matrix, and taking the data group as the operation unit, each group of data is assigned to the logic unit and its corresponding thread of the parallel processor. Multiple threads synchronously perform type conversion on a single 8-bit data in the nth row shifted data to obtain the first converted data. Similarly, the parallel processor can divide the column mixed coefficient data into multiple groups in the form of data blocks, and perform parallel type conversion on the data type of each group based on this. For example, using a 4×4 data matrix with column mixed coefficient data, and taking data groups as the operation unit, each group of data is assigned to a logic unit and its corresponding thread in a parallel processor. Multiple threads synchronously perform type conversion on individual 8-bit data in the column mixed coefficient data to obtain coefficient-converted data. As can be seen from the above, the serial encryption processing of all data is improved into parallel encryption processing. In the NPU / GPU, multiple arithmetic logic units and multiple threads execute in parallel, effectively leveraging the high efficiency of NPU / GPU for batch computing tasks with fewer bits. At the same time, using NPU / GPU parallel encryption processing to encrypt and decrypt dynamic data streams in a big data environment fully utilizes the hardware computing power of the parallel processor, greatly reducing data encryption time and improving execution efficiency. In addition, the parallel processor has a relatively specialized function and is more secure than a general-purpose CPU, thus improving the security of encrypted data.

[0100] It should be noted that the data in the nth row of shifted data is synchronously converted to obtain the first converted data, and synchronously converted to the data in the column mixed coefficient data to obtain the coefficient converted data. This data can be allocated to different logical units and their corresponding threads, thereby enabling multiple threads to execute synchronously, which reduces computation time and speeds up data encryption.

[0101] It should be noted that steps 603 and 604 can be executed simultaneously to reduce computation time and speed up data encryption.

[0102] Step 604: Based on the first index data, coefficient index data, first transformation data and coefficient transformation data, obtain the nth column mixed data after the nth round of column mixing processing, so as to obtain the sub-ciphertext data.

[0103] In this embodiment of the application, the parallel processor performs synchronous type conversion on the data in the nth row of shifted data to obtain first converted data, and performs synchronous type conversion on the data in the column mixed coefficient data to obtain coefficient converted data. Then, based on the first index data, coefficient index data, first converted data and coefficient converted data, the nth column mixed data after the nth round of column mixed processing is obtained to obtain the sub-ciphertext data.

[0104] In some embodiments, step 604 provided in the above embodiments can be implemented by steps 701 to 704, such as... Figure 13 The diagram shown is a flowchart illustrating the data encryption method provided in an embodiment of this application. Figure 12 and Figure 13 The steps shown are explained below.

[0105] Step 701: Perform a synchronous addition operation on the data in the first index data and the data in the coefficient index data to obtain the first operation data, and perform a logical AND operation on the first transformation data and the coefficient transformation data to obtain the second operation data.

[0106] In some embodiments, the parallel processor can divide the first index data into multiple groups in the form of data blocks, and also divide the coefficient index data into multiple groups in the same form of data blocks. Parallel operations can then be performed on each group of data based on this. For example, given a 4×4 matrix where both the first index data and the coefficient index data are 4×4 matrices, during matrix addition, the operation is performed on a data group basis. A single 8-bit data point in the first index data and the corresponding 8-bit coefficient index data are allocated to the logic unit and its corresponding thread of the parallel processor. Multiple threads synchronously add the single 8-bit data point to the corresponding 8-bit coefficient index data. Therefore, there will be 16 parallel addition operations. Then, the data after each addition operation are combined to obtain the first operation data.

[0107] In some embodiments, the parallel processor can divide the first transformation data into multiple groups in the form of data blocks, and also divide the coefficient transformation data into multiple groups in the same form of data blocks. Parallel operations can then be performed on each group of data based on this. For example, if the first transformation data is a 4×4 data matrix and the coefficient transformation data is a 4×4 matrix, during matrix addition, the operation is performed on a data group basis. A single 8-bit data point in the first transformation data and the corresponding 8-bit coefficient transformation data are allocated to the logic unit and its corresponding thread of the parallel processor. Multiple threads synchronously add the single 8-bit data point to the corresponding 8-bit coefficient transformation data. Therefore, there will be 16 parallel addition operations. Then, the data after each addition operation are combined to obtain the first operation data.

[0108] Step 702: If there is a portion of the first operational data that is greater than a preset data threshold, obtain the difference between the portion of the data and the preset data threshold, and replace the portion of the data in the first operational data with the difference.

[0109] In some embodiments, the preset data threshold is 0xFF, and the preset data threshold is used to determine whether there is overflow data in the first operation data.

[0110] In some embodiments, the partial data may be one piece of data in the first operational data or multiple pieces of data in the first operational data. This application does not impose specific limitations on this.

[0111] In some embodiments, the parallel processor determines whether there is any data in the first operational data that exceeds a preset data threshold. If so, it is determined that there is overflowing data in the first operational data. In this case, the preset data threshold is subtracted from the overflowing data to obtain the difference, and the overflowing data in the first operational data is replaced with this difference. If the preset data threshold is not exceeded, it is determined that there is no overflowing data in the first operational data, and no replacement processing is required.

[0112] Step 703: Obtain the third multiplication lookup table, and in parallel mode, perform synchronous vector indexing on the data in the replaced first operation data based on the third multiplication lookup table to obtain the second index data.

[0113] In some embodiments, the parallel processor obtains a third multiplication lookup table. Since each data in the replaced first operation data is 1 byte, the high 4 bits of each data in the replaced first operation data are used as the row index and the low 4 bits as the column index. In parallel mode, the index data of the row index and column index in the first multiplication lookup table is searched, and the data in the replaced first operation data is replaced with the index data to obtain the second index data.

[0114] Step 704: Determine the data position in the second operation data that corresponds to the specific data, and replace the data in the second index data that corresponds to the data position with the target data to obtain the nth column of mixed data.

[0115] In some embodiments, specific data is false.

[0116] In some embodiments, the target data can be predefined data, such as 0x00, or other hexadecimal data, without specific limitations.

[0117] In some embodiments, the parallel processor determines the data position in the second operational data corresponding to a specific data, and replaces the data in the second index data corresponding to the data position with the target data to obtain the nth column of mixed data. For example, both the second operational data and the second index data are 4×4 data matrices. The processor obtains the data position in the second operational data corresponding to the data being false, and replaces the data in the second index data corresponding to the data position with 0x00.

[0118] In some embodiments, after N rounds of data encryption processing, the Nth key operation data after the Nth round of key addition processing is obtained, it is determined that the multi-round encryption processing of the data to be encrypted is completed, and the Nth key operation data is determined to be sub-ciphertext data.

[0119] In this embodiment, after the parallel processor has processed the data to be encrypted through N rounds of encryption, resulting in the Nth key operation data after the Nth round of key addition, it determines that the multi-round encryption processing of the data to be encrypted is complete and identifies the Nth key operation data as sub-ciphertext data. Thus, the serial encryption processing of all data is improved into a parallel encryption processing form. In the NPU / GPU, multiple arithmetic logic units execute the encryption in parallel via multiple threads, effectively leveraging the high efficiency of the NPU / GPU for batch computing tasks with a small number of bits. Simultaneously, using NPU / GPU parallel encryption processing to encrypt and decrypt dynamic data streams in a big data environment fully utilizes the hardware computing power of the parallel processor, greatly reducing data encryption time and improving execution efficiency. Furthermore, the parallel processor's relatively specialized function provides higher security than a general-purpose CPU, enhancing the security of encrypted data.

[0120] In one feasible application scenario, since the column mixing process is the same as the reverse column mixing process, refer to... Figure 14 As shown, Figure 14 The diagram shown is a flowchart of the column-mixed / inverse-column-mixed neural network operator. Here, the column-mixed / inverse-column-mixed neural network operator will be explained.

[0121] The first step is to perform a test on the fourth state matrix and GF(2). 8 The matrix multiplication lookup table (LTABLE) is used to perform a gather vector indexing to obtain the first index matrix.

[0122] The fourth state matrix here refers to the row shift data in any iteration of the loop iteration process. Here, the first index matrix corresponds to the first index data mentioned above.

[0123] The second step is to compare the column mixing coefficient matrix / inverse column mixing coefficient matrix with GF(2). 8 The matrix multiplication lookup table (LTABLE) is used to gather vector indexes to obtain the coefficient index matrix.

[0124] Here, the column mixed coefficient matrix (POLYNOMIAL) and the inverse column mixed coefficient matrix (INVPOLYNOMIAL) are different. The column mixed coefficient matrix is ​​used during data encryption, while the inverse column mixed coefficient matrix is ​​used during data decryption. The coefficient index matrix corresponds to the coefficient index data mentioned above.

[0125] The third step is to perform an add operation on the first index matrix and the coefficient index matrix to obtain the first operation matrix.

[0126] Here, the first operation matrix corresponds to the first operation data mentioned above.

[0127] The fourth step is to apply the WHERE condition to the first operation matrix to obtain the selected first operation matrix.

[0128] Here, the WHERE condition selection includes determining whether the data in the first operation matrix is ​​greater than a preset data threshold of 0xFF. If the data is greater than 0xFF, then data is subtracted by 0xFF, while other data remain unchanged. Here, the selected first operation matrix corresponds to the replaced first operation data mentioned above.

[0129] Fifth step, perform operations on the selected first operation matrix and GF(2) 8 The matrix multiplication lookup table (LTABLE) is used to gather vector indexes to obtain the second index matrix.

[0130] Here, the second index matrix corresponds to the second index data mentioned above.

[0131] Step 6: Perform a cast type conversion on the column mixing coefficient matrix / inverse column mixing coefficient matrix to obtain the coefficient transformation matrix.

[0132] Here, cast type conversion can be understood as converting a byte data matrix into a boolean type. Specifically, data with a byte value of 0x00 is converted to false; data with a byte value other than 0x00 is converted to true. For example, [0x11, 0x00, 0x07, 0x00] ==> [true, false, true, false].

[0133] Here, the coefficient transformation matrix corresponds to the coefficient transformation data mentioned above.

[0134] Step 7: Perform a cast type conversion on the fourth state matrix to obtain the first conversion matrix.

[0135] Here, the first transformation matrix corresponds to the first transformation data mentioned above.

[0136] Step 8: Perform a Logical AND operation on the first transformation matrix and the coefficient transformation matrix to obtain the second operation matrix.

[0137] Here, the second operation matrix corresponds to the second operation data mentioned above.

[0138] Step 9: Based on the second operation matrix, perform Where condition selection on the second index matrix to obtain the column mixed matrix.

[0139] Here, the Where condition selection includes: if the data at the corresponding position in the second operation matrix is ​​false, then the data at the corresponding position in the second index matrix is ​​0x00; if the data at other positions in the second operation matrix is ​​true, then the data at the corresponding position in the second index matrix remains unchanged. Here, the column mixing matrix corresponds to the column mixing data mentioned above.

[0140] In a feasible application scenario, the embodiments of this application combine the overall process of the data encryption algorithm. Figure 5 , Figure 8 , Figure 10 , Figure 14 as well as Figure 15 To explain, firstly, the parallel processor obtains multiple data to be encrypted corresponding to the multimedia data, and N subkeys key[1] to key[N] corresponding to the initial key key[0]. Secondly, based on the initial key key[0] and the N subkeys key[1] to key[N], the parallel processor performs parallel encryption processing on each data to be encrypted. Specifically, based on the initial key key[0] and the data to be encrypted, the initial ciphertext is obtained through the key addition operator. In the first round of data encryption, the initial ciphertext is byte-permuted through the byte substitution operator to obtain the first permuted data. Then, the first permuted data is row-shifted through the row shift operator to obtain the first row-shifted data. Further, the first row-shifted data is column-mixed through the column mixing operator to obtain the first column-mixed data. Finally, based on the first subkey key[1], the first column-mixed data is key-operated through the key addition operator to obtain the first key-operated data. Thus, the first round of encryption of the data to be encrypted is completed.

[0141] Furthermore, the first key operation data is used as the input data for the next round. After N-1 rounds of encryption processing, the N-1 key operation data is obtained.

[0142] Using the (N-1)th key operation data as the input data for the Nth round, the Nth round of data encryption is performed. The (N-1)th key operation data is byte-permuted using a byte permutation operator to obtain the Nth permuted data. Then, the Nth permuted data is row-shifted using a row shift operator to obtain the Nth row-shifted data. Further, based on the Nth subkey key[N], the Nth row-shifted data is processed using a key addition operator to obtain the Nth key operation data, which is then identified as the sub-ciphertext data corresponding to the data to be encrypted. Finally, all the sub-ciphertext data corresponding to the data to be encrypted are combined according to the grouping order of the data to be encrypted to obtain the target ciphertext data. Thus, the encryption process of the data to be encrypted is completed.

[0143] In a feasible application scenario, the embodiments of this application combine the overall process of the data decryption algorithm. Figure 5 , Figure 8 , Figure 10 , Figure 14 as well as Figure 16 To explain, firstly, the parallel processor obtains multiple sub-ciphertext data corresponding to the target ciphertext data, and N sub-keys key[1] to key[N] corresponding to the initial key key[0]. Secondly, based on the initial key key[0] and the N sub-keys key[1] to key[N], the parallel processor performs parallel decryption processing on each sub-ciphertext data. Specifically, based on the Nth sub-key key[N] and the sub-ciphertext data, the initial plaintext is obtained through the key addition operator. In the first round of data decryption, the inverse byte substitution operator is used... The initial plaintext is subjected to inverse byte permutation to obtain the first inverse permutation data; then, the first inverse permutation data is subjected to inverse shift operation by the inverse shift operator to obtain the first inverse shift data; further, the first inverse shift data is subjected to inverse column mixing operation by the inverse column mixing operator to obtain the first inverse column mixed data; finally, based on the (N-1)th subkey key[N-1], the first inverse column mixed data is subjected to key operation processing by the key addition operator to obtain the first key operation data; thus, the first round of decryption of the sub-ciphertext data is completed.

[0144] Furthermore, the first key operation data is used as the input data for the new round. After N-1 rounds of decryption, the N-1 key operation data is obtained.

[0145] Using the (N-1)th key operation data as the input data for the Nth round, the Nth round of data decryption is performed. The (N-1)th key operation data is subjected to inverse byte permutation using the inverse byte permutation operator to obtain the Nth inverse permutation data. Then, the Nth inverse permutation data is subjected to inverse shifting using the inverse shifting operator to obtain the Nth inverse shifting data. Further, based on the initial key key[0], the Nth inverse shifting data is subjected to key operation using the key addition operator to obtain the Nth key operation data, and the Nth key operation data is determined to be the sub-plaintext data (i.e., the data to be encrypted) corresponding to the sub-ciphertext data. Finally, all the sub-plaintext data corresponding to the sub-ciphertext data are combined according to the grouping order of the sub-ciphertext data to obtain the target plaintext data, i.e., multiple data to be encrypted. Thus, the decryption process of the sub-ciphertext data is completed.

[0146] It should be noted that the descriptions of the same steps and contents as in other embodiments in this embodiment can be found in the descriptions in other embodiments, and will not be repeated here.

[0147] Based on the foregoing embodiments, this application provides a data encryption device that can be used to implement... Figure 2 , Figure 4 , Figure 7 , Figure 9 , Figures 12-13 A corresponding data encryption method is provided; see [link / reference]. Figure 17 As shown, the data encryption device 17 includes:

[0148] The module 1701 is used to obtain multiple data to be encrypted corresponding to the multimedia data, and the extended key corresponding to the initial key; the extended key is a number of subkeys obtained by expanding the initial key through multiple rounds of key expansion;

[0149] Processing module 1702 is used to perform multiple rounds of encryption processing in parallel processing mode on each of the multiple data to be encrypted using an extended key, so as to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing;

[0150] The processing module 1702 is also used to combine the sub-ciphertext data corresponding to the data to be encrypted according to the grouping order of the data to be encrypted, so as to obtain the target ciphertext data.

[0151] In other embodiments of this application, the processing module 1702 is further configured to select the nth subkey corresponding to the nth round of encryption processing from the extended key; wherein 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; obtain the nth intermediate encrypted data after the nth round of encryption processing on the data to be encrypted; and in parallel processing mode, perform synchronous XOR processing on the data in the nth intermediate encrypted data and the key at the corresponding position of the nth subkey to obtain the nth key operation data after the nth round of key addition processing, so as to obtain the subciphertext data.

[0152] In other embodiments of this application, the processing module 1702 is further configured to, when performing the (n-1)th round of key addition processing on the data to be encrypted using the extended key to obtain the (n-1)th key operation data, obtain the permutation parameters corresponding to the data in the first permutation data and the (n-1)th key operation data; wherein, 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; in parallel mode, all data in the (n-1)th key operation data are synchronously replaced with the target parameters corresponding to the permutation parameters in the first permutation data to obtain the nth permutation data after the nth round of byte permutation processing, so as to obtain the sub-ciphertext data.

[0153] In other embodiments of this application, the processing module 1702 is further configured to obtain the row shift parameter corresponding to the data in the nth permutation data when the nth round of byte permutation processing is performed on the data to be encrypted using the extended key to obtain the nth permutation data; wherein 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; in parallel processing mode, the data in the nth permutation data is subjected to row shift processing according to the row shift parameter to obtain the nth row shifted data after the nth round of row shift processing, so as to obtain the sub-ciphertext data.

[0154] In other embodiments of this application, the processing module 1702 is further configured to obtain a first multiplication lookup table and a second multiplication lookup table when the data to be encrypted is subjected to the nth round of row shifting processing using the extended key to obtain the nth row shifted data; wherein 1≤n≤N-1, and n is an integer, N is the total number of rounds of encryption processing, and the first multiplication lookup table and the second multiplication lookup table are different; in parallel mode, the data in the nth row shifted data is synchronized with the first multiplication lookup table to obtain the first index data, and the data in the column mixed coefficient data is synchronized with the second multiplication lookup table to obtain the coefficient index data; the data in the nth row shifted data is synchronized with the type conversion to obtain the first conversion data, and the data in the column mixed coefficient data is synchronized with the type conversion to obtain the coefficient conversion data; based on the first index data, the coefficient index data, the first conversion data and the coefficient conversion data, the nth column mixed data after the nth round of column mixing processing is obtained to obtain the sub-ciphertext data.

[0155] In other embodiments of this application, the processing module 1702 is further configured to perform synchronous addition operations on the data in the first index data and the data in the coefficient index data to obtain the first operational data, and to perform a logical AND operation on the first transformed data and the coefficient transformed data to obtain the second operational data; if there is a portion of the data in the first operational data that is greater than a preset data threshold, obtain the difference between the portion of the data and the preset data threshold, and replace the portion of the data in the first operational data with the difference; obtain a third multiplication lookup table, and in parallel mode, perform synchronous vector indexing on the data in the replaced first operational data based on the third multiplication lookup table to obtain the second index data; determine the data position in the second operational data that corresponds to a specific data, and replace the data in the second index data that corresponds to the data position with the target data to obtain the nth column of mixed data.

[0156] In other embodiments of this application, the processing module 1702 is further configured to determine that the multi-round encryption processing of the data to be encrypted is completed after obtaining the Nth key operation data after the Nth round of key addition processing, and to determine that the Nth key operation data is sub-ciphertext data.

[0157] Based on the foregoing embodiments, this application provides an electronic device that can be used to implement... Figure 2 , Figure 4 , Figure 7 , Figure 9 , Figures 12-13 A corresponding data encryption method is provided; see [link / reference]. Figure 18 As shown, the electronic device 18 ( Figure 18 Electronic device 18 in the middle corresponds to Figure 17 The data encryption device 17 in the device includes: a memory 1801 and a parallel processor 1802, wherein the parallel processor 1802 is used to execute the data encryption program stored in the memory 1801, and the electronic device 18 uses the parallel processor 1802 to implement the following steps:

[0158] Obtain multiple data to be encrypted corresponding to the multimedia data, and the extended key corresponding to the initial key; the extended key is a set of multiple subkeys obtained by expanding the initial key through multiple rounds of key expansion;

[0159] Using an extended key, multiple rounds of encryption processing are performed on each of the multiple data to be encrypted in parallel processing mode to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing.

[0160] According to the grouping order of the data to be encrypted, the corresponding sub-ciphertext data are combined to obtain the target ciphertext data.

[0161] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0162] Select the nth subkey corresponding to the nth round of encryption from the extended key; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption; obtain the nth intermediate encrypted data after the nth round of encryption processing on the data to be encrypted; in parallel processing mode, perform synchronous XOR processing on the data in the nth intermediate encrypted data and the key at the corresponding position of the nth subkey to obtain the nth key operation data after the nth round of key addition processing, so as to obtain the subciphertext data.

[0163] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0164] When the extended key is used to perform the (n-1)th round of key addition on the data to be encrypted to obtain the (n-1)th key operation data, the permutation parameters corresponding to the data in the first permutation data and the (n-1)th key operation data are obtained; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; in parallel mode, all data in the (n-1)th key operation data are synchronously replaced with the target parameters corresponding to the permutation parameters in the first permutation data to obtain the nth permutation data after the nth round of byte permutation processing, so as to obtain the sub-ciphertext data.

[0165] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0166] When performing the nth round of byte permutation on the data to be encrypted using the extended key to obtain the nth permuted data, the row shift parameter corresponding to the data in the nth permuted data is obtained; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; in parallel processing mode, the data in the nth permuted data is row shifted according to the row shift parameter to obtain the nth row shifted data after the nth round of row shifting processing, so as to obtain the sub-ciphertext data.

[0167] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0168] When the extended key is used to perform the nth round of row shifting on the data to be encrypted, resulting in the nth row of shifted data, a first multiplication lookup table and a second multiplication lookup table are obtained; where 1≤n≤N-1, and n is an integer, and N is the total number of rounds of encryption processing. The first multiplication lookup table and the second multiplication lookup table are different. In parallel mode, the data in the nth row of shifted data is synchronized using the first multiplication lookup table to obtain the first index data, and the data in the column mixed coefficient data is synchronized using the second multiplication lookup table to obtain the coefficient index data. The data in the nth row of shifted data is synchronized using the first type conversion to obtain the first conversion data, and the data in the column mixed coefficient data is synchronized using the second type conversion to obtain the coefficient conversion data. Based on the first index data, the coefficient index data, the first conversion data, and the coefficient conversion data, the nth column mixed data after the nth round of column mixing processing is obtained, thus obtaining the sub-ciphertext data.

[0169] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0170] The data in the first index data and the data in the coefficient index data are synchronously added to obtain the first operational data. The first transformed data and the coefficient transformed data are then logically ANDed to obtain the second operational data. If there is a portion of the first operational data that is greater than a preset data threshold, the difference between the portion of the data and the preset data threshold is obtained, and the portion of the first operational data is replaced with the difference. A third multiplication lookup table is obtained, and in parallel mode, the data in the replaced first operational data is synchronously vector-indexed based on the third multiplication lookup table to obtain the second index data. The data position in the second operational data that corresponds to a specific data is determined, and the data in the second index data that corresponds to the data position is replaced with the target data to obtain the nth column of mixed data.

[0171] In other embodiments of this application, the parallel processor 1802 is used to execute a data encryption program stored in the memory 1801 to perform the following steps:

[0172] Given the Nth key operation data after the Nth round of key addition, it is determined that the multi-round encryption process of the data to be encrypted is complete, and the Nth key operation data is determined to be the sub-ciphertext data.

[0173] This application provides a storage medium storing one or more programs that can be executed by one or more processors. The programs obtain multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to an initial key. The extended key is a set of subkeys obtained by expanding the initial key through multiple rounds. Using the extended key, multiple rounds of encryption processing are performed on each of the multiple data to be encrypted in parallel processing mode to obtain sub-ciphertext data corresponding to each data to be encrypted. The encryption processing includes key addition, byte substitution, row shifting, and column mixing. The subkeys are then processed according to the grouping order of the data to be encrypted. The application combines the sub-ciphertext data to obtain the target ciphertext data. In other words, it uses an initial key and an extended key to perform multiple rounds of parallel encryption processing on each piece of data to be encrypted, achieving parallel processing of large amounts of data. This fully utilizes the hardware computing power of the parallel processor, greatly reducing data encryption time and improving execution efficiency. At the same time, the parallel processor has a relatively specialized function and is more secure than a general-purpose CPU, thus improving the security of the encrypted data. Finally, the multiple sub-ciphertext data are recombine to obtain the target ciphertext data, enabling efficient encryption during the data encryption process. Furthermore, the use of a parallel processor releases CPU memory resources and reduces the CPU's computational burden.

[0174] It should be noted that the aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; it can also be various terminals that include one or any combination of the above-mentioned memory, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0175] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0176] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0177] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing module, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0178] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0179] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0180] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data encryption method, characterized in that, The method includes: Obtain multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to the initial key; the extended key is a plurality of subkeys obtained by performing multiple rounds of key expansion on the initial key; Using the extended key, each of the plurality of data to be encrypted is subjected to multiple rounds of encryption processing in parallel processing mode to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing. According to the grouping order of the data to be encrypted, the sub-ciphertext data corresponding to the data to be encrypted are combined to obtain the target ciphertext data; The step of using the extended key to perform multiple rounds of encryption processing on each of the plurality of data to be encrypted in parallel processing mode to obtain sub-ciphertext data corresponding to each data to be encrypted includes: When the data to be encrypted is subjected to the nth round of row shifting using the extended key to obtain the nth row shifted data, a first multiplication lookup table, a second multiplication lookup table, and column mixed coefficient data are obtained; where 1≤n≤N-1, and n is an integer, N is the total number of rounds of encryption processing, and the first multiplication lookup table and the second multiplication lookup table are different; In the parallel processing mode, the data in the nth row of shifted data is synchronously vector-indexed based on the first multiplication lookup table to obtain the first index data, and the data in the column mixed coefficient data is synchronously vector-indexed based on the second multiplication lookup table to obtain the coefficient index data; The data in the nth row of shifted data is synchronously converted to obtain first converted data, and the data in the column mixed coefficient data is synchronously converted to obtain coefficient converted data. The data in the first index data and the data in the coefficient index data are added synchronously to obtain the first operation data, and the first conversion data and the coefficient conversion data are logically ANDed to obtain the second operation data. Obtain the third multiplication lookup table, and in the parallel processing mode, perform synchronous vector indexing on the data in the first operation data based on the third multiplication lookup table to obtain the second index data; Determine the data position in the second operational data that corresponds to a specific data, and replace the data in the second index data that corresponds to the data position with the target data to obtain the nth column of mixed data.

2. The data encryption method according to claim 1, characterized in that, The step involves using the extended key to perform multiple rounds of encryption processing on each of the plurality of data to be encrypted in parallel processing mode, obtaining sub-ciphertext data corresponding to each data to be encrypted, including: Select the nth subkey corresponding to the nth round of encryption from the extended key; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption. Obtain the nth intermediate encrypted data after the nth round of encryption processing on the data to be encrypted; In the parallel processing mode, the data in the nth intermediate encrypted data and the key at the corresponding position of the nth subkey are synchronously XORed to obtain the nth key operation data after the nth round of key addition processing, so as to obtain the subciphertext data.

3. The data encryption method according to claim 1, characterized in that, The step involves using the extended key to perform multiple rounds of encryption processing on each of the plurality of data to be encrypted in parallel processing mode, obtaining sub-ciphertext data corresponding to each data to be encrypted, including: When the extended key is used to perform the (n-1)th round of key addition on the data to be encrypted to obtain the (n-1)th key operation data, the permutation parameters corresponding to the data in the first permutation data and the (n-1)th key operation data are obtained; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; In the parallel processing mode, all data in the (n-1)th key operation data are synchronously replaced with the target parameter corresponding to the permutation parameter in the first permutation data to obtain the nth permutation data after the nth round of byte permutation processing, so as to obtain the sub-ciphertext data.

4. The data encryption method according to claim 1, characterized in that, The step involves using the extended key to perform multiple rounds of encryption processing on each of the plurality of data to be encrypted in parallel processing mode, obtaining sub-ciphertext data corresponding to each data to be encrypted, including: When the data to be encrypted is subjected to the nth round of byte permutation using the extended key to obtain the nth permuted data, the row shift parameter corresponding to the data in the nth permuted data is obtained; where 1≤n≤N, and n is an integer, and N is the total number of rounds of encryption processing; In the parallel processing mode, the data in the nth permutation data is subjected to row shifting processing according to the row shifting parameters to obtain the nth row shifted data after the nth round of row shifting processing, so as to obtain the sub-ciphertext data.

5. The data encryption method according to claim 1, characterized in that, Before performing synchronous vector indexing on the data in the first operational data based on the third multiplication lookup table to obtain the second index data, the method includes: If there is a portion of the first operational data that is greater than a preset data threshold, the difference between the portion of the data and the preset data threshold is obtained, and the portion of the first operational data is replaced with the difference, so that the replaced first operational data is used as the first operational data.

6. The data encryption method according to any one of claims 1 to 5, characterized in that, The method further includes: Given the Nth key operation data after the Nth round of key addition processing, it is determined that the multi-round encryption processing of the data to be encrypted is completed, and the Nth key operation data is determined to be the sub-ciphertext data.

7. A data encryption device, characterized in that, The device includes: The acquisition module is used to acquire multiple data to be encrypted corresponding to multimedia data, and an extended key corresponding to the initial key; the extended key is a plurality of subkeys obtained by performing multiple rounds of key expansion on the initial key; The processing module is used to perform multiple rounds of encryption processing in parallel processing mode on each of the plurality of data to be encrypted using the extended key, so as to obtain the sub-ciphertext data corresponding to each data to be encrypted; the encryption processing includes key addition processing, byte substitution processing, row shifting processing and column mixing processing; The processing module is further configured to combine the sub-ciphertext data corresponding to the data to be encrypted according to the grouping order of the data to be encrypted, so as to obtain the target ciphertext data; The processing module is further configured to, when performing the nth round of row shifting processing on the data to be encrypted using the extended key to obtain the nth row shifted data, obtain a first multiplication lookup table, a second multiplication lookup table, and column mixed coefficient data; wherein, 1≤n≤N-1, and n is an integer, N is the total number of rounds of encryption processing, and the first multiplication lookup table and the second multiplication lookup table are different; In the parallel processing mode, the data in the nth row of shifted data is synchronously vector-indexed based on the first multiplication lookup table to obtain first index data, and the data in the column mixed coefficient data is synchronously vector-indexed based on the second multiplication lookup table to obtain coefficient index data; the data in the nth row of shifted data is synchronously type-converted to obtain first converted data, and the data in the column mixed coefficient data is synchronously type-converted to obtain coefficient converted data; the data in the first index data and the data in the coefficient index data are synchronously added to obtain first operational data, and the first converted data and the coefficient converted data are logically ANDed to obtain second operational data; Obtain the third multiplication lookup table, and in the parallel processing mode, perform synchronous vector indexing on the data in the first operation data based on the third multiplication lookup table to obtain the second index data; Determine the data position in the second operational data that corresponds to a specific data, and replace the data in the second index data that corresponds to the data position with the target data to obtain the nth column of mixed data.

8. An electronic device, characterized in that, The electronic device includes: Memory, used to store executable instructions; A parallel processor, when executing executable instructions stored in the memory, implements the data encryption method according to any one of claims 1 to 6.

9. A computer storage medium, characterized in that, The computer storage medium stores one or more programs, which can be executed by one or more processors to implement the data encryption method as described in any one of claims 1 to 6.

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