Control integrated circuit, television receiver and method

Abstract

The present disclosure relates to control integrated circuits, television receivers, and methods. The present invention provides a control integrated circuit, a related television receiver, and a method for maintaining control of video output to a conditional access module by reference clock regeneration. The control integrated circuit can include an input control circuit, a frame processing circuit, a clock control circuit, and an output control circuit. The input control circuit receives a transport stream (TS) data signal from a demodulator circuit, the frame processing circuit performs frame processing operations on the TS data signal to prepare a plurality of frames, the clock control circuit generates a second reference clock signal from a TS active signal as a substitute for a first reference clock signal, and the output control circuit outputs the plurality of frames to the conditional access module in accordance with the second reference clock signal to allow the conditional access module to perform conditional access control for the television receiver.

Description

Technical Field

[0001] This invention relates to digital television, and more particularly to a control integrated circuit for maintaining video output of a Conditional Access Module (CAM) by means of regenerating a reference clock, a related television receiver, and a related method. Background Technology

[0002] According to relevant technologies, Digital Video Broadcasting (DVB) television receivers can use conditional access modules to decrypt program information. These conditional access modules can be any product from multiple manufacturers, offering various decryption algorithm options. However, some problems may arise. For example, the demodulator in the DVB television receiver may generate a set of output signals representing the demodulation result. The DVB television receiver can output this set of signals to the conditional access module to attempt to decrypt the program information. However, the clock signal in this set of signals may be a high-speed clock signal with a fixed frequency. In particular, the frequency of this high-speed clock signal may be much higher than the data rate of the data signals in this set of signals. This could cause malfunctions in the conditional access module, resulting in abnormal display images output by the DVB television receiver (e.g., pixelation). Therefore, a novel method and related architecture are needed to achieve a television receiver with reliable control with little or no side effects. Summary of the Invention

[0003] One object of the present invention is to provide a control integrated circuit, a related television receiver, and a related method for maintaining video output of a conditional access module by means of regenerating a reference clock, in order to solve the above-mentioned problems.

[0004] Another object of the present invention is to provide a control integrated circuit, a related television receiver, and a related method for maintaining the video output of a conditional access module by means of a reference clock regeneration, so as to ensure the normal operation of the television receiver.

[0005] At least one embodiment of the present invention provides a control integrated circuit for maintaining video output to a conditional access module by means of a reference clock regeneration, wherein the control integrated circuit is disposed in a television receiver. The control integrated circuit may include: an input control circuit; a frame processing circuit coupled to the input control circuit; a clock control circuit; and an output control circuit coupled to the frame processing circuit and the clock control circuit. For example, the input control circuit can be used to receive a first transport stream (TS) data signal from the demodulator circuit in the television receiver, wherein the first transport stream data signal carries at least video data; the frame processing circuit can be used to perform frame processing operations on the first transport stream data signal according to a predetermined frame size to prepare multiple frames corresponding to the first transport stream data signal; the clock control circuit can be used to receive a first transport stream valid (TS valid) signal from the demodulator circuit, and generate a second reference clock signal based on the first transport stream valid signal as a replacement for the first reference clock signal generated by the demodulator circuit; and the output control circuit can be used to output the multiple frames to the conditional access module according to the second reference clock signal, so as to allow the conditional access module to perform conditional access for the television receiver. Access (CA) control, wherein the output control circuit outputs the second reference clock signal to the conditional access module, so that the conditional access module receives the plurality of frames based on the second reference clock signal instead of the first reference clock signal.

[0006] According to some embodiments, the present invention further provides a television receiver including the aforementioned control integrated circuit, wherein the television receiver may include a tuner circuit and a demodulator circuit. For example, the tuner circuit may be used to perform a tuning operation based on at least one radio frequency signal to generate at least one modulated signal, wherein the at least one radio frequency signal is received through the antenna of the television receiver; and the demodulator circuit may be used to perform a demodulator operation on the at least one radio frequency signal to generate the first transmission stream.

[0007] At least one embodiment of the present invention provides a method for maintaining video output to a conditional access module by means of regenerating a reference clock, wherein the method is applicable to a control integrated circuit disposed in a television receiver. The method may include: receiving a first transmission stream data signal of a first transmission stream from a demodulator circuit in a television receiver using an input control circuit in the control integrated circuit, wherein the first transmission stream data signal carries at least video data; performing frame processing operations on the first transmission stream data signal according to a predetermined frame size using a frame processing circuit in the control integrated circuit to prepare a plurality of frames corresponding to the first transmission stream data signal; receiving a first transmission stream valid signal of the first transmission stream from the demodulator circuit using a clock control circuit in the control integrated circuit, and generating a second reference clock signal according to the first transmission stream valid signal as a substitute for the first reference clock signal generated by the demodulator circuit; and outputting the plurality of frames to a conditional access module according to the second reference clock signal using an output control circuit in the control integrated circuit, thereby allowing the conditional access module to perform conditional access control for the television receiver, wherein the output control circuit outputs the second reference clock signal to the conditional access module so that the conditional access module receives the plurality of frames according to the second reference clock signal instead of the first reference clock signal.

[0008] One advantage of this invention is that, through a carefully designed control mechanism, the control integrated circuit, television receiver, and method of this invention can dynamically generate a correct reference clock (e.g., the second reference clock signal), regardless of whether the first reference clock signal generated by the demodulator circuit is appropriate. Compared to related technologies, the control integrated circuit and method of this invention can realize a television receiver with robust control without side effects or with a low likelihood of side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a control integrated circuit for maintaining video output to a conditional access module by means of a reference clock regeneration, according to an embodiment of the present invention. The conditional access module and the demodulator circuit in a television receiver containing the control integrated circuit are also shown. Figure 1 This is for ease of understanding.

[0010] Figure 2 Illustration according to an embodiment of the present invention Figure 1 Some implementation details of the architecture shown.

[0011] Figure 3This is a schematic diagram of a control integrated circuit for maintaining the video output of the conditional access module by means of a reference clock regeneration, according to another embodiment of the present invention, wherein compared to Figure 1 As shown in the architecture, the demodulator circuit can be integrated into the control integrated circuit in this embodiment.

[0012] Figure 4 Illustration according to an embodiment of the present invention Figure 3 Some implementation details of the architecture shown.

[0013] Figure 5 Illustration according to an embodiment of the present invention Figure 1 Some implementation details of the transmission rate detection circuit shown.

[0014] Figure 6 A flowchart illustrating a method for maintaining video output to a conditional access module by means of regenerating a reference clock, according to an embodiment of the present invention, is shown, wherein the method can be applied to Figure 1 and Figure 3 Each of the control integrated circuits shown is a control integrated circuit and Figure 2 and Figure 4 Any of the television receivers shown.

[0015] Figure 7 The first partial workflow of the method is illustrated according to an embodiment of the present invention.

[0016] Figure 8 The second part of the workflow of this method is illustrated. Detailed Implementation

[0017] Figure 1 This is a schematic diagram of an integrated circuit (IC) 100 for maintaining video output to a Conditional Access Module (CAM) 10C by means of a reference clock regeneration, according to an embodiment of the present invention. The CAM 10C and a demodulator circuit 10D in a television receiver 10 containing the control IC 100 are also shown. Figure 1For ease of understanding, the control IC 100 located in the television receiver 10 may include multiple components, such as the transmission stream processing module 100F, etc. The transmission stream processing module 100F may include an input control circuit 110, a frame processing circuit 120, an output control circuit 130, and a clock control circuit 140. The frame processing circuit 120 may include a framer 122, a direct memory access (DMA) circuit 124, and a random access memory (RAM) 126. The clock control circuit 140 may include a rate detection circuit 142 and a phase-locked loop (PLL) 144.

[0018] The input control circuit 110 can receive the transport stream data signal TS1_data of the transport stream TS1 from the demodulator circuit 10D for further processing, wherein the transport stream data signal TS1_data carries at least video data, but the invention is not limited thereto. For example, the transport stream TS1 may conform to at least one standard of the Moving Picture Experts Group (MPEG), in particular, it may conform to the format of the MPEG-2 transport stream (MPEG2-TS), and the transport stream data signal TS1_data may also carry audio data. In addition, the frame processing circuit 120 may perform frame processing operations on the transport stream data signal TS1_data according to a predetermined frame size PFS (e.g., 188 bytes) to prepare multiple frames corresponding to the transport stream data signal TS1_data. For example, framer 122 can obtain the plurality of frames from the transmission stream data signal TS1_data at least according to a predetermined frame size PFS, such as 188 bytes, and in particular, identify one frame from each 188-byte segment of the transmission stream data signal TS1_data. RAM 126 can temporarily store the plurality of frames, and DMA circuit 124 can access the plurality of frames, in particular, write the plurality of frames obtained by framer 122 into RAM 126.

[0019] like Figure 1As shown, the clock control circuit 140 receives the valid transmission stream signal TS1_valid from the demodulator circuit 10D, and generates a reference clock signal TS2_clk based on the valid transmission stream signal TS1_valid, as an alternative clock to the reference clock signal TS1_clk generated by the demodulator circuit 10D. For example, the transmission rate detection circuit 142 can detect the frequency of a predetermined waveform (e.g., rising / falling edges) on the valid transmission stream signal TS1_valid to generate an intermediate clock signal, such as a clock signal CLK0, and the PLL 144 can perform a phase-locked operation based on this intermediate clock signal, such as the clock signal CLK0, to generate the reference clock signal TS2_clk. Furthermore, the output control circuit 130 can output the multiple frames to the CAM 10C according to the reference clock signal TS2_clk, so as to allow the CAM 10C to perform conditional access (CA) control for the television receiver 10. The output control circuit 130 can output the reference clock signal TS2_clk to the CAM 10C so that the CAM 10C receives the multiple frames according to the reference clock signal TS2_clk instead of the reference clock signal TS1_clk.

[0020] According to this embodiment, the demodulator circuit 10D is located outside the control IC 100. Specifically, the control IC 100 may further include an input port P_In and an output port P_Out. The input port P_In can be used to receive a plurality of first transmission stream signals of transmission stream TS1 from the demodulator circuit 10D, wherein the plurality of first transmission stream signals include a transmission stream valid signal TS1_valid, a reference clock signal TS1_clk, a synchronization signal TS1_sync, and a transmission stream data signal TS1_data. The output port P_Out can be used to output a plurality of second transmission stream signals corresponding to transmission stream TS2 of transmission stream TS1 to the CAM 10C, wherein the plurality of second transmission stream signals include a transmission stream valid signal TS2_valid, a reference clock signal TS2_clk, a synchronization signal TS2_sync, and a transmission stream data signal TS2_data. The control IC 100 can output the plurality of frames to the CAM 10C through the transmission stream data signal TS2_data.

[0021] based on Figure 1The architecture shown allows the control IC 100 to dynamically generate a correct reference clock, such as the reference clock signal TS2_clk, regardless of whether the reference clock signal TS1_clk generated by the demodulator circuit 10D is appropriate. For example, when the frequency of the reference clock signal TS1_clk is much higher than the data rate of the transmitted streaming data signal TS1_data, the control IC 100 of this invention can avoid problems in related technologies, such as any errors caused by the reference clock signal TS1_clk, abnormal display issues, and CAM product compatibility problems.

[0022] For ease of understanding, the television receiver 10 may be a DVB television receiver, and the CAM 10C may be used to perform video decryption for the television receiver 10, so that the television receiver 10 can obtain the decrypted video data if the video data contains encrypted video data. The connection and interaction between the control IC 100 and the CAM 10C may conform to the DVB Common Interface (CI) standard, but the present invention is not limited thereto.

[0023] Figure 2 Illustration according to an embodiment of the present invention Figure 1 Some implementation details of the architecture shown. For example... Figure 2 As shown, the control IC 100 may include multiple transmission stream processing modules such as transmission stream processing modules 100F and 100G (labeled as "TS processing modules" in the figure for simplicity) and decoder circuitry 10DEC. For example, the architecture of transmission stream processing module 100G may be the same as that of transmission stream processing module 100F, but the invention is not limited thereto. In some examples, the architecture of transmission stream processing module 100G may be similar to that of transmission stream processing module 100F.

[0024] The control IC 100 can use the output control circuit 130 to output the multiple frames to the CAM 10C according to the reference clock signal TS2_clk, so as to allow multiple stages of circuitry in the data processing path of the television receiver 10 to perform data processing to generate display data for display. For example, such as Figure 2As shown, the multi-stage circuit may include a tuner circuit 10T, a demodulator circuit 10D, a transmission stream processing module 100F, a CAM 10C, a transmission stream processing module 100G, and a decoder circuit 10DEC. The demodulator circuit 10D is the preceding stage circuit of the transmission stream processing module 100F, the CAM 10C is the following stage circuit of the transmission stream processing module 100F, the transmission stream processing module 100G is the following stage circuit of the CAM 10C, and the decoder circuit 10DEC is the following stage circuit of the transmission stream processing module 100G.

[0025] The tuner circuit 10T can perform a tuning operation based on at least one radio frequency signal to generate at least one modulated signal, wherein the at least one radio frequency signal is received through the antenna 10A of the television receiver 10. The demodulator circuit 10D can perform a demodulation operation on the at least one radio frequency signal to generate a transmission stream TS1. Additionally, the display data is decoded display data generated by the decoder circuit 10DEC. For the sake of simplicity, similar details are not repeated here in this embodiment.

[0026] Figure 3 This is a schematic diagram of a control IC for maintaining video output to a CAM10C by means of a reference clock regeneration, according to another embodiment of the present invention, wherein compared to Figure 1 In the architecture shown, the demodulator circuit 10D can be integrated into the control IC in this embodiment. Due to the change in architecture, the control IC and the television receiver in this embodiment can be referred to as control IC 200 and television receiver 20, respectively, wherein the demodulator circuit 10D is built into control IC 200. For the sake of simplicity, similar details will not be repeated here.

[0027] Figure 4 Illustration according to an embodiment of the present invention Figure 3 Some implementation details of the architecture shown. For example... Figure 4 As shown, the control IC 200 may include a demodulator circuit 10D, a transmission stream processing module 100F and 100G (labeled "TS processing module" for simplicity), and a decoder circuit 10DEC. For the sake of simplicity, similar contents will not be repeated here in this embodiment.

[0028] Figure 5 Illustration based on an embodiment of the present invention Figure 1The following are some implementation details of the transmission rate detection circuit 142. The transmission rate detection circuit 142 may include logic circuitry 142L, counter 142C, and register 142R. Logic circuitry 142L controls the operation of transmission rate detection circuitry 142, counter 142C counts to generate at least one count value (e.g., one or more count values), such as count value CNT, and register 142R temporarily stores count value CNT. For example, logic circuitry 142L may control the counting operation of counter 142C to obtain count value CNT based on the transmission stream valid signal TS1_valid, set at least one parameter (e.g., rate_CNT) based on count value CNT, and generate clock signal CLK0 based on clock signal TP_CLK based on the at least one parameter, but the invention is not limited thereto.

[0029] Figure 6 A flowchart illustrating a method for maintaining video output to a conditional access module by means of regenerating a reference clock, according to an embodiment of the present invention, is shown, wherein the method can be applied to Figure 1 and Figure 3 The control ICs 100 and 200 shown respectively, and either of the control integrated circuits, and Figure 2 and Figure 4 Either of the television receivers 10 and 20 shown respectively. For example, the control IC 100 (or 200) can perform parallel processing, in particular, the operations of steps S10 and S20 are performed in parallel. Furthermore, under the control of the control IC 100 (or 200), the television receiver 10 (or 20) can utilize the multi-stage circuitry such as the tuner circuit 10T, demodulator circuit 10D, transmission stream processing module 100F, CAM 10C, transmission stream processing module 100G, and decoder circuit 10DEC to process data to generate display data for display.

[0030] In step S10, the control IC 100 (or 200) can use the transmission stream processing module 100F to perform transmission stream processing (labeled "TS processing" for simplicity). Step S10 may include multiple sub-steps, such as steps S11 to S13.

[0031] In step S11, the control IC 100 (or 200) may use the input control circuit 110 to receive the transmission stream data signal TS1_data of the transmission stream TS1 from the demodulator circuit 10D for further processing, wherein the transmission stream data signal TS1_data carries at least video data.

[0032] In step S12, the control IC 100 (or 200) may use the frame processing circuit 120 to perform frame processing operations on the transmission stream data signal TS1_data according to a predetermined frame size PFS (e.g., 188 bits) to prepare multiple frames corresponding to the transmission stream data signal TS1_data.

[0033] In step S13, the control IC 100 (or 200) can use the output control circuit 130 to output the multiple frames to the CAM 10C according to the reference clock signal TS2_clk, so as to allow the CAM 10C to perform the CA control for the TV receiver 10 (or 20). The output control circuit 130 outputs the reference clock signal TS2_clk to the CAM 10C so that the CAM 10C receives the multiple frames according to the reference clock signal TS2_clk instead of the reference clock signal TS1_clk.

[0034] In step S20, the control IC 100 (or 200) can use the clock control circuit 140 to receive the transmission stream valid signal TS1_valid of the transmission stream TS1 from the demodulator circuit 10D, and generate a reference clock signal TS2_clk based on the transmission stream valid signal TS1_valid, as a substitute clock for the reference clock signal TS1_clk generated by the demodulator circuit 10D.

[0035] The control IC 100 (or 200) operating according to this method can dynamically generate a correct reference clock, such as the reference clock signal TS2_clk, regardless of whether the reference clock signal TS1_clk generated by the demodulator circuit 10D is appropriate. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0036] To better understand, this method is available Figure 6 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 6 Add, delete, or modify within the workflow shown.

[0037] Figure 7 and Figure 8 According to an embodiment of the present invention, a first partial process and a second partial process in the workflow of the method are respectively illustrated, wherein nodes A and B can indicate the connection between the first partial process and the second partial process.

[0038] In step S30, the transmission stream processing module 100F can receive the transmission stream TS1 from the demodulator circuit 10D using the input control circuit 110, and monitor the transmission stream TS1 (e.g., the transmission stream valid signal TS1_valid) using the transmission rate detection circuit 142 (e.g., logic circuit 142L).

[0039] In step S31, when the rising edge of the valid transmission stream signal TS1_valid is detected, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can enable the counter 142C to start counting.

[0040] In step S32, the transmission rate detection circuit 142 (e.g., logic circuit 142L) may use counter 142C to count and generate a latest count value, such as count value CNT, for storage in register 142R. For example, counter 142C may count according to clock signal TP_CLK, such as the counting operation described above, in particular counting the cycles of pulses on clock signal TP_CLK in an increment, such as one, starting from an initial value such as zero.

[0041] For ease of understanding, the frequency TP_CLK_f of the clock signal TP_CLK (e.g., 250 MHz) is typically greater than the frequency TS1_valid_f of the valid transmission stream signal TS1_valid (e.g., when the valid transmission stream signal TS1_valid is active), such as the frequency at which two consecutive rising edges occur on the valid transmission stream signal TS1_valid, and in particular, may be greater than the frequency TS1_clk_f of the reference clock signal TS1_clk (not shown in the figures), but the invention is not limited thereto. For example, the valid transmission stream signal TS1_valid may be inactive in certain time intervals and therefore cannot be directly used as the aforementioned clock signal CLK0.

[0042] In step S33, the transmission rate detection circuit 142 (e.g., logic circuit 142L) checks whether the next rising edge of the transmission stream valid signal TS1_valid is detected. If yes, proceed to step S34; if no, proceed to step S32 to continue counting using counter 142C.

[0043] In step S34, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can stop the counter 142C from counting and calculate the latest count value, such as the count value CNT, as a ratio of the number of bits (PFS*8) of a frame of the transmission stream data signal TS1_data in the transmission stream TS1 to the rate_CNT. In particular, the rate_CNT is calculated based on the latest count value CNT and the predetermined frame size PFS (e.g., 188 bits), as follows:

[0044] Rate_CNT = (CNT / (PFS * 8)); or

[0045] Rate_CNT=(CNT / (188*8))=(CNT / 1504), if PFS=188;

[0046] The Rate_CNT can indicate the measurement result obtained by measuring the transmission stream TS1 using the cycle of the clock signal TP_CLK, such as the cycle count per bit of the transmission stream data signal TS1_data, but the present invention is not limited thereto.

[0047] In step S35, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can calculate a temporary value of the frequency TS2_clk_f (not shown in the figure) of the reference clock signal TS2_clk based on the frequency TP_CLK_f of the clock signal TP_CLK and the ratio Rate_CNT, as shown below:

[0048] TS2_clk_f=(TP_CLK_f / Rate_CNT);

[0049] The transmission rate detection circuit 142 (e.g., logic circuit 142L) can determine whether the frequency TS2_clk_f of the reference clock signal TS2_clk is equal to the temporary value such as (TP_CLK_f / Rate_CNT) and / or whether further adjustment of the frequency TS2_clk_f is needed, based on whether the transmission streams TS1 and TS2 are transmitted in the same transmission mode (e.g., parallel transmission mode or serial transmission mode).

[0050] For ease of understanding, assume that the transmission stream TS2 is transmitted in a parallel transmission mode (rather than a sequential transmission mode). The transmission rate detection circuit 142 (e.g., logic circuit 142L) can determine whether the transmission streams TS1 and TS2 are transmitted in the same transmission mode, and in particular, whether the transmission stream TS1 is transmitted in a sequential transmission mode, in order to determine whether the frequency TS2_clk_f of the reference clock signal TS2_clk needs to be further adjusted.

[0051] In step S36, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can determine whether the transmission stream TS1 is transmitted in a sequential transmission mode. If yes, proceed to step S37; if no, proceed to step S38.

[0052] In step S37, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can calculate (e.g., update) the frequency TS2_clk_f of the reference clock signal TS2_clk according to a predetermined ratio (e.g., 8), as follows:

[0053] TS2_clk_f / =8;

[0054] The symbol " / =" represents division assignment.

[0055] In step S38, the transmission rate detection circuit 142 (e.g., logic circuit 142L) can set the frequency of the clock signal CLK0 to the frequency TS2_clk_f to generate the clock signal CLK0. For example, the generation of the clock signal CLK0 can be achieved by clock gating or other methods, but the present invention is not limited thereto. In addition, the clock control circuit 140 can use the phase-locked loop 144 to perform a phase-locking operation based on the output clock signal CLK0 to generate the reference clock signal TS2_clk.

[0056] In step S39, the transmission stream processing module 100F can use the output control circuit 130 to output the plurality of frames in RAM 126 to CAM 10C according to the reference clock signal TS2_clk (e.g., its frequency TS2_clk_f).

[0057] To better understand, this method is available Figure 7 and Figure 8 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 7 and Figure 8 Add, delete, or modify in the workflow shown.

[0058] According to some embodiments, each of the plurality of frames can be considered as a transmission stream packet, wherein the transmission stream packet may contain 188 bytes. The framer 122 may begin receiving data carried by the transmission stream data signal TS1_data in response to a predetermined waveform (e.g., a rising edge) on the synchronization signal TS1_sync, specifically identifying a frame from each 188-byte data segment to classify the data into the plurality of frames. Upon receiving any of the plurality of frames, the framer 122 may trigger the DMA circuit 124 to write that frame acquired by the framer 122 into RAM 126. Additionally, the control IC 100 (or 200) may utilize the transmission rate detection circuit 142 for... Figure 7 and Figure 8The illustrated workflow involves operations to determine the time required to transmit data for a frame (e.g., a streaming packet). Specifically, it calculates the actual data rate of the streaming signal TS1 (e.g., the streaming data signal TS1_data) as the frequency TS2_clk_f of the reference clock signal TS2_clk. The output control circuit 130 then outputs the plurality of frames from RAM 126 to CAM 10C according to the frequency TS2_clk_f of the reference clock signal TS2_clk. For simplicity, similar details in these embodiments are not repeated here.

[0059] In the above embodiments, the number of input / output terminals for at least one of the transmission streams TS1 and TS2 may vary depending on the transmission mode (e.g., parallel transmission mode or sequential transmission mode). For example, in a parallel transmission mode, the input / output terminals for transmission stream TS1 (or TS2) may include:

[0060] (1) Clock terminal, used for input / output of reference clock signal TS1_clk (or TS2_clk);

[0061] (2) Synchronization terminal, used for input / output of synchronization signal TS1_sync (or TS2_sync);

[0062] (3) Valid terminal, used for input / output of the stream valid signal TS1_valid (or TS2_valid); and

[0063] (4) Eight data terminals for transmitting eight bits of input / output of the streaming data signal TS1_data (or TS2_data);

[0064] The total number of the above-listed input / output terminals is eleven. Additionally, for sequential transmission mode, the input / output terminals of the transmission stream TS1 may include:

[0065] (1) Clock terminal, used for input / output of reference clock signal TS1_clk;

[0066] (2) Synchronization terminal, used for input / output of synchronization signal TS1_sync;

[0067] (3) Valid terminal, used for input / output of the stream valid signal TS1_valid; and

[0068] (4) Data terminal, used for input / output of streaming data signal TS1_data;

[0069] The total number of input / output terminals listed above is four.

[0070] According to some embodiments, RAM 126 may be implemented using dynamic random access memory (DRAM), static random access memory (SRAM), or the like. For the sake of simplicity, similar details in these embodiments will not be repeated here.

[0071] The control ICs 100 and 200, television receivers 10 and 20, and the method of the present invention can dynamically generate a correct reference clock, such as a reference clock signal TS2_clk, regardless of whether the reference clock signal TS1_clk generated by the demodulator circuit 10D is appropriate. Compared with related technologies, the control IC and method of the present invention can realize a television receiver with reliable control with little or no side effects.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0073] Symbol Explanation

[0074] 10,20: TV receiver

[0075] 10C: Conditional Access Module (CAM)

[0076] 10D: Demodulator circuit

[0077] 10DEC: Decoder Circuit

[0078] 10T: Tuner Circuit

[0079] 10A: Antenna

[0080] 100, 200: Control Integrated Circuits (ICs)

[0081] 100F, 100G: Transmission Stream (TS) Processing Module

[0082] 110: Input control circuit

[0083] 120: Frame processing circuit

[0084] 122: Framer

[0085] 124: Direct Memory Access (DMA) circuit

[0086] 126: Random Access Memory (RAM)

[0087] 130: Output control circuit

[0088] 140: Clock control circuit

[0089] 142: Transmission Rate Detection Circuit

[0090] 142C: Counter

[0091] 142L: Logic Circuits

[0092] 142R: Register

[0093] 144: Phase-locked loop (PLL)

[0094] P_In: Input port

[0095] P_Out: Output port

[0096] TS1, TS2: Transmit streaming signals

[0097] TS1_valid, TS2_valid: Valid transmission stream signals

[0098] TS1_clk, TS2_clk: Reference clock signals

[0099] TS1_sync, TS2_sync: Synchronization signals

[0100] TS1_data, TS2_data: Transmit stream data signals

[0101] CLK0, TP_CLK: Clock signals

[0102] CNT: Count value

[0103] Rate_CNT: Rate

[0104] S10~S13, S20, S30~S39: Steps

Claims

1. A control integrated circuit for maintaining video output to a conditional access module by means of a reference clock regeneration, the control integrated circuit being disposed in a television receiver, the control integrated circuit comprising: An input control circuit is used to receive a first transmission stream data signal of a first transmission stream from a demodulator circuit in the television receiver, wherein the first transmission stream data signal carries at least video data. A frame processing circuit, coupled to the input control circuit, is used to perform frame processing operations on the first transmission stream data signal according to a predetermined frame size to prepare multiple frames corresponding to the first transmission stream data signal. A clock control circuit is used to receive a first valid transmission stream signal from the demodulator circuit and generate a second reference clock signal based on the first valid transmission stream signal as a substitute for the first reference clock signal generated by the demodulator circuit. as well as An output control circuit, coupled to the frame processing circuit and the clock control circuit, is used to output the plurality of frames to the conditional access module according to the second reference clock signal, so as to allow the conditional access module to perform conditional access control for the television receiver. The output control circuit outputs the second reference clock signal to the conditional access module so that the conditional access module receives the plurality of frames according to the second reference clock signal instead of the first reference clock signal.

2. The control integrated circuit of claim 1, wherein the television receiver is a digital video broadcast television receiver, and the conditional access module is used to decrypt video for the television receiver, so as to allow the television receiver to obtain decrypted video data if the video data contains encrypted video data.

3. The control integrated circuit of claim 1, wherein the clock control circuit comprises: Transmission rate detection circuitry is used to detect the frequency of a predetermined waveform appearing on the valid signal of the first transmission stream to generate an intermediate clock signal; and A phase-locked loop, coupled to the transmission rate detection circuit, is used to perform a phase-locking operation based on the intermediate clock signal to generate the second reference clock signal.

4. The control integrated circuit of claim 1, wherein the frame processing circuit comprises: A framer is used to obtain the plurality of frames from the first transmission stream data signal at least according to the predetermined frame size; Random access memory, used to temporarily store the multiple frames; and A direct memory access circuit, coupled to the framer and the random access memory, is used to access the multiple frames.

5. The control integrated circuit as claimed in claim 1, wherein the transmission stream processing module in the control integrated circuit includes the input control circuit, the frame processing circuit, and the output control circuit; and the control integrated circuit uses the output control circuit to output the plurality of frames to the conditional access module according to the second reference clock signal, so as to allow multiple circuits on the data processing path in the television receiver to perform data processing to generate display data for display, wherein the multiple circuits include the demodulator circuit, the transmission stream processing module, and the conditional access module, the demodulator circuit is the preceding stage circuit of the transmission stream processing module, and the conditional access module is the following stage circuit of the transmission stream processing module.

6. The control integrated circuit as claimed in claim 5, wherein the multi-level circuit further includes a decoder circuit and another transmission stream processing module, the other transmission stream processing module being the next level circuit of the conditional access module, the decoder circuit being the next level circuit of the other transmission stream processing module, and the display data being decoded display data generated by the decoder circuit.

7. The control integrated circuit of claim 1, wherein the demodulator circuit is built into the control integrated circuit.

8. The control integrated circuit of claim 1, wherein the demodulator circuit is located outside the control integrated circuit; and the control integrated circuit further comprises: An input port is used to receive a plurality of first transmission stream signals from the demodulator circuit, wherein the plurality of first transmission stream signals include a first transmission stream valid signal, a first reference clock signal, a first synchronization signal, and a first transmission stream data signal; and The output port is used to output multiple second transmission stream signals corresponding to the first transmission stream to the conditional access module. The multiple second transmission stream signals include a second transmission stream valid signal, a second reference clock signal, a second synchronization signal, and a second transmission stream data signal. The control integrated circuit outputs the multiple frames to the conditional access module through the second transmission stream data signal.

9. A television receiver comprising the control integrated circuit as claimed in claim 1, wherein the television receiver comprises: A tuner circuit for tuning to generate at least one modulated signal based on at least one radio frequency signal, wherein the at least one radio frequency signal is received through the antenna of the television receiver; and The demodulator circuit is used to demodulate the at least one radio frequency signal to generate the first transmission stream.

10. A method for maintaining video output to a conditional access module by means of regenerating a reference clock, the method being applicable to a control integrated circuit disposed in a television receiver, the method comprising: The input control circuit in the control integrated circuit receives a first transmission stream data signal of a first transmission stream from the demodulator circuit in the television receiver, wherein the first transmission stream data signal carries at least video data. The frame processing circuit in the control integrated circuit performs frame processing operations on the first transmission stream data signal according to a predetermined frame size to prepare multiple frames corresponding to the first transmission stream data signal. The clock control circuit in the control integrated circuit receives a first valid transmission stream signal from the demodulator circuit, and generates a second reference clock signal based on the first valid transmission stream signal, as a replacement for the first reference clock signal generated by the demodulator circuit; and The output control circuit in the control integrated circuit outputs the plurality of frames to the conditional access module according to the second reference clock signal, so as to allow the conditional access module to perform conditional access control for the television receiver. The output control circuit outputs the second reference clock signal to the conditional access module so that the conditional access module receives the plurality of frames according to the second reference clock signal instead of the first reference clock signal.

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