Array substrate, manufacturing method thereof, display panel and display device

Abstract

An array substrate, a manufacturing method thereof, a display panel and a display device. The array substrate comprises a substrate (1), a driving circuit layer (2) arranged on one side of the substrate (1) and comprising a plurality of data lines (22) and a plurality of scan lines (21), and a metal layer (3) arranged on the side of the driving circuit layer (2) away from the substrate (1) and comprising a plurality of metal blocks (31) arranged at intervals and located at intersections of the data lines (22) and the scan lines (21), which helps to adjust the flatness at the intersections, maintain the height uniformity and the distribution stability of other structures formed at the intersections.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to an array substrate and manufacturing method, display panel and display device. BACKGROUND

[0002] A liquid crystal display (LCD) is generally formed by an array substrate and a color film substrate being opposite to each other and liquid crystal being injected between the two substrates.

[0003] In order to maintain the cell gap between the array substrate and the color film substrate, a spacer with a certain thickness is generally added between the two substrates before the two substrates are opposite to each other to maintain the cell gap. However, in the prior art, the wiring on the array substrate is complex, resulting in different heights of the spacers on the array substrate.

[0004] The above information disclosed in the background section is only intended to strengthen the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present disclosure aims to provide an array substrate and manufacturing method, display panel and display device, which helps to adjust the flatness at the intersection of data lines and scan lines.

[0006] To achieve the above-mentioned purposes, the present disclosure adopts the following technical solutions:

[0007] According to a first aspect of the present disclosure, a display panel is provided, comprising:

[0008] a substrate, comprising a display area and a peripheral area located at the periphery of the display area;

[0009] a driving circuit layer, located on one side of the substrate and in the display area, comprising a plurality of data lines and a plurality of scan lines, the plurality of data lines extending along a first direction and being arranged at intervals along a second direction, the plurality of scan lines extending along the second direction and being arranged at intervals along the first direction, the second direction and the first direction being perpendicular to each other, the data lines and the scan lines intersecting each other to define a plurality of sub-pixel areas;

[0010] a metal layer, located on the side of the driving circuit layer away from the substrate and in the display area, the metal layer comprising a plurality of metal blocks arranged at intervals, the metal blocks being located at the intersections of the data lines and the scan lines.

[0011] In an example embodiment of the present disclosure, the metal layer further comprises a plurality of touch signal lines, a projection of the touch signal lines on the substrate substrate is located outside a projection of the sub-pixel region on the substrate substrate, and the projection of the touch signal lines on the substrate substrate at least partially overlaps with the projection of the data lines on the substrate substrate.

[0012] The metal block comprises a touch connection metal block and a metal spacer block, the touch connection metal block is connected with the touch signal line, and the metal spacer block is spaced apart from the touch signal line.

[0013] In an example embodiment of the present disclosure, the array substrate further comprises:

[0014] A common electrode is arranged on a side of the driving circuit layer away from the substrate substrate, the common electrode comprises a plurality of spaced-apart touch units, and the touch unit comprises a plurality of mutually connected common electrode blocks.

[0015] A plurality of pixel electrodes are arranged on a side of the common electrode away from the substrate substrate.

[0016] The metal layer is arranged between the driving circuit layer and the common electrode, or on a side of the common electrode away from the substrate substrate.

[0017] The touch connection metal block comprises a first touch metal block and a second touch metal block, the touch signal line is connected with one of the common electrode blocks in the touch unit through the first touch metal block, and the second touch metal block is not connected with the common electrode block; and the metal spacer block is connected with the common electrode block through a via.

[0018] In an example embodiment of the present disclosure, the touch unit comprises a plurality of common electrode blocks arranged in an array, wherein at least two common electrode blocks are arranged along the first direction to form a column, and at least two common electrode blocks are arranged along the second direction to form a row.

[0019] The touch unit comprises a plurality of common electrode blocks arranged in an array, wherein at least two common electrode blocks are arranged along the first direction to form a column, and at least two common electrode blocks are arranged along the second direction to form a row.

[0020] The column connection part comprises an upper connection part connected to an upper region of the common electrode block and a lower connection part connected to a lower region of the common electrode block.

[0021] In an example embodiment of the present disclosure, the sub-pixel regions include red sub-pixel regions, green sub-pixel regions, and blue sub-pixel regions, at least one of the red sub-pixel regions, at least one of the green sub-pixel regions, and at least one of the blue sub-pixel regions are arranged along the second direction to form a pixel unit region, and one pixel unit region corresponds to one common electrode block.

[0022] A projection of the row connection portion on the substrate substrate is located between projections of two adjacent sub-pixel regions corresponding to the common electrode block on the substrate substrate.

[0023] In an example embodiment of the present disclosure, the common electrode block includes a main body and a first protruding portion and a second protruding portion connected to one side of the main body, the first protruding portion is connected to a middle portion of one side of the main body, and a projection of the first protruding portion on the substrate substrate is located between projections of two adjacent sub-pixel regions corresponding to the common electrode block on the substrate substrate, and the second protruding portion is connected to a corner of the main body.

[0024] The metal spacer block includes a first spacer block, a projection of the first spacer block on the substrate substrate at least partially overlaps the first protruding portion, and the first spacer block is connected to the first protruding portion through a via hole.

[0025] The number of the first protruding portions is plural, and when two adjacent rows of the common electrode blocks are connected, part of the first protruding portions are multiplexed as the row connection portions.

[0026] A projection of the first touch metal block on the substrate substrate at least partially overlaps a projection of the second protruding portion of one common electrode block in the touch unit on the substrate substrate, and the first touch metal block is connected to the second protruding portion through a via hole.

[0027] In an example embodiment of the present disclosure, in the second direction, projections of part of the data lines on the substrate substrate are located within a projection of the touch signal line on the substrate substrate.

[0028] In an example embodiment of the present disclosure, in the second direction, a width of the touch signal line is 5.2-6.2 μm, and a width of the data line is 2.5-3.5 μm.

[0029] In an example embodiment of the present disclosure, the metal spacer block comprises a first side, a second side and a third side connected in sequence, the second side and the third side are located on one side of the first side along the first direction and are parallel to the first side, the distance between the second side and the first side is greater than the distance between the third side and the first side, and the orthogonal projection of the connecting via of the metal spacer block and the common electrode block on the substrate substrate is located between the orthogonal projections of the first side and the second side on the substrate substrate.

[0030] In an example embodiment of the present disclosure, the size of the metal spacer block in the second direction is 16-17 μm, the distance between the first side and the second side is 11.6-12.6 μm, and the distance between the first side and the third side is 9.2-10.2 μm.

[0031] In an example embodiment of the present disclosure, the orthogonal projection of the touch signal line on the substrate substrate is located between the orthogonal projections of the red sub-pixel region and the blue sub-pixel region on the substrate substrate.

[0032] In an example embodiment of the present disclosure, the driving circuit layer further comprises:

[0033] A gate layer is provided on one side of the substrate substrate, the scan line and the gate layer are provided in the same layer, and the gate layer comprises a gate, and the scan line is connected with the gate;

[0034] A gate insulating layer is provided on the side of the gate layer away from the substrate substrate, and the gate insulating layer covers the surface of the gate layer;

[0035] An active layer is provided on the side of the gate insulating layer away from the substrate substrate;

[0036] A source-drain layer comprises a source covering one end of the active layer and a drain covering the other end of the active layer, the data line and the source-drain layer are provided in the same layer, and the data line is connected with the drain.

[0037] In an example embodiment of the present disclosure, the orthogonal projection of the metal block on the substrate substrate covers the gap between the orthogonal projections of the source and the drain on the substrate substrate.

[0038] In an example embodiment of the present disclosure, the array substrate further comprises:

[0039] A signal lead line is provided on one side of the substrate substrate and located in the peripheral region, comprising a data lead line and a scan lead line, the data lead line is connected with the data line and provided in the same layer, and the scan lead line is provided in the same layer with the scan line;

[0040] A touch lead wire is disposed on one side of the substrate and located in the peripheral area, and the touch lead wire is connected with the touch signal line and arranged in the same layer;

[0041] The orthogonal projection of the data lead wire, the scan lead wire and the touch lead wire on the substrate at least partially overlaps.

[0042] In an exemplary embodiment of the present disclosure, the peripheral area includes a binding area; and the array substrate further includes:

[0043] A pad is disposed on one side of the substrate and located in the binding area, and the pad includes a first pad, a second pad and a third pad;

[0044] The first pad is connected with the data lead wire, the first pad includes a first conductive layer and a second conductive layer, the first conductive layer is arranged in the same layer as the data line, the second conductive layer is arranged in the same layer as the pixel electrode, and the second conductive layer is connected with the first conductive layer through a via hole;

[0045] The second pad is connected with the scan lead wire, the second pad includes a third conductive layer and a fourth conductive layer, the third conductive layer is arranged in the same layer as the scan line, the fourth conductive layer is arranged in the same layer as the pixel electrode, and the fourth conductive layer is connected with the third conductive layer through a via hole;

[0046] The third pad is connected with the touch lead wire, the third pad includes a fifth conductive layer and a sixth conductive layer, the fifth conductive layer is arranged in the same layer as the touch signal line, the sixth conductive layer is arranged in the same layer as the pixel electrode, and the sixth conductive layer is connected with the fifth conductive layer through a via hole.

[0047] According to a second aspect of the present disclosure, a manufacturing method of an array substrate is provided, comprising:

[0048] A substrate is provided, and the substrate includes a display area and a peripheral area located at the periphery of the display area;

[0049] A drive circuit layer is formed on one side of the substrate, and the drive circuit layer is located in the display area and includes a plurality of data lines and a plurality of scan lines, the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scan lines extend along the second direction and are arranged at intervals along the first direction, the second direction and the first direction intersect, and the data lines and the scan lines intersect each other to define a plurality of sub-pixel areas;

[0050] A metal layer is formed on the side of the driving circuit layer away from the substrate, the metal layer is located in the display area, and the metal layer includes a plurality of metal blocks arranged at intervals, and the metal blocks are located at intersections of the data lines and the scan lines.

[0051] According to a third aspect of the present disclosure, a display panel is provided, comprising:

[0052] The array substrate according to the first aspect;

[0053] A color film substrate is arranged on one side of the array substrate;

[0054] A plurality of spacers are arranged between the array substrate and the color film substrate, the spacers correspond to the metal blocks one by one, and at least half of the top end of the projection of the spacers on the substrate is located in the projection of the metal blocks on the substrate.

[0055] A liquid crystal layer is arranged between the array substrate and the color film substrate.

[0056] In an exemplary embodiment of the present disclosure, the sub-pixel area includes a red sub-pixel area, a blue sub-pixel area, and a green sub-pixel area, the spacers include main spacers, and the projection of the main spacers on the substrate is located between the projections of the red sub-pixel area and the blue sub-pixel area on the substrate.

[0057] In an exemplary embodiment of the present disclosure, the projection of the spacers on the substrate partially overlaps the gap between the projections of the source and the drain on the substrate.

[0058] According to a fourth aspect of the present disclosure, a display device is provided, comprising the display panel according to the third aspect.

[0059] The array substrate provided by the present disclosure comprises a substrate, a driving circuit layer, and a metal layer, wherein the metal layer includes a plurality of metal blocks arranged at intervals, and the metal blocks are located at intersections of data lines and scan lines. The metal blocks help to adjust the flatness at the intersection positions of the data lines and the scan lines, so as to maintain the uniformity in height and stability in distribution position of other structures formed at the positions of the metal blocks. BRIEF DESCRIPTION OF DRAWINGS

[0060] The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0061] Figure 1 FIG. 1 is a schematic view of a display panel in an exemplary embodiment of the present disclosure;

[0062] Figure 2is a schematic diagram of a cross section of a display panel in another exemplary embodiment of the present disclosure;

[0063] Figure 3 is a schematic diagram of a substrate structure in an exemplary embodiment of the present disclosure;

[0064] Figure 4 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0065] Figure 5 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0066] Figure 6 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0067] Figure 7 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0068] Figure 8 is Figure 7 is a cross-sectional view along direction A-A in FIG.

[0069] Figure 9 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0070] Figure 10 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0071] Figure 11 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0072] Figure 12 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0073] Figure 13 is Figure 12 is a cross-sectional view along direction B-B in FIG.

[0074] Figure 14 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0075] Figure 15 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0076] Figure 16 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0077] Figure 17 is a schematic diagram of a planar structure of an array substrate in an exemplary embodiment of the present disclosure;

[0078] The main element reference signs in the figures are explained as follows:

[0079] 1-substrate substrate; 11-display area; 12-peripheral area; 2-driving circuit layer; 21-scan line; 22-data line; 23-source-drain layer; 23S-source electrode; 23D-drain electrode; 24-gate layer; 25-gate insulating layer; 26-active layer; 27-planarization layer; 3-metal layer; 31-metal block; 311-touch connection metal block; 3111-first touch metal block; 3112-second touch metal block; 312-metal spacer block; 312a-first side; 312b-second side; 312c-third side; 312d-fourth side; 312e-fifth side; 3121-first pad block; 3122-second pad block; 32-touch signal line; 4-spacer; 41-main spacer; 42-sub spacer; 5-common electrode; 51-touch unit; 511-common electrode block; 511a-main body; 511b-first protruding part; 511c-second protruding part; 512-row connection part; 513-column connection part; 5131-upper connection part; 5132-lower connection part; 501-first passivation layer; 502-second passivation layer; 6-pixel electrode; 7-liquid crystal layer; 8-color filter substrate; 9-sub-pixel area; 90-pixel unit area; 91-red sub-pixel area; 92-green sub-pixel area; 93-blue sub-pixel area; 01-data lead line; 02-scan lead line; 03-touch lead line; 04-first pad; 041-first conductive layer; 042-second conductive layer; 05-second pad; 051-third conductive layer; 052-fourth conductive layer; 06-third pad; 061-fifth conductive layer; 062-sixth conductive layer; 001-insulating layer; 002-insulating layer; 003-passivation layer; 004-passivation layer. DETAILED DESCRIPTION

[0080] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

[0081] In the drawings, the thickness of regions and layers can be exaggerated for clarity. Like reference numerals in different drawings denote like features, structures, or characteristics, and thus their detailed descriptions will be omitted.

[0082] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the

[0083] When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure by means of another structure.

[0084] The terms "one", "a", "said" are used to indicate the presence of one or more elements / components / etc.; the terms "include" and "have" are used to indicate an open-ended inclusion of one or more elements / components / etc. in the thing, material, etc. recited; the terms "first", "second", etc. are used only to distinguish one element / component / etc. from another, and do not require or imply a particular order or number of elements / components / etc.

[0085] The array substrate of the liquid crystal display panel usually has various wirings, such as scan lines and data lines. In the related art, in order not to affect the aperture ratio of the display panel, the width of the wirings such as the scan lines and the data lines is usually designed to be narrow, which causes the height of the spacers located thereon to be inconsistent and the stability to be poor, thereby adversely affecting the cell gap of the liquid crystal display panel.

[0086] As shown in Figures 1 to 4 The array substrate provided by the present disclosure includes a substrate 1, a drive circuit layer 2, and a metal layer 3. The substrate 1 includes a display area 11 and a peripheral area 12 located at the periphery of the display area 11. The drive circuit layer 2 is located on one side of the substrate 1 and in the display area 11, and includes a plurality of data lines 22 and a plurality of scan lines 21. The data lines 22 and the scan lines 21 cross each other to define a plurality of sub-pixel areas 9. The metal layer 3 is located on the side of the drive circuit layer 2 away from the substrate 1 and in the display area 11. The metal layer 3 includes a plurality of metal blocks 31 arranged at intervals. The metal blocks 31 are located at the intersections of the data lines 22 and the scan lines 21.

[0087] The array substrate provided by the present disclosure comprises a substrate 1, a driving circuit layer 2 and a metal layer 3, wherein the metal layer 3 comprises a plurality of metal blocks 31 arranged at intervals, and the metal blocks 31 are located at the intersections of the data lines 22 and the scan lines 21. The metal blocks 31 help to adjust the flatness at the intersections of the data lines 22 and the scan lines 21, so that when other structures are formed at the positions of the metal blocks 31, the uniformity in height and the stability in distribution position of the structures can be maintained.

[0088] The components of the array substrate provided by the embodiments of the present disclosure will be described in detail below in combination with the drawings:

[0089] An array substrate provided in the embodiments of the present disclosure can be used to form a TFT-LCD (Thin Film Transistor Liquid Crystal Display) display panel.

[0090] As shown in Figures 1 to 4 , Figure 7 , the substrate 1 comprises a display area 11 and a non-display area 11 located at the periphery of the display area 11. The substrate 1 can be a substrate of inorganic material or a substrate of organic material. For example, in an embodiment of the present disclosure, the material of the substrate 1 can be a glass material such as soda-lime glass, quartz glass or sapphire glass, or a metal material such as stainless steel, aluminum or nickel. In another embodiment of the present disclosure, the material of the substrate 1 can be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN) or a combination thereof. The substrate 1 can also be a flexible substrate. For example, in an embodiment of the present disclosure, the material of the substrate 1 can be polyimide (PI). The substrate 1 can also be a composite of multiple layers of materials. For example, in an embodiment of the present disclosure, the substrate 1 can comprise a Bottom Film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer which are sequentially stacked.

[0091] The driving circuit layer 2 is arranged on one side of the substrate 1 and in the display area 11. The driving circuit layer 2 includes a plurality of data lines 22 and a plurality of scan lines 21. The data lines 22 and the scan lines 21 cross each other to define a plurality of sub-pixel areas 9. The data lines 22 are arranged on the side of the scan lines 21 away from the substrate 1. The data lines 22 and the scan lines 21 can have various designs in terms of extension direction and arrangement direction.

[0092] As shown in FIG. 1, in an embodiment, the plurality of data lines 22 extend in the column direction and are arranged in the row direction, and the plurality of scan lines 21 extend in the row direction and are arranged in the column direction. It should be noted that in the present disclosure, the row direction and the column direction are relative, and the intersection angle of the row direction and the column direction can be greater than 0° and less than or equal to 90°. Figure 4 As shown in FIG. 2, in a specific embodiment, the plurality of data lines 22 extend in a first direction X and are arranged in a second direction Y. The first direction X and the second direction Y intersect, and the intersection angle is greater than 0° and less than or equal to 90°. The plurality of scan lines 21 extend in the second direction Y and are arranged in the first direction X. In a specific embodiment, the first direction X is perpendicular to the second direction Y.

[0093] Figure 7 As shown in FIG. 3, in a specific embodiment, the plurality of data lines 22 extend in a first direction X and are arranged in a second direction Y. The first direction X and the second direction Y intersect, and the intersection angle is greater than 0° and less than or equal to 90°. The plurality of scan lines 21 extend in the second direction Y and are arranged in the first direction X. In a specific embodiment, the first direction X is perpendicular to the second direction Y.

[0094] The scan lines 21 and the data lines 22 can be a layer of conductive material or a stack of multiple layers of conductive material. For example, in an embodiment of the present disclosure, the scan lines 21 can include a first conductive material layer, a second conductive material layer, and a first conductive material layer stacked in sequence, i.e., in a sandwich structure. The first conductive material layer can be made of a corrosion-resistant metal or alloy, such as molybdenum. The second conductive material layer can be made of a high-conductivity metal or alloy, such as copper, aluminum, silver, etc. For another example, in another embodiment of the present disclosure, the scan lines 21 can include a layer of conductive material, such as molybdenum. The data lines 22 can be made of the same conductive material as the scan lines 21.

[0095] As shown in FIG. 4, in some embodiments, the driving circuit layer 2 further includes a gate layer 24 arranged on one side of the substrate 1. The scan lines 21 are arranged in the same layer as the gate layer 24. The gate layer includes a gate electrode connected to the scan lines 21 for providing a scan signal. The gate layer 24 can be made of a metal material or an alloy material to ensure good conductivity. Of course, the gate layer 24 can also be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc. Figure 1 Figure 2 Figure 7 Figure 8 As shown in FIG. 4, in some embodiments, the driving circuit layer 2 further includes a gate layer 24 arranged on one side of the substrate 1. The scan lines 21 are arranged in the same layer as the gate layer 24. The gate layer includes a gate electrode connected to the scan lines 21 for providing a scan signal. The gate layer 24 can be made of a metal material or an alloy material to ensure good conductivity. Of course, the gate layer 24 can also be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc.

[0096] ​​​​The gate layer 24 and the scan line 21 can be formed by photolithography, and the scan line 21 and the gate layer 24 can be formed by the same photolithography process. For example, a conductive material layer can be deposited on one side of the substrate 1 first, and then the conductive material layer can be patterned to obtain the required scan line 21 and gate layer 24.

[0097] The driving circuit layer 2 also includes a gate insulating layer 25, disposed on the side of the gate layer 24 away from the substrate 1, and the gate insulating layer 25 covers the surface of the gate layer 24. The gate insulating layer 25 can be a single film layer such as silicon nitride, silicon oxide, or aluminum oxide, or a multi-film layer formed by a combination of these. The gate insulating layer 25 can be formed by deposition methods, for example, a silicon oxide layer can be formed as a gate insulating material layer by vapor phase chemical deposition, and the gate insulating material layer can be patterned to form the gate insulating layer 25.

[0098] The driving circuit layer 2 also includes an active layer 26, which is disposed on the side of the gate insulating layer 25 away from the substrate 1. The active layer 26 can be made of polysilicon or IGZO (indium gallium zinc oxide), and its conductivity at different locations can be changed by processes such as doping.

[0099] The driving circuit layer 2 also includes a source-drain layer 23, which includes a source 23S covering one end of the active layer 26 and a drain 23D covering the other end of the active layer 26. The data line 22 is disposed on the same layer as the source-drain layer 23. The data line 22 is connected to the drain 23D.

[0100] The gate layer 24, gate insulating layer 25, active layer 26, and source / drain layer 23 can be used to form a thin-film transistor. The thin-film transistor is located in the sub-pixel region 9 and serves as a component of the pixel driving circuit to drive the liquid crystal pixel region.

[0101] In one embodiment, the driving circuit / 2 further includes a planarization layer 27 disposed on the side of the source / drain layer 23 away from the substrate 1, and the planarization layer 27 covers the surface of the source / drain layer 23.

[0102] like Figure 1 , Figure 2 , Figure 4 and Figure 7 As shown, the metal layer 3 is disposed on the side of the driving circuit layer 2 away from the substrate 1 and located in the display area 11. The metal layer 3 includes a plurality of spaced metal blocks 31, which are located at the intersections of the data lines 22 and the scan lines 21. The plurality of metal blocks 31 can be arranged in a matrix array, and a metal block 31 is disposed at each intersection of the data lines 22 and the scan lines 21.

[0103] like Figure 7 and Figure 8As shown, in some embodiments, the orthographic projection of the metal block 31 on the substrate 1 covers the gap between the orthographic projections of the source electrode 23S and the drain electrode 23D on the substrate 1. That is, there is a gap between the orthographic projections of the source electrode 23S and the drain electrode 23D on the substrate 1, and the orthographic projection of the metal block 31 on the substrate 1 is located within this gap and covers it.

[0104] like Figure 7 As shown, in some embodiments of this disclosure, the metal layer 3 further includes multiple touch signal lines 32. The orthographic projection of the touch signal lines 32 on the substrate 1 is outside the orthographic projection of the sub-pixel region 9 on the substrate 1, and the orthographic projection of the touch signal lines 32 on the substrate 1 at least partially overlaps with the orthographic projection of the data line 22 on the substrate 1, so as to reduce the impact of the touch signal lines 32 on the pixel aperture ratio. The metal block 31 includes a touch connection metal block 311 and a metal spacer block 312. The touch connection metal block 311 is connected to the touch signal lines 32, and there is a gap between the metal spacer block 312 and the touch signal lines 32. Specifically, in one embodiment, the touch connection metal block 311 is in direct contact with the touch signal lines 32.

[0105] In the second direction Y, the orthographic projection of a portion of the data line 22 onto the substrate 1 lies within the orthographic projection of the touch signal line 32 onto the substrate 1. That is, in the second direction Y, the width of the touch signal line 32 is greater than the width of the data line 22 to reduce common electrode voltage ripple. In one specific embodiment, in the second direction Y, the width of the touch signal line 32 is 5.2-6.2 μm, and the width of the data line 22 is 2.5-3.5 μm.

[0106] In this embodiment, the touch connection metal block 311, the metal spacer block 312, and the touch signal line 32 can be formed using the same material and the same photolithography process. A metal material layer can be deposited on the side of the driving circuit layer 2 away from the substrate 1, and then the metal material layer can be patterned to obtain the desired touch connection metal block 311, metal spacer block 312, and touch signal line 32.

[0107] like Figure 1 , Figure 2 , Figures 6 to 8 As shown, in some embodiments of this disclosure, the array substrate further includes a common electrode 5 and a plurality of pixel electrodes 6. The common electrode 5 is disposed on the side of the driving circuit layer 2 away from the substrate 1, and the plurality of pixel electrodes 6 are disposed on the side of the common electrode 5 away from the substrate 1. In one embodiment, a first passivation layer 501 and / or a second passivation layer 502 are further formed between the common electrode 5 and the pixel electrodes 6, and the pixel electrodes 6 are connected to the source electrode in the source-drain layer 23 through vias.

[0108] likeFigures 6 to 8 As shown, the common electrode 5 includes a plurality of spaced-apart touch units 51, and each touch unit 51 includes a plurality of interconnected common electrode blocks 511. A plurality of pixel electrodes 6 are disposed on the side of the common electrode 5 away from the substrate 1. Each pixel electrode 6 corresponds to a sub-pixel region 9.

[0109] In this embodiment, the common electrode 5 is reused as a touch electrode. In related technologies, this principle can be used to fabricate a Touch and Display Driver Integration (TDDI) touchscreen, integrating the touch sensor into the display and combining the touch chip and display chip into a single chip, making the screen thinner and meeting the design requirements for thinner display products.

[0110] like Figure 6 As shown, in this embodiment, the array substrate is provided with multiple touch units 51 (self-capacitance electrodes) on the same layer and insulated from each other. When a human body does not touch the screen, the capacitance of each touch unit 51 is a fixed value. When a human body touches the screen, the capacitance of the corresponding touch unit 51 is the fixed value plus the capacitance of the human body. The touch detection chip determines the touch position by detecting the change in capacitance value of each touch unit 51 during the touch period.

[0111] like Figure 1 and Figure 2 As shown, metal layer 3 is disposed on the side of driving circuit layer 2 away from substrate 1. In one embodiment, metal layer 3 is disposed on the side of common electrode 5 away from substrate 1. Figure 1 In another embodiment, the metal layer 3 may be disposed on the side of the common electrode 5 near the substrate 1. Figure 2 ).

[0112] like Figure 7 As shown, the metal block 31 includes a touch-connecting metal block 311 and a metal spacer block 312. The touch-connecting metal block 311 includes a first touch metal block 3111 and a second touch metal block 3112. The touch signal line 32 is connected to a common electrode block 511 in the touch unit 51 through the first touch metal block 3111, so that the capacitance value of the touch unit 51 can be transmitted to the touch detection chip through the touch signal line 32, allowing the touch detection chip to accurately determine the touched capacitor electrode and make a corresponding response. The second touch metal block 3112 is not connected to the common electrode block 511. There is a gap between the metal spacer block 312 and the touch signal line 32, meaning that the metal spacer block 312 and the touch signal line 32 are not directly connected. The metal spacer block 312 is connected to the common electrode block 511 at its corresponding position so that the voltage of the metal spacer block 312 is equal to the voltage of the common electrode block 511, thus avoiding the adverse effect of the metal spacer block 312 on the electric field due to its floating.

[0113] When the metal layer 3 is arranged on the side of the common electrode 5 close to the substrate 1, i.e. between the driving circuit layer 2 and the common electrode 5, the metal layer 3 can be formed on the side of the driving circuit layer 2 away from the substrate 1 first, then a passivation layer is formed on the side of the metal layer 3 away from the substrate 1, and a via hole is etched at a specific position of the formed passivation layer to expose the metal layer 3 at the specific position, after which the common electrode 5 is formed on the side of the passivation layer away from the substrate 1, and some of the common electrode blocks 511 in the formed common electrode 5 can be connected to some of the metal blocks 31 in the metal layer 3 through the via hole. The area of the via hole can be set to 9-25 μm 2 The shape of the orthographic projection of the via hole on the substrate 1 can be approximately circular, elliptical, irregular polygonal, or regular polygonal, etc., which is not limited in the present disclosure.

[0114] When the metal layer 3 is arranged on the side of the common electrode 5 away from the substrate 1, such as between the common electrode 5 and the pixel electrode 6( Figure 8 ), the common electrode 5 can be formed on the side of the driving circuit layer 2 away from the substrate 1 first, then a passivation layer 501 is formed on the side of the common electrode 5 away from the substrate 1, and after that a via hole is etched at a specific position of the formed passivation layer 501 to expose the common electrode 5 at the specific position. Then the metal layer 3 is formed on the side of the passivation layer 501 away from the substrate 1, and some of the metal blocks 31 in the formed metal layer 3 can be connected to some of the common electrode blocks 511 in the common electrode 5 through the via hole. The area of the via hole can be set to 9-25 μm 2 The shape of the orthographic projection of the via hole on the substrate 1 can be approximately circular, elliptical, irregular polygonal, or regular polygonal, etc., which is not limited in the present disclosure.

[0115] As Figure 7 and Figure 11As shown, in some embodiments of this disclosure, the metal spacer block 312 includes a first side 312a, a second side 312b, and a third side 312c connected in sequence. The second side 312b and the third side 312c are located on one side of the first side 312a along the first direction X and are substantially parallel to the first side 312a. The distance between the second side 312b and the first side 312a is greater than the distance between the third side 312c and the first side 312a. The orthographic projection of the connection via between the metal spacer block 312 and the common electrode block 511 on the substrate 1 is located between the orthographic projections of the first side 312a and the second side 312b on the substrate 1. In a specific embodiment, the first side 312a, the second side 312b, and the third side 312c are substantially parallel to the second direction Y, and the lengths of the second side 312b and the third side 312c are both less than the length of the first side 312a. Furthermore, the metal spacer block 312 also includes a fourth side 312d and a fifth side 312e located at both ends of the first side 312a in the second direction Y, the fourth side 312d and the fifth side 312e being approximately perpendicular to the first side 312a. The first side 312a, the fourth side 312d, the second side 312b, the third side 312c and the fifth side 312e are connected in sequence to form a closed shape.

[0116] like Figure 7 and Figure 11 As shown, in this embodiment, by increasing the distance between the second side 312b and the first side 312a, the area of ​​the metal spacer block 312 containing the second side 312b and the common electrode block 511 above it have a stacked area, thereby facilitating the connection between the metal spacer block 312 and the common electrode block 511.

[0117] Similarly, the shape design of the metal spacer block 312 is also applicable to the first touch metal block 3111. For example... Figure 7 As shown, when the first touch metal block 3111 is connected to the common electrode block 511, its shape can be the same as the metal spacer block 312. When the second touch metal block 3112 does not need to be connected to the common electrode block, its shape can be set according to actual needs. For example, the second touch metal block 3112 can be a regular polygon, and its orthographic projection on the substrate 1 can be an axially symmetric regular polygon, such as a bilaterally symmetric regular hexagon or octagon. Furthermore, the orthographic projection of the second touch metal block 3112 on the substrate 1 can also be a centrally symmetric regular polygon. Figure 7 As shown, in one specific embodiment, the second touch metal block is a regular octagon that is symmetrical from left to right, and the size of the second touch metal block 3112 in the second direction Y is 16-17μm, and the size in the first direction X is 9.2-10.2μm.

[0118] In one specific embodiment, the metal spacer block 312 has a size of 16-17 μm in the second direction Y, the distance between the second side 312b and the first side 312a is 11.6-12.6 μm, and the distance between the third side 312c and the first side 312a is 9.2-10.2 μm.

[0119] like Figure 6 , Figure 7 , Figure 9 and Figure 10 As shown, in some embodiments of this disclosure, the touch unit 51 includes a plurality of common electrode blocks 511 arranged in an array. At least two common electrode blocks 511 are arranged in a column along a first direction X, and at least two common electrode blocks are arranged in a row along a second direction Y. Adjacent rows of common electrode blocks 511 are connected by a row connection portion 512, and adjacent columns of common electrode blocks 511 are connected by a column connection portion 513. The column connection portion 513 includes an upper connection portion 5111 connected to the upper region of the common electrode block 511 and a lower connection portion 5112 connected to the lower region of the common electrode block. That is, the column connection portion 513 between two adjacent common electrode blocks 511 includes an upper connection portion 5131 and a lower connection portion 5132 to ensure the stability and firmness of the connection of the common electrode blocks 511. The row connection portion 512 and the column connection portion 513 are disposed on the same layer as the common electrode blocks 511.

[0120] The size of the common electrode block 511 can be set according to the actual situation. For example, it can be set according to the number of corresponding sub-pixel areas 9 or pixel electrodes 6.

[0121] like Figure 6 and Figure 7 As shown, in some embodiments of this disclosure, the sub-pixel region 9 includes a red sub-pixel region 91, a green sub-pixel region 92, and a blue sub-pixel region 93. At least one red sub-pixel region 91, at least one green sub-pixel region 92, and at least one blue sub-pixel region 93 are arranged and combined to form a pixel unit region 90, and one pixel unit region 90 corresponds to a common electrode block 511. The orthographic projection of the row connection portion 512 on the substrate 1 is located between the orthographic projections of two adjacent sub-pixel regions corresponding to the common electrode block 511 on the substrate 1.

[0122] In one specific embodiment, a red sub-pixel region 91, a green sub-pixel region 92, and a blue sub-pixel region 93 are arranged sequentially along the second direction Y to form a pixel unit region 90, and a common electrode block 511 corresponds to a pixel unit region 90. The orthographic projection of the row connection portion 512 on the substrate 1 is located between the orthographic projections of the green sub-pixel region 92 and the blue sub-pixel region 93 corresponding to the common electrode block 511 on the substrate 1.

[0123] In some embodiments of this disclosure, the first touch metal block 3111 and the metal spacer block 312 can be connected to the common electrode block 511 through different connection positions.

[0124] like Figure 9 and Figure 10 As shown, in this embodiment, the common electrode block 511 includes a main body 511a and a first protrusion 511b and a second protrusion 511c connected to one side of the main body 511a. The first protrusion 511b is connected to the middle part of one side of the main body 511a, and the orthographic projection of the first protrusion 511b on the substrate 1 is located between the orthographic projections of two adjacent sub-pixel areas 9 corresponding to the common electrode block 511 on the substrate 1. The second protrusion 511c is connected to the corner of the main body 511a.

[0125] The number of first protrusions 511b can be set according to the number of sub-pixel areas 9 corresponding to the common electrode block 511. For example, when the common electrode block 511 corresponds to three sub-pixel areas 9, the number of first protrusions 511b can be two, respectively located between two adjacent sub-pixel areas 9.

[0126] like Figure 7 , Figure 9 and Figure 10 As shown, the metal spacer block 312 includes a first spacer block 3121. The orthographic projection of the first spacer block 3121 on the substrate 1 at least partially overlaps with the first protrusion 511b, and the first spacer block 3121 is connected to the first protrusion 511b through a via. In one specific embodiment, there are multiple first protrusions 511b, and the shapes and sizes of different first protrusions 511b may be the same or different. When two adjacent rows of common electrode blocks 511 are connected, a portion of the first protrusions 511b is reused as a row connection portion 512. For example, the first protrusion 511b located between the green sub-pixel area 92 and the blue sub-pixel area 93 is reused as a row connection portion 512. In this case, the size of the first protrusion 511b can be set according to the distance between two adjacent rows of common electrode blocks 511.

[0127] In some embodiments, there are multiple second protrusions 511b, wherein a touch-connecting metal block 311 is provided at a corresponding position of some second protrusions 511b, and a metal spacer block 312 is provided at a corresponding position of some second protrusions 511c.

[0128] When a touch signal line 32 is arranged around the common electrode block 511, the touch connection metal block 311 connecting the touch signal line 32 can be disposed at the corresponding position of the second protrusion 511c of the common electrode block 511. Specifically, when the touch signal line 32 needs to be connected to the common electrode block 511 through the first touch metal block 3111, the orthographic projection of the first touch metal block 3111 on the substrate 1 at least partially overlaps with the orthographic projection of the second protrusion 511c of one of the common electrode blocks 511 in the touch unit 51 on the substrate 1, and the first touch metal block 3111 is connected to the second protrusion 511c through a via. When no touch signal line 32 is provided around the common electrode block 511, a metal spacer block 312 can be provided at the corresponding position of the second protrusion 511c of the common electrode block 511. The metal spacer block 312 also includes a second pad block 3122. The orthographic projection of the second pad block 3122 on the substrate 1 at least partially overlaps with the second protrusion 511c, and the second pad block 3122 is connected to the second protrusion 511c through a via.

[0129] like Figure 3 , Figure 12 and Figure 13 As shown, in some embodiments of this disclosure, the array substrate further includes signal leads and touch leads 03 located in the peripheral region 12. The signal leads are disposed on one side of the substrate 1 and located in the peripheral region 12, including data leads 01 and scan leads 02. The data leads 01 are connected to the data line 22 and are disposed on the same layer, while the scan leads 02 are disposed on the same layer as the scan line 21. The touch leads 03 are disposed on one side of the substrate 1 and located in the peripheral region 12, and are connected to the touch signal line 32 and are disposed on the same layer. The orthographic projections of the data leads 01, scan leads 02, and touch leads 03 on the substrate 1 at least partially overlap.

[0130] In some embodiments, an insulating layer 001 is further disposed between each film layer of the data lead 01, scan lead 02, and touch lead 03. In this embodiment, the three layers of data lead 01, scan lead 02, and touch lead 03 overlap, which helps to reduce the width of the fan-shaped area and realize the narrow bezel design of the array substrate in this area. At the same time, the three layers of leads are stacked and kept insulated from each other by the insulating layer 001, which can effectively reduce the risk of short circuits between the leads. The linewidths of data lead 01, scan lead 02, and touch lead 03 can be set according to actual conditions. In a specific embodiment, the linewidth of data lead 01, scan lead 02, and touch lead 03 can be 2.7 μm, and when the three layers are on the same layer, the line spacing can be 2.3 μm.

[0131] like Figure 14 and Figure 15As shown, in some embodiments of the present disclosure, the peripheral region 12 further comprises a binding region. In this region, the peripheral leads are connected with the chip, realizing the transmission of touch and display signals. Each lead can be connected with the chip through a transition hole.

[0132] The array substrate further comprises a pad, which is arranged on one side of the substrate 1 and located in the binding region, and the pad comprises a first pad 04, a second pad 05 and a third pad 06; the first pad 04 is connected with the data lead 01, and the first pad 04 comprises a first conductive layer 041 and a second conductive layer 042, the first conductive layer 041 is arranged in the same layer as the data line 22, and the second conductive layer 042 is arranged in the same layer as the pixel electrode 6, and the second conductive layer 042 is connected with the first conductive layer 041 through a via hole.

[0133] The second pad 05 is connected with the scanning lead 02, and the second pad 05 comprises a third conductive layer 051 and a fourth conductive layer 052, the third conductive layer 051 is arranged in the same layer as the scanning line 21, and the fourth conductive layer 052 is arranged in the same layer as the pixel electrode 6, and the fourth conductive layer 052 is connected with the third conductive layer 051 through a via hole.

[0134] The third pad 06 is connected with the touch lead 03, and the third pad 06 comprises a fifth conductive layer 061 and a sixth conductive layer 062, the fifth conductive layer 061 is arranged in the same layer as the touch signal line 32, and the sixth conductive layer 062 is arranged in the same layer as the pixel electrode 6, and the sixth conductive layer 062 is connected with the fifth conductive layer 061 through a via hole.

[0135] In a specific embodiment, an insulating layer 002 is further arranged between the third conductive layer 051 and the first conductive layer 041, and a passivation layer 003 is further arranged between the third conductive layer 051 and the fifth conductive layer 061. The fifth conductive layer 061 is provided with a passivation layer 004 on the side away from the third conductive layer 051, and the second conductive layer 042, the fourth conductive layer 052 and the sixth conductive layer 062 are arranged on the side of the passivation layer 004 away from the fifth conductive layer 061 and the third conductive layer 051, and are connected with the first conductive layer 041, the third conductive layer 051 and the fifth conductive layer 061 respectively through via holes. The second conductive layer 042, the fourth conductive layer 052 and the sixth conductive layer 062 can be connected with the chip, thereby realizing the connection of each lead with the chip to complete the transmission of each signal.

[0136] As Figure 1 , Figure 2 and Figure 5As shown, the display panel provided by the present disclosure also includes the array substrate in any of the above embodiments, and further includes a color film substrate 8, a plurality of spacers 4, and a liquid crystal layer 7. The color film substrate 8 is arranged on one side of the array substrate. The plurality of spacers 4 are arranged between the array substrate and the color film substrate 8, the spacers 4 correspond to the metal blocks 31 one by one, and at least half of the top end (the end close to the array substrate) of the spacers 4 on the substrate 1 is located within the projection of the metal block 31 on the substrate 1. That is, the metal block 31 can well support the spacer 4, avoiding the spacer 4 from being offset due to unstable support. A multi-dimensional electric field is generated between the pixel electrode 6 and the common electrode 5, which is used to drive the liquid crystal in the liquid crystal layer 7 to deflect, thereby controlling the light output of the liquid crystal display panel in the pixel area.

[0137] The display panel provided by the present disclosure includes the metal layer 3 and the spacer 4, wherein the metal layer 3 includes a plurality of metal blocks 31 arranged at intervals, the spacer 4 is arranged on the side of the metal layer 3 away from the substrate 1, and the projection of the spacer 4 on the substrate 1 is located within the projection of the metal block 31 on the substrate 1, so that the metal block 31 can stably support the spacer 4 and make the spacer 4 keep consistency in height.

[0138] As shown in some embodiments, Figure 16 the projection of the spacer 4 on the substrate 1 partially overlaps with the gap between the projections of the source 23S and the drain 23D on the substrate 1. That is, there is a gap between the projections of the source 23S and the drain 23D on the substrate 1, and the projection of the spacer 4 on the substrate 1 partially overlaps with the gap.

[0139] The spacer 4 includes a main spacer 41 and an auxiliary spacer 42. The main spacer 41 plays a role in controlling the cell gap, and the auxiliary spacer 42 plays a role in auxiliary support and adjustment. The main spacer 41 and the auxiliary spacer 42 can be arranged according to a certain rule.

[0140] As shown in some embodiments of the present disclosure, Figure 5 and Figure 7 the projection of the main spacer 41 on the substrate 1 is located between the projections of the red sub-pixel area 91 and the blue sub-pixel area 93 on the substrate 1. In actual application, when the array substrate and the like are pressed, the main spacer 41 may be offset under the action of external force, thereby affecting the display of the sub-pixels in the adjacent area. Generally, the transmittance of the red sub-pixel and the blue sub-pixel is lower than that of the green sub-pixel, so the present disclosure arranges the main spacer 41 between the red sub-pixel area 91 and the blue sub-pixel area 93 to reduce the influence of the display effect after the main spacer 41 is offset. The arrangement position of the auxiliary spacer 42 can be set according to actual design requirements, which can be located between any two sub-pixel areas 9.

[0141] Correspondingly, the orthogonal projection of the touch signal line 32 on the substrate 1 is located between the orthogonal projection of the red sub-pixel region 91 and the blue sub-pixel region 93 on the substrate 1. That is, the touch signal line 32 is also arranged between the red sub-pixel region 91 and the blue sub-pixel region 93.

[0142] As shown in FIG. 1, the display device 100 includes a substrate 1, a driving circuit layer 2, and a metal layer 3. Figures 1 to 4 And Figure 17 The present disclosure also provides a manufacturing method of an array substrate, including:

[0143] In step S100, a substrate 1 is provided, the substrate 1 including a display region 11 and a peripheral region 12 located at the periphery of the display region 11.

[0144] In step S200, a driving circuit layer 2 is formed on one side of the substrate 1, the driving circuit layer 2 being located in the display region 11 and including a plurality of data lines 22 and a plurality of scan lines 21, the plurality of data lines 22 extending along a first direction X and being arranged at intervals along a second direction Y, the plurality of scan lines 21 extending along the second direction Y and being arranged at intervals along the first direction X, the second direction Y and the first direction X being perpendicular to each other, the data lines 22 and the scan lines 21 crossing each other to define a plurality of sub-pixel regions 9.

[0145] In step S300, a metal layer 3 is formed on the side of the driving circuit layer 2 away from the substrate 1, the metal layer 3 being located in the display region 11 and including a plurality of metal blocks 31 arranged at intervals, the metal blocks 31 being located at the intersections of the data lines 22 and the scan lines 21.

[0146] As shown in FIG. 1, the display device 100 includes a substrate 1, a driving circuit layer 2, and a metal layer 3. Figure 8 In some embodiments of the present disclosure, forming the driving circuit layer 2 on one side of the substrate 1 includes:

[0147] In some embodiments of the present disclosure, forming the driving circuit layer 2 on one side of the substrate 1 includes:

[0148] In some embodiments of the present disclosure, forming the driving circuit layer 2 on one side of the substrate 1 includes:

[0149] In some embodiments of the present disclosure, forming the driving circuit layer 2 on one side of the substrate 1 includes:

[0150] In some embodiments of the present disclosure, forming the driving circuit layer 2 on one side of the substrate 1 includes:

[0151] The display device of the present disclosure can be a mobile phone, a tablet computer, a television, or the like electronic device, which will not be listed one by one here.

[0152] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc., which should be considered as part of the present disclosure.

[0153] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components presented in the specification. The present disclosure can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in the specification extends to all alternative combinations of two or more individual features mentioned or obvious from the text and / or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of the specification illustrate the best way known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. An array substrate, characterized by, The application relates to an array substrate, which comprises a substrate, a driving circuit layer, a metal layer and a common electrode. The substrate comprises a display area and a peripheral area located at the periphery of the display area. The driving circuit layer is located on one side of the substrate and in the display area, and comprises a plurality of data lines and a plurality of scan lines. The data lines extend along a first direction and are arranged at intervals along a second direction. The scan lines extend along the second direction and are arranged at intervals along the first direction. The second direction intersects the first direction. The data lines and the scan lines cross each other to define a plurality of sub-pixel areas.

2. The array substrate of claim 1, wherein, The metal layer is located on the side of the driving circuit layer away from the substrate and in the display area.

3. The array substrate of claim 2, wherein, The metal layer comprises a plurality of metal blocks arranged at intervals. The metal blocks are located at the intersections of the data lines and the scan lines. The metal layer further comprises a plurality of touch signal lines. The metal blocks comprise touch connection metal blocks and metal spacer blocks. The touch connection metal blocks are connected with the touch signal lines. The metal spacer blocks have a spacing from the touch signal lines. The common electrode is located on the side of the driving circuit layer away from the substrate. The common electrode comprises a plurality of touch units arranged at intervals. The touch units comprise a plurality of common electrode blocks connected with each other. The touch connection metal blocks comprise first touch metal blocks and second touch metal blocks. The touch signal lines are connected with one common electrode block in the touch unit through the first touch metal blocks. The second touch metal blocks are not connected with the common electrode blocks. The metal spacer blocks are connected with the common electrode blocks through vias. The common electrode blocks comprise a main body and first and second protruding parts connected with one side of the main body. The first protruding part is connected with the middle part of one side of the main body. The orthogonal projection of the first protruding part on the substrate is located between the orthogonal projections of two adjacent sub-pixel areas corresponding to the common electrode block on the substrate. The second protruding part is connected with a corner of the main body. The metal spacer blocks comprise first spacer blocks. The orthogonal projection of the first spacer blocks on the substrate at least partially overlaps the first protruding part. The first spacer blocks are connected with the first protruding part through vias. The orthogonal projection of the first touch metal blocks on the substrate at least partially overlaps the orthogonal projection of the second protruding part of one common electrode block in the touch unit on the substrate. The first touch metal blocks are connected with the second protruding part through vias. The orthogonal projection of the touch signal lines on the substrate is located outside the orthogonal projection of the sub-pixel areas on the substrate. The orthogonal projection of the touch signal lines on the substrate at least partially overlaps the orthogonal projection of the data lines on the substrate. The array substrate further comprises a plurality of pixel electrodes located on the side of the common electrode away from the substrate. The metal layer is located between the driving circuit layer and the common electrode, or the common electrode faces away from the substrate.

4. The array substrate of claim 3, wherein, The touch unit comprises a plurality of common electrode blocks arranged in an array, wherein at least two of the common electrode blocks are arranged along the first direction to form a column, and at least two of the common electrode blocks are arranged along the second direction to form a row. The common electrode blocks in adjacent two rows are connected by row connecting portions, and the common electrode blocks in adjacent two columns are connected by column connecting portions. The column connecting portion comprises an upper connecting portion connected to an upper region of the common electrode block and a lower connecting portion connected to a lower region of the common electrode block.

5. The array substrate of claim 4, wherein, The sub-pixel regions comprise red sub-pixel regions, green sub-pixel regions and blue sub-pixel regions, at least one red sub-pixel region, at least one green sub-pixel region and at least one blue sub-pixel region are arranged along the second direction to form a pixel unit region, and one pixel unit region corresponds to one common electrode block. The orthogonal projection of the row connecting portion on the substrate substrate is located between the orthogonal projections of the adjacent two sub-pixel regions corresponding to the common electrode block on the substrate substrate.

6. The array substrate of claim 5, wherein, The number of the first protruding portions is multiple, and when the adjacent two rows of common electrode blocks are connected, part of the first protruding portions are multiplexed as the row connecting portions.

7. The array substrate of claim 2, wherein, In the second direction, the orthogonal projection of part of the data lines on the substrate substrate is located within the orthogonal projection of the touch signal line on the substrate substrate.

8. The array substrate of claim 7, wherein, In the second direction, the width of the touch signal line is 5.2-6.2μm, and the width of the data line is 2.5-3.5μm.

9. The array substrate of claim 3, wherein, The metal spacer block comprises a first edge, a second edge and a third edge connected in sequence, the second edge and the third edge are located on one side of the first edge along the first direction and are parallel to the first edge, the distance between the second edge and the first edge is greater than the distance between the third edge and the first edge, and the orthogonal projection of the connection hole of the metal spacer block and the common electrode block on the substrate substrate is located between the orthogonal projections of the first edge and the second edge on the substrate substrate.

10. The array substrate of claim 9, wherein, The size of the metal spacer block in the second direction is 16-17μm, the distance between the first edge and the second edge is 11.6-12.6μm, and the distance between the first edge and the third edge is 9.2-10.2μm.

11. The array substrate of claim 5, wherein, The orthogonal projection of the touch signal line on the substrate substrate is located between the orthogonal projections of the red sub-pixel region and the blue sub-pixel region on the substrate substrate.

12. The array substrate of claim 1, wherein, The driving circuit layer further comprises: a gate layer provided on one side of the substrate substrate, the scan line and the gate layer are provided in the same layer, the gate layer comprises a gate, and the scan line is connected with the gate; a gate insulating layer provided on the side of the gate layer away from the substrate substrate, the gate insulating layer covers the surface of the gate layer; an active layer provided on the side of the gate insulating layer away from the substrate substrate; a source-drain layer comprising a source electrode covering one end of the active layer and a drain electrode covering the other end of the active layer, the data line and the source-drain layer are provided in the same layer, and the data line is connected with the drain electrode.

13. The array substrate of claim 12, wherein, A projection of the metal block on the substrate substrate covers a gap between a projection of the source electrode and a projection of the drain electrode on the substrate substrate.

14. The array substrate of claim 3, wherein, The array substrate further comprises: a signal lead wire disposed on one side of the substrate substrate and located in the peripheral area, comprising a data lead wire and a scan lead wire, the data lead wire being connected with the data line and arranged in the same layer, and the scan lead wire being arranged in the same layer with the scan line; a touch lead wire disposed on one side of the substrate substrate and located in the peripheral area, the touch lead wire being connected with the touch signal line and arranged in the same layer; wherein a projection of the data lead wire, the scan lead wire and the touch lead wire on the substrate substrate at least partially overlaps.

15. The array substrate of claim 14, wherein, The peripheral area comprises a binding area; the array substrate further comprises: a pad disposed on one side of the substrate substrate and located in the binding area, the pad comprising a first pad, a second pad and a third pad; wherein the first pad is connected with the data lead wire, the first pad comprising a first conductive layer and a second conductive layer, the first conductive layer being arranged in the same layer with the data line, and the second conductive layer being arranged in the same layer with the pixel electrode, the second conductive layer being connected with the first conductive layer through a via hole; the second pad is connected with the scan lead wire, the second pad comprising a third conductive layer and a fourth conductive layer, the third conductive layer being arranged in the same layer with the scan line, and the fourth conductive layer being arranged in the same layer with the pixel electrode, the fourth conductive layer being connected with the third conductive layer through a via hole; the third pad is connected with the touch lead wire, the third pad comprising a fifth conductive layer and a sixth conductive layer, the fifth conductive layer being arranged in the same layer with the touch signal line, and the sixth conductive layer being arranged in the same layer with the pixel electrode, the sixth conductive layer being connected with the fifth conductive layer through a via hole.

16. A manufacturing method of an array substrate, characterized by, comprises: a substrate substrate is provided, the substrate substrate comprises a display area and a peripheral area located periphery of the display area; a driving circuit layer is formed on one side of the substrate substrate, the driving circuit layer is located in the display area, comprising a plurality of data lines and a plurality of scan lines, a plurality of the data lines extend along a first direction and are arranged at intervals along a second direction, a plurality of the scan lines extend along the second direction and are arranged at intervals along the first direction, the second direction and the first direction intersect, and the data lines and the scan lines intersect each other to define a plurality of sub-pixel areas; a metal layer is formed on the side of the driving circuit layer away from the substrate substrate, the metal layer is located in the display area, the metal layer comprises a plurality of spaced-apart metal blocks, the metal blocks are located at the intersections of the data lines and the scan lines; the metal layer further comprises a plurality of touch signal lines, the metal blocks comprise touch connection metal blocks and metal spacer blocks, the touch connection metal blocks are connected with the touch signal lines, and there is a spacing between the metal spacer blocks and the touch signal lines; The method further comprises: forming a common electrode on a side of the drive circuit layer away from the substrate, the common electrode comprising a plurality of spaced touch units, each of the touch units comprising a plurality of mutually connected common electrode blocks; the touch connection metal block comprises a first touch metal block and a second touch metal block, the touch signal line is connected to one of the common electrode blocks in the touch unit through the first touch metal block, and the second touch metal block is not connected to the common electrode block; the metal spacer block is connected to the common electrode block through a via hole; The common electrode block comprises a main body and a first protruding portion and a second protruding portion connected to one side of the main body, the first protruding portion is connected to the middle of one side of the main body, and the orthographic projection of the first protruding portion on the substrate is located between the orthographic projections of the corresponding adjacent two sub-pixel regions of the common electrode block on the substrate, and the second protruding portion is connected to the corner of the main body; the metal spacer block comprises a first spacer block, the orthographic projection of the first spacer block on the substrate at least partially overlaps the first protruding portion, and the first spacer block is connected to the first protruding portion through a via hole; the orthographic projection of the first touch metal block on the substrate at least partially overlaps the orthographic projection of the second protruding portion of one of the common electrode blocks in the touch unit on the substrate, and the first touch metal block is connected to the second protruding portion through a via hole.

17. A display panel, characterized by Comprise: The array substrate of any one of claims 1-15; A color filter substrate arranged on one side of the array substrate; A plurality of spacers arranged between the array substrate and the color filter substrate, the spacers corresponding one-to-one to the metal blocks, and at least half of the orthographic projection of the top end of the spacer on the substrate is located within the orthographic projection of the metal block on the substrate; A liquid crystal layer arranged between the array substrate and the color filter substrate.

18. The display panel of claim 17, wherein, The sub-pixel regions comprise red sub-pixel regions, blue sub-pixel regions, and green sub-pixel regions, and the spacers comprise main spacers, the orthographic projection of the main spacer on the substrate being located between the orthographic projections of the red sub-pixel regions and the blue sub-pixel regions on the substrate.

19. A display panel, characterized by Comprise: The array substrate of claim 12 or 13; A color filter substrate arranged on one side of the array substrate; A plurality of spacers arranged between the array substrate and the color filter substrate, the spacers corresponding one-to-one to the metal blocks, and at least half of the orthographic projection of the top end of the spacer on the substrate is located within the orthographic projection of the metal block on the substrate; A liquid crystal layer arranged between the array substrate and the color filter substrate; The orthographic projection of the spacer on the substrate at least partially overlaps the gap between the orthographic projections of the source and the drain on the substrate.

20. A display device comprising: The display panel of any one of claims 17-19.

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