Assessing background leakage to select write voltage in memory devices

Abstract

A memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage for application to the memory cells when performing a program operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage as a normal or default voltage, and a second write voltage as an elevated write voltage. The controller applies a pre-sense voltage and a pre-read voltage to the memory cells, and determines first and second respective currents resulting from the application of these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold greater than the first threshold (indicating the memory cells are not toggling), the controller selects the second (elevated) write voltage.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 167,618, filed February 4, 2021, entitled “Evaluation of Background Leakage to Select Write Voltage in Memory Devices,” the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to memory devices, and more specifically (but not limited to) evaluating background leakage to select memory devices for applying write voltages to memory cells when performing write operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device typically has two states, usually represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for a long time even without an external power supply. Volatile memory cells can lose their stored state over time unless they are periodically refreshed by an external power supply.

[0006] A storage device is an example of a memory device. A typical computer storage device has a controller that receives data access requests from a host computer and performs programmed computational tasks to implement the requests in a manner specific to the media and structure configured within the storage device. In one example, the memory controller manages the data stored in the memory and communicates with the computer device. In some examples, the memory controller is used in solid-state drives in mobile devices or laptop computers, or in media in digital cameras.

[0007] Firmware can be used to operate the memory controller of a specific storage device. In one instance, a computer system or device communicates with the memory controller when reading data from or writing data to the memory device.

[0008] Memory devices typically store data in memory cells. In some cases, memory cells exhibit non-uniform variable electrical characteristics that can arise from a variety of factors, including statistical process variations, cyclic events (e.g., read or write operations on the memory cell), or drift (e.g., changes in the resistance of chalcogenide alloys).

[0009] In one instance, the set of data (e.g., codewords, pages) is read by determining the read voltage (e.g., the median of a threshold voltage) of the memory cell storing the set of data. In some cases, the memory device may include an array of PCM cells arranged in a 3D architecture (e.g., a crosspoint architecture for storing a set of data). The PCM cells in the crosspoint architecture may represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages. In some cases, encoding (e.g., error correction encoding (ECC)) may be used to store data to recover data from errors in the data stored in the memory cell.

[0010] For a variable resistance memory cell (e.g., a PCM cell), one of several states (e.g., a resistance state) can be configured. For example, a single-level cell (SLC) can be programmed to be one of two states (e.g., logic 1 or 0), depending on whether the cell is programmed to be a resistance above or below a specific level. As an additional example, various variable resistance memory cells can be programmed to be one of several different states corresponding to multiple data states, such as 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc. Such cells may be referred to as multi-state cells, multi-digit cells, and / or multi-level cells (MLCs).

[0011] The state of a variable-resistance memory cell can be determined by sensing the current flowing through the cell in response to an applied interrogation voltage (e.g., reading). The sensed current, which varies based on the cell's resistance, can indicate the cell's state (e.g., the binary data stored in the cell). The resistance of a programmed variable-resistance memory cell can drift (e.g., shift) over time. Resistance drift can lead to erroneous sensing of the variable-resistance memory cell (e.g., determining that the cell is in a state different from its programmed state, and other problems).

[0012] For example, a PCM cell can be programmed into a reset state (amorphous state) or a set state (crystalline state). A reset pulse (e.g., a pulse used to program the cell into a reset state) can consist of a relatively high current pulse applied to the cell over a relatively short time interval, causing the phase change material of the cell to melt and rapidly cool, resulting in a relatively small amount of crystallization. Conversely, a set pulse (e.g., a pulse used to program the cell into a set state) can consist of a relatively low current pulse applied to the cell over a relatively long time interval and having a slower quenching rate (which leads to increased crystallization of the phase change material).

[0013] A programming signal can be applied to a selected memory cell to program the cell to a target state. A read signal can be applied to a selected memory cell to read the cell (e.g., to determine the state of the cell). For example, the programming signal and the read signal can be current and / or voltage pulses. Attached Figure Description

[0014] The embodiments are illustrated by way of example rather than limitation in the accompanying drawings, wherein similar element symbols indicate similar elements.

[0015] Figure 1 This paper demonstrates an evaluation background leak based on some embodiments to select a memory device for the write voltage applied to a memory cell during a write operation.

[0016] Figure 2 A voltage driver is shown to drive the voltage distribution applied to a memory cell according to some embodiments.

[0017] Figure 3 A memory device configured with a driver to implement voltage distribution is shown according to some embodiments.

[0018] Figure 4 A memory cell having a bit line driver and a word line driver configured to implement voltage distribution is shown according to some embodiments.

[0019] Figure 5 This demonstrates a series of voltage pulses applied to a memory cell according to some embodiments.

[0020] Figure 6 Examples of memory cells including selection devices according to some embodiments are shown.

[0021] Figure 7 This paper demonstrates a method, according to some embodiments, for evaluating background leakage to select the write voltage to be applied to a memory cell during a write operation. Detailed Implementation

[0022] The following disclosure describes various embodiments of a memory device for evaluating background leakage to select the write voltage applied to a memory cell during a write operation. At least some of the embodiments herein relate to memory devices exhibiting background leakage attributable to memory cells in the memory array other than the target memory cell to be programmed.

[0023] In some cases, the memory device may include an array of memory cells arranged in a 3D architecture (e.g., a cross-point architecture for storing a set of data). The memory cells in the cross-point architecture may represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0024] In one instance, the memory device stores data used by a host device (e.g., a computing device in an autonomous vehicle or another computing device that accesses data stored in the memory device). In another instance, the memory device is a solid-state drive installed in an electric vehicle.

[0025] In one example, the memory device exhibiting background leakage uses bipolar operation on the memory array. In one example, a bipolar selection voltage is used to select the memory cells of the memory array. In one example, the memory cells of the memory device are arranged in a cross-point architecture. In one example, each memory cell is formed using a single selection device. In one example, the selection device comprises a chalcogenide material. Other types of memory devices may exhibit background leakage.

[0026] Background leakage can negatively impact write operations by requiring higher write voltages to offset the losses caused by it. In one instance, background leakage is caused by memory cells that share the same word lines and / or bit lines as the target memory cell to be programmed. Background leakage is the sum of the subthreshold currents of background memory cells (cells other than the target cell) that occur when the word lines and / or bit lines shared with the target cell are biased.

[0027] For example, background leakage can be caused by any of several reasons. In some cases, memory cells are in good operating conditions, but many cells are in a set state with low threshold voltages, resulting in a high sum of subthreshold currents (which can negatively impact write operation reliability by increasing write errors). In other cases, some memory cells are relatively "short" (e.g., more conductive due to defects and / or other reasons). These cells have high subthreshold currents, or in some cases, can even be skipped by applying partial bias voltage to the word line or bit line. Such cells can significantly contribute to leakage current affecting the main sensing circuitry.

[0028] In one example, a large number of memory cells serving as the background for target bits are written to a set state with a low threshold voltage via a programming operation. This can lead to high background leakage when programming target bits. Therefore, a higher write voltage is required (e.g., to program target bits in a reset state with a high threshold voltage, which requires a high write voltage to overcome the high background leakage). However, using a static or fixed high write voltage as the default voltage to program all target bits in the memory array is wasteful of power, as most target bits can typically be reliably programmed using a lower write voltage.

[0029] In one instance, the memory device comprises a stacked memory array. As the degree of stacking and / or lateral scaling increases (where a larger number of bits share the same wires), background leakage can become significant. Furthermore, background leakage can vary significantly between a severe extreme case (the most challenging target bit to program) and a more optimistic case (a more typical target bit that is easier to program). The severe extreme case corresponds to operating on the target bit after all or most of the relevant background memory cells have been refreshed (e.g., rewritten to a low threshold voltage set state, making the leakage current through each background memory cell high). The optimistic case corresponds to a significant period of time in which the background memory cells have drifted (leading to an increased threshold voltage). To cover the extreme case when using a static write voltage, a relatively “strong” select / write strength is needed to handle the current delivery problem caused by background leakage. However, this presents a technical problem of wasted power because the conditions of the severe extreme case do not apply in most cases of programming typical target memory cells.

[0030] Given the above, background leakage presents a technical problem where higher write voltages must be applied to the bias word lines and / or bit lines to overcome background leakage and perform successful write operations with an acceptable error rate. This may require the use of high static / fixed write voltages. However, using higher write voltages is wasteful of power because higher write voltages are only occasionally needed to cover the extreme cases where background leakage is high. If background leakage is low (as is typically the case for most target memory cells in a memory array), then higher static write voltages result in excessive and unnecessary power consumption of the memory device.

[0031] Furthermore, in some cases, the aforementioned conditions can significantly degrade the durability and performance of a memory device due to higher voltage cycling of the memory cells, potentially leading to the memory device failing to operate correctly. Consequently, systems using data from the memory device may malfunction. For example, a vehicle using the data to control a vehicle may be involved in a collision, resulting in physical damage or injury.

[0032] To address these and other technical issues, memory devices evaluate background leakage to dynamically select the write voltage applied to the target memory cell during a write operation. In various embodiments, a pre-sensing step is performed in addition to a pre-read step during a write operation. The pre-sensing step is used to evaluate background leakage.

[0033] In one embodiment, if background leakage is determined to meet at least one criterion (e.g., current sensor and / or other collected data associated with leakage is greater than a threshold), then the controller of the memory device dynamically increases the write voltage used to program each target memory cell with a leaky background memory cell. The controller is configured to program each of the memory cells in the memory array by applying the write voltage. The controller selects the write voltage for programming based on various criteria, including an assessment of background leakage. The write voltage may be a default voltage typically applied to memory cells that do not exhibit significant background leakage. If significant background leakage is determined by the controller, then the controller selects an increased write voltage with an amount greater than the default normal write voltage.

[0034] The advantages provided by the various embodiments described herein for memory devices that evaluate background leakage to select write voltages include one or more of the following: Reduced power consumption of the memory device; the memory controller can dynamically customize the amount of write voltage applied to the memory cell as part of a write operation; the bit line write voltage can be reduced for typical cases and increased if background leakage is determined to be above a threshold; and increased endurance of the memory device (e.g., due to lower voltage cycling of the memory cells).

[0035] In one embodiment, the controller programs each memory cell in the memory array by selecting a first write voltage (e.g., a default write voltage) or a second write voltage (e.g., an elevated write voltage) to be applied to the respective memory cell. The magnitude of the second write voltage is greater than the first write voltage.

[0036] When programming a specific first memory cell in the memory array, the controller applies a pre-sensed voltage to the first memory cell. When performing a write operation by applying a write voltage to the memory cell, the polarity of the pre-sensed voltage remains the same as the polarity of the subsequent select / write voltage. A first current originating from the applied pre-sensed voltage is sensed. The controller determines whether the first current exceeds a first threshold.

[0037] The controller applies a prefetch voltage to the first memory cell. Typically, the prefetch voltage is applied after the presensing voltage (but in some cases, this order may be reversed). A second current is sensed from the applied prefetch voltage. The controller determines whether the second current is below a second threshold greater than a first threshold. In response to determining that the first current exceeds the first threshold (e.g., background is flagged as potentially leaking) and that the second current is below the second threshold (e.g., the target memory cell to be programmed is not transitioning and is in a reset state), the controller programs the first memory cell by applying a second write voltage.

[0038] In one embodiment, when programming is performed in normal write mode, the memory device uses a pre-sensing step prior to a pre-read step. In the pre-sensing step, a voltage bias is applied to the memory cell via one or more voltage drivers. A current sensor determines whether the resulting current through the memory cell is greater than a target pre-sensed current amplitude. If so, the controller determines that there is potentially significant background leakage. A flag is set in the controller to indicate potentially high background leakage.

[0039] The prefetch step is used to determine the logic state of a memory cell and whether a write operation is needed to change the cell's state to a new target logic state. A prefetch voltage is applied to the memory cell, and a current sensor determines whether the current flowing through the memory cell is greater than the target prefetch current amplitude. The target prefetch current amplitude is lower than the target prefetch current amplitude.

[0040] The dynamic increase in write voltage based on assessing background leakage, as described herein, can be performed in both unipolar and bipolar memory devices. In one example of a unipolar memory device, each memory cell includes a phase change material and a selection device, and the memory cells are arranged in a three-dimensional cross-point architecture. In one example of a bipolar memory device, each memory cell includes a chalcogenide as part of the selection device (SD). In one example, each memory cell further includes a top electrode (e.g., carbon) above the chalcogenide and a bottom electrode (e.g., carbon) below the chalcogenide.

[0041] In one example, the bipolar memory device includes memory cells, each containing a chalcogenide as a logic storage element. The pre-sensing voltage and the write voltage have the same polarity. In one example, the pre-read voltage has a negative polarity, and the corresponding write voltage has a positive polarity. The pre-sensing voltage and the pre-read voltage are applied to each memory cell in the memory array before the write voltage is applied to program the memory cell as part of the programming operation.

[0042] In one example of a bipolar memory device, a bipolar read operation can be performed by the memory device. For this device, two cases can each present extreme scenarios, where the select / write strength is increased to overcome any significant background leakage detected. The first case is a reset-on-write operation, and the second case is a set-on-reset write operation.

[0043] In the first scenario, the target memory cell is currently in a reset state, and the desired target state is a set state. A pre-sensing read is performed in the same direction as the set write pulse. If the resulting current exceeds a pre-sensing current threshold, a flag indicating potential background leakage is set. Next, a pre-fetch voltage is applied to determine the state of the memory cell. In response to the flag being set and the pre-fetch returning to a reset logic state, the controller selects a stronger select / write voltage to program the memory cell. Conversely, if either pre-sensing step detects a low current below a threshold, or if the pre-fetch step indicates that the memory cell is already in a set state, the controller does not increase the select / write voltage.

[0044] In the second scenario, the target memory cell is currently in an set state, and the desired target state is a reset state. A pre-sensing read is performed in the same direction as the reset write pulse. If the resulting current exceeds the pre-sensing current threshold, a flag indicating potential background leakage is set. Next, a pre-fetch voltage is applied to determine the state of the memory cell. In response to the flag being set and the pre-fetch returning to a set logic state, the controller selects a stronger select / write voltage to program the memory cell. Conversely, if either pre-sensing step detects a low current below the threshold, or if the pre-fetch step indicates that the memory cell is already in a reset state, the controller does not increase the select / write voltage.

[0045] Figure 1 This illustration describes a memory device 101 for evaluating background leakage according to some embodiments to select the write voltage applied to memory cells 110, 112 of memory array 102 during write operations. The memory device 101 has a memory controller 120 that applies pre-sensed and pre-read voltages as part of a write operation, as described above. The memory controller 120 includes one or more processing devices 116 and a memory 118. In one example, the memory 118 stores firmware executed by the processing device 116 to apply the pre-sensed and pre-read voltages (and write voltages, as described below).

[0046] The memory controller 120 may use a bias circuit system 124 to generate voltages for applying pre-sensing and pre-read voltages. The bias circuit system 124 may also generate voltages for applying write voltages to memory cells 110, 112 as part of a programming operation. In one embodiment, the bias circuit system 124 is implemented by one or more voltage drivers. The bias circuit system 124 may further be used to generate read voltages for read operations performed on the memory array 102 (e.g., in response to a read command from the host device 126).

[0047] Memory device 101 includes a sensing circuitry system 122 for sensing the state of each memory cell in memory array 102. In one example, the sensing circuitry system 122 includes a current sensor (e.g., a sensing amplifier) ​​for detecting the current caused by applying various pre-sensing and pre-read voltages to the memory cells in memory array 102. In one example, a bias circuitry system 124 applies pre-sensing and pre-read voltages to memory cells 110. The sensing circuitry system 122 senses the current associated with each of the memory cells 110 caused by applying a pre-sensing or pre-read voltage. In one example, the pre-sensing or pre-read voltage is applied as described above.

[0048] In one instance, if the sensing circuitry 122 determines that the corresponding current originating from applying a pre-sensed voltage to a memory cell is greater than a fixed threshold (e.g., a predetermined level of current or a threshold current), then the memory controller 120 determines that background leakage may occur and sets a flag stored in the memory 118.

[0049] In one instance, if the sensing circuitry 122 determines that the current originating from the application of the prefetch voltage to the memory cell is greater than a corresponding fixed threshold (e.g., a predetermined level of current or a threshold current), then the memory controller 120 determines that the memory cell has switched.

[0050] In one embodiment, memory cells 110 and 112 correspond to different memory types (e.g., single-level cells or three-level cells). In one example, the materials used to form the selection means for each memory cell are different. The pre-sensing and / or pre-fetch voltage applied to memory cell 110 corresponds to the material used to form memory cell 110. The pre-sensing and / or pre-fetch voltage applied to memory cell 112 is different and corresponds to the material used to form memory cell 112.

[0051] In one embodiment, memory controller 120 receives a write command from host device 126. The write command is accompanied by data to be written to memory array 102 (e.g., user data of a user of host device 126). In response to receiving the write command, controller 120 initiates a programming operation by applying pre-sensing and pre-read voltages to memory cells 110. Controller 120 determines the corresponding current originating from the applied pre-sensing and pre-read voltages.

[0052] Next, controller 120 determines the specific memory cell 110 to which a write voltage will be applied to program the memory cell. In one embodiment, controller 120 determines whether the existing programming state (e.g., logic state zero) of each cell is equal to the target programming state (e.g., logic state zero). If the existing programming state is equal to the target programming state, then no write voltage is applied (e.g., this is normal write mode). If the existing programming state is different from the target programming state, then a write voltage is applied to the specific memory cell. In one example, a write voltage of 3 to 8 volts is applied across the memory cell by applying voltage bias to the word line and bit line used to select the cell. In one example, in the case of a chalcogenide memory cell, a write voltage of a first polarity is applied to program the cell to a first logic state (e.g., set state), and a second write voltage of the opposite polarity is applied to program the cell to a second different logic state (e.g., reset state).

[0053] In one embodiment, a forced write operation is performed where a specific memory cell is programmed to a target programmed state, regardless of whether the memory cell has transitioned. In one instance, a forced write is performed to make the memory cell more robust in its ability to reliably store the target logical state.

[0054] In one example, controller 120 may use a write voltage (e.g., a write pulse) to write logic state to a memory cell, such as memory cells 110, 112, during a write operation. The write pulse can be applied by providing a first voltage to a bit line and a second voltage to a word line to select the memory cell. Circuitry coupled to the memory cell and its access lines may be used to provide the write voltage (e.g., access line drivers included in decoder circuitry). The circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The resulting voltage applied to the memory cell is the difference between the first voltage and the second voltage. In some embodiments, the write pulse may be of the same duration as the read pulse. In some embodiments, the duration is 10 to 50 ns. In some embodiments, the duration is 1 to 100 ns. In some embodiments, the duration is 1 ns to 1 microsecond. In some embodiments, writing to the memory cell may take the same amount of time as reading from the memory cell.

[0055] In one instance, the polarity of the write pulse can be a first polarity or a second polarity (e.g., positive or negative). For example, the write pulse can apply a voltage to the memory cell with the first polarity (e.g., 6V for the bit line and 0V for the word line).

[0056] In one example, circuitry coupled to the access lines to the memory cell is used to provide read pulses (e.g., access line drivers included in decoder circuitry). The circuitry can be controlled by internal control signals provided by control logic (e.g., controller 120). The read voltage or pulse can be a voltage applied to the memory cell over a period of time (e.g., 10 to 50 ns, 1 to 100 ns, 1 ns to 1 microsecond). In some embodiments, the read pulse can be a square pulse. In some embodiments, the read pulse can be a ramp, that is, a linearly increasing voltage can be applied across the memory cell.

[0057] In one instance, for a chalcogenide memory cell, the read voltage is always applied with the same fixed polarity. In another instance, the prefetch voltage has the same polarity, and the read voltage has the opposite polarity to the prefetch voltage.

[0058] In one example, a pre-fetch step is performed after the pre-sensing step. After being accessed (e.g., selected), the memory cell is read or sensed by a current sensor (e.g., sensing circuitry 122) to determine the memory cell's storage state. For example, a voltage may be applied to the memory cell (using word lines and bit lines), and the presence of the resulting current may depend on the applied voltage and the memory cell's threshold voltage. In some cases, more than one voltage may be applied. Additionally, if the applied voltage does not cause current flow, other voltages may be applied until current is detected by the current sensor. By evaluating the voltage that causes current flow, the stored logic state of the memory cell can be determined. In some cases, the voltage magnitude may ramp up until current flow is detected (e.g., the memory cell is turned on, activated, conducts current, or becomes active). In other cases, predetermined voltages may be applied sequentially until current is detected. Similarly, current may be applied to the memory cell, and the magnitude of the voltage used to create the current may depend on the memory cell's resistance or threshold voltage.

[0059] In some cases, memory cells (e.g., PCM cells) contain materials that can change their crystalline configuration (e.g., between a crystalline phase and an amorphous phase), which in turn determines the threshold voltage of the memory cell used to store information. In other cases, memory cells contain materials that remain in a crystalline configuration (e.g., an amorphous phase) and that can exhibit a variable threshold voltage to store information.

[0060] Current sensors can incorporate various transistors or amplifiers to detect and amplify signal differences. The detected logic state of the output memory cell can then be used as an output via a column decoder. In some cases, the sensing component can be part of either a column decoder or a row decoder.

[0061] Figure 2 A voltage driver 203 is shown to drive a voltage distribution applied to memory cell 201 according to some embodiments. As described above, voltage driver 203 is configured to drive a voltage applied to memory cell 201 during a pre-sensing or pre-fetching step. In one embodiment, voltage driver 203 is implemented by a plurality of voltage drivers. In one example, a portion of the voltage drivers is a bit line driver, and another portion of the voltage drivers is a word line driver. Voltage driver 203 is an example of bias circuit system 124. Memory cell 201 is an example of memory cells 110, 112.

[0062] When a pre-sensing voltage is applied to memory cell 201, current sensor 207 determines the current originating from the applied pre-sensing voltage. In one example, voltage driver 203 applies the pre-sensing voltage by driving the bit line to a positive voltage and the word line to a negative voltage. Voltage driver 203 may similarly apply a pre-fetch voltage to memory cell 201. Current sensor 207 is an example of sensing circuitry system 122.

[0063] After applying the prefetch voltage, when the voltage applied to memory cell 201 is higher than the threshold voltage of the programmed cell, current sensor 207 is configured to determine whether memory cell 201 is conductive based on the current traveling through memory cell 201. If current sensor 207 detects the amount of current corresponding to the programmed cell, then memory cell 201 is determined to be programmed as a set cell with a low voltage threshold (corresponding to data different from data represented by a reset cell with a high voltage threshold). If current sensor 207 does not detect the amount of current corresponding to the programmed cell, then memory cell is determined to be a reset cell corresponding to predetermined data represented by a high voltage threshold (e.g., a cell that has not been programmed after a reset or erase operation, or a cell that has been programmed to have a high voltage threshold).

[0064] Figure 3 A memory device is shown, according to some embodiments, configured with a driver to drive voltages on access lines for selecting memory cells in memory array 333. For example, Figure 2 The memory cell 201 described herein can be used in memory cell array 333.

[0065] Figure 3 The memory device includes a controller 331 that operates bit line drivers 337 and word line drivers 335 to access individual memory cells (e.g., 201) in the array 333. The controller 331 is an example of a memory controller 120. The memory array 333 is an example of a memory array 102.

[0066] Bit line driver 337 and / or word line driver 335 may be derived from, for example Figure 2 This is implemented using the voltage driver 203 described herein. In one example, each memory cell (e.g., 201) in array 333 can be accessed via a voltage driven by a pair of bit line drivers and word line drivers, as described in Figure 4 As explained in the text.

[0067] Figure 4A memory cell 401, according to some embodiments, is shown having a bit line driver 447 and a word line driver 445 configured to apply voltages to memory cells. For example, the bit line driver 447 drives a first voltage applied to a row of memory cells in array 333; and the word line driver 445 drives a second voltage applied to a column of memory cells in array 333. The memory cells 401 in the rows and columns of memory cell array 333 experience a voltage difference between the first voltage driven by the bit line driver 447 and the second voltage driven by the word line driver 445. When the first voltage is higher than the second voltage, the memory cell 401 experiences one voltage polarity (e.g., positive polarity); and when the first voltage is lower than the second voltage, the memory cell 401 experiences the opposite voltage polarity (e.g., negative polarity).

[0068] For example, when memory cell 401 is configured to be prefetched with a positive voltage polarity, bit line driver 447 can be configured to drive a positive voltage.

[0069] For example, when memory cell 401 is configured to be prefetched with a negative voltage polarity, word line driver 445 can be configured to drive a positive voltage.

[0070] For example, during a write operation, both bit line driver 447 and word line driver 445 can drive voltages of different magnitudes (e.g., to perform pre-sensing, pre-reading, and write steps). For instance, bit line driver 447 can be configured to drive positive voltages of different magnitudes; and word line driver 445 can be configured to drive negative voltages of different magnitudes. The difference between the voltage driven by bit line driver 447 and the voltage driven by word line driver 445 corresponds to the voltage applied to memory cell 401.

[0071] In one example, bit line driver 337 can be used to drive parallel wires (e.g., 441) arranged in one direction and disposed in one layer of the crosspoint memory; and word line driver 435 can be used to drive parallel wires (e.g., 443) arranged in another direction and disposed in another layer of the crosspoint memory. Wires (e.g., 441) connected to bit line driver (e.g., 447) and wires (e.g., 443) connected to word line driver (e.g., 445) extend in the two layers in orthogonal directions. Memory cell array 333 is sandwiched between the two layers of wires; and memory cells (e.g., 401) in array 333 are formed at the intersection of two wires (e.g., 441 and 443) in the integrated circuit die of the crosspoint memory.

[0072] Figure 5A series of voltage pulses applied to memory cells according to some embodiments are illustrated. In one example, voltage pulses are applied to memory cells 110, 112 of memory array 102. In one example, voltage pulses are applied to memory cells 201 or 401. In one example, voltage pulses are generated by bias circuitry system 124. In one example, voltage pulses are driven by voltage driver 203.

[0073] In one embodiment, the voltage pulse includes a pre-sensing voltage 502, a pre-read voltage 504, and a write voltage 506. The write voltage 506 may be, for example, a first write voltage or a second write voltage (e.g., selected by a controller or voltage driver). The first write voltage is a default or normal write voltage. The first write voltage is applied using bit line bias 510 and word line bias 512. The second write voltage is an elevated write voltage. The second write voltage is applied using bit line bias 508 and word line bias 514, such that the total voltage applied to the memory cell has a larger value.

[0074] In one embodiment, the controller selects a first write voltage or a second write voltage based on feedback from applying a pre-sensing voltage 502 and a pre-read voltage 504 to the memory cell. In one embodiment, the feedback is provided by a current sensor. In one example, the current sensor is current sensor 207. In one example, the controller is a memory controller 120 that selects a second write voltage in response to determining, based on feedback from applying the pre-sensing voltage 502, that the background is leaking and further that the memory cell is not fluctuating and is in a reset state.

[0075] In one embodiment, the voltage driver selects a first write voltage or a second write voltage based on feedback. In one example, the voltage driver is voltage driver 203. In one example, the voltage driver is bit line driver 337 and / or word line driver 335. In one example, the voltage driver is implemented in a CMOS circuitry system beneath a stacked memory array.

[0076] In one instance, Figure 5 The bit line bias is applied by bias circuitry 124 or bit line driver 447. In one example... Figure 5 The word line bias is applied by the bias circuit system 124 or the word line driver 445.

[0077] In one embodiment, the write voltage 506 is a series of voltage pulses applied to change the voltage of the memory cell. In one instance, the set / reset write pulses are used to crystallize / amorphize the memory cell. In another instance, the set / reset write pulses are used to switch cells in different polarities to create different polarization states (e.g., polarization caused by polarization effects).

[0078] In one instance, using Figure 5 A series of voltage pulses are used to perform a reset-time set write operation, which changes the state of the voltage threshold of the memory cell from high (indicating "reset" with bit value 0) to low (indicating "set" with bit value 1).

[0079] In one instance, using Figure 5 A series of voltage pulses are used to perform a reset-time set-write operation, which causes the opposite change, where the voltage threshold moves from low (indicating "set" or 1) to high (indicating "reset" or 0).

[0080] In one instance, other cases may include reset-on-write operations and set-on-write operations. In both cases, the state of the memory cell's voltage threshold does not change significantly. Write pulses are typically not used.

[0081] In one instance, once a memory cell transitions, the current flowing through the memory cell jumps to a high level; and the high voltage on the memory cell cannot be maintained. The voltage on the memory cell drops (the transition occurs). Once the memory cell transitions, the non-overlapping voltage bias (biased at the target bit) drops.

[0082] In one embodiment, the write voltage 506 is selected based on the location of the memory cells in the memory array. For example, the drift may vary for different regions in the memory array. The amount of boost applied to the write voltage 506 may vary based on the location of the memory cells. In one instance, the boost to be applied may be determined by a lookup table in the memory of the controller or voltage driver, which defines the level of boost for each memory array location.

[0083] In one embodiment, the write voltage 506 is selected to have a variable value that depends on the degree of background leakage, as determined from feedback from the pre-sensing voltage 502.

[0084] In one embodiment, the write voltage 506 is selected based on the degree of error in the operation, as determined by the controller. In one instance, the controller determines the error rate associated with read and / or write operations. Based on the error rate, the controller can adjust the boost level applied to the write voltage 506.

[0085] In one instance, background leakage is attributed to the sum of currents from background memory cells sharing bit lines and / or word lines with the target memory cell. The feedback measured by a current sensor is this sum of currents. In one instance, the current sensor may measure the sum of currents from both the bit lines and word lines and add them together, or logically OR either of these sums to determine if it is above a threshold. When the applied voltage is below the expected threshold for the memory cell at the bit line and word line, the measurement is dominated by background leakage (and can therefore be considered an indicator of leakage). When a memory cell transitions at the bit line and word line, the measurement is dominated by the current of the transitioned memory cell (and can therefore be considered an indicator of the threshold level).

[0086] In one instance, only a portion (e.g., about half) of the voltage is applied to each bit line and word line to cause the memory cell to switch. Therefore, only the memory cell at the bit line and word line is selected or "addressed" because other cells sharing the bit line or word line will only receive a portion of the voltage required for the switch. If a memory cell on the same bit line (or word line) is "short" (defective) and switches at less than half the voltage, it has a switching current at low voltages that can promote background leakage.

[0087] In one instance, when background leakage is determined, it is necessary to apply a stronger "force" (higher voltage) to rewrite the state of the memory cell (but this is not necessary if the state of the memory cell will remain the same). Alternatively, if there is no background leakage (and therefore energy saving), then a typically lower voltage can be used for rewriting.

[0088] In one example, a pre-sensing voltage and a pre-fetch voltage are applied to memory cells 110 or 112 for write operations to memory array 102. In one example, the voltage is generated by a bias circuit system 124, such as that controlled by controller 120. In one example, memory cell 110 is a single-level cell (SLC). In one example, the pre-sensing voltage or pre-fetch voltage is the voltage difference applied across the memory cell from the voltage bias word line and voltage bias bit line used to select the cell.

[0089] In one instance, the pre-sensing or pre-read voltage is applied for a time ranging from 10 to 100 nanoseconds. In one instance, the applied pre-sensing or pre-read voltage is 50 to 600 millivolts. In one instance, the applied voltage is 100 to 300 millivolts. In one instance, the memory cell may be a multi-state cell, such as an MLC or a TLC.

[0090] In one embodiment, according to some embodiments, the programming state of a memory cell is determined by applying a prefetch voltage to the memory cell during a write operation. In one example, the memory cell is memory cell 110, and the prefetch voltage is implemented by memory controller 120.

[0091] In one example, a prefetch voltage is applied to a total of 100 memory cells. The current through each memory cell is sensed by a current sensor (e.g., a sense amplifier). Memory cells with current exceeding a fixed threshold are considered to be transitioning. Memory cells with current below the fixed threshold are not considered to be transitioning.

[0092] After determining the existing programming state of each memory cell as described above, the memory controller determines the programming mode for programming the memory cell. In one embodiment, a normal write programming mode is used. In this mode, the controller determines the target state for each memory cell.

[0093] In an example of normal write programming mode, the memory cell is in a reset state. For each such cell with a target set state, a write voltage is applied to the memory cell. For each such cell with a target reset state, no write voltage is applied to the cell.

[0094] In one embodiment, the controller determines to implement a forced write programming mode. In this mode, each memory cell is selected, and an appropriate programming write voltage is applied to the memory cell based on the target state. For example, even if the memory cell is already in an existing programmed reset state, the memory cell is programmed to the target reset state.

[0095] Figure 6 Examples of memory units 602 including selection devices 610 according to some embodiments are shown. In one example, the selection device 610 includes a chalcogenide. Memory unit 602 is an example of memory units 110, 112.

[0096] The top electrode 608 electrically connects the selector 610 to the bit line 604, and the bottom electrode 612 electrically connects the selector 610 to the word line 606. In one example, electrodes 608 and 612 are formed of carbon material.

[0097] In one example, the selection device 610 includes a chalcogenide (e.g., a chalcogenide material and / or a chalcogenide alloy). The threshold voltage nature of the selection device may be based on the polarity of the voltage applied to the memory cell.

[0098] In one example, a logic state can be written to memory cell 602, the logic state corresponding to one or more data bits. The logic state can be written to the memory cell by applying voltages of different polarities at different voltage and / or current values. The memory cell can be read by applying a voltage of a single polarity. The write and read protocols can utilize different threshold voltages derived from selection devices of different polarities. In one example, the memory cell may require short, relatively low power pulses for reading. The chalcogenide material of the selection device may or may not undergo a phase transition during read and / or write. In some cases, the chalcogenide material may not be a phase change material.

[0099] Figure 7 This illustrates methods, according to some embodiments, for evaluating background leakage to select the write voltage to be applied to a memory cell during a write operation. For example, Figure 7 The method can be found Figure 1 This is implemented in the system. In one example, the memory controller 120 evaluates background leakage (e.g., by applying one or more pre-sensed voltages to different memory cells and using sensing circuitry system 122 to monitor feedback current) to select the write voltage to be applied to memory cell 110 when a write operation is performed.

[0100] Figure 7 The method can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, Figure 7 The method comprises at least part of one or more processing devices (e.g., Figure 1 The processing device 116) and / or one or more voltage drivers (e.g., Figure 2 The voltage driver 203) is executed.

[0101] Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0102] At block 701, a pre-sensing voltage is applied to a memory cell of the memory array. In one example, the pre-sensing voltage is pre-sensing voltage 502. In one example, the memory cell is memory cell 201.

[0103] At box 703, a first current originating from an applied pre-sensor voltage is sensed. In one example, the first current is measured by current sensor 207.

[0104] At block 705, it is determined whether the first current exceeds a first threshold. In one example, this is determined by logic in memory controller 120 and / or voltage driver 203.

[0105] At box 707, a prefetch voltage is applied to the memory cell. In one example, the prefetch voltage is prefetch voltage 504.

[0106] At block 709, a second current originating from an applied pre-readout voltage is sensed. In one instance, the second current is measured by current sensor 207 (or a different current sensor than the one that measures the first current).

[0107] At block 711, it is determined whether the second current is lower than a second threshold. In one example, this is determined by logic in memory controller 120 and / or voltage driver 203.

[0108] At block 713, in response to determining that a first current exceeds a first threshold and a second current is below a second threshold, the write voltage applied to the memory cell is increased. In one example, the memory controller 120 selects the increased write voltage 506. In one example, voltages 508 and 514 are used to apply the increased write voltage.

[0109] In one embodiment, a system includes: a memory array (e.g., 102, 333) comprising memory cells; and a controller (e.g., 120) configured to: program each of the memory cells by applying a first write voltage (e.g., a default or normal write voltage 510, 512) or a second write voltage (e.g., an elevated write voltage 508, 514) to the respective memory cell, wherein the second write voltage is greater than the first write voltage; apply a pre-sensing voltage to a first memory cell of the memory array; sense a first current originating from the applied pre-sensing voltage; determine whether the first current exceeds a first threshold; apply a pre-read voltage to the first memory cell; sense a second current originating from the applied pre-read voltage; and determine whether the second current is below a second threshold, wherein the second threshold is greater than the first threshold. In response to determining that the first current exceeds the first threshold (e.g., potential background leakage) and determining that the second current is below the second threshold (e.g., the cell is not transitioning and is in a reset state), the first memory cell is programmed by applying the second write voltage.

[0110] In one embodiment, the first memory cell is in a first logic state corresponding to a first threshold voltage (e.g., a reset with high Vt), and programming the first memory cell includes programming the first memory cell to a second logic state corresponding to a second threshold voltage (e.g., a set with low Vt), and the second threshold voltage is lower than the first threshold voltage.

[0111] In one embodiment, the prefetch voltage is a first prefetch voltage, and the controller is further configured to: apply a pre-sensing voltage to a second memory cell; sense a third current originating from the application of the pre-sensing voltage to the second memory cell; determine whether the third current exceeds a first threshold (e.g., determine whether the second cell has background leakage); apply a second prefetch voltage to the second memory cell; sense a fourth current originating from the application of the second prefetch voltage to the second memory cell; and determine whether the fourth current is below a second threshold (e.g., determine whether the second cell has switched). In response to determining that the third current exceeds the first threshold (e.g., the background is marked as potentially leaking) and determining that the fourth current is not below the second threshold (e.g., the cell has switched and is in a set state), the second memory cell is programmed by applying a first write voltage (e.g., the write voltage does not increase).

[0112] In one embodiment, the second memory cell is in a first logic state corresponding to a first threshold voltage (e.g., a set state with low Vt), and programming the second memory cell includes programming the second memory cell to a second logic state corresponding to a second threshold voltage (e.g., a reset state with high Vt), and the second threshold voltage is greater than the first threshold voltage.

[0113] In one embodiment, the controller is further configured to: apply a pre-sensing voltage to a third memory cell; sense a fifth current originating from the application of the pre-sensing voltage to the third memory cell; determine whether the fifth current exceeds a first threshold (e.g., determine whether the background of the third cell is leaking); and, in response to determining that the fifth current does not exceed the first threshold (e.g., the background is not leaking), program the third memory cell by applying a first write voltage (e.g., the write voltage does not increase).

[0114] In one embodiment, the controller is further configured to apply a third prefetch voltage to the third memory cell to determine that the third memory cell is in a first logic state (e.g., set or reset). Programming the third memory cell involves programming the third memory cell to a second logic state opposite to the first logic state.

[0115] In one embodiment, the first memory cell includes a chalcogenide, a top electrode above the chalcogenide, and a bottom electrode below the chalcogenide.

[0116] In one embodiment, the pre-sensing voltage has the same polarity as the second write voltage.

[0117] In one embodiment, as part of the programming operation, a sense voltage and a pre-read voltage are applied to a first memory cell, and the programming operation is performed in response to the controller receiving a write command from the host device.

[0118] In one embodiment, a prefetch voltage is applied to determine the existing logic state of the first memory cell (e.g., reset), and the controller is further configured to compare a target logic state (e.g., set) of the first memory cell with the existing logic state. Programming the first memory cell is a further response to determining that the target logic state differs from the existing logic state.

[0119] In one embodiment, the target logical state corresponds to a write command received from the host device (e.g., the host requests to store data in a set state instead of a reset state).

[0120] In one embodiment, the first threshold is 25 microamps, and the second write voltage is at least 200 millivolts higher than the first write voltage.

[0121] In one embodiment, the controller is further configured to select the magnitude of the second write voltage based on the magnitude of the first current when programming the first memory cell.

[0122] In one embodiment, the controller is further configured to: determine the error rate associated with reading data from the memory cell; and select the magnitude of the second write voltage based on the error rate when programming the first memory cell.

[0123] In one embodiment, a method includes: programming each of a plurality of memory cells in a memory array by applying a first write voltage (e.g., a default write voltage) or a second write voltage (e.g., a boost write voltage) to a respective memory cell, wherein the second write voltage is greater than the first write voltage; applying a pre-sensing voltage to a first memory cell in the memory array; sensing a first current originating from the applied pre-sensing voltage; determining whether the first current exceeds a first threshold (e.g., determining whether background leakage occurs); applying a pre-fetch voltage to the first memory cell; sensing a second current originating from the applied pre-fetch voltage; and determining whether the second current is below a second threshold, wherein the second threshold is greater than the first threshold (e.g., determining whether a cell transitions). In response to determining that the first current exceeds the first threshold (e.g., background leakage) and determining that the second current is below the second threshold (e.g., the cell does not transition and is in a set state), programming the first memory cell by applying a second write voltage (e.g., writing the cell to a reset state), wherein the applied second write voltage has the opposite polarity to the pre-fetch voltage.

[0124] In one embodiment, the pre-sensing voltage has the same polarity as the second write voltage applied to the first memory cell.

[0125] In one embodiment, the prefetch voltage is a first prefetch voltage; and the first prefetch voltage and the second write voltage are applied to the first memory cell as part of a first programming operation performed in response to a first write command received by the controller from the host device. The method further includes: receiving a second write command from the host device by the controller; and in response to receiving the second write command, performing a second programming operation on the second memory cell including applying the second prefetch voltage to the second memory cell and applying the first write voltage to the second memory cell.

[0126] In one embodiment, each memory cell in the memory array is a chalcogenide memory cell; and the controller is configured to apply a second write voltage having a first polarity to program the corresponding memory cell to a first logic state (e.g., a set or reset state) and a second opposite polarity to program the corresponding memory cell to a second logic state (e.g., the opposite of the first logic state).

[0127] In one embodiment, the pre-sensing voltage is a first pre-sensing voltage, and the pre-fetch voltage is a first pre-fetch voltage. The method further includes: applying a second pre-sensing voltage to a second memory cell of the memory array; sensing a third current originating from the applied second pre-sensing voltage; determining that the third current exceeds a third threshold (e.g., setting a flag indicating possible background leakage in the second cell); applying the second pre-fetch voltage to the second memory cell; sensing a fourth current originating from the applied second pre-fetch voltage; and determining that the fourth current is higher than a fourth threshold (e.g., the second cell switches). In response to determining that the third current exceeds the second threshold (e.g., setting a flag) and determining that the fourth current is higher than the fourth threshold (e.g., the second cell switches and is in a reset state), the second memory cell is programmed by applying a first write voltage (e.g., the write voltage does not increase).

[0128] In one embodiment, a system includes: a memory array comprising memory cells; and at least one voltage driver connected to the memory cells and configured to: drive a pre-sensed voltage on the memory cells during operation for programming the memory cells; drive a pre-read voltage on the memory cells during operation after driving the pre-sensed voltage; and after driving the pre-sensed voltage, select a first write voltage (e.g., a default write voltage) or a second write voltage (e.g., a boost write voltage) to drive the memory cells during operation, wherein the second write voltage is greater than the first write voltage. The system further includes at least one current sensor connected to the memory cells and configured to: determine whether a first current originating from the driving pre-sensed voltage exceeds a first threshold; and determine whether a second current originating from the driving pre-read voltage is below a second threshold. In response to determining that the first current exceeds the first threshold (e.g., background leakage) and determining that the second current is below the second threshold (e.g., the cell is not switching and is in a reset state), the voltage driver selects the second write voltage to drive the memory cells.

[0129] This disclosure includes various means for performing methods and implementing systems described above, including a data processing system for performing these methods, and a computer-readable medium containing instructions that, when executed on the data processing system, cause the system to perform these methods.

[0130] The descriptions and figures are illustrative and should not be considered limiting. Numerous specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details have not been described to avoid ambiguity. References to one or more embodiments in this disclosure are not necessarily references to the same embodiment; and such references indicate at least one.

[0131] As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0132] In this specification, the reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the described embodiment is included in at least one embodiment of this disclosure. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment, and a single or alternative embodiment is not necessarily mutually exclusive with other embodiments. Furthermore, various features that may be exhibited by some embodiments but not others are described. Similarly, various requirements that may be required by some embodiments but not others are described.

[0133] In this description, various functions and / or operations may be described as being executed by software code or caused by computer instructions for simplicity. However, those skilled in the art will recognize that such expressions mean that the functions and / or operations originate from the execution of code by one or more processing devices (e.g., microprocessors, application-specific integrated circuits (ASICs), graphics processors, and / or field-programmable gate arrays (FPGAs)). Alternatively, or in combination, functions and operations may be implemented using dedicated circuit systems (e.g., logic circuit systems) with or without software instructions. Embodiments may be implemented using hard-wired circuitry without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0134] Although some embodiments may be implemented in fully functional computers and computer systems, various embodiments are capable of being distributed as computing products in various forms and can be applied regardless of the specific type of computer-readable media used to actually implement the distribution.

[0135] At least some of the disclosed aspects can be embodied, at least in part, in software. That is, the technology can be implemented in a computing device or other system in response to its processing means (e.g., a microprocessor) executing a sequence of instructions contained in a memory (e.g., ROM, volatile RAM, non-volatile memory, cache, or remote storage device).

[0136] Routines executed to implement embodiments may be implemented as part of an operating system, middleware, service delivery platform, SDK (Software Development Kit) component, web service, or other specific application, component, program, object, module, or sequence of instructions (sometimes referred to as a computer program). The calling interface to these routines may be exposed to the software development community as an API (Application Programming Interface). A computer program typically includes one or more instructions set at different times in various memories and storage devices within a computer, and when read and executed by one or more processors in the computer, these instructions cause the computer to perform operations necessary to perform various aspects of its functions.

[0137] Computer-readable media can be used to store software and data that, when executed by a computing device, causes the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Parts of this software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of the data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or within the same communication session. Data and instructions can be fully obtained before the application is executed. Alternatively, portions of data and instructions can be dynamically obtained as needed. Therefore, it is not required that the data and instructions be entirely located on the computer-readable media at a particular time.

[0138] Examples of computer-readable media include (but are not limited to) recordable and non-recordable media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, disk storage media, optical storage media (e.g., optical disc read-only memory (CD-ROM), digital versatile disc (DVD), etc.). Computer-readable media can store instructions. Other examples of computer-readable media include (but are not limited to) non-volatile embedded devices using NOR flash or NAND flash architectures. Media used in these architectures may include unmanaged NAND devices and / or managed NAND devices, such as eMMC, SD, CF, UFS, and SSD.

[0139] Generally, non-transitory computer-readable media includes any mechanism that provides (e.g., stores) information in a form accessible to computing devices (e.g., computers, mobile devices, network devices, personal digital assistants, manufacturing tools with controllers, any device having one or more processors, etc.). As used herein, "computer-readable media" may include a single medium or multiple media (e.g., media storing one or more sets of instructions).

[0140] In various embodiments, hardwired circuitry systems may be combined with software and firmware instructions to implement some of the techniques. Therefore, the techniques are neither limited to any particular combination of hardware circuitry systems and software, nor to any particular source of instructions executed by a computing device.

[0141] The various embodiments described herein can be implemented using a wide variety of different types of computing devices. As used herein, examples of "computing device" include (but are not limited to) servers, centralized computing platforms, systems with multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic kiosks, general-purpose computers, electronic document readers, tablet computers, laptop computers, smartphones, digital cameras, home appliances, televisions, or digital music players. Additional examples of computing devices include devices that are part of the so-called "Internet of Things" (IoT). Such "things" may occasionally interact with their owners or administrators who can monitor or modify settings on these things. In some cases, such owners or administrators act as users regarding the "thing" device. In some instances, a user's primary mobile device (e.g., an iPhone) may act as an administrator server regarding paired "thing" devices worn by the user (e.g., an Apple Watch).

[0142] In some embodiments, the computing device may be a computer or a host system, implemented as, for example, a desktop computer, a laptop computer, a web server, a mobile device, or other computing device including memory and processing means. The host system may include or be coupled to a memory subsystem, such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system may access multiple memory subsystems via a unified communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0143] In one instance, the host system is host device 126. In one instance, the memory subsystem is memory device 101.

[0144] In some embodiments, a computing device is a system that includes one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system-on-a-chip (SoC), or another suitable processor.

[0145] In one example, the computing device is a controller for a memory system. The controller includes a processing unit and a memory containing instructions executed by the processing unit to control various operations of the memory system.

[0146] Although some diagrams illustrate several operations in a specific order, operations that are not dependent on order can be reordered, and other operations can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, others will be obvious to those skilled in the art, and therefore an exhaustive list of alternatives is not presented. Furthermore, it should be recognized that stages can be implemented in hardware, firmware, software, or any combination thereof.

[0147] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A system comprising: a memory array including memory cells; and a controller configured to: program each of the memory cells by applying a first write voltage or a second write voltage to a respective memory cell, wherein the second write voltage is greater than the first write voltage; apply a pre-sense voltage to a first memory cell of the memory array; sense a first current resulting from applying the pre-sense voltage; determine whether the first current exceeds a first threshold; apply a pre-read voltage to the first memory cell; sense a second current resulting from applying the pre-read voltage; determine whether the second current is below a second threshold, wherein the second threshold is greater than the first threshold; and in response to determining that the first current exceeds the first threshold, and determining that the second current is below the second threshold, program the first memory cell by applying the second write voltage.

2. The system of claim 1, wherein the first memory cell is in a first logical state corresponding to a first threshold voltage, programming the first memory cell comprises programming the first memory cell to a second logical state corresponding to a second threshold voltage, and the second threshold voltage is lower than the first threshold voltage.

3. The system of claim 1, wherein the pre-read voltage is a first pre-read voltage, and the controller is further configured to: apply a pre-sense voltage to a second memory cell; sense a third current resulting from applying the pre-sense voltage to the second memory cell; determine whether the third current exceeds the first threshold; apply a second pre-read voltage to the second memory cell; sense a fourth current resulting from applying the second pre-read voltage to the second memory cell; determine whether the fourth current is below the second threshold; and in response to determining that the third current exceeds the first threshold, and determining that the fourth current is not below the second threshold, program the second memory cell by applying the first write voltage.

4. The system of claim 3, wherein the second memory cell is in a first logical state corresponding to a first threshold voltage, programming the second memory cell comprises programming the second memory cell to a second logical state corresponding to a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage.

5. The system of claim 3, wherein the controller is further configured to: apply a pre-sense voltage to a third memory cell; sense a fifth current resulting from applying the pre-sense voltage to the third memory cell; determine whether the fifth current exceeds the first threshold; and in response to determining that the fifth current does not exceed the first threshold, program the third memory cell by applying the first write voltage.

6. The system of claim 5, wherein the controller is further configured to: apply a third pre-read voltage to the third memory cell to determine that the third memory cell is in a first logical state; wherein programming the third memory cell comprises programming the third memory cell to a second logic state opposite the first logic state.

7. The system of claim 1, wherein the first memory cell comprises a chalcogenide, a top electrode over the chalcogenide, and a bottom electrode under the chalcogenide.

8. The system of claim 1, wherein the pre-sense voltage has a same polarity as the second write voltage.

9. The system of claim 1, wherein the pre-sense voltage and the pre-read voltage are applied to the first memory cell as part of a program operation, and the program operation is performed in response to the controller receiving a write command from a host device.

10. The system of claim 1, wherein the pre-read voltage is applied to determine an existing logic state of the first memory cell, and the controller is further configured to: compare a target logic state of the first memory cell to the existing logic state; wherein programming the first memory cell is further in response to determining that the target logic state is different than the existing logic state.

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