A light emitting device, a preparation method thereof, a display panel, and a display device

Abstract

A light emitting device includes a first electrode, an electron transport layer, a quantum dot light emitting layer, and a second electrode. The electron transport layer is disposed on a side of the first electrode. The quantum dot light emitting layer is disposed on a side of the electron transport layer distal from the first electrode. The second electrode is disposed on a side of the quantum dot light emitting layer distal from the first electrode. The light emitting device further includes a plurality of adjustment patterns. The plurality of adjustment patterns are spaced apart in a normal projection of the plurality of adjustment patterns on a reference plane. The reference plane is parallel to a plane in which the first electrode is disposed. The plurality of adjustment patterns are disposed between the first electrode and the quantum dot light emitting layer and in contact with the electron transport layer. At least a portion of a normal projection of the electron transport layer on the reference plane is located in a gap region of the normal projection of the plurality of adjustment patterns on the reference plane. The plurality of adjustment patterns are configured to block electrons transported from the first electrode to the quantum dot light emitting layer or form electron traps to trap the electrons transported from the first electrode to the quantum dot light emitting layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting device and its preparation method, a display panel, and a display device. Background Technology

[0002] Quantum dots, as novel luminescent materials, possess advantages such as high light purity, high quantum efficiency, tunable color emission, and long lifespan, making them a research hotspot for novel light-emitting diodes (LEDs). Therefore, quantum dot light-emitting diodes (QLEDs) using quantum dot materials as the luminescent layer have become a major research direction for novel display devices. Summary of the Invention

[0003] On one hand, a light-emitting device is provided. The light-emitting device includes a first electrode, an electron transport layer, a quantum dot light-emitting layer, and a second electrode. The electron transport layer is disposed on one side of the first electrode. The quantum dot light-emitting layer is disposed on the side of the electron transport layer away from the first electrode. The second electrode is disposed on the side of the quantum dot light-emitting layer away from the first electrode. The light-emitting device further includes a plurality of adjustment patterns. The orthographic projections of the plurality of adjustment patterns on a reference plane are spaced apart. The reference plane is parallel to the plane containing the first electrode. The plurality of adjustment patterns are disposed between the first electrode and the quantum dot light-emitting layer, and are in contact with the electron transport layer. At least a portion of the orthographic projection of the electron transport layer on the reference plane is located in the gap region between the orthographic projections of the plurality of adjustment patterns on the reference plane. The plurality of adjustment patterns are configured to block electrons transmitted from the first electrode to the quantum dot light-emitting layer; or to form electron traps to capture electrons transmitted from the first electrode to the quantum dot light-emitting layer.

[0004] In some embodiments, the plurality of conditioning patterns comprise an insulating transparent oxide material.

[0005] In some embodiments, the plurality of conditioning patterns comprise hole-transporting transparent oxide materials.

[0006] In some embodiments, the plurality of conditioning patterns include at least one of the oxides of molybdenum, nickel, zirconium, and vanadium.

[0007] In some embodiments, the lowest unoccupied molecular orbital energy level of the hole-transporting transparent oxide material is shallower than the lowest unoccupied molecular orbital energy level of the electron transport layer.

[0008] In some embodiments, the light-emitting device further includes a hole transport layer disposed between the quantum dot light-emitting layer and the second electrode, wherein the plurality of adjustment patterns are made of the same material as the hole transport layer.

[0009] In some embodiments, the plurality of adjustment patterns include at least two two-dimensional semiconductor layers, the at least two two-dimensional semiconductor layers forming a moiré superlattice structure.

[0010] In some embodiments, the at least two two-dimensional semiconductor layers comprise a combination of at least two of tungsten disulfide, tungsten diselenide, molybdenum selenide, tungsten sulfide, graphene, borene, boron nitride, and bismuth oxychloride nanosheets.

[0011] In some embodiments, the plurality of adjustment patterns are arranged in multiple rows and columns. The spacing between any two adjacent rows of adjustment patterns is equal, and / or the spacing between any two adjacent columns of adjustment patterns is equal.

[0012] In some embodiments, the surface of the second electrode away from the first electrode has an undulating topography.

[0013] In some embodiments, the plurality of adjustment patterns are disposed within the electron transport layer. The electron transport layer includes a first surface in contact with the first electrode and a second surface in contact with the quantum dot light-emitting layer. A spacing is provided between the plurality of adjustment patterns and the first surface, and between the plurality of adjustment patterns and the second surface.

[0014] In some embodiments, the electron transport layer includes a first electron transport sublayer and a second electron transport sublayer, wherein the first electron transport sublayer is closer to the first electrode than the second electron transport sublayer. The plurality of adjustment patterns are located between the first and second electron transport sublayers, wherein the second electron transport sublayer at least partially fills the gaps between the plurality of adjustment patterns and is in contact with the first electron transport sublayer.

[0015] In some embodiments, the plurality of adjustment patterns are disposed between the electron transport layer and the quantum dot light-emitting layer.

[0016] In some embodiments, the quantum dot light-emitting layer contacts the electron transport layer through the gaps between the plurality of adjustment patterns.

[0017] In some embodiments, the number of lattice defects per unit area in the surface of the plurality of adjustment patterns in contact with the quantum dot light-emitting layer is less than the number of lattice defects per unit area in the surface of the electron transport layer in contact with the quantum dot light-emitting layer.

[0018] In some embodiments, the plurality of adjustment patterns are disposed between the first electrode and the electron transport layer. The electron transport layer contacts the first electrode through the gaps between the plurality of adjustment patterns.

[0019] In some embodiments, the electron transport layer is an N-type inorganic semiconductor thin film.

[0020] On the other hand, a light-emitting device is provided. The light-emitting device includes a first electrode, an electron transport layer, a quantum dot light-emitting layer, a second electrode, and a modulation layer. The electron transport layer is disposed on one side of the first electrode. The quantum dot light-emitting layer is disposed on the side of the electron transport layer away from the first electrode. The second electrode is disposed on the side of the quantum dot light-emitting layer away from the first electrode. The modulation layer is disposed between the first electrode and the quantum dot light-emitting layer and is in contact with the electron transport layer. The modulation layer has a continuous film structure and includes at least two two-dimensional semiconductor layers forming a moiré superlattice structure. The modulation layer is configured to form an electron trap to capture electrons transported from the first electrode to the quantum dot light-emitting layer.

[0021] In some embodiments, the conditioning layer comprises a combination of at least two of tungsten disulfide, tungsten diselenide, molybdenum selenide, tungsten sulfide, graphene, borene, boron nitride, and bismuth oxychloride nanosheets.

[0022] In some embodiments, the rotation angle between two adjacent two-dimensional semiconductor layers is less than or equal to 10°.

[0023] In some embodiments, the electron transport layer includes a first electron transport sublayer and a second electron transport sublayer. The first electron transport sublayer, the modulation layer, and the second electron transport sublayer are stacked sequentially along a direction perpendicular to the plane containing the first electrode and pointing from the first electrode to the quantum dot emitting layer. Alternatively, the modulation layer is disposed between the electron transport layer and the quantum dot emitting layer; or, the modulation layer is disposed between the first electrode and the electron transport layer.

[0024] In some embodiments, the electron transport layer is an N-type inorganic semiconductor thin film.

[0025] In some embodiments, the surface roughness of the electron transport layer is less than that of the quantum dot light-emitting layer.

[0026] On the other hand, a method for fabricating a light-emitting device is provided. The method includes forming a first electrode on a substrate. An electron transport layer comprising an N-type inorganic semiconductor material is formed on the side of the first electrode away from the substrate. A quantum dot light-emitting layer is formed on the side of the electron transport layer away from the substrate. A second electrode is formed on the side of the quantum dot light-emitting layer away from the substrate. The method further includes, after forming the first electrode and before forming the quantum dot light-emitting layer, forming a plurality of spaced-apart adjustment patterns that are in contact with the electron transport layer. At least a portion of the orthographic projection of the electron transport layer onto the substrate is located in the gap region between the orthographic projections of the plurality of adjustment patterns onto the substrate.

[0027] In some embodiments, the plurality of conditioning patterns are formed before or after the formation of the electron transport layer.

[0028] In some embodiments, forming the electron transport layer and forming the plurality of adjustment patterns includes forming a first electron transport sublayer on the side of the first electrode away from the substrate. A plurality of adjustment patterns are formed on the side of the first electron transport sublayer away from the substrate. A second electron transport sublayer is formed on the side of the plurality of adjustment patterns away from the substrate. The first electron transport sublayer and the second electron transport sublayer together form an electron transport layer.

[0029] In some embodiments, forming the plurality of adjustment patterns includes depositing a preset material based on a mask to form a plurality of adjustment patterns spaced apart. Alternatively, depositing a preset material to form an adjustment film; patterning the adjustment film to form a plurality of adjustment patterns spaced apart.

[0030] In some embodiments, the electron transport layer is formed using a sputtering process.

[0031] On the other hand, a method for fabricating a light-emitting device is provided. The method includes forming a first electrode on a substrate. An electron transport layer, comprising an N-type inorganic semiconductor material, is formed on the side of the first electrode away from the substrate. A quantum dot light-emitting layer is formed on the side of the electron transport layer away from the substrate. A second electrode is formed on the side of the quantum dot light-emitting layer away from the substrate. The method further includes, after forming the first electrode and before forming the quantum dot light-emitting layer, forming a conditioning layer. The conditioning layer is in contact with the electron transport layer; the conditioning layer is a continuous film structure and comprises at least two two-dimensional semiconductor layers forming a moiré superlattice structure.

[0032] On the other hand, a display panel is provided. The display panel includes a back panel and a plurality of light-emitting devices. The back panel includes a substrate and a plurality of pixel circuits disposed on the substrate.

[0033] Multiple light-emitting devices are disposed on the backplate, and the multiple light-emitting devices are the light-emitting devices described in any of the above embodiments. The first electrode of at least one light-emitting device is close to the backplate relative to the second electrode, and the first electrode of one of the light-emitting devices is electrically connected to a pixel circuit.

[0034] In some embodiments, the spacing between two adjacent light-emitting devices is a first spacing. Each light-emitting device includes a plurality of spaced adjustment patterns, and the spacing between two adjacent adjustment patterns is a second spacing. The second spacing is less than or equal to the first spacing.

[0035] In some embodiments, the light-emitting device has a light-emitting area; the area of ​​the plurality of adjustment patterns is less than or equal to the area of ​​the light-emitting area.

[0036] In some embodiments, the display panel further includes a pixel defining layer. The pixel defining layer is disposed on the side of the plurality of pixel circuits away from the substrate. The pixel defining layer has a plurality of openings, at least a portion of the quantum dot light-emitting layer of one of the light-emitting devices is located within one opening, the opening defining the light-emitting area of ​​the corresponding light-emitting device.

[0037] On the other hand, a display device is provided. The display device includes a display panel. The display panel is the display panel described in any of the above embodiments. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0040] Figure 2 This is a top view of a display panel according to some embodiments;

[0041] Figure 3 for Figure 2 The image shows a cross-sectional view of a display panel along section line ZZ'.

[0042] Figure 4 This is a structural diagram of a light-emitting device according to some embodiments;

[0043] Figure 5A for Figure 3 A magnified view of a portion of the Q area on the central display panel;

[0044] Figure 5B for Figure 3 Another magnified view of point Q on the central display panel;

[0045] Figure 5C for Figure 3 Another magnified view of point Q on the central display panel;

[0046] Figure 6A This is a top view of an electronic transport layer according to some embodiments;

[0047] Figure 6B This is another top view of the electronic transport layer according to some embodiments;

[0048] Figure 6C This is another top view of the electronic transport layer according to some embodiments;

[0049] Figure 7A for Figure 3 Another magnified view of point Q on the central display panel;

[0050] Figure 7B for Figure 3 Another magnified view of point Q on the central display panel;

[0051] Figure 7C for Figure 3 Another magnified view of point Q on the central display panel;

[0052] Figures 8-12 This is a flowchart of a method for fabricating a light-emitting device according to some embodiments. Detailed Implementation

[0053] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0054] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0056] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0057] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0058] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0059] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] This disclosure provides a light-emitting device 11, a method for fabricating the same, a display panel 10, and a display device 100, among other embodiments. The light-emitting device 11, its fabrication method, the display panel 10, and the display device 100 are described below.

[0066] like Figure 1 As shown, some embodiments of this disclosure provide a display device 100, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0067] In some embodiments, such as Figure 1 As shown. The display device 100 includes a display panel 10, which is a QLED display panel.

[0068] like Figure 2 As shown, the display panel 10 has a display area A and a peripheral area B located on at least one side of the display area A. (See attached image) Figure 2 The illustration is based on the example of the surrounding area B enclosing the display area A.

[0069] The display area A is the area for displaying the image, and it is configured to set sub-pixels P. The peripheral area B is a non-display area, which can be configured to set up scan drive circuits, circuit traces, and bonding pins, etc.

[0070] For example, such as Figure 2 and Figure 3 As shown, the display panel 10 includes a plurality of sub-pixels P disposed on one side of the substrate 121 and located in the display area A. The plurality of sub-pixels P are arranged in multiple rows and multiple columns. Each row of sub-pixels P may include a plurality of sub-pixels P arranged along the second direction X, and each column of sub-pixels P may include a plurality of sub-pixels P arranged along the first direction Y.

[0071] In some embodiments, such as Figure 3 As shown, the display panel 10 includes a light-emitting device 11 and a backplane (BP) 12. The backplane 12 includes a substrate 121 and a plurality of pixel circuits 122 disposed on the substrate 121. For example... Figure 2 and Figure 3 As shown, each sub-pixel P includes a light-emitting device 11 and a pixel circuit 122.

[0072] like Figure 3 As shown, the pixel circuit 122 includes multiple thin-film transistors. Each thin-film transistor includes an active layer, a source, a drain, and a gate, with the source and drain respectively in contact with the active layer.

[0073] like Figure 3 As shown, perpendicular to the substrate 121 and pointing from the pixel circuit 122 towards the light-emitting device 11, the light-emitting device 11 includes a first electrode 111, a light-emitting functional layer 112, and a second electrode 113 arranged sequentially. That is, the first electrode 111 is closer to the back plate 12 than the second electrode 113. The light-emitting functional layer 112 is disposed on the side of the first electrode 111 away from the back plate 12, and the second electrode 113 is disposed on the side of the light-emitting functional layer 112 away from the first electrode 111.

[0074] In some embodiments, a first electrode 111 is electrically connected to the source or drain of a driving transistor in a pixel circuit 122, and the first electrode 111 is the anode and the second electrode 113 is the cathode, i.e., a normal structure. In other embodiments, a first electrode 111 is electrically connected to the source or drain of a driving transistor in a pixel circuit 122, and the first electrode 111 is the cathode and the second electrode 113 is the anode, i.e., an inverted structure.

[0075] Among them, such as Figure 3 and Figure 4As shown, the light-emitting functional layer 112 includes a quantum dot light-emitting layer 114, an electron transport layer (ETL) 115, a hole transport layer (HTL) 116, and / or a hole injection layer (HIL) 117.

[0076] It is understood that the stacking direction of the film layers included in the light-emitting functional layer 112 in the upright structure is opposite to the stacking direction of the film layers included in the light-emitting functional layer 112 in the inverted structure. The following is an illustrative example of the light-emitting functional layer 112 including an electron transport layer 115, a quantum dot light-emitting layer 114, a hole transport layer 116, and a hole injection layer 117.

[0077] In the upright structure, the hole injection layer 117 is disposed on the side of the first electrode 111 closer to the second electrode 113. The hole transport layer 116 is disposed on the side of the hole injection layer 117 away from the first electrode 111. The quantum dot light-emitting layer 114 is disposed on the side of the hole transport layer 116 away from the first electrode 111. The electron transport layer 115 is disposed on the side of the quantum dot light-emitting layer 114 away from the first electrode 111.

[0078] In an inverted structure, such as Figure 4 As shown, an electron transport layer 115 is disposed on the side of the first electrode 111 near the second electrode 113. A quantum dot light-emitting layer 114 is disposed on the side of the electron transport layer 115 away from the first electrode 111. A hole transport layer 116 is disposed on the side of the quantum dot light-emitting layer 114 away from the first electrode 111. A hole injection layer 117 is disposed on the side of the hole transport layer 116 away from the first electrode 111.

[0079] like Figure 3 and Figure 4 As shown, the display panel 10 also includes a pixel delimiting layer (PDL). The PDL is disposed on the side of the plurality of pixel circuits 122 away from the substrate 121. The PDL has a plurality of openings, at least a portion of the quantum dot light-emitting layer 114 of a light-emitting device 11 is located in one opening, and the opening defines the light-emitting area of ​​the corresponding light-emitting device 11.

[0080] In related technologies, before fabricating multiple film layers between the first electrode 111 and the second electrode 113 using inkjet printing, a pixel defining layer (PDL) is pre-fabricated. The ink portion used to fabricate the light-emitting functional layer 112 covers the opening sidewalls of the pixel defining layer (PDL) and the top of the pixel defining layer (PDL), which greatly affects the morphology and thickness uniformity of the light-emitting functional layer 112. This has a significant impact on the performance and uniformity of the light-emitting device 11, and consequently affects the mass production of quantum dot light-emitting diodes.

[0081] To reduce the uneven thickness of multiple film layers between the first electrode 111 and the second electrode 113, an electron transport layer 115 is formed using a sputtering process. However, the electron transport layer 115 formed by sputtering has a high material mobility and injects more electrons, affecting the carrier balance. This leads to excess charge accumulating in the quantum dot emitting layer 114, where photons transfer energy to nearby free charges, resulting in nonradiative recombination. This reduces the quantum yield and ultimately affects the luminous efficiency of the light-emitting device 11.

[0082] Based on this, some embodiments of the present disclosure provide a light-emitting device 11. For example... Figure 5A As shown, the light-emitting device 11 also includes a plurality of adjustment patterns 118. The orthographic projections of the plurality of adjustment patterns 118 on the reference plane M are distributed at intervals. The reference plane M is parallel to the plane where the first electrode 111 is located.

[0083] Among them, such as Figure 3 and Figure 5A As shown, multiple adjustment patterns 118 can be distributed on the same reference plane M or on different reference planes M. That is, the spacing between multiple adjustment patterns 118 and the first electrode 111 can be equal or unequal, depending on actual needs. This disclosure does not specifically limit this.

[0084] Multiple adjustment patterns 118 are disposed between the first electrode 111 and the quantum dot light-emitting layer 114, and in contact with the electron transport layer 115. At least a portion of the orthographic projection of the electron transport layer 115 onto the reference plane M is located in the gap region between the orthographic projections of the multiple adjustment patterns 118 onto the reference plane M. The multiple adjustment patterns 118 are configured to block electrons transported from the first electrode 111 to the quantum dot light-emitting layer 114; or to form electron traps to capture electrons transported from the first electrode 111 to the quantum dot light-emitting layer 114. In other words, the light-emitting device 11 can block or capture electrons transported from the first electrode 111 to the quantum dot light-emitting layer 114 through the multiple adjustment patterns 118, thereby reducing electron transport, increasing carrier balance, and reducing the accumulation of excess electrons in the quantum dot.

[0085] As described above, in the embodiments of this disclosure, the multiple adjustment patterns 118 between the first electrode 111 and the quantum dot light-emitting layer 114 can block electrons transmitted from the first electrode 111 to the quantum dot light-emitting layer 114, or form electron traps to capture electrons transmitted from the first electrode 111 to the quantum dot light-emitting layer 114. Thus, while ensuring that electrons still have a transmission path—that is, while the multiple adjustment patterns 118 do not block electron transmission—the electron transmission path is reduced, and the electron transmission capability is decreased. Ultimately, this improves the luminous efficiency of the light-emitting device 11.

[0086] In some embodiments, the area of ​​the plurality of adjustment patterns 118 is less than or equal to the area of ​​the light-emitting region of the light-emitting device 11. Furthermore, the plurality of adjustment patterns 118 may be made of the same material as the hole transport layer 116.

[0087] In some embodiments, the plurality of modulated patterns 118 comprise an insulating transparent oxide material having a band gap exceeding 4 eV, a lowest unoccupied molecular orbital (LUMO) level shallower than -3 eV, and a highest occupied molecular orbital (HOMO) level deeper than -7 eV. Furthermore, the charge mobility of the insulating transparent oxide material is less than or equal to 10. -6 cm 2 / (V·s), by blocking electrons, reduces electron transport.

[0088] Exemplarily, the plurality of adjustment patterns 118 include at least one of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that silicon oxide includes SiO, SiO2, and Si2O6, and this disclosure does not specifically limit the types of silicon oxide.

[0089] In other embodiments, the plurality of modulated patterns 118 include hole-transporting transparent oxide materials. The lowest unoccupied molecular orbital energy level of the hole-transporting transparent oxide material is shallower than the lowest unoccupied molecular orbital energy level of the electron transport layer 115. The hole-transporting transparent oxide material can trap electrons, acting as an electron trap and reducing electron transport.

[0090] Exemplary, the plurality of adjustment patterns 118 include at least one of the oxides of molybdenum, nickel, zirconium, and vanadium, which are not specifically limited in this embodiment of the disclosure.

[0091] It should be noted that molybdenum oxides include molybdenum oxide, molybdenum dioxide, and molybdenum trioxide; nickel oxides include nickel oxide and nickel trioxide; zirconium oxides include zirconium dioxide; and vanadium oxides include vanadium monoxide, vanadium trioxide, vanadium dioxide, and vanadium pentoxide, but the embodiments disclosed herein are not limited to these.

[0092] In some other embodiments, the plurality of modulated patterns 118 include at least two two-dimensional semiconductor layers forming a moiré superlattice structure. These modulated patterns 118 can form electron traps, confining electrons within the lattice structure, thereby reducing electron transport.

[0093] It should be noted that a moiré superlattice structure is an assembly of at least two layers of two-dimensional materials through perpendicular stacking under the influence of interlayer van der Waals forces, achieving a coupling structure between two incoherent crystals that can rotate relative to each other. A moiré superlattice structure can be formed by interlayers of homogeneous materials at different angles, or by heterogeneous materials due to lattice mismatch.

[0094] It should be noted that the principle of moiré superlattice structure is as follows: when atomically thin crystals are assembled (the thickness of a single atomically thin layer is generally...), For example, the thickness of a single layer of graphene is Interlayer lattice mismatch and rotation lead to different moiré superlattice structures. The reciprocal space in the moiré superlattice directly affects the momentum space, and interlayer interactions can change phonon modes and charge distribution, thereby regulating its band structure and charge distribution. Taking homogeneous graphene as an example, when the interlayer rotation angle is relatively small (less than 5°), the interlayer coupling is relatively strong, especially when the rotation angle is close to the magic angle (1.1°), the electron motion slows down and can be approximately considered as localized in the superlattice. In addition, by constructing superlattices between structures such as borophene, graphene / boron nitride, transition metal dichalcogenides, and transition metal dichalcogenide heterojunctions, their band structure and electronic properties can also be tuned. For different two-dimensional materials, different interlayer angles are required to have the strongest effect on electrons. Generally, this angle does not exceed 10°, and most of these angles are below 5°. For example, the optimal angle for bilayer graphene is 1.1°, and the optimal angle for graphene / boron nitride is 2°.

[0095] Exemplary, at least two two-dimensional semiconductor layers include combinations of at least two of tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum selenide, tungsten sulfide, graphene, borene, boron nitride, and helical bismuth oxychloride (BiOCl) nanosheets, which are not specifically limited in this disclosure.

[0096] In some embodiments, such as Figure 5A As shown, the surface of the second electrode 113 away from the first electrode 111 has an undulating morphology to improve the light extraction efficiency of the light-emitting device 11.

[0097] The undulating morphology of the surface of the second electrode 113 away from the first electrode 111 refers to the fact that the surface of the second electrode 113 away from the first electrode 111 is uneven. For example, the surface of the second electrode 113 away from the first electrode 111 has multiple protrusions, each protrusion corresponding to an adjustment pattern 118, thereby causing the light-emitting surface of the light-emitting device 11 (the surface of the second electrode 113 away from the first electrode 111) to exhibit a certain curved structure, and improving the light-emitting efficiency of the light-emitting device 11.

[0098] In some embodiments, such as Figure 5A As shown, multiple adjustment patterns 118 are disposed inside the electron transport layer 115. The electron transport layer 115 includes a first surface 1150 in contact with the first electrode 111 and a second surface 1151 in contact with the quantum dot light-emitting layer 114. Spacing is provided between the multiple adjustment patterns 118 and the first surface 1150, and between the multiple adjustment patterns 118 and the second surface 1151.

[0099] Among them, such as Figure 5A As shown, the electron transport layer 115 includes a first electron transport sublayer 1152 and a second electron transport sublayer 1153, with the first electron transport sublayer 1152 being closer to the first electrode 111 than the second electron transport sublayer 1153. A plurality of adjustment patterns 118 are located between the first electron transport sublayer 1152 and the second electron transport sublayer 1153, with at least a portion of the second electron transport sublayer 1153 filling the gaps between the plurality of adjustment patterns 118 and contacting the first electron transport sublayer 1152.

[0100] In other embodiments, such as Figure 5B As shown, multiple adjustment patterns 118 are disposed between the electron transport layer 115 and the quantum dot light-emitting layer 114. The quantum dot light-emitting layer 114 contacts the electron transport layer 115 through the gaps between the multiple adjustment patterns 118. The multiple adjustment patterns 118, located between the electron transport layer 115 and the quantum dot light-emitting layer 114, can act as electron traps to reduce electron transport. Furthermore, since lattice defects quench the quantum dot light-emitting layer 114, and the number of lattice defects per unit area on the surface where the multiple adjustment patterns 118 contact the quantum dot light-emitting layer 114 is less than the number of lattice defects per unit area on the surface where the electron transport layer 115 contacts the quantum dot light-emitting layer 114, the multiple adjustment patterns 118 disposed between the electron transport layer 115 and the quantum dot light-emitting layer 114 can also act as a passivation layer. By reducing the contact area between the electron transport layer 115 and the quantum dot light-emitting layer 114, the quenching effect of the film layer in contact with the quantum dot light-emitting layer 114 on the quantum dot light-emitting layer 114 is reduced.

[0101] For example, the electron transport layer 115 can be made of zinc oxide, and the adjustment pattern 118 can be made of silicon monoxide. In this way, the number of lattice defects per unit area in the surface of the adjustment pattern 118 in contact with the quantum dot light-emitting layer 114 is much smaller than the number of lattice defects per unit area in the surface of the electron transport layer 115 in contact with the quantum dot light-emitting layer 114. This can significantly reduce the quenching effect of the film layer in contact with the quantum dot light-emitting layer 114 on the quantum dot light-emitting layer 114.

[0102] In some other embodiments, such as Figure 5CAs shown, multiple adjustment patterns 118 are disposed between the first electrode 111 and the electron transport layer 115. The electron transport layer 115 contacts the first electrode 111 through the gaps between the multiple adjustment patterns 118.

[0103] The contact area between the pattern 118 and the quantum dot light-emitting layer 114 can be adjusted to be 30%–70% of the area of ​​the quantum dot light-emitting layer 114, and the contact area between the electron transport layer 115 and the quantum dot light-emitting layer 114 can also be adjusted to be 30%–70% of the area of ​​the quantum dot light-emitting layer 114. For example, the contact area between the pattern 118 and the quantum dot light-emitting layer 114 can be adjusted to be 30% of the area of ​​the quantum dot light-emitting layer 114, and the contact area between the electron transport layer 115 and the quantum dot light-emitting layer 114 can be 70% of the area of ​​the quantum dot light-emitting layer 114. Another example is that the contact area between the pattern 118 and the quantum dot light-emitting layer 114 can be adjusted to be 70% of the area of ​​the quantum dot light-emitting layer 114, and the contact area between the electron transport layer 115 and the quantum dot light-emitting layer 114 can be 30% of the area of ​​the quantum dot light-emitting layer 114.

[0104] In some embodiments, such as Figure 6A As shown, the orthographic projection of at least one adjustment pattern 118 onto the reference plane M is circular. In other embodiments, such as Figure 6B As shown, the orthographic projection of at least one adjustment pattern 118 onto the reference plane M is triangular. In some other embodiments, such as Figure 6C As shown, the orthographic projection of at least one adjustment pattern 118 onto the reference plane M is a regular quadrilateral. Furthermore, the adjustment pattern 118 can also be a rhombus, trapezoid, or ellipse. This disclosure does not specifically limit the shape. Different shapes can increase the roughness of the film interface, thereby reducing the proportion of optical waveguide modes and increasing the light emission ratio.

[0105] Based on the above, such as Figure 6A , Figure 6B and Figure 6C As shown, multiple adjustment patterns 118 can be arranged in multiple rows and columns. The spacing between any two adjacent rows of adjustment patterns 118 is equal, and / or, the spacing between any two adjacent columns of adjustment patterns 118 is equal.

[0106] Among them, such as Figure 5CAs shown, the thickness H1 of the adjustment pattern 118 is 0.5 nm to 20 nm. This range needs to take into account the thickness of a single atomic layer, while the thickness H2 of the electron transport layer 115 is 20 nm to 60 nm. Therefore, the thickness H1 of the adjustment pattern 118 does not exceed 20 nm, ensuring that the adjustment pattern 118 does not affect the overall conductive channel of the light-emitting device 11. The spacing D3 between adjacent adjustment patterns 118 is 0.5 μm to 20 μm. This spacing D3 takes into account the pixel size; approximately 10 μm for a 500 ppi pixel and approximately 20 μm for a 300 ppi pixel, and the spacing D3 is designed not to exceed the pixel size. In addition, the area of ​​the adjustment pattern 118 is approximately 5% to 50% of the QLED pixel size.

[0107] Embodiments of this disclosure also provide a light-emitting device 11. The light-emitting device 11 includes an adjustment layer 119, such as... Figure 7A As shown, the light-emitting device 11 includes a first electrode 111, an electron transport layer 115, a quantum dot light-emitting layer 114, a hole transport layer 116, a hole injection layer 117, a second electrode 113, and a regulating layer 119. The electron transport layer 115 is disposed on one side of the first electrode 111. The quantum dot light-emitting layer 114 is disposed on the side of the electron transport layer 115 away from the first electrode 111. The hole transport layer 116 is disposed on the side of the quantum dot light-emitting layer 114 away from the first electrode 111. The hole injection layer 117 is disposed on the side of the hole transport layer 116 away from the first electrode 111. The second electrode 113 is disposed on the side of the hole injection layer 117 away from the first electrode 111. The regulating layer 119 is disposed between the first electrode 111 and the quantum dot light-emitting layer 114, and is in contact with the electron transport layer 115. The regulating layer 119 is a continuous film structure, and the regulating layer 119 includes at least two two-dimensional semiconductor layers, which form a moiré superlattice structure. The modulation layer 119 is configured to form an electron trap to capture electrons transported by the first electrode 111 to the quantum dot light-emitting layer 114. This modulation layer 119 forms an electron trap, confining electrons within the lattice structure, thereby reducing electron transport and improving the luminous efficiency of the light-emitting device 11.

[0108] It should be noted that this moiré superlattice structure can confine electrons within the lattice structure, thereby reducing electron transport, but it does not completely block electron transport. Therefore, the modulation layer 119 can be a continuous monolayer structure, meaning that the contact area between the electron transport layer 115 and the quantum dot emitting layer 114 is zero.

[0109] In some embodiments, the regulating layer 119 comprises a combination of at least two of tungsten disulfide, tungsten diselenide, molybdenum selenide, tungsten sulfide, graphene, borene, boron nitride, and helical bismuth oxychloride nanosheets. This disclosure does not specifically limit the embodiments thereof.

[0110] In some embodiments, the rotation angle between two adjacent two-dimensional semiconductor layers is less than or equal to 10° to exert the strongest binding effect on electrons.

[0111] In some embodiments, such as Figure 7A As shown, the electron transport layer 115 includes a first electron transport sublayer 1152 and a second electron transport sublayer 1153. Along a plane perpendicular to the first electrode 111 and pointing from the first electrode 111 to the quantum dot light-emitting layer 114, the first electron transport sublayer 1152, the modulation layer 119, and the second electron transport sublayer 1153 are stacked sequentially.

[0112] In other embodiments, such as Figure 7B As shown, the regulating layer 119 is disposed between the electron transport layer 115 and the quantum dot emitting layer 114. The regulating layer 119 can act as an electron trap, reducing electron transport, and can also reduce the contact area between the electron transport layer 115 and the quantum dot emitting layer 114, thereby reducing the quenching effect of the electron transport layer 115 on the quantum dot emitting layer 114. Furthermore, since lattice defects quench the quantum dot emitting layer 114, and the number of lattice defects per unit area on the surface where the regulating layer 119 contacts the quantum dot emitting layer 114 is less than the number of lattice defects per unit area on the surface where the electron transport layer 115 contacts the quantum dot emitting layer 114, the regulating layer 119 disposed between the electron transport layer 115 and the quantum dot emitting layer 114 can also act as a passivation layer, reducing the quenching effect of the film layer in contact with the quantum dot emitting layer 114 on the quantum dot emitting layer 114 by reducing the contact area between the electron transport layer 115 and the quantum dot emitting layer 114.

[0113] In some other embodiments, such as Figure 7C As shown, the adjustment layer 119 is disposed between the first electrode 111 and the electron transport layer 115.

[0114] The display panel 10 provided in the embodiments of this disclosure includes the light-emitting device 11 described in any of the above embodiments.

[0115] Among them, such as Figure 3 As shown, when the light-emitting device 11 includes multiple adjustment patterns 118, the spacing between two adjacent light-emitting devices 11 is the first spacing D1. The spacing between two adjacent adjustment patterns 118 is the second spacing D2. The second spacing D2 is less than or equal to the first spacing D1.

[0116] The methods for fabricating the light-emitting device 11 provided in some embodiments of this disclosure, such as Figure 8 As shown, it includes: S11 to S15.

[0117] S11, A first electrode 111 is formed on the substrate.

[0118] For example, a first conductive layer is formed on the surface of a substrate by coating or chemical deposition, and a plurality of first electrodes 111 are formed by mask exposure, development and etching processes on the first conductive layer.

[0119] The material of the first conductive layer can be glass, polyethylene terephthalate (PET), transparent indium tin oxide (ITO), fluorine-doped tin dioxide (FTO film), or conductive polymer, or it can be an opaque metal electrode such as aluminum (Al) or silver (Ag). The embodiments disclosed herein are not limited to these.

[0120] S12. An electron transport layer 115 is formed on the side of the first electrode 111 away from the substrate. The electron transport layer 115 includes an N-type inorganic semiconductor material.

[0121] Exemplarily, the electron transport layer 115 can be formed using a sol-gel method, a nanoparticle spin coating method, or a sputtering process. For example, the electron transport layer 115 can be formed using a sputtering process. The electron transport layer 115 is an N-type inorganic semiconductor thin film. The N-type inorganic semiconductor thin film includes zinc oxide (ZnO) or zinc oxide (ZnO) films doped with magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), etc., with a thickness of 50 nm to 300 nm. The embodiments disclosed herein are not limited to these.

[0122] In some embodiments, the surface roughness of the electron transport layer 115 is less than the surface roughness of the quantum dot light-emitting layer 114. This reduces electron transport and improves the luminous efficiency of the light-emitting device 11. The electron transport layer 115 can be formed by a sputtering process, and the surface roughness of the sputtered electron transport layer 115 is less than 3 nm. The surface roughness of the electron transport layer 115 is less than the surface roughness of the quantum dot light-emitting layer 114.

[0123] S14. A quantum dot light-emitting layer 114 is formed on the side of the electron transport layer 115 away from the substrate.

[0124] For example, the quantum dot light-emitting layer 114 can be formed using an inkjet printing process. The thickness of the quantum dot light-emitting layer 114 is 20 nm to 50 nm, but the embodiments disclosed herein are not limited to this.

[0125] S15. A second electrode 113 is formed on the side of the quantum dot light-emitting layer 114 away from the substrate.

[0126] For example, a second conductive layer is formed on the side of the quantum dot light-emitting layer 114 away from the substrate by coating or chemical deposition, and a plurality of second electrodes 113 are formed by mask exposure, development and etching processes on the second conductive layer.

[0127] The material of the second conductive layer can be a metal such as aluminum (Al) or silver (Ag), or it can be indium zinc oxide (IZO) deposited by magnetron sputtering with a thickness of 10 nm to 100 nm. The embodiments disclosed herein are not limited to this.

[0128] Between S11 and S14, the above preparation method also includes S13.

[0129] S13, forming multiple adjustment patterns 118 with intervals.

[0130] In the above steps, the plurality of adjustment patterns 118 are in contact with the electron transport layer 115. At least a portion of the orthographic projection of the electron transport layer 115 onto the substrate is located in the gap region between the orthographic projections of the plurality of adjustment patterns 118 onto the substrate.

[0131] For example, multiple adjustment patterns 118 can be formed by direct deposition using a mask, or by mask exposure, development, and etching.

[0132] S13 can be performed before or after S12, and this disclosure does not make any specific restrictions on this.

[0133] As described above, the first electrode 111 is closer to the backplate 12 than the second electrode 113, and the first electrode 111 of a light-emitting device 11 is electrically connected to a pixel circuit 122, forming an inverted structure. Thus, by using sputtering to form the electron transport layer 115, and then inkjet printing to form the quantum dot light-emitting layer 114, the electron transport layer 115 formed by sputtering will not cover the sidewalls and top of the pixel boundary layer (PDL) openings. The thickness of the electron transport layer 115 is uniform, which improves the uniformity of the thickness of the quantum dot light-emitting layer 114 formed in subsequent processes, thereby improving the performance of the light-emitting device 11.

[0134] In some embodiments, such as Figure 9 As shown, an electron transport layer 115 is formed and a plurality of adjustment patterns 118 are formed, including: S121, S122 and S123.

[0135] S121. A first electron transport sublayer 1152 is formed on the side of the first electrode 111 away from the substrate.

[0136] Exemplarily, the first electron transport sublayer 1152 can be formed using a sol-gel method, a nanoparticle spin coating method, or a sputtering process. For example, the first electron transport sublayer 1152 is formed using a sputtering process. The first electron transport sublayer 1152 is an N-type inorganic semiconductor thin film. N-type inorganic semiconductor thin films include zinc oxide (ZnO) or zinc oxide (ZnO) thin films doped with magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), etc., and the embodiments disclosed herein are not limited to these.

[0137] S122, Multiple adjustment patterns 118 are formed on the side of the first electron transport sublayer 1152 away from the substrate.

[0138] For example, multiple adjustment patterns 118 can be formed by direct deposition using a mask, or by mask exposure, development, and etching.

[0139] S123. A second electron transport sublayer 1153 is formed on the side of the plurality of adjustment patterns 118 away from the substrate. The first electron transport sublayer 1152 and the second electron transport sublayer 1153 form an electron transport layer 115.

[0140] Exemplarily, the second electron transport sublayer 1153 is an N-type inorganic semiconductor thin film. N-type inorganic semiconductor thin films include zinc oxide (ZnO) or zinc oxide (ZnO) thin films doped with magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), etc., and the embodiments disclosed herein are not limited thereto. Furthermore, the thickness of the second electron transport sublayer 1153 can be deposited as needed using magnetron sputtering.

[0141] In some embodiments, such as Figure 10 and Figure 11 As shown, S122 includes S1221 or S1222 to S1223.

[0142] S1221. Based on the mask plate, a preset material is deposited to form multiple adjustable patterns 118 with spacing.

[0143] The aforementioned preset material is the material for adjusting pattern 118, as detailed above, and will not be repeated here.

[0144] S1222, Deposit the preset material to form an conditioning membrane.

[0145] The aforementioned preset material is the material for adjusting pattern 118, as detailed above, and will not be repeated here.

[0146] S1223, Patterned adjustment film, forming multiple adjustment patterns 118 spaced apart.

[0147] For example, the conditioning film is subjected to mask exposure, development and etching processes to form a plurality of spaced conditioning patterns 118.

[0148] In other embodiments, such as Figure 12 As shown, the method for preparing the light-emitting device 11 provided in some embodiments of this disclosure includes: S21 to S24.

[0149] S21. A first electrode 111 is formed on the substrate.

[0150] For example, a first conductive layer is formed on the surface of a substrate by coating or chemical deposition, and a plurality of first electrodes 111 are formed by mask exposure, development and etching processes on the first conductive layer.

[0151] The material of the first conductive layer can be glass, polyethylene terephthalate (PET), transparent indium tin oxide (ITO), fluorine-doped tin dioxide (FTO film), or conductive polymers, or it can be an opaque metal electrode such as aluminum (Al) or silver (Ag). The embodiments disclosed herein are not limited to these.

[0152] S22, an electron transport layer 115 is formed on the side of the first electrode 111 away from the substrate.

[0153] Exemplarily, the electron transport layer 115 can be formed using a sol-gel method, a nanoparticle spin coating method, or a sputtering process. For example, the electron transport layer 115 can be formed using a sputtering process. The electron transport layer 115 is an N-type inorganic semiconductor thin film. The N-type inorganic semiconductor thin film includes zinc oxide (ZnO) or zinc oxide (ZnO) films doped with magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), etc., with a thickness of 50 nm to 300 nm. The embodiments disclosed herein are not limited to these.

[0154] S24. A quantum dot light-emitting layer 114 is formed on the side of the electron transport layer 115 away from the substrate.

[0155] For example, the thickness of the quantum dot light-emitting layer 114 is 20nm to 50nm, and different thicknesses can be deposited as needed by inkjet printing or other methods. The embodiments disclosed herein are not limited to this.

[0156] In this design, the first electrode 111 of a light-emitting device 11 is electrically connected to a pixel circuit 122, forming an inverted structure, thereby improving the uniformity of the thickness of the quantum dot light-emitting layer 114. Furthermore, the side of the quantum dot light-emitting layer 114 closest to the first electrode 111 consists only of a sputtered electron transport layer 115, thus addressing the problem of ink covering the opening sidewalls and top of the pixel delimiting layer (PDL) during inkjet printing of the quantum dot light-emitting layer 114.

[0157] S25. A second electrode 113 is formed on the side of the quantum dot light-emitting layer 114 away from the substrate.

[0158] For example, the second electrode 113 can be a metal such as aluminum (Al) or silver (Ag), or it can be deposited with indium zinc oxide (IZO) by magnetron sputtering with a thickness of 10 nm to 100 nm. The embodiments disclosed herein are not limited thereto.

[0159] Between S21 and S24, the above preparation method also includes S23.

[0160] S23, Forming adjustment layer 119

[0161] In the above steps, the adjustment layer 119 is in contact with the electron transport layer 115; the adjustment layer 119 is a continuous film structure, and the adjustment layer 119 includes at least two two-dimensional semiconductor layers, which form a moiré superlattice structure.

[0162] For example, the multiple adjustment layers 119 can be formed by direct deposition using a mask, or by mask exposure, development, and etching.

[0163] S23 can be performed before or after S22; this disclosure does not specify any particular timeframe.

[0164] In summary, the light-emitting device 11 provided in some embodiments of this disclosure uses multiple adjustment patterns 118 to block electrons transmitted from the first electrode 111 to the quantum dot light-emitting layer 114 or to form electron traps to capture electrons transmitted from the first electrode 111 to the quantum dot light-emitting layer 114. While ensuring that electrons still have a transmission path, the multiple adjustment patterns 118 do not block electron transmission, but rather narrow the electron transmission path, thus reducing electron transmission capability. Furthermore, the adjustment layer 119 forms electron traps, confining electrons within the crystal lattice structure, thereby reducing electron transmission and ultimately improving the luminous efficiency of the light-emitting device 11.

[0165] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A light-emitting device, comprising: First electrode; An electron transport layer disposed on one side of the first electrode; A quantum dot light-emitting layer disposed on the side of the electron transport layer away from the first electrode; A second electrode is disposed on the side of the quantum dot light-emitting layer away from the first electrode; The light-emitting device further includes multiple adjustment patterns, which are distributed at intervals on the orthographic projection of the multiple adjustment patterns onto a reference plane, the reference plane being parallel to the plane where the first electrode is located; the multiple adjustment patterns are disposed between the first electrode and the quantum dot light-emitting layer, and are in contact with the electron transport layer; At least a portion of the orthographic projection of the electron transport layer onto the reference plane is located in the gap region of the orthographic projections of the plurality of adjustment patterns onto the reference plane; the first electrode and the electron transport layer are in contact at least in the gap region, and the electron transport layer and the quantum dot emitting layer are in contact at least in the gap region; The plurality of adjustment patterns are configured to block electrons transmitted from the first electrode to the quantum dot light-emitting layer; or to form electron traps to capture electrons transmitted from the first electrode to the quantum dot light-emitting layer.

2. The light-emitting device according to claim 1, wherein, The plurality of adjustment patterns comprise an insulating transparent oxide material.

3. The light-emitting device according to claim 1, wherein, The plurality of modulation patterns include hole-transmission type transparent oxide materials.

4. The light-emitting device according to claim 3, wherein, The plurality of conditioning patterns include at least one of the oxides of molybdenum, nickel, zirconium, and vanadium.

5. The light-emitting device according to claim 3 or 4, wherein, The lowest unoccupied molecular orbital energy level of the hole-transporting transparent oxide material is shallower than the lowest unoccupied molecular orbital energy level of the electron transport layer.

6. The light-emitting device according to claim 3, wherein, The light-emitting device further includes a hole transport layer disposed between the quantum dot light-emitting layer and the second electrode, wherein the plurality of adjustment patterns are made of the same material as the hole transport layer.

7. The light-emitting device according to claim 1, wherein, The plurality of adjustment patterns include at least two two-dimensional semiconductor layers, which form a moiré superlattice structure.

8. The light-emitting device according to claim 7, wherein, The at least two two-dimensional semiconductor layers include a combination of at least two of tungsten disulfide, tungsten diselenide, molybdenum selenide, tungsten sulfide, graphene, borene, boron nitride, and bismuth oxychloride nanosheets.

9. The light-emitting device according to claim 1, wherein, The multiple adjustment patterns are arranged in multiple rows and columns; The spacing between any two adjacent rows of adjustment patterns is equal, and / or the spacing between any two adjacent columns of adjustment patterns is equal.

10. The light-emitting device according to claim 1, wherein, The surface of the second electrode, away from the first electrode, has an undulating topography.

11. The light-emitting device according to claim 1, wherein, The plurality of adjustment patterns are disposed inside the electronic transport layer; The electron transport layer includes a first surface in contact with the first electrode and a second surface in contact with the quantum dot light-emitting layer; the plurality of adjustment patterns are spaced apart from the first surface and from the second surface.

12. The light-emitting device according to claim 11, wherein, The electron transport layer includes a first electron transport sublayer and a second electron transport sublayer, wherein the first electron transport sublayer is closer to the first electrode relative to the second electron transport sublayer; the plurality of adjustment patterns are located between the first electron transport sublayer and the second electron transport sublayer, wherein at least part of the second electron transport sublayer fills the gap between the plurality of adjustment patterns and is in contact with the first electron transport sublayer.

13. The light-emitting device according to claim 1, wherein, The plurality of adjustment patterns are disposed between the electron transport layer and the quantum dot light-emitting layer.

14. The light-emitting device according to claim 13, wherein, The quantum dot luminescent layer contacts the electron transport layer through the gaps between the plurality of adjustment patterns.

15. The light-emitting device according to claim 13 or 14, wherein, The number of lattice defects per unit area on the surface where the plurality of adjustment patterns contact the quantum dot light-emitting layer is less than the number of lattice defects per unit area on the surface where the electron transport layer contacts the quantum dot light-emitting layer.

16. The light-emitting device according to claim 1, wherein, The plurality of adjustment patterns are disposed between the first electrode and the electron transport layer, and the electron transport layer contacts the first electrode through the gaps between the plurality of adjustment patterns.

17. The light-emitting device according to claim 1, wherein, The electron transport layer is an N-type inorganic semiconductor thin film.

18. The light-emitting device according to claim 1, wherein, The surface roughness of the electron transport layer is less than that of the quantum dot light-emitting layer.

19. A method for fabricating a light-emitting device, comprising: A first electrode is formed on the substrate; An electron transport layer is formed on the side of the first electrode away from the substrate, the electron transport layer comprising an N-type inorganic semiconductor material; A quantum dot light-emitting layer is formed on the side of the electron transport layer away from the substrate; A second electrode is formed on the side of the quantum dot light-emitting layer away from the substrate; The method further includes, after forming the first electrode and before forming the quantum dot light-emitting layer, forming a plurality of spaced adjustment patterns that are in contact with the electron transport layer; at least a portion of the orthographic projection of the electron transport layer onto the substrate is located in the gap region of the orthographic projection of the plurality of adjustment patterns onto the substrate; the first electrode and the electron transport layer are in contact at least in the gap region, and the electron transport layer and the quantum dot light-emitting layer are in contact at least in the gap region.

20. The preparation method according to claim 19, wherein, The plurality of adjustment patterns are formed before or after the formation of the electron transport layer.

21. The preparation method according to claim 19, wherein, Forming the electron transport layer and forming the plurality of modulation patterns includes: A first electron transport sublayer is formed on the side of the first electrode away from the substrate; Multiple adjustment patterns are formed on the side of the first electron transport sublayer away from the substrate; A second electron transport sublayer is formed on the side of the plurality of adjustment patterns away from the substrate; The first electron transport sublayer and the second electron transport sublayer form an electron transport layer.

22. The preparation method according to any one of claims 19 to 21, wherein, Forming the plurality of adjustment patterns includes: Based on a mask, a pre-set material is deposited to form multiple spaced, adjustable patterns; or, A preset material is deposited to form an adjustment film; the adjustment film is patterned to form multiple adjustment patterns that are spaced apart.

23. The preparation method according to claim 19, wherein, The electron transport layer is formed using a sputtering process.

24. A display panel, comprising: A backplane, the backplane including a substrate and a plurality of pixel circuits disposed on the substrate; A plurality of light-emitting devices disposed on the back plate, wherein the plurality of light-emitting devices are light-emitting devices as described in any one of claims 1 to 18, wherein the first electrode of at least one light-emitting device is close to the back plate relative to the second electrode, and the first electrode of one of the light-emitting devices is electrically connected to a pixel circuit.

25. The display panel according to claim 24, wherein, The spacing between two adjacent light-emitting devices is the first spacing; The light-emitting device includes multiple adjustable patterns spaced apart, and the spacing between two adjacent adjustable patterns is a second spacing; The second spacing is less than or equal to the first spacing.

26. The display panel according to claim 24 or 25, wherein, The light-emitting device has a light-emitting area; the area of ​​the plurality of adjustment patterns is less than or equal to the area of ​​the light-emitting area.

27. The display panel according to claim 24, further comprising: A pixel defining layer is disposed on the side of the plurality of pixel circuits away from the substrate. The pixel defining layer has a plurality of openings. At least a portion of the quantum dot light-emitting layer of one of the light-emitting devices is located in one opening. The opening defines the light-emitting area of ​​the corresponding light-emitting device.

28. A display device, comprising: The display panel is the display panel as described in any one of claims 24 to 27.

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