Display device

Abstract

This invention discloses a display device, comprising: a first substrate, a first conductive layer, a first electrode, a second substrate, a display dielectric layer, and a second electrode. The first conductive layer and the first electrode are located between the first substrate and the second substrate, the display dielectric layer is located between the first electrode and the second substrate, and the second electrode is located between the display dielectric layer and the second substrate. The first electrode includes a plurality of electrically separated first lower electrode patterns and a plurality of first upper electrode patterns, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively electrically connected to a plurality of first conductive lines of the first conductive layer, the plurality of first lower electrode patterns have a plurality of first gaps between them, and the plurality of first upper electrode patterns overlap the plurality of first gaps.

Description

Technical Field

[0001] This invention relates to an optoelectronic device, and more particularly to a display device. Background Technology

[0002] Reflective liquid crystal displays (LCDs) offer advantages in energy efficiency and environmental friendliness. They utilize the reflection or absorption of ambient light to generate bright or dark states for display purposes, thus eliminating the need for a backlight. Generally, the liquid crystal layer of a reflective LCD can switch between a transmissive and reflective state driven by an electric field formed by upper and lower electrodes, thereby achieving the dark and bright states of each sub-pixel. The effective area of ​​each sub-pixel is determined by the overlapping area of ​​the upper and lower electrodes, while the non-overlapping area is the ineffective area. However, due to the linewidth limitations of the manufacturing process, the ratio of ineffective to effective area increases with increasing pixel density (pixels per inch, PPI), leading to a significant decrease in the reflectivity of reflective LCDs. Summary of the Invention

[0003] The present invention provides a display device having improved reflectivity.

[0004] One embodiment of the present invention provides a display device, comprising: a first substrate, a first conductive layer, a first electrode, a second substrate, a display dielectric layer, and a second electrode. The first conductive layer is located on the first substrate and includes a plurality of first conductive lines. The first electrode is located on the first substrate and includes a plurality of electrically separated first lower electrode patterns and a plurality of first upper electrode patterns, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively electrically connected to the plurality of first conductive lines, a plurality of first gaps are present between the plurality of first lower electrode patterns, and the plurality of first upper electrode patterns overlap the plurality of first gaps. The first conductive layer and the first electrode are located between the first substrate and the second substrate. The display dielectric layer is located between the first electrode and the second substrate. The second electrode is located between the display dielectric layer and the second substrate.

[0005] In one embodiment of the present invention, the plurality of first conductors described above are each electrically independent.

[0006] In one embodiment of the present invention, the plurality of first lower electrode patterns described above are separated from each other.

[0007] In one embodiment of the present invention, the plurality of first upper electrode patterns described above are separated from each other.

[0008] In one embodiment of the present invention, the plurality of first lower electrode patterns extend in the same direction as the plurality of first upper electrode patterns.

[0009] In one embodiment of the present invention, the overlap width between the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm.

[0010] In one embodiment of the present invention, the potentials of the overlapping first upper electrode pattern and the first lower electrode pattern are different.

[0011] In one embodiment of the present invention, the spacing between adjacent first lower electrode patterns and first upper electrode patterns is greater than 0 and less than 10 μm.

[0012] In one embodiment of the present invention, the second electrode includes a plurality of second lower electrode patterns, and the extending direction of the plurality of second lower electrode patterns is perpendicular to the extending direction of the plurality of first lower electrode patterns.

[0013] In one embodiment of the present invention, the second electrode further includes a plurality of second upper electrode patterns, and the plurality of second upper electrode patterns extend in the same direction as the plurality of second lower electrode patterns.

[0014] In one embodiment of the present invention, the plurality of second lower electrode patterns are provided with a plurality of second gaps, and the plurality of second upper electrode patterns overlap the plurality of second gaps respectively.

[0015] In one embodiment of the present invention, the display device further includes a second conductive layer located between the second substrate and the display medium layer, and includes a plurality of second conductive lines, wherein a plurality of second lower electrode patterns and a plurality of second upper electrode patterns are electrically connected to the plurality of second conductive lines respectively.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1A This is a perspective view of a display device 10 according to an embodiment of the present invention;

[0018] Figure 1B It is along Figure 1A A schematic diagram of the cross section drawn by section line A-A';

[0019] Figure 1C yes Figure 1A A top view of the first substrate 110, the first electrode 130, and the first conductive layer 150 of the display device 10;

[0020] Figure 1D yes Figure 1A A top view of the second substrate 120, the second electrode 140, and the second conductive layer 160 of the display device 10;

[0021] Figures 2A to 6B This is a cross-sectional schematic diagram of the steps of a method for manufacturing the first electrode 130 of a display device 10 according to an embodiment of the present invention.

[0022] Figure 7 This is a top view of a first substrate 110, a first electrode 130, a first conductive layer 750, and a driving element 181, according to another embodiment of the present invention.

[0023] Figure 8 This is a top view of the second substrate 120, the second electrode 140, and the second conductive layer 860 according to another embodiment of the present invention.

[0024] Figure 9 This is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention.

[0025] Symbol Explanation

[0026] 10,20: Display device

[0027] 110: First substrate

[0028] 111: Surface

[0029] 120: Second substrate

[0030] 121: Surface

[0031] 130: First electrode

[0032] 131: First lower electrode pattern layer

[0033] 132: First upper electrode pattern layer

[0034] 140: Second electrode

[0035] 141: Second lower electrode pattern layer

[0036] 142: Second upper electrode pattern layer

[0037] 150,750: First conductor layer

[0038] 152,752: First conductor

[0039] 160,860: Second conductor layer

[0040] 162,862: Second conductor

[0041] 170: Display media layer

[0042] 181, 182: Driving elements

[0043] A-A',B-B',C-C',D-D',E-E',F-F': Profile lines

[0044] AF: Connector

[0045] D1: First Direction

[0046] D2: Second Direction

[0047] E1B: First lower electrode pattern

[0048] E1T: First upper electrode pattern

[0049] E2B: Second lower electrode pattern

[0050] E2T: Second upper electrode pattern

[0051] G1, G2, G3, G4: Gap

[0052] I11, I12, I21, I22: Insulating layer

[0053] IP: Striped insulation pattern

[0054] PD1, PD21, PD22: Connecting pads

[0055] PN1, PN2: Pins

[0056] S1, S2, S3, S4: Side

[0057] V1, V2, V3: Through holes

[0058] W1, W2, W3, W5, W6, W7: Width

[0059] W4, W8: Spacing Detailed Implementation

[0060] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate elements are present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0061] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first "element," "component," "region," "layer," or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one" or indicating "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0063] Furthermore, relative terms such as "down" or "bottom" and "up" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being "down" of another element will be oriented "up" of that element. Thus, the exemplary term "down" can include both "down" and "up" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "down" or "below" of another element will be oriented "above" that element. Thus, the exemplary terms "down" or "below" can include both "up" and "down" orientations.

[0064] Given the specific number of measurements discussed and the associated errors (i.e., limitations of the measurement system), the terms "about," "approximately," or "substantially" as used herein include the value and the average value within an acceptable range of deviations from the specific value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms "about," "approximately," or "substantially" as used herein may be chosen based on optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, rather than applying a single standard deviation to all properties.

[0065] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0066] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Therefore, variations in shape as a result of, for example, manufacturing techniques and / or tolerances, are expected in the illustrations. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0067] Figure 1A This is a perspective view of a display device 10 according to an embodiment of the present invention. Figure 1B It is along Figure 1A A schematic diagram of the cross section line A-A'. Figure 1C yes Figure 1A A top view of the first substrate 110, the first electrode 130, and the first conductive layer 150 of the display device 10. Figure 1D yes Figure 1A A top view of the second substrate 120, the second electrode 140, and the second conductive layer 160 of the display device 10.

[0068] Please refer to Figures 1A to 1D The display device 10 may include a first substrate 110 and a second substrate 120. In some embodiments, the first substrate 110 overlaps the second substrate 120. In some embodiments, the first substrate 110 and the second substrate 120 are opposite to each other, and the surface 111 of the first substrate 110 faces the surface 121 of the second substrate 120. In some embodiments, the first substrate 110 and the second substrate 120 are transparent substrates. For example, the substrates 110 and 120 are made of glass, organic polymers, or other suitable materials.

[0069] In some embodiments, the display device 10 further includes a first electrode 130, which is disposed on a first substrate 110. In some embodiments, the first electrode 130 is located between the first substrate 110 and a second substrate 120. The first electrode 130 may include a plurality of mutually separated strip electrodes. In some embodiments, the plurality of strip electrodes of the first electrode 130 do not all belong to the same film layer. In some embodiments, the plurality of strip electrodes of the first electrode 130 are distributed across two film layers.

[0070] For example, the first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132. In some embodiments, the display device 10 further includes an insulating layer 112, which separates the first lower electrode pattern layer 131 from the first upper electrode pattern layer 132.

[0071] In some embodiments, the first lower electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the plurality of first lower electrode patterns E1B are separated from each other. In some embodiments, the first lower electrode patterns E1B have a strip pattern, and the plurality of first lower electrode patterns E1B extend parallel to each other along a first direction D1. In some embodiments, there are a plurality of gaps G1 between the plurality of first lower electrode patterns E1B, and the width W1 of the plurality of gaps G1 along a second direction D2 is substantially the same. In some embodiments, the first direction D1 is perpendicular to the second direction D2. In some embodiments, the width W1 of the gaps G1 is approximately 10 μm.

[0072] In some embodiments, a first upper electrode pattern layer 132 is located above a first lower electrode pattern layer 131, and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T separated from each other. In some embodiments, the first upper electrode patterns E1T have a strip pattern, and the extending direction of the first upper electrode patterns E1T is the same as the extending direction of the first lower electrode patterns E1B. In some embodiments, the plurality of first upper electrode patterns E1T extend parallel to each other along a first direction D1. In some embodiments, a plurality of gaps G2 are provided between the plurality of first upper electrode patterns E1T, and the width W2 of the plurality of gaps G2 along a second direction D2 is substantially the same. In some embodiments, the width W2 of the gaps G2 is approximately 10 μm.

[0073] In some embodiments, a plurality of first upper electrode patterns E1T partially overlap a plurality of first lower electrode patterns E1B. In some embodiments, the overlap width W3 between the first lower electrode pattern E1B and the first upper electrode pattern E1T is approximately 1.5 μm to 3 μm. In some embodiments, the potentials of the overlapping first upper electrode patterns E1T and the first lower electrode patterns E1B are not the same. In some embodiments, the voltage of the first upper electrode pattern E1T is approximately 80% to 95% of the voltage of the overlapping first lower electrode patterns E1B.

[0074] In some embodiments, multiple first upper electrode patterns E1T partially overlap multiple gaps G1 between multiple first lower electrode patterns E1B. In some embodiments, the side S1 of the first upper electrode pattern E1T in a direction perpendicular to its extending direction (i.e., the second direction D2) partially overlaps the first lower electrode pattern E1B, and the side S2 of the first upper electrode pattern E1T opposite to the side S1 does not overlap the first lower electrode pattern E1B. In some embodiments, the distance W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B is greater than 0 and less than 10 μm. That is, each first upper electrode pattern E1T only partially overlaps one corresponding first lower electrode pattern E1B and does not overlap the remaining first lower electrode patterns E1B to avoid parasitic capacitance. In some embodiments, the distance W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B can be further reduced to about 2 μm to 5 μm to reduce the invalid area of ​​each sub-pixel. In some embodiments, the spacing W4 is the minimum spacing between the first upper electrode pattern E1T and the non-overlapping first lower electrode pattern E1B.

[0075] In some embodiments, the display device 10 further includes a first conductive layer 150, which is located on a first substrate 110. In some embodiments, the display device 10 further includes an insulating layer 111, which separates the first conductive layer 150 from the first electrode 130. In some embodiments, the first conductive layer 150 is located between the first substrate 110 and the second substrate 120. In some embodiments, the first conductive layer 150 includes a plurality of first conductive lines 152, each of which is electrically independent. In some embodiments, the plurality of first conductive lines 152 are physically separated from each other. In some embodiments, a plurality of first lower electrode patterns E1B and a plurality of first upper electrode patterns E1T of the first electrode 130 are electrically connected to the plurality of first conductive lines 152.

[0076] In some embodiments, the display device 10 further includes a driving element 181, and a plurality of first conductors 152 of the first conductor layer 150 are electrically connected to the driving element 181. In some embodiments, the driving element 181 is disposed on the first substrate 110. In some embodiments, the display device 10 further includes a plurality of pads PD1, and the plurality of pads PD1 are respectively electrically connected to the plurality of first conductors 152 and the driving element 181. In this way, the driving element 181 can individually provide signals to a plurality of first lower electrode patterns E1B and a plurality of first upper electrode patterns E1T.

[0077] In some embodiments, the display device 10 further includes a display medium layer 170, which is located between the first electrode 130 and the second substrate 120. In some embodiments, a first upper electrode pattern layer 132 of the first electrode 130 is located between a first lower electrode pattern layer 131 and the display medium layer 170. In some embodiments, the display medium layer 170 contains display medium molecules, such as cholesteric liquid crystal (CLC) molecules. In some embodiments, the cholesteric liquid crystal molecules can switch between a focal conic state, a homeotropic state, and a planar state. When the cholesteric liquid crystal molecules are in the focal conic state or the homeotropic state, the display medium layer 170 can be in a transmissive state. When the cholesteric liquid crystal molecules are in the planar state, the display medium layer 170 can be in a reflective state and reflect incoming light, and the wavelength of the reflected light can be determined by the pitch of the cholesteric liquid crystal molecules.

[0078] In some embodiments, the display device 10 further includes a second electrode 140, which is located between the display medium layer 170 and the second substrate 120. In some embodiments, the display medium layer 170 is located between the first electrode 130 and the second electrode 140. The second electrode 140 may include a plurality of mutually separated strip electrodes, and the extending direction of the second electrode 140 intersects the extending direction of the first electrode 130. In this way, the overlapping area of ​​the first electrode 130 and the second electrode 140 can drive the display medium molecules in the display medium layer 170 to change direction, thereby serving as the effective area of ​​an individual sub-pixel of the display device 10. In some embodiments, the plurality of strip electrodes of the second electrode 140 do not all belong to the same film layer. In some embodiments, the plurality of strip electrodes of the second electrode 140 are distributed across two film layers.

[0079] For example, the second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142. In some embodiments, the second upper electrode pattern layer 142 of the second electrode 140 is located between the second lower electrode pattern layer 141 and the display medium layer 170. In some embodiments, the display device 10 further includes an insulating layer 122, and the insulating layer 122 separates the second lower electrode pattern layer 141 and the second upper electrode pattern layer 142.

[0080] In some embodiments, the second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, which are separated from each other. In some embodiments, the second lower electrode patterns E2B have a strip pattern, and the plurality of second lower electrode patterns E2B extend parallel to each other along a second direction D2. In some embodiments, the extending direction of the second lower electrode patterns E2B intersects the extending direction of the first lower electrode pattern E1B. In some embodiments, a plurality of gaps G3 are provided between the plurality of second lower electrode patterns E2B, and the width W5 of the plurality of gaps G3 along the first direction D1 is substantially the same. In some embodiments, the width W5 of the gaps G3 is approximately 10 μm.

[0081] In some embodiments, a second upper electrode pattern layer 142 is located above a second lower electrode pattern layer 141, and the second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T separated from each other. In some embodiments, the second upper electrode patterns E2T have a strip pattern, and the extending direction of the second upper electrode patterns E2T is the same as the extending direction of the second lower electrode patterns E2B. In some embodiments, the plurality of second upper electrode patterns E2T extend parallel to each other along a second direction D2. In some embodiments, the extending direction of the second upper electrode patterns E2T intersects the extending direction of the first upper electrode pattern E1T. In some embodiments, a plurality of gaps G4 are provided between the plurality of second upper electrode patterns E2T, and the width W6 of the plurality of gaps G4 along the first direction D1 is substantially the same. In some embodiments, the width W6 of the gaps G4 is approximately 10 μm.

[0082] In some embodiments, a plurality of second upper electrode patterns E2T partially overlap a plurality of second lower electrode patterns E2B. In some embodiments, the overlap width W7 between the second lower electrode pattern E2B and the second upper electrode pattern E2T is approximately 1.5 μm to 3 μm. In some embodiments, the potentials of the overlapping second upper electrode patterns E2T and the second lower electrode patterns E2B are not the same. In some embodiments, the voltage of the second upper electrode pattern E2T is approximately 80% to 95% of the voltage of the overlapping second lower electrode patterns E2B.

[0083] In some embodiments, the maximum electric field strength formed in the display dielectric layer 170 by the overlapping first upper electrode pattern E1T and the first lower electrode pattern E1B is substantially the same. In some embodiments, the maximum electric field strength formed in the display dielectric layer 170 by the overlapping second upper electrode pattern E2T and the second lower electrode pattern E2B is substantially the same.

[0084] In some embodiments, multiple second upper electrode patterns E2T partially overlap multiple gaps G3 between multiple second lower electrode patterns E2B. In some embodiments, the side S3 of the second upper electrode pattern E2T in the direction perpendicular to its extending direction (i.e., the second direction D2) (i.e., the first direction D1) partially overlaps the second lower electrode pattern E2B, and the side S4 of the second upper electrode pattern E2T opposite to the side S3 does not overlap the second lower electrode pattern E2B. In some embodiments, the distance W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B is greater than 0 and less than 10 μm. That is, each second upper electrode pattern E2T only partially overlaps one corresponding second lower electrode pattern E2B and does not overlap the remaining second lower electrode patterns E2B to avoid parasitic capacitance. In some embodiments, the distance W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B can be further reduced to about 2 μm to 5 μm to reduce the invalid area of ​​each sub-pixel. In some embodiments, the spacing W8 is the minimum spacing between the second upper electrode pattern E2T and the non-overlapping second lower electrode pattern E2B.

[0085] Since the spacing W4 between the first upper electrode pattern E1T and the first lower electrode pattern E1B and the spacing W8 between the second upper electrode pattern E2T and the second lower electrode pattern E2B can be further reduced, the proportion of the ineffective area where the first electrode 130 and the second electrode 140 do not overlap with each other to the effective area where the first electrode 130 and the second electrode 140 overlap with each other can be further reduced, thereby improving the reflectivity of the display device 10.

[0086] In some embodiments, the display device 10 further includes a second conductive layer 160 disposed on a second substrate 120 and located between a first substrate 110 and a second substrate 120. In some embodiments, the second conductive layer 160 is located between a second electrode 140 and a second substrate 120. In some embodiments, the display device 10 further includes an insulating layer 121, which separates the second conductive layer 160 from the second electrode 140. In some embodiments, the second conductive layer 160 includes a plurality of second conductive lines 162, each of which is electrically independent. In some embodiments, the plurality of second conductive lines 162 are physically separated from each other. In some embodiments, a plurality of second lower electrode patterns E2B and a plurality of second upper electrode patterns E2T of the second electrode 140 are electrically connected to the plurality of second conductive lines 162. In some embodiments, the display device 10 further includes a plurality of pads PD22 disposed on the second substrate 120, and the plurality of pads PD22 are electrically connected to the plurality of second conductive lines 162.

[0087] In some embodiments, the first lower electrode pattern layer 131, the first upper electrode pattern layer 132, the second lower electrode pattern layer 141, and the second upper electrode pattern layer 142 are made of transparent conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable transparent conductive materials. In some embodiments, the insulating layers I11, I12, I21, and I22 may be made of transparent insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, a stack of the above materials, or other suitable materials. In some embodiments, the first conductive layer 150 and the second conductive layer 160 are made of metals with good conductivity, such as aluminum, molybdenum, titanium, copper, or alloys or stacks of the above metals, but the present invention is not limited thereto.

[0088] In some embodiments, the display device 10 further includes a driving element 182, and a plurality of second wires 162 of the second conductive layer 160 are electrically connected to the driving element 182. In some embodiments, the driving element 182 is disposed on the first substrate 110, and the driving elements 181 and 182 are respectively disposed on different sides of the first substrate 110. In some embodiments, the display device 10 further includes a plurality of pads PD21, and the plurality of pads PD21 are electrically connected to the plurality of second wires 162 and the driving element 182 respectively. For example, the display device 10 further includes a plurality of connectors AF, and when the first substrate 110 and the second substrate 120 are assembled to form a configuration as shown in the figure, the connection is made as shown in the figure. Figure 1B In the illustrated display structure, multiple connectors AF can be electrically connected to multiple pads PD21 on the first substrate 110 and multiple pads PD22 on the second substrate 120, respectively, so that multiple second wires 162 can be electrically connected to the driving element 182 through multiple pads PD22, multiple connectors AF, and multiple pads PD21, respectively. In this way, the driving element 182 can individually provide signals to multiple second lower electrode patterns E2B and multiple second upper electrode patterns E2T.

[0089] In some embodiments, the pads PD1, PD21, and PD22 are made of highly conductive metals, such as aluminum, molybdenum, titanium, copper, or alloys or stacks of the above metals, but the present invention is not limited thereto. In some embodiments, the connector AF is made of anisotropic conductive film (ACF).

[0090] In some embodiments, the display device 10 includes three sets of... Figure 1BThe display structure shown above allows the three sets of display structures to be stacked vertically, with the overlapping areas of the first electrode 130 and the second electrode 140 in each set overlapping each other. Furthermore, the display medium molecules in the display medium layer 170 of each set of display structures can be adjusted so that the reflected light wavelengths of the display medium layer 170 in each set of display structures are different. In this way, the overlapping area of ​​the first electrode 130 and the second electrode 140 in each set of display structures can serve as a sub-pixel of the display device 10, and the overlapping sub-pixels in the three sets of display structures can constitute a pixel of the display device 10, enabling the display device 10 to achieve full-color display using a "superimposed" primary color system.

[0091] The following uses Figures 2A to 9 Further embodiments of the present invention will be described, and the following will be used... Figures 1A to 1D The component designations and related content of the embodiments are as follows: the same designations are used to represent the same or similar components, and descriptions of identical technical content are omitted. For explanations of the omitted parts, please refer to... Figures 1A to 1D The embodiments described below will not be repeated.

[0092] Figures 2A to 6B This is a cross-sectional schematic diagram illustrating the steps of a method for manufacturing the first electrode 130 of a display device 10 according to an embodiment of the present invention. Figures 2A to 6B middle, Figure 2B It is along Figure 2A A schematic diagram of the cross section drawn by section line B-B'; Figure 3B It is along Figure 3A A schematic diagram of the cross section drawn by section line C-C'; Figure 4B It is along Figure 4A A schematic diagram of the cross section drawn by the section line D-D'; Figure 5B It is along Figure 5A A schematic diagram of the cross section drawn by the section line E-E'; Figure 6B It is along Figure 6A A schematic diagram of the cross section drawn by the section line F-F'.

[0093] First, please refer to Figure 2A and Figure 2B A first conductive layer 150 is formed on the first substrate 110. The first conductive layer 150 may include a plurality of first conductive lines 152, and the plurality of first conductive lines 152 are separated from each other. In some embodiments, the plurality of first conductive lines 152 extend parallel to each other in the same direction. In some embodiments, a plurality of pads PD1 and a plurality of pads PD21 may also be formed on the first substrate 110, and the plurality of first conductive lines 152 are respectively connected to the plurality of pads PD1.

[0094] Next, please refer to Figure 3A and Figure 3BAn insulating layer I11 is formed on the first conductive layer 150 and the first substrate 110. The insulating layer I11 may have a plurality of through holes V1, and the plurality of through holes V1 overlap, for example, an odd number of first conductive lines 152, such that a portion of the odd number of first conductive lines 152 is exposed.

[0095] Next, please refer to Figure 4A and Figure 4B A first lower electrode pattern layer 131 is formed on the insulating layer I11. The first lower electrode pattern layer 131 may include a plurality of first lower electrode patterns E1B, and the plurality of first lower electrode patterns E1B overlap the plurality of through holes V1 of the insulating layer I11, so that the plurality of first lower electrode patterns E1B can be electrically connected to an odd number of first wires 152 through the through holes V1 respectively.

[0096] Next, please refer to Figure 5A and Figure 5B An insulating layer I12 is formed on the first lower electrode pattern layer 131 and the insulating layer I11. Next, a plurality of through-holes V2 are formed penetrating the insulating layers I11 and I12, and the plurality of through-holes V2 overlap an even number of first conductive lines 152, such that a portion of the even number of first conductive lines 152 is exposed. In some embodiments, when the plurality of through-holes V1 of the insulating layer I11 expose an even number of first conductive lines 152, the plurality of through-holes V2 expose an odd number of first conductive lines 152.

[0097] In some embodiments, multiple through-holes V2 may be formed simultaneously with multiple through-holes V3, which penetrate insulating layers I11 and I12, and overlap multiple pads PD1 and multiple pads PD21 respectively. In other words, the multiple through-holes V3 expose multiple pads PD1 and multiple pads PD21 respectively.

[0098] Next, please refer to Figure 6A and Figure 6B A first upper electrode pattern layer 132 is formed on the insulating layer I12. The first upper electrode pattern layer 132 may include a plurality of first upper electrode patterns E1T, and the plurality of first upper electrode patterns E1T overlap a plurality of through holes V2, so that the plurality of first upper electrode patterns E1T can be electrically connected to an even number of first wires 152 through the through holes V2 respectively.

[0099] In some embodiments, one side of the first upper electrode pattern E1T may partially overlap with the corresponding first lower electrode pattern E1B as needed, and the spacing between the other side of the non-overlapping first lower electrode pattern E1B of the first upper electrode pattern E1T and the adjacent first lower electrode pattern E1B may be less than 10 μm. For example, by adjusting the relative positions of the photomask used to form the first upper electrode pattern E1T and the photomask used to form the first lower electrode pattern E1B, the minimum spacing between the other side of the non-overlapping first lower electrode pattern E1B of the first upper electrode pattern E1T and the non-overlapping first lower electrode pattern E1B can be easily made less than 10 μm, for example, this minimum spacing is about 2 μm to 5 μm, to reduce the invalid area of ​​each sub-pixel.

[0100] In some embodiments, the manufacturing method of the second electrode 140 is similar to the manufacturing method of the first electrode 130 described above, and will not be repeated here.

[0101] In some embodiments, driving elements 181 and 182 may also be disposed on the first substrate 110, and the plurality of pins PN1 of driving element 181 may pass through the plurality of through holes V3 and be electrically connected to the plurality of pads PD1, and the plurality of pins PN2 of driving element 182 (see reference) Figure 1B It can also pass through multiple through holes V3 to electrically connect multiple pads PD21.

[0102] Figure 7 This is a top view schematic diagram of a first substrate 110, a first electrode 130, a first conductive layer 750, and a driving element 181 according to another embodiment of the present invention. Figure 1C Compared to the first conductor layer 150 shown, Figure 7 The main difference of the first conductor layer 750 shown is that multiple first conductors 752 of the first conductor layer 750 also extend below multiple first lower electrode patterns E1B and multiple first upper electrode patterns E1T of the first electrode 130, respectively, to accelerate the signal transmission speed of the first lower electrode patterns E1B and the first upper electrode patterns E1T, thereby reducing the signal delay of each sub-pixel. In some embodiments, the linewidth W9 of the first conductor 752 is 5μm to 10μm.

[0103] Figure 8 This is a top view schematic diagram of the second substrate 120, the second electrode 140, and the second conductive layer 860 according to another embodiment of the present invention. Figure 1D Compared to the second conductor layer 160 shown, Figure 8The main difference of the second conductor layer 860 shown is that multiple second conductors 862 of the second conductor layer 860 also extend below multiple second lower electrode patterns E2B and multiple second upper electrode patterns E2T of the second electrode 140, respectively, to accelerate the signal transmission speed of the second lower electrode patterns E2B and the second upper electrode patterns E2T, thereby reducing the signal delay of each sub-pixel. In some embodiments, the linewidth W10 of the second conductors 862 is 5μm to 10μm.

[0104] Figure 9 This is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention. The display device 20 includes: a first substrate 110, a second substrate 120, a first electrode 130, a second electrode 140, a display medium layer 170, a driving element 182, pads PD21 and PD22, a connector AF, and insulating layers I11, I12, I21, and I22. The first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132. The first lower electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T. The second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142. The second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, and the second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T.

[0105] With Figure 1B Compared to the display device 10 shown, Figure 9 The main difference in the display device 20 is that the insulating layer I12 of the display device 20 only covers the portion of the first lower electrode pattern E1B that overlaps with the first upper electrode pattern E1T to achieve electrical separation between the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, the insulating layer I12 includes a plurality of mutually separated strip-shaped insulating patterns IP. In some embodiments, the extending direction of the plurality of strip-shaped insulating patterns IP is parallel to the extending direction of the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, each strip-shaped insulating pattern IP partially overlaps the corresponding first lower electrode pattern E1B, and each strip-shaped insulating pattern IP partially overlaps the corresponding first upper electrode pattern E1T.

[0106] In summary, the display device of the present invention increases the ratio of the effective area where the first electrode and the second electrode overlap to the ineffective area where the first electrode and the second electrode do not overlap by reducing the minimum spacing between the first upper electrode pattern and the non-overlapping first lower electrode pattern, and by reducing the minimum spacing between the second upper electrode pattern and the non-overlapping second lower electrode pattern, thereby improving the reflectivity of the display device.

[0107] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A display device, comprising: First substrate; A first conductive layer is located on the first substrate and includes a plurality of first conductive lines; A first electrode, located on the first substrate, includes a plurality of electrically separated first lower electrode patterns and a plurality of first upper electrode patterns, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively electrically connected to the plurality of first wires, the plurality of first lower electrode patterns have a plurality of first gaps between them, and the plurality of first upper electrode patterns respectively overlap the plurality of first gaps. Each of the plurality of first upper electrode patterns partially overlaps only one of the plurality of first lower electrode patterns, and Each of the plurality of first upper electrode patterns has a side edge, the side edge being in the same direction of extension as the plurality of first upper electrode patterns, and the vertical projection of the side edge on the first substrate being separate from the vertical projection of each of the plurality of first lower electrode patterns on the first substrate. The second substrate, wherein the first conductive layer and the first electrode are located between the first substrate and the second substrate; A display dielectric layer is located between the first electrode and the second substrate; as well as The second electrode is located between the display medium layer and the second substrate.

2. The display device of claim 1, wherein each of the plurality of first wires is electrically independent.

3. The display device of claim 1, wherein the plurality of first lower electrode patterns are separated from each other.

4. The display device of claim 1, wherein the plurality of first upper electrode patterns are separated from each other.

5. The display device of claim 1, wherein the plurality of first lower electrode patterns extend in the same direction as the plurality of first upper electrode patterns.

6. The display device of claim 1, wherein the overlap width between the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm.

7. The display device of claim 1, wherein the potentials of the overlapping first upper electrode pattern and the first lower electrode pattern are different.

8. The display device of claim 1, wherein the distance between the side of the non-overlapping first lower electrode pattern of the first upper electrode pattern and the adjacent non-overlapping first lower electrode pattern is greater than 0 and less than 10 μm.

9. The display device of claim 1, wherein the second electrode comprises a plurality of second lower electrode patterns, and the extending direction of the plurality of second lower electrode patterns is perpendicular to the extending direction of the plurality of first lower electrode patterns.

10. The display device of claim 9, wherein the second electrode further comprises a plurality of second upper electrode patterns, and the plurality of second upper electrode patterns extend in the same direction as the plurality of second lower electrode patterns.

11. The display device of claim 10, wherein the plurality of second lower electrode patterns have a plurality of second gaps between them, and the plurality of second upper electrode patterns respectively overlap the plurality of second gaps.

12. The display device of claim 10, further comprising a second conductive layer located between the second substrate and the display medium layer, and including a plurality of second conductive lines, wherein the plurality of second lower electrode patterns and the plurality of second upper electrode patterns are respectively electrically connected to the plurality of second conductive lines.

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