Wafer warpage adjustment structure and preparation method thereof

Abstract

The embodiments of the present disclosure disclose a wafer warping adjustment structure and a preparation method thereof. The wafer warping adjustment structure comprises a wafer, the wafer comprising oppositely arranged upper and lower surfaces, the upper surface being used for forming a semiconductor device; a first dielectric layer located on the upper surface of the wafer; and a second dielectric layer located on the lower surface of the wafer. The first and second dielectric layers each comprise a first region and / or a second region, and further comprise other regions except the first and / or second regions. The first region covers a part of the wafer that protrudes in a direction perpendicular to the surface of the wafer and extending from the wafer to the dielectric layer in an independent state, and the second region covers a part of the wafer that is recessed in the direction perpendicular to the surface of the wafer and extending from the wafer to the dielectric layer in the independent state. The thermal expansion coefficient of the material of the first region is greater than the thermal expansion coefficient of the material of the wafer, and the thermal expansion coefficient of the material of the second region is less than the thermal expansion coefficient of the material of the wafer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor process technology, and in particular to a wafer warpage adjustment structure and its preparation method. Background Technology

[0002] Warpage occurs during wafer manufacturing as wafer size increases or thickness decreases. Warpage occurs due to the differences in the coefficients of thermal expansion (CTE) between the various components that make up a chip or semiconductor package, when chips or packages are manufactured on a wafer. Warpage refers to the undesirable bending of a semiconductor chip or semiconductor package. Summary of the Invention

[0003] In view of this, the present disclosure provides a wafer warpage adjustment structure and a method for preparing the same.

[0004] According to a first aspect of the present disclosure, a wafer warpage adjustment structure is provided, comprising:

[0005] A wafer, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device;

[0006] A first dielectric layer is located on the upper surface of the wafer;

[0007] The second dielectric layer is located on the lower surface of the wafer;

[0008] Both the first dielectric layer and the second dielectric layer include a first region and / or a second region, and also include other regions besides the first region and / or the second region; wherein,

[0009] The first region covers the portion of the wafer that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer in an independent state; the second region covers the portion of the wafer that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer in an independent state; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.

[0010] In some embodiments, the material of the first region of the first dielectric layer and the second dielectric layer includes silicon nitride or silicon carbide;

[0011] The material of the second region of the first dielectric layer and the second dielectric layer includes quartz.

[0012] In some embodiments, the coefficient of thermal expansion of the materials in the first region of the first dielectric layer and the second dielectric layer is greater than the coefficient of thermal expansion of the materials in other regions of the first dielectric layer and the second dielectric layer.

[0013] The coefficient of thermal expansion of the materials in the second region of the first dielectric layer and the second dielectric layer is less than that of the materials in other regions of the first dielectric layer and the second dielectric layer.

[0014] In some embodiments, the thickness of the first region of the first dielectric layer and the second dielectric layer is greater than or equal to the thickness of other regions of the first dielectric layer and the second dielectric layer.

[0015] In some embodiments, the thickness of the first region of the first dielectric layer and the second dielectric layer is 1 to 4 times the thickness of the other regions of the first dielectric layer and the second dielectric layer.

[0016] In some embodiments, the dielectric layer of the first region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.

[0017] In some embodiments, the dielectric layer of the second region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.

[0018] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.

[0019] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.

[0020] According to a second aspect of the present disclosure, a method for preparing a wafer warp adjustment structure is provided, comprising:

[0021] A wafer is provided, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device; the wafer includes a warped region;

[0022] A first dielectric layer is formed on the upper surface of the wafer;

[0023] A second dielectric layer is formed on the lower surface of the wafer;

[0024] Both the first dielectric layer and the second dielectric layer include a first region and / or a second region, and also include other regions besides the first region and / or the second region; wherein,

[0025] The first region covers the portion of the wafer warped region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, and the second region covers the portion of the wafer warped region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.

[0026] In some embodiments, the material of the first region of the first dielectric layer and the second dielectric layer includes silicon nitride or silicon carbide;

[0027] The material of the second region of the first dielectric layer and the second dielectric layer includes quartz.

[0028] In some embodiments, the coefficient of thermal expansion of the materials in the first region of the first dielectric layer and the second dielectric layer is greater than the coefficient of thermal expansion of the materials in other regions of the first dielectric layer and the second dielectric layer.

[0029] The coefficient of thermal expansion of the materials in the second region of the first dielectric layer and the second dielectric layer is less than that of the materials in other regions of the first dielectric layer and the second dielectric layer.

[0030] In some embodiments, forming a first dielectric layer on the upper surface of the wafer and forming a second dielectric layer on the lower surface of the wafer includes:

[0031] A first dielectric prelayer is formed on the upper surface of the wafer;

[0032] A second dielectric pre-layer is formed on the lower surface of the wafer;

[0033] Etching portions of the first dielectric prelayer and the second dielectric prelayer in the first region to form a first trench; filling the first trench with a first material, wherein the coefficient of thermal expansion of the first material is greater than the coefficient of thermal expansion of the wafer material; and / or,

[0034] The first dielectric prelayer and the second dielectric prelayer are etched in portions of the second region to form a second trench; the second trench is filled with a second material, the coefficient of thermal expansion of the second material being less than that of the material of the wafer.

[0035] In some embodiments, the thickness of the first region of the first dielectric layer and the second dielectric layer is greater than or equal to the thickness of other regions of the first dielectric layer and the second dielectric layer.

[0036] In some embodiments, the thickness of the first region of the first dielectric layer and the second dielectric layer is 1 to 4 times the thickness of the other regions of the first dielectric layer and the second dielectric layer.

[0037] In some embodiments, the dielectric layer of the first region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.

[0038] In some embodiments, the dielectric layer of the second region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.

[0039] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.

[0040] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.

[0041] In some embodiments, the warped region of the wafer is shaped like a saddle or a wave.

[0042] In this embodiment, a dielectric layer is formed on the upper and lower surfaces of the wafer. The thermal expansion coefficient of the protruding portion of the dielectric layer in the direction extending from the wafer to the dielectric layer is greater than that of the wafer, and the thermal expansion coefficient of the recessed portion in the direction extending from the wafer to the dielectric layer is less than that of the wafer. This allows for the formation of materials with different thermal expansion coefficients in local areas to improve wafer warpage. The process is simple, flexible, and fast, applicable to any complex warpage shape, and can be used in wafer stacking of different wafer systems to achieve the integration of multilayer wafer systems. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the wafer warpage adjustment structure provided in an embodiment of the present disclosure;

[0045] Figures 2a to 2e Other examples of wafer warp adjustment structures provided in embodiments of this disclosure;

[0046] Figure 3 This is a schematic diagram of the wafer warpage adjustment structure after leveling, provided in an embodiment of the present disclosure.

[0047] Figure 4 A schematic flowchart illustrating the fabrication method of the wafer warp adjustment structure provided in this embodiment of the disclosure;

[0048] Figures 5a to 5f This is a schematic diagram of the wafer warp adjustment structure provided in the embodiments of this disclosure during the fabrication process.

[0049] Explanation of reference numerals in the attached figures:

[0050] 10 - Wafer; 11 - Top surface; 12 - Bottom surface;

[0051] 21-First dielectric layer; 22-Second dielectric layer; 21'-First dielectric layer pre-layer; 22'-Second dielectric layer pre-layer; 201-First trench; 202-Second trench;

[0052] 210 - First region; 211 - First sub-region of the first layer; 212 - First sub-region of the second layer; 213 - First sub-region of the first layer; 214 - Second sub-region of the first layer; 215 - Third sub-region of the first layer;

[0053] 220 - Second region; 221 - First layer, second sub-region; 222 - Second layer, second sub-region; 223 - First second sub-region; 224 - Second second sub-region; 225 - Third second sub-region;

[0054] 230 - Other areas;

[0055] 30 - Mask layer; 301 - Patterned mask layer. Detailed Implementation

[0056] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0057] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0063] During the wafer manufacturing process, the silicon wafers used to make the wafers may have irregular warping deformation beforehand, or the wafers may be cooled from a high temperature of about 400°C to a room temperature of 25°C after the wafers are made. During this process, the coefficient of thermal expansion (CTE) of the internal dielectric materials (such as Si and SiO2) will be mismatched, which will cause the wafers to warp and deform, which is not conducive to chip manufacturing.

[0064] In some embodiments, flattening is mainly achieved by adding a dielectric layer to the wafer. However, this method can only be applied to the entire area and it is difficult to achieve "local" adjustment. This is because the same wafer chips are usually kept the same or each photomask is the same, and the dielectric layer formed is made of the same material. Therefore, it is difficult to ensure that the wafer is completely flattened. Furthermore, this method cannot flatten wafers with complex shapes (such as saddle-shaped or wavy shapes).

[0065] Based on this, the present disclosure provides a wafer warpage adjustment structure. Figure 1 This is a schematic diagram of the wafer warpage adjustment structure provided in an embodiment of the present disclosure.

[0066] See Figure 1 The wafer warpage adjustment structure includes:

[0067] Wafer 10, the wafer 10 including an upper surface 11 and a lower surface 12 disposed opposite to each other, the upper surface 11 being used to form a semiconductor device;

[0068] The first dielectric layer 21 is located on the upper surface 11 of the wafer 10;

[0069] The second dielectric layer 22 is located on the lower surface 12 of the wafer 10;

[0070] Both the first dielectric layer 21 and the second dielectric layer 22 include a first region 210 and / or a second region 220, and also include other regions 230 besides the first region 210 and / or the second region 220; wherein,

[0071] The first region 210 covers the portion of the wafer 10 that protrudes in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer in an independent state; the second region 220 covers the portion of the wafer 10 that is recessed in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer in an independent state; the coefficient of thermal expansion of the material of the first region 210 is greater than the coefficient of thermal expansion of the material of the wafer 10; the coefficient of thermal expansion of the material of the second region 220 is less than the coefficient of thermal expansion of the material of the wafer 10.

[0072] In this embodiment, materials with different coefficients of thermal expansion are formed in local areas to improve the warpage of the wafer. The process is simple, flexible and fast, applicable to any complex warpage shape, and can be applied to wafer stacking in different wafer systems to achieve the integration of multi-layer wafer systems.

[0073] In one embodiment, the material of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 includes silicon nitride or silicon carbide; the material of the second region 220 of the first dielectric layer 21 and the second dielectric layer 22 includes quartz.

[0074] In one embodiment, the coefficient of thermal expansion of the material of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is greater than the coefficient of thermal expansion of the material of the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22;

[0075] The coefficient of thermal expansion of the material in the second region 220 of the first dielectric layer 21 and the second dielectric layer 22 is less than the coefficient of thermal expansion of the material in the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22.

[0076] The coefficient of thermal expansion of the first and second dielectric layers in the outwardly convex regions is greater than that in other regions of the first and second dielectric layers, while the coefficient of thermal expansion of the inwardly concave regions is smaller than that in other regions. Thus, the coefficient of thermal expansion of other regions is between that of the first and second regions, and these other regions can also play a role in improving wafer warpage, thereby better leveraging the improvement effect of the first and second dielectric layers on wafer warpage.

[0077] Specifically, the wafer is made of silicon (Si), which has a coefficient of thermal expansion of 2.7 × 10⁻⁶. -6 / ℃, the material of the first dielectric layer and the second dielectric layer, excluding the first region and / or the second region, is silicon dioxide (SiO2), and the coefficient of thermal expansion of silicon dioxide is 0.55×10. -6 At ℃, the coefficient of thermal expansion of silicon nitride (SiN) is 3.2 × 10⁻⁶. -6At ℃, the coefficient of thermal expansion of silicon carbide (SiC) is 2.8 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of quartz is 0.33×10⁻⁶. -6 / ℃. This data shows that the coefficient of thermal expansion of silicon nitride or silicon carbide is greater than that of silicon and silicon dioxide, while the coefficient of thermal expansion of quartz is less than that of silicon and silicon dioxide. In other words, the coefficient of thermal expansion of the material in the first region is greater than that of the wafer material and the materials in other regions of the first and second dielectric layers excluding the first and / or second regions. The coefficient of thermal expansion of the material in the second region is less than that of the wafer material and the materials in other regions of the first and second dielectric layers excluding the first and / or second regions.

[0078] In one embodiment, such as Figure 2a As shown, the thickness of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is greater than or equal to the thickness of other regions 230 of the first dielectric layer 21 and the second dielectric layer 22. The thickness of the first dielectric layer and the second dielectric layer in the first region is greater than or equal to the thickness of other regions of the first dielectric layer and the second dielectric layer. Therefore, the first dielectric layer and the second dielectric layer have better thermal expansion and contraction effects in this region, which can better improve the wafer warpage problem.

[0079] Specifically, in one embodiment, the thickness of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is 1 to 4 times the thickness of the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22. Within this thickness range, the first and second dielectric layers have the best effect on improving wafer warpage, ensuring that the thickness is not too small to improve wafer warpage, nor too large to overcorrect the wafer and cause it to bend in the opposite direction.

[0080] In one embodiment, the dielectric layer of the first region 210 includes multiple dielectric layers, and in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer of the first region 210 decreases in a stepwise manner.

[0081] Thus, the dielectric layer closest to the wafer in the first region has the largest coefficient of thermal expansion and a larger difference in coefficient of thermal expansion with the wafer, which can better improve the wafer warpage. Meanwhile, the dielectric layer farther away from the wafer has a decreasing coefficient of thermal expansion, which can better adjust the degree of warpage and avoid overcorrection.

[0082] Specifically, such as Figure 2bAs shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward the dielectric layer, the first region 210 includes a first sub-region 211 and a second sub-region 212, wherein the coefficient of thermal expansion of the materials of the first sub-region 211 and the second sub-region 212 decreases in a stepwise manner.

[0083] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 211 of the first layer and the first sub-region 212 of the second layer can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 211 of the first layer and the first sub-region 212 of the second layer can use the same material, but different concentrations of ions can be doped in each layer to reduce the coefficients of thermal expansion of the first sub-region 211 of the first layer and the first sub-region 212 of the second layer in a stepwise manner.

[0084] In one embodiment, the dielectric layer of the second region 220 includes multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer of the second region 220 increases in a stepwise manner in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer.

[0085] Thus, the dielectric layer closest to the wafer in the second region has the smallest coefficient of thermal expansion and a larger difference in coefficient of thermal expansion with the wafer, which can better improve wafer warpage. Meanwhile, the dielectric layer farther from the wafer has an increasing coefficient of thermal expansion, which can better adjust the degree of warpage and avoid overcorrection.

[0086] Specifically, such as Figure 2b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward the dielectric layer, the second region 220 includes a first layer second sub-region 221 and a second layer second sub-region 222, wherein the coefficient of thermal expansion of the materials of the first layer second sub-region 221 and the second layer second sub-region 222 increases in a stepwise manner.

[0087] Specifically, in some embodiments, the coefficients of thermal expansion of the first layer second sub-region 221 and the second layer second sub-region 222 can be increased in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first layer second sub-region 221 and the second layer second sub-region 222 can use the same material, but different concentrations of ions can be doped in each layer to increase the coefficients of thermal expansion of the first layer second sub-region 221 and the second layer second sub-region 222 in a stepwise manner.

[0088] In some embodiments, the dielectric layer of the first region of the wafer warp adjustment structure includes multiple dielectric layers, and the dielectric layer of the second region includes a single dielectric layer; in other embodiments, the dielectric layer of the first region includes a single dielectric layer, and the dielectric layer of the second region includes multiple dielectric layers; in still other embodiments, such as Figure 2b As shown, the dielectric layer of the first region includes multiple dielectric layers, and the dielectric layer of the second region includes multiple dielectric layers.

[0089] In one embodiment, the coefficient of thermal expansion of the material in the first region 210 of the dielectric layer decreases in a stepwise manner along the direction of decreasing curvature of the curve corresponding to the protrusion.

[0090] Specifically, such as Figure 2c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the first region 210 includes a first sub-region 213, a second first sub-region 214, and a third first sub-region 215. The coefficients of thermal expansion of the materials of the first first sub-region 213, the second first sub-region 214, and the third first sub-region 215 decrease in a stepwise manner.

[0091] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.

[0092] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be made of the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be reduced in a stepwise manner.

[0093] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region 220 of the dielectric layer increases in a stepwise manner.

[0094] Specifically, such as Figure 2cAs shown, along the direction of decreasing curvature of the curve corresponding to the depression, the second region 220 includes a first second sub-region 223, a second second sub-region 224, and a third second sub-region 225. The coefficients of thermal expansion of the materials of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 increase in a stepwise manner.

[0095] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.

[0096] Specifically, in some embodiments, the coefficients of thermal expansion of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 can increase in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 can use the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 increase in a stepwise manner.

[0097] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region remains unchanged; in other embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region remains unchanged, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner; in still other embodiments, such as Figure 2c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, and along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner.

[0098] In one embodiment, the curved shape of the wafer can be saddle-shaped or wavy.

[0099] Specifically, in some embodiments, such as Figures 1 to 2c As shown, the wafer is bent in a wavy shape; in some other embodiments, such as Figure 2d and Figure 2e As shown, the wafer is bent in a saddle shape, wherein, as Figure 2d As shown, the first dielectric layer 21 and the second dielectric layer 22 only include the first region 210, as... Figure 2e As shown, the first dielectric layer 21 and the second dielectric layer 22 only include the second region 220.

[0100] In this embodiment of the disclosure, after forming materials with different coefficients of thermal expansion in local areas of a bent wafer, the wafer can be leveled so that the wafer ultimately reaches the desired shape. Figure 3 The shape shown.

[0101] This disclosure also provides a method for fabricating a wafer warp adjustment structure; please refer to the appendix for details. Figure 4 As shown in the figure, the method includes the following steps:

[0102] Step 401: Provide a wafer, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device; the wafer including a warped region;

[0103] Step 402: A first dielectric layer is formed on the upper surface of the wafer; a second dielectric layer is formed on the lower surface of the wafer; both the first dielectric layer and the second dielectric layer include a first region and / or a second region, and also include other regions besides the first region and / or the second region; wherein, the first region covers the portion of the wafer warp region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer to the dielectric layer, and the second region covers the portion of the wafer warp region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer to the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.

[0104] The preparation method of the wafer warp adjustment structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0105] Figures 5a to 5f This is a schematic diagram of the wafer warp adjustment structure provided in the embodiments of this disclosure during the fabrication process.

[0106] First, see Figure 5a Step 401 is performed, providing a wafer 10, the wafer 10 including an upper surface 11 and a lower surface 12 disposed opposite to each other, the upper surface 11 being used to form a semiconductor device; the wafer 10 includes a warped region.

[0107] Next, see Figures 5b to 5fStep 402 is executed, forming a first dielectric layer 21 on the upper surface 11 of the wafer 10; forming a second dielectric layer 22 on the lower surface 12 of the wafer 10; both the first dielectric layer 21 and the second dielectric layer 22 include a first region 210 and / or a second region 220, and also include other regions 230 besides the first region 210 and / or the second region 220; wherein, the first region 210 covers the portion of the warped region of the wafer 10 that protrudes in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer, and the second region 220 covers the portion of the warped region of the wafer 10 that is recessed in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer; the coefficient of thermal expansion of the material of the first region 210 is greater than the coefficient of thermal expansion of the material of the wafer 10; the coefficient of thermal expansion of the material of the second region 220 is less than the coefficient of thermal expansion of the material of the wafer 10.

[0108] In one embodiment, the formation of a first dielectric layer 21 on the upper surface 11 of the wafer 10 and the formation of a second dielectric layer 22 on the lower surface 12 of the wafer 10 includes:

[0109] A first dielectric prelayer 21' is formed on the upper surface 11 of the wafer 10;

[0110] A second dielectric prelayer 22' is formed on the lower surface 12 of the wafer 10;

[0111] Etching portions of the first dielectric prelayer 21' and the second dielectric prelayer 22' in the first region forms a first trench 201; filling the first trench 201 with a first material, the first material having a coefficient of thermal expansion greater than that of the material of the wafer 10; and / or,

[0112] The first dielectric layer pre-layer 21' and the second dielectric layer pre-layer 22' are etched in portions of the second region to form a second trench 202; the second trench 202 is filled with a second material, the coefficient of thermal expansion of the second material being less than the coefficient of thermal expansion of the material of the wafer 10.

[0113] Specifically, see first. Figure 5b A first dielectric layer prelayer 21' is formed on the upper surface 11 of the wafer 10; a second dielectric layer prelayer 22' is formed on the lower surface 12 of the wafer 10.

[0114] In practice, the first dielectric layer pre-layer 21' and the second dielectric layer pre-layer 22' can be formed using one or more thin film deposition processes; specifically, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0115] Next, see Figures 5c to 5e Etching portions of the first dielectric prelayer 21' and the second dielectric prelayer 22' in the first region to form a first trench 201; and / or etching portions of the first dielectric prelayer 21' and the second dielectric prelayer 22' in the second region to form a second trench 202.

[0116] Specifically, a mask layer 30 can be grown on the upper and lower surfaces of the first dielectric prelayer 21' and the second dielectric prelayer 22'. Then, the mask layer 30 is patterned to form a patterned mask layer 301, displaying the pattern of the first trench and / or the second trench to be etched. This patterning can be achieved through photolithography. The mask layer 30 can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the mask layer 30 is a photoresist mask, it is patterned through steps such as exposure, development, and resist removal. Next, the first trench 201 and / or the second trench 202 with a certain depth are etched according to the pattern of the first trench and / or the second trench to be etched.

[0117] Here, for example, a wet or dry etching process can be used to form the first trench 201 and / or the second trench 202.

[0118] Next, see Figure 5f The first trench 201 is filled with a first material, the coefficient of thermal expansion of which is greater than that of the material of the wafer 10; and / or the second trench 202 is filled with a second material, the coefficient of thermal expansion of which is less than that of the material of the wafer 10.

[0119] In one embodiment, the material of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 includes silicon nitride or silicon carbide; the material of the second region 220 of the first dielectric layer 21 and the second dielectric layer 22 includes quartz.

[0120] In one embodiment, the coefficient of thermal expansion of the material of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is greater than the coefficient of thermal expansion of the material of the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22;

[0121] The coefficient of thermal expansion of the material in the second region 220 of the first dielectric layer 21 and the second dielectric layer 22 is less than the coefficient of thermal expansion of the material in the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22.

[0122] The coefficient of thermal expansion of the first and second dielectric layers in the outwardly convex regions is greater than that in other regions of the first and second dielectric layers, while the coefficient of thermal expansion of the inwardly concave regions is smaller than that in other regions. Thus, the coefficient of thermal expansion of other regions is between that of the first and second regions, and these other regions can also play a role in improving wafer warpage, thereby better leveraging the improvement effect of the first and second dielectric layers on wafer warpage.

[0123] In one embodiment, such as Figure 2b As shown, the thickness of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is greater than or equal to the thickness of other regions 230 of the first dielectric layer 21 and the second dielectric layer 22. The thickness of the first dielectric layer and the second dielectric layer in the first region is greater than or equal to the thickness of other regions of the first dielectric layer and the second dielectric layer. Therefore, the first dielectric layer and the second dielectric layer have better thermal expansion and contraction effects in this region, which can better improve the wafer warpage problem.

[0124] Specifically, in one embodiment, the thickness of the first region 210 of the first dielectric layer 21 and the second dielectric layer 22 is 1 to 4 times the thickness of the other regions 230 of the first dielectric layer 21 and the second dielectric layer 22. Within this thickness range, the first and second dielectric layers have the best effect on improving wafer warpage, ensuring that the thickness is not too small to improve wafer warpage, nor too large to overcorrect the wafer and cause it to bend in the opposite direction.

[0125] In one embodiment, the dielectric layer of the first region 210 includes multiple dielectric layers, and in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer of the first region 210 decreases in a stepwise manner.

[0126] Thus, the dielectric layer closest to the wafer in the first region has the largest coefficient of thermal expansion and a larger difference in coefficient of thermal expansion with the wafer, which can better improve the wafer warpage. Meanwhile, the dielectric layer farther away from the wafer has a decreasing coefficient of thermal expansion, which can better adjust the degree of warpage and avoid overcorrection.

[0127] Specifically, such as Figure 2b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward the dielectric layer, the first region 210 includes a first sub-region 211 and a second sub-region 212, wherein the coefficient of thermal expansion of the materials of the first sub-region 211 and the second sub-region 212 decreases in a stepwise manner.

[0128] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 211 of the first layer and the first sub-region 212 of the second layer can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 211 of the first layer and the first sub-region 212 of the second layer can use the same material, but different concentrations of ions can be doped in each layer to reduce the coefficients of thermal expansion of the first sub-region 211 of the first layer and the first sub-region 212 of the second layer in a stepwise manner.

[0129] In one embodiment, the dielectric layer of the second region 220 includes multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer of the second region 220 increases in a stepwise manner in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer.

[0130] Thus, the dielectric layer closest to the wafer in the second region has the smallest coefficient of thermal expansion and a larger difference in coefficient of thermal expansion with the wafer, which can better improve wafer warpage. Meanwhile, the dielectric layer farther from the wafer has an increasing coefficient of thermal expansion, which can better adjust the degree of warpage and avoid overcorrection.

[0131] Specifically, such as Figure 2b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward the dielectric layer, the second region 220 includes a first layer second sub-region 221 and a second layer second sub-region 222, wherein the coefficient of thermal expansion of the materials of the first layer second sub-region 221 and the second layer second sub-region 222 increases in a stepwise manner.

[0132] Specifically, in some embodiments, the coefficients of thermal expansion of the first layer second sub-region 221 and the second layer second sub-region 222 can be increased in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first layer second sub-region 221 and the second layer second sub-region 222 can use the same material, but different concentrations of ions can be doped in each layer to increase the coefficients of thermal expansion of the first layer second sub-region 221 and the second layer second sub-region 222 in a stepwise manner.

[0133] In some embodiments, the dielectric layer of the first region of the wafer warp adjustment structure includes multiple dielectric layers, and the dielectric layer of the second region includes a single dielectric layer; in other embodiments, the dielectric layer of the first region includes a single dielectric layer, and the dielectric layer of the second region includes multiple dielectric layers; in still other embodiments, such as Figure 2b As shown, the dielectric layer of the first region includes multiple dielectric layers, and the dielectric layer of the second region includes multiple dielectric layers.

[0134] In one embodiment, the coefficient of thermal expansion of the material in the first region 210 of the dielectric layer decreases in a stepwise manner along the direction of decreasing curvature of the curve corresponding to the protrusion.

[0135] Specifically, such as Figure 2c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the first region 210 includes a first sub-region 213, a second first sub-region 214, and a third first sub-region 215. The coefficients of thermal expansion of the materials of the first first sub-region 213, the second first sub-region 214, and the third first sub-region 215 decrease in a stepwise manner.

[0136] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.

[0137] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be made of the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first sub-region 213, the second sub-region 214, and the third sub-region 215 can be reduced in a stepwise manner.

[0138] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region 220 of the dielectric layer increases in a stepwise manner.

[0139] Specifically, such as Figure 2c As shown, along the direction of decreasing curvature of the curve corresponding to the depression, the second region 220 includes a first second sub-region 223, a second second sub-region 224, and a third second sub-region 225. The coefficients of thermal expansion of the materials of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 increase in a stepwise manner.

[0140] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.

[0141] Specifically, in some embodiments, the coefficients of thermal expansion of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 can increase in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 can use the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first second sub-region 223, the second second sub-region 224, and the third second sub-region 225 increase in a stepwise manner.

[0142] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region remains unchanged; in other embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region remains unchanged, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner; in still other embodiments, such as Figure 2c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, and along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner.

[0143] In one embodiment, the warped region of the wafer is saddle-shaped or wavy.

[0144] Specifically, in some embodiments, such as Figure 5f As shown, the wafer is bent in a wavy shape; in some other embodiments, such as Figure 2d and Figure 2e As shown, the wafer is bent in a saddle shape, wherein, as Figure 2d As shown, the first dielectric layer 21 and the second dielectric layer 22 only include the first region 210, as... Figure 2e As shown, the first dielectric layer 21 and the second dielectric layer 22 only include the second region 220.

[0145] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A wafer warpage adjustment structure, characterized in that, include: A wafer, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device; A first dielectric layer is located on the upper surface of the wafer; The second dielectric layer is located on the lower surface of the wafer; Both the first dielectric layer and the second dielectric layer include a first region and / or a second region, and also include other regions besides the first region and / or the second region; wherein, The first region covers the portion of the wafer that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer in an independent state; the second region covers the portion of the wafer that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer in an independent state; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.

2. The wafer warpage adjustment structure according to claim 1, characterized in that, The materials of the first dielectric layer and the first region of the second dielectric layer include silicon nitride or silicon carbide; The material of the second region of the first dielectric layer and the second dielectric layer includes quartz.

3. The wafer warpage adjustment structure according to claim 1, characterized in that, The coefficient of thermal expansion of the materials in the first region of the first dielectric layer and the second dielectric layer is greater than the coefficient of thermal expansion of the materials in other regions of the first dielectric layer and the second dielectric layer. The coefficient of thermal expansion of the materials in the second region of the first dielectric layer and the second dielectric layer is less than that of the materials in other regions of the first dielectric layer and the second dielectric layer.

4. The wafer warpage adjustment structure according to claim 1, characterized in that, The thickness of the first region of the first dielectric layer and the second dielectric layer is greater than or equal to the thickness of the other regions of the first dielectric layer and the second dielectric layer.

5. The wafer warpage adjustment structure according to claim 4, characterized in that, The thickness of the first region of the first dielectric layer and the second dielectric layer is 1 to 4 times the thickness of the other regions of the first dielectric layer and the second dielectric layer.

6. The wafer warpage adjustment structure according to claim 1, characterized in that, The dielectric layer of the first region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner.

7. The wafer warpage adjustment structure according to claim 1, characterized in that, The dielectric layer of the second region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner.

8. The wafer warpage adjustment structure according to claim 1, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.

9. The wafer warpage adjustment structure according to claim 1, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.

10. A method for preparing a wafer warp adjustment structure, characterized in that, include: A wafer is provided, the wafer including an upper surface and a lower surface disposed opposite to each other, the upper surface being used to form a semiconductor device; The wafer includes warped regions; A first dielectric layer is formed on the upper surface of the wafer; A second dielectric layer is formed on the lower surface of the wafer; Both the first dielectric layer and the second dielectric layer include a first region and / or a second region, and also include other regions besides the first region and / or the second region; wherein, The first region covers the portion of the wafer warped region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, and the second region covers the portion of the wafer warped region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.

11. The method according to claim 10, characterized in that, The materials of the first dielectric layer and the first region of the second dielectric layer include silicon nitride or silicon carbide; The material of the second region of the first dielectric layer and the second dielectric layer includes quartz.

12. The method according to claim 10, characterized in that, The coefficient of thermal expansion of the materials in the first region of the first dielectric layer and the second dielectric layer is greater than the coefficient of thermal expansion of the materials in other regions of the first dielectric layer and the second dielectric layer. The coefficient of thermal expansion of the materials in the second region of the first dielectric layer and the second dielectric layer is less than that of the materials in other regions of the first dielectric layer and the second dielectric layer.

13. The method according to claim 10, characterized in that, The process includes forming a first dielectric layer on the upper surface of the wafer and forming a second dielectric layer on the lower surface of the wafer; comprising: A first dielectric prelayer is formed on the upper surface of the wafer; A second dielectric pre-layer is formed on the lower surface of the wafer; Etching portions of the first dielectric prelayer and the second dielectric prelayer in the first region to form a first trench; filling the first trench with a first material, wherein the coefficient of thermal expansion of the first material is greater than the coefficient of thermal expansion of the wafer material; and / or, The first dielectric prelayer and the second dielectric prelayer are etched in portions of the second region to form a second trench; the second trench is filled with a second material, the coefficient of thermal expansion of the second material being less than that of the material of the wafer.

14. The method according to claim 10, characterized in that, The thickness of the first region of the first dielectric layer and the second dielectric layer is greater than or equal to the thickness of the other regions of the first dielectric layer and the second dielectric layer.

15. The method according to claim 14, characterized in that, The thickness of the first region of the first dielectric layer and the second dielectric layer is 1 to 4 times the thickness of the other regions of the first dielectric layer and the second dielectric layer.

16. The method according to claim 10, characterized in that, The dielectric layer of the first region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner.

17. The method according to claim 10, characterized in that, The dielectric layer of the second region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner.

18. The method according to claim 10, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.

19. The method according to claim 10, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.

20. The method according to claim 10, characterized in that, The warped region of the wafer is saddle-shaped or wavy.

Images