A probe test bench, preparation method and CP test device

Abstract

The present invention belongs to the technical field of CP testing, and discloses a probe test bench, a preparation method and a CP testing device. The probe test bench reshapes the return path of chip electrical signals through GND PADs and PADs that are connected to each other in a one-to-one correspondence. Specifically, the electrical signals of the chip pass through the PADs arranged on the MLO and then flow back to the GND PADs on the LGP components, which can avoid the problem that the chip electrical signals need to pass through the MLO and the PCB in the prior art, thereby effectively shortening the return path of the chip electrical signals, thereby helping to reduce interference such as signal loss and crosstalk, being beneficial to signal transmission, making the test effect obvious, reducing chip test failures and defective product generation, and more truly reflecting the performance of the chip itself.

Description

Technical Field

[0001] The present invention relates to the technical field of CP testing, and in particular to a probe testing platform, a preparation method and a CP testing device. Background Art

[0002] With the development of semiconductors and the increasing requirements for chip functions, the complexity and cost of chip design and production have also increased in the post-Moore era. Due to the high integration, the power consumption density is getting higher and higher, and power supply and heat dissipation are also facing huge challenges. The chiplet / known good die packaging (chiplet / known good die multi-module packaging) is used. This type of chip is mostly integrated with large pin counts, high-frequency signals, RF (radio frequency), etc., with relatively high requirements, requiring more test items, and high testing requirements.

[0003] At the same time, the design and wiring arrangement of such chips are very complex, and the types and numbers of signals are relatively large and complex, so they often fail to meet the chip design requirements in CP testing (wafer testing). Due to various reasons, the chip design leads to insufficient or uneven distribution of VSS PAD (ground pins), which makes the signal return path longer during the test, or causes digital and analog signal loss or even crosstalk, which causes errors in the test results. The current in the circuit has a return path, and digital circuits usually use ground and power planes to complete the return. The return paths of high-frequency signals and low-frequency signals are different. The return path of low-frequency signals is an impedance path, and the return path of high-frequency signals is an inductive path. When it comes to high-frequency switching and other situations, the components on the PCB (printed circuit board) produce impedance, inductive and magnetic field noise when they are powered on, which can easily cause signal crosstalk to other paths, causing test failures. Pure resistance circuits will also have interference, so choosing the shortest return path and avoiding PCB for return in advance is the correct solution.

[0004] In conventional CP testing, chip signals are usually transmitted through probe card + MLO (probe card + multi-layer organic carrier), and then transferred to ATE tester (automatic integrated circuit test) through PCB (load board) (test load board) to complete signal transmission. PCB is also the place where signals change and crosstalk are the greatest. In this process, conventional structures cannot improve the signal loss or crosstalk caused by the circuit return path. Currently, in addition to pre-designing in chip design and PCB design to avoid excessively long return paths, of course, these designs will only shorten the return path to a certain extent, but at the same time, there are phenomena such as signal loss and noise caused by components on the PCB. At the same time, it is difficult to solve this problem by improving the probe card structure.

[0005] Therefore, the above problems need to be solved urgently. Summary of the invention

[0006] The object of the present invention is to provide a probe test station, a preparation method and a CP test device to solve the problem of signal loss or crosstalk caused by a circuit return path in the prior art.

[0007] To achieve this object, the present invention adopts the following technical solutions:

[0008] A probe test bench is used to connect a chip to be tested with an ATE test machine to complete a performance test of the chip to be tested. The probe test bench includes a PCB, and the probe test bench also includes:

[0009] MLO, the MLO is arranged on the PCB, and a PAD is arranged on the MLO;

[0010] An LGP component, wherein a GND PAD is disposed on the LGP component, and the GND PAD is connected to the PAD in a one-to-one correspondence;

[0011] A first MEMS probe, wherein one end of the first MEMS probe is connected to the MLO, and the other end of the first MEMS probe is configured to be connected to the chip to be tested.

[0012] Preferably, the PAD is arranged on a side of the MLO close to the LGP component, and the GND PAD is arranged on a side of the LGP component close to the MLO.

[0013] Preferably, the GND PAD is connected to the PAD in a one-to-one correspondence via a second MEMS probe.

[0014] A CP testing device comprises an ATE testing machine, and the CP testing device further comprises a probe testing station as claimed in any one of claims 1 to 3.

[0015] A method for preparing a probe test station based on the above-mentioned probe test station, the method for preparing the probe test station comprising the following steps:

[0016] Providing an LGP component, on which the GND PAD is processed;

[0017] Providing an MLO, on which a PAD matching the GND PAD is processed;

[0018] The LGP component and the MLO are assembled on the main body of the probe test station, and the GND PAD is connected to the PAD in a one-to-one correspondence.

[0019] Preferably, the step of providing an LGP component comprises:

[0020] The GND PAD is processed on the LGP component by photolithography technology.

[0021] Preferably, the step of providing an LGP component is specifically:

[0022] S1. Plate a layer of gold on the surface of the LGP component;

[0023] S2, coating a layer of photoresist on the surface of the gold layer;

[0024] S3, forming a desired pattern on a mask, and then transferring the pattern on the mask to the photoresist through a photolithography process;

[0025] S4, exposing the photoresist so that a preset area thereof is dissolved;

[0026] S5, using a developer to remove the dissolved region of the photoresist to form a preset pattern of the GND PAD;

[0027] S6. Etching the gold layer and removing the photoresist to form the GND PAD.

[0028] Preferably, step S1 includes plating a gold layer on the surface of the LGP component by using electroplating technology.

[0029] Preferably, the step of providing an MLO comprises:

[0030] The PAD matched with the GND PAD is processed on the MLO by photolithography technology.

[0031] Preferably, the GND PAD is connected to the PAD in one-to-one correspondence through a second MEMS probe; after the step of assembling the LGP component and the MLO to the main body of the probe test bench and making the GND PAD connected to the PAD in one-to-one correspondence, the method further comprises:

[0032] The GND PAD is connected to the PAD in a one-to-one correspondence through the second MEMS probe.

[0033] Beneficial effects of the present invention:

[0034] The present invention reshapes the return path of the chip electrical signal by connecting the GND PAD and PAD in one-to-one correspondence with each other. Specifically, the chip electrical signal passes through the PAD set on the MLO and then flows back to the GND PAD on the LGP component, which can avoid the problem that the chip electrical signal needs to pass through the MLO and the PCB in the prior art, thereby effectively shortening the return path of the chip electrical signal, thereby helping to reduce interference such as signal loss and crosstalk, which is beneficial to signal transmission, making the test effect obvious, reducing chip test failures and the generation of defective products, and more truly reflecting the performance of the chip itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of the probe test bench provided by the present invention;

[0036] Figure 2 yes Figure 1 The enlarged view of point A in the middle;

[0037] Figure 3 It is a flow chart of the method for preparing the probe test bench provided by the present invention;

[0038] Figure 4 It is a flow chart of the method for preparing the LGP component provided by the present invention.

[0039] In the figure:

[0040] 100. chip to be tested; 200. ATE test machine; 1. PCB; 2. MLO; 21. PAD; 3. LGP component; 31. GND PAD; 4. first MEMS probe; 5. second MEMS probe. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0044] In the description of this embodiment, the terms "upper", "lower", "left", "right", etc., and the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of description and simplified operation, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.

[0045] Based on the content mentioned above, in conventional CP testing, chip signals are usually transmitted through probe card + MLO (probe + multi-layer organic on carrier board), and then transferred to ATE tester (automatic integrated circuit tester) through PCB (load board) (test load board) to complete signal transmission. PCB is also the place where signals change and crosstalk are the largest. In this process, conventional structures cannot improve the signal loss or crosstalk caused by the circuit return path. At present, in addition to pre-designing in chip design and PCB design to avoid excessively long return paths, of course, these designs will only shorten the return path to a certain extent, but at the same time, there are phenomena such as signal loss and noise caused by components on the PCB. At the same time, it is difficult to solve this problem by improving the probe card structure.

[0046] See also Figures 1 to 4 In order to solve the problem of signal loss or crosstalk caused by the circuit return path in the above-mentioned prior art, the present embodiment provides a probe test bench, a preparation method and a CP test device. The probe test bench is used to connect the chip to be tested 100 and the ATE test machine 200 to complete the performance test of the chip to be tested 100. The probe test bench includes PCB1, MLO2, LGP component 3 and a first MEMS probe 4. MLO2 is arranged on PCB1, and PAD21 is arranged on MLO2. GND PAD31 is arranged on LGP component 3, and GND PAD31 is connected with PAD21 in a one-to-one correspondence. One end of the first MEMS probe 4 is connected to MLO2, and the other end is configured to be connected to the chip to be tested 100.

[0047] It can be understood that the return path of the chip electrical signal is reshaped by the one-to-one corresponding GND PAD31 and PAD21. Specifically, the chip electrical signal passes through PAD21 set on MLO2 and then flows back to GND PAD31 on the LGP component 3, which can avoid the problem that the chip electrical signal needs to pass through MLO2 and PCB1 in the prior art, thereby effectively shortening the return path of the chip electrical signal, thereby helping to reduce interference such as signal loss and crosstalk, which is beneficial to signal transmission, making the test effect obvious, reducing chip test failures and the generation of defective products, and more truly reflecting the performance of the chip itself.

[0048] It should be noted that the specific parameters of the above-mentioned PCB1, MLO2, LGP component 3, first MEMS probe 4 and other components are selected according to the actual application scenario, and this embodiment does not make specific requirements and restrictions on this. In addition, the probe test bench also includes other components for ensuring its normal operation, such as UGP components, etc., which will not be described in detail.

[0049] Further, PAD21 is arranged on the side of MLO2 close to LGP component 3, and GND PAD31 is arranged on the side of LGP component 3 close to MLO2. It can be understood that, by respectively arranging GND PAD31 and PAD21 on the side where LGP component 3 and MLO2 are close to each other, on the one hand, the distance between GND PAD31 and PAD21 can be effectively shortened, which helps to further shorten the return path of the chip electrical signal; on the other hand, GND PAD31 and PAD21 are arranged relative to each other, which is more convenient for assembling the probe test bench.

[0050] Preferably, GND PAD31 and PAD21 are connected one-to-one through the second MEMS probe 5. It is understandable that the MEMS probe is a prior art and has excellent conductivity, reliable operation, and low cost, which helps to improve the service life and production cost of the probe test bench.

[0051] The preparation method of the probe test station based on the above may include the following steps:

[0052] Provide an LGP component 3, and process a GND PAD 31 on the LGP component 3;

[0053] An MLO2 is provided, and a PAD21 adapted to the GND PAD31 is processed on the MLO2;

[0054] The LGP component 3 and the MLO 2 are assembled on the main body of the probe test station, and the GND PAD 31 and the PAD 21 are connected one by one.

[0055] Therefore, the preparation method of the probe test bench provided in this embodiment processes GNDPAD31 on the LGP component 3 and processes PAD21 compatible with GND PAD31 on MLO2, and then assembles LGP component 3 and MLO2 to the main body of the probe test bench, thereby reshaping the return path of the chip electrical signal through the one-to-one connected GND PAD31 and PAD21, and can avoid the problem that the chip electrical signal needs to pass through MLO2 and PCB1 in the prior art, thereby effectively shortening the return path of the chip electrical signal, and further helps to reduce interference such as signal loss and crosstalk, which is beneficial to signal transmission, making the test effect obvious, reducing chip test failures and the generation of defective products, and more truly reflecting the performance of the chip itself.

[0056] It should be noted that there is no order distinction in the preparation of the LGP component 3 and the MLO 2 in this embodiment, and the preparation of the LGP component 3 and the MLO 2 can also be carried out simultaneously to shorten the production cycle of the probe test station.

[0057] Preferably, after the steps of assembling the LGP component 3 and the MLO 2 onto the main body of the probe test station and making the GND PAD 31 and the PAD 21 connected one by one, the following steps are included:

[0058] The GND PAD31 and the PAD21 are connected in a one-to-one correspondence through the second MEMS probe 5 .

[0059] It is understandable that the MEMS probe is an existing technology and has excellent conductivity, reliable operation, and low cost of use, which helps to improve the service life and production cost of the probe test bench.

[0060] Preferably, the step of providing an LGP component 3 comprises:

[0061] The GND PAD 31 is processed on the LGP component 3 by photolithography technology, which helps to improve the precision of the GND PAD 31.

[0062] Similarly, the steps of providing an MLO2 include:

[0063] PAD21 that matches GND PAD31 is processed on MLO2 through photolithography technology, which helps to improve the precision of PAD21.

[0064] Specifically, the steps of providing an LGP component 3 are as follows:

[0065] S1, plating a layer of gold on the surface of LGP component 3;

[0066] S2, coating a layer of photoresist on the surface of the gold layer;

[0067] S3, forming a desired pattern on the mask, and then transferring the pattern on the mask to the photoresist through a photolithography process;

[0068] S4, exposing the photoresist so that a predetermined area thereof is dissolved;

[0069] S5, using a developer to remove the dissolved area of ​​the photoresist to form a preset GND PAD31 pattern;

[0070] S6. Etch the gold layer and remove the photoresist to form GND PAD31.

[0071] Further, step S1 includes using electroplating technology to plate a gold layer on the surface of the LGP component 3. It is understandable that the use of electroplating technology can ensure the flatness of the gold layer and has high efficiency. It should be noted that any electroplating method such as magnetron sputtering, electroplating, chemical electroplating, etc. can be used, and this embodiment does not make specific requirements and restrictions on this.

[0072] This embodiment also provides a CP test device, which includes an ATE test machine 200 and the above-mentioned probe test bench. It can be understood that the CP test device including the probe test bench also helps to reduce interference such as signal loss and crosstalk, is beneficial to signal transmission, makes the test effect obvious, reduces chip test failures and defective products, and can more truly reflect the performance of the chip itself. It should be noted that the ATE test machine 200 is in the prior art and will not be described in detail.

[0073] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, various obvious changes, readjustments and substitutions can be made without departing from the protection scope of the present invention. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A probe test bench, used to connect a chip to be tested (100) with an ATE test machine (200) to complete a performance test of the chip to be tested (100), the probe test bench comprising a PCB (1), characterized in that: The probe test station also includes: An MLO (2), wherein the MLO (2) is disposed on the PCB (1), and a PAD (21) is disposed on the MLO (2); An LGP component (3), wherein a GND PAD (31) is provided on the LGP component (3), and the GND PAD (31) is connected to the PAD (21) in a one-to-one correspondence; A first MEMS probe (4), one end of which is connected to the MLO (2) and the other end of which is configured to be connected to the chip to be tested (100).

2. The probe test station according to claim 1 is characterized in that: The PAD (21) is disposed on a side of the MLO (2) close to the LGP component (3), and the GND PAD (31) is disposed on a side of the LGP component (3) close to the MLO (2).

3. The probe test station according to claim 2 is characterized in that: The GND PAD (31) is connected to the PAD (21) in a one-to-one correspondence via a second MEMS probe (5).

4. A CP testing device, comprising an ATE testing machine (200), characterized in that: The CP testing device further comprises a probe testing station as described in any one of claims 1-3.

5. A method for preparing a probe test station based on the probe test station according to any one of claims 1 to 3, characterized in that: The probe test bench preparation method comprises the following steps: Providing an LGP component (3), wherein the GND PAD (31) is processed on the LGP component (3); Providing an MLO (2), wherein a PAD (21) adapted to the GND PAD (31) is processed on the MLO (2); The LGP component (3) and the MLO (2) are assembled onto the main body of the probe test bench, and the GNDPAD (31) and the PAD (21) are connected in a one-to-one correspondence.

6. The method for preparing a probe test station according to claim 5, characterized in that: The step of providing an LGP component (3) comprises: The GND PAD (31) is processed on the LGP component (3) by photolithography technology.

7. The method for preparing a probe test station according to claim 5, characterized in that: The step of providing an LGP component (3) is specifically: S1, plating a layer of gold on the surface of the LGP component (3); S2, coating a layer of photoresist on the surface of the gold layer; S3, forming a desired pattern on a mask, and then transferring the pattern on the mask to the photoresist through a photolithography process; S4, exposing the photoresist so that a preset area thereof is dissolved; S5, using a developer to remove the dissolved region of the photoresist to form a preset pattern of the GND PAD (31); S6, etching the gold layer and removing the photoresist to form the GND PAD (31).

8. The method for preparing a probe test station according to claim 7, characterized in that: Step S1 includes plating a gold layer on the surface of the LGP component (3) using electroplating technology.

9. The method for preparing a probe test station according to claim 5, characterized in that: The step of providing an MLO (2) comprises: The PAD (21) adapted to the GND PAD (31) is processed on the MLO (2) by photolithography technology.

10. The method for preparing a probe test station according to claim 5, characterized in that: The GND PAD (31) is connected to the PAD (21) in a one-to-one correspondence via a second MEMS probe (5); After the step of assembling the LGP component (3) and the MLO (2) onto the main body of the probe test station and connecting the GND PAD (31) and the PAD (21) in a one-to-one correspondence, the method further comprises: The GND PAD (31) is connected to the PAD (21) in a one-to-one correspondence via the second MEMS probe (5).

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