Method, device, quantum chip and electronic device for generating quantum state preparation circuit

Abstract

The present application relates to a method and apparatus for generating a quantum state preparation circuit, a quantum chip, and an electronic device. The quantum chip can be applied to various intelligent terminals and vehicle-mounted devices. The method includes: determining a first unitary operator corresponding to n qubits; obtaining at least two second unitary operators for performing phase shift on the n qubits; determining a third unitary operator for permuting the qubits of the control register and the qubits of the target register into r c qubits and r t qubits; generating a diagonal unitary matrix quantum circuit based on the first unitary operator, the second unitary operator, the third unitary operator, a fourth unitary operator for restoring r t qubits, and a diagonal unitary matrix operator corresponding to r c qubits; combining each diagonal unitary matrix quantum circuit with single-bit gates to obtain at least two uniform control gates; and combining the at least two uniform control gates into a quantum state preparation circuit. Using this method can effectively reduce the circuit depth.

Description

Technical Field

[0001] The present application relates to the field of quantum technology, and in particular to a method, device, electronic device, storage medium and computer program product for generating a quantum state preparation circuit. Background Art

[0002] In the field of quantum technology, it is usually necessary to load classical data into quantum states, a process called quantum state preparation. The quantum state preparation process is an important process in the field of quantum technology and often occupies most of the running time of quantum algorithms. Therefore, optimizing quantum state preparation helps improve the running efficiency of quantum algorithms.

[0003] The circuit depth of the current quantum state preparation circuit is 0(2 n ), n is the number of quantum bits, and theoretically the depth of the quantum state preparation circuit is bounded by Ω(2 n / n), that is, the existing quantum state preparation circuit is not the most optimal circuit in the asymptotic sense, and there is still much room for improvement. Summary of the invention

[0004] Based on this, it is necessary to provide a method, device, electronic device, computer-readable storage medium and computer program product for generating a quantum state preparation circuit that can effectively reduce the circuit depth in order to address the above-mentioned technical problems.

[0005] In a first aspect, the present application provides a method for generating a quantum state preparation circuit. The method comprises:

[0006] Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0007] Obtaining at least two second unitary operators for phase shifting the n quantum bits;

[0008] Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r t The third unitary operator of qubits;

[0009] Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0010] Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0011] The at least two uniform control gates are combined into a quantum state preparation circuit.

[0012] In a second aspect, the present application also provides a device for generating a quantum state preparation circuit. The device comprises:

[0013] The first determination module is used to determine the first unitary operator corresponding to the n quantum bits; the first unitary operator is used to convert r of the n quantum bits v qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0014] A first acquisition module, used to acquire at least two second unitary operators for phase shifting the n quantum bits;

[0015] The second determining module is used to determine the quantum bits of the control register and the quantum bits of the target register to be replaced by the r c qubits and the r t The third unitary operator of qubits;

[0016] A generating module for restoring the r based on the first unitary operator, the second unitary operator, the third unitary operator, t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0017] A first combining module, used for combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0018] The second combining module is used to combine the at least two uniform control gates into a quantum state preparation circuit.

[0019] In a third aspect, a quantum chip includes a quantum state preparation circuit, wherein the quantum state preparation circuit is implemented by a method for generating a quantum state preparation circuit, and the method for generating a quantum state preparation circuit includes:

[0020] Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0021] Obtaining at least two second unitary operators for phase shifting the n quantum bits;

[0022] Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r t The third unitary operator of qubits;

[0023] Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0024] Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0025] The at least two uniform control gates are combined into a quantum state preparation circuit.

[0026] In a fourth aspect, the present application further provides an electronic device. The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0027] Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0028] Obtaining at least two second unitary operators for phase shifting the n quantum bits;

[0029] Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r i The third unitary operator of qubits;

[0030] Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0031] Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0032] The at least two uniform control gates are combined into a quantum state preparation circuit.

[0033] In a fifth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0034] Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0035] Obtaining at least two second unitary operators for phase shifting the n quantum bits;

[0036] Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r t The third unitary operator of qubits;

[0037] Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0038] Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0039] The at least two uniform control gates are combined into a quantum state preparation circuit.

[0040] In a sixth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0041] Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits v qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0042] Obtaining at least two second unitary operators for phase shifting the n quantum bits;

[0043] Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r tThe third unitary operator of qubits;

[0044] Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0045] Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates;

[0046] The at least two uniform control gates are combined into a quantum state preparation circuit.

[0047] The method, device, electronic device, storage medium and computer program product for generating the quantum state preparation circuit determine the first unitary operator corresponding to the n quantum bits; the first unitary operator is used to convert r of the n quantum bits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. c qubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The diagonal unitary matrix operators corresponding to the qubits are used to generate diagonal unitary matrix quantum circuits, thereby effectively reducing the circuit depth of the diagonal unitary matrix quantum circuits. Then, each diagonal unitary matrix quantum circuit is combined with a single-bit gate to obtain at least two uniform control gates; at least two uniform control gates are combined into a quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit, and further effectively reducing the time of quantum state preparation, thereby improving the operating efficiency of quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A diagram of an application environment of a method for generating a quantum state preparation circuit in one embodiment;

[0049] Figure 2 is a schematic diagram of n-path limitation of a quantum circuit in one embodiment;

[0050] Figure 3 A schematic diagram of a circuit framework for preparing a quantum state of n quantum bits in one embodiment;

[0051] Figure 4Schematic diagram of the structure of a uniform control gate of n quantum bits in one embodiment;

[0052] Figure 5 A schematic diagram of decomposing a diagonal unitary matrix to obtain a first unitary operator, a second unitary operator, a third unitary operator, a fourth unitary operator and a diagonal unitary matrix operator in one embodiment;

[0053] Figure 6 A quantum circuit framework of a diagonal unitary matrix under path restriction in one embodiment;

[0054] Figure 7 A schematic diagram of a flow chart of a method for generating a quantum state preparation circuit in one embodiment;

[0055] Figure 8 The CNOT gate CNOT under path restriction in one embodiment j i Schematic diagram of the implementation;

[0056] Fig. 9 A schematic diagram of a process for preparing a quantum state in one embodiment;

[0057] Fig.10 is a structural block diagram of a generating device of a quantum state preparation circuit in one embodiment;

[0058] Fig.11 A structural block diagram of a generating device of a quantum state preparation circuit in another embodiment;

[0059] Fig.12 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] The method for generating a quantum state preparation circuit provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the electronic device 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The electronic device 102 can be used to generate a quantum state preparation circuit 1042, and the quantum chip 104 can be finally made according to the quantum state preparation circuit 1042.

[0062] The electronic device 102 may be an industrial intelligent device for making a quantum state preparation circuit 1042, such as a photolithography device, a robot arm, and other equipment required for industrial production. After the quantum chip 104 is made using the quantum state preparation circuit 1042, the quantum chip 104 may be integrated into various intelligent terminals, including: smart phones, tablet computers, laptop computers, desktop computers, smart speakers, smart watches, IoT devices, and portable wearable devices. The IoT devices may be smart speakers, smart TVs, smart air conditioners, and smart car-mounted devices. Portable wearable devices may be smart watches, smart bracelets, head-mounted devices, and the like.

[0063] Before further describing the embodiments of the present invention in detail, the nouns, terms, symbols, parameters and basic quantum gates involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are applicable to the following explanations:

[0064] (1) Quantum Computation: A computing method that uses the superposition and entanglement properties of quantum states to quickly complete computing tasks.

[0065] (2) Quantum bit (Qubit): The form of quantum information.

[0066] (3) Quantum Circuit: A quantum computing model consisting of a series of quantum gate sequences, and the calculation is completed by quantum gates.

[0067] (4) Quantum chip (superconducting quantum chip): The central processing unit of a quantum computer. This quantum computer is a machine that uses the superposition principle of quantum mechanics and quantum entanglement to perform calculations. It has strong parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate.

[0068] (5) i-Gray code cycle: {0,1} n The sequence of all n-bit strings in (referred to as n-bit string sequence) satisfies that two adjacent bit strings have exactly one bit difference and the first and last bit strings have exactly one bit difference. For any i∈[n], let represents a sequence of n-bit strings, and for any i∈[n], For any j∈{2,3,…,2 n}, h ij express and Different bit subscripts, let h i1 express and Different bit subscripts, then:

[0069]

[0070] The bit string sequence constructed above is called It is an (i,n)-Gray code circle, which is referred to as i-Gray code circle in this application. It should be noted that in the subsequent embodiments, unless otherwise specified, the Gray code circle may also refer to i-Gray code circle.

[0071] (6) n-path restriction (abbreviated as path restriction): If in an n-quantum circuit, a two-bit gate (CNOT) is only allowed to act on two adjacent qubits, then the n-quantum circuit is said to be under n-path restriction. Figure 2 As shown in (a), Figure 2 (a) represents the n-path restriction of an n-qubit circuit, with vertex R 1 ,R 2 ,…,R n Represent n qubits respectively. If two qubits are connected by an edge, the two-bit gate can act on these two qubits.

[0072] (7) d-dimensional grid restriction (i.e., multidimensional grid restriction): In an n-quantum circuit arranged in a d-dimensional grid, a two-bit gate is only allowed to act on two adjacent qubits. This quantum circuit arranged in a d-dimensional grid is said to be under the d-dimensional grid restriction. Figure 2 As shown in (b), in a quantum circuit arranged in a 2D grid, the points on the 2D grid represent quantum bits, with a total of m1×m2=n quantum bits. If two quantum bits are connected by an edge, the two-bit gate can act on these two quantum bits. Figure 2 As shown in (c), in a quantum circuit arranged in a 3D grid, the points on the 3D grid represent quantum bits, with a total of m1×m2×m3=n quantum bits. If two quantum bits are connected by an edge, the two-bit gate can act on these two quantum bits.

[0073] (8) Basic symbols involved in this application: [n] represents the set {1, 2, …, n}. represents a binary field (a finite field). 1 ,…,x n ) T ,y=(y 1 ,…,y n ) T ∈{0,1} n , And the inner product Both addition and multiplication are defined on binary fields. n and 1 nRepresents a vector of length n with all 0s and all 1s respectively. i represents a vector whose i-th element is 1 and the other elements are 0. For any set of positive integers S, |ψ> s It means that the quantum state |ψ> consists of quantum bits in the set S.

[0074] (9) The basic quantum gates involved in this application are shown in Table 1:

[0075] Table 1

[0076]

[0077]

[0078] (10) The basic quantum gate parameters involved in this application are as follows:

[0079]

[0080] r t =(n-τ) / 2

[0081] r c =(n+τ) / 2

[0082]

[0083] in, Indicates rounding up.

[0084] (11) The problem of preparing quantum states under path restriction is defined as follows: Given any quantum state satisfying ‖v‖ 2 =1 complex vector Given an initial state Prepare n-bit quantum state:

[0085]

[0086] where {|k>:k=0,1,…,2 n -1} is a set of computational bases for quantum systems. In the design of quantum state preparation circuits, only arbitrary single-bit quantum gates and two-bit gates are allowed, and two-bit gates are only allowed to act on two adjacent bits.

[0087] In order to have a clearer and more intuitive understanding of the present application, the design process of the quantum state preparation circuit under n-path restriction is first described here in conjunction with an embodiment. Figure 6 The specific contents are as follows:

[0088] S602, decomposing the quantum state preparation circuit into uniform control gates according to the target quantum state.

[0089] Among them, the number of uniform control gates decomposed is n, which are V 1 ,V 2 ,…,V n ,like Figure 3 shown.

[0090] S604, further decompose each uniform control gate to obtain a diagonal unitary matrix and a single-bit gate.

[0091] Among them, after each uniform control gate is decomposed, three diagonal unitary matrices and four single-qubit gates can be obtained, such as Figure 4 shown.

[0092] Through the two steps S3602 and S604, the quantum state preparation circuit is decomposed into a series of diagonal unitary matrices Λ j (j∈[n]) and a single-bit gate (i.e., a single-qubit gate). Therefore, by realizing any diagonal unitary matrix quantum circuit under path restriction, we can directly obtain the quantum state preparation circuit under path restriction.

[0093] S606, construct a diagonal unitary matrix quantum circuit under path restriction.

[0094] By utilizing combinatorial techniques and recursive methods, a quantum circuit of a diagonal unitary matrix is ​​realized under path constraints, and the quantum circuit is an optimal depth circuit in an asymptotic sense.

[0095] From Table 1, we can see that the diagonal unitary matrix Λ n The role of is to implement the following transformation on each vector |x> in the calculation basis:

[0096]

[0097] There is {α s :s∈{0,1} n -{0 n}}satisfy:

[0098]

[0099] In constructing a diagonal unitary matrix quantum circuit under path restriction, the real number set {α s :s∈{0,1} n -{0 n}}.

[0100] Therefore, the implementation of S606 is divided into five sub-steps, as follows:

[0101] S6062, Constructing n-qubit unitary operators

[0102] S6064, Constructing n-qubit unitary operators

[0103] S6066, Constructing n-qubit unitary operators

[0104] S6068, construction Unitary operators of qubits

[0105] S6070, construction Diagonal unitary operators of qubits

[0106] Then, using the unitary operator And we get the diagonal unitary matrix Λ n ,like Figure 5 As shown, a diagonal unitary matrix quantum circuit is constructed, the diagonal unitary matrix quantum circuit and the single-bit gate are combined into a uniform control gate, and finally the uniform control gate is used to combine into a quantum state preparation circuit.

[0107] In one embodiment, Figure 7 As shown, a method for generating a quantum state preparation circuit is provided, and the method is applied to an electronic device as an example for explanation, and includes the following steps:

[0108] S702, determine the first unitary operator corresponding to n quantum bits.

[0109] Among them, the first unitary operator For r of n qubits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2. Through the first unitary operator You can use the previous r c The qubits are replaced into the control register, and the latter r t The quantum bits are replaced into the target register, that is:

[0110]

[0111] Since the first unitary operator is a reversible linear transformation on the computational basis. Therefore, the circuit implementation of the reversible linear transformation under path restriction or multidimensional grid restriction can obtain the first unitary operator Therefore, under the path restriction or multidimensional grid restriction, the first unitary operator can be represented by a circuit with a depth of O(n 2 ) is implemented by a two-bit gate; wherein the path restriction means that the two-bit gate acts on two adjacent quantum bits among the n quantum bits.

[0112] For a two-bit gate The control bit of the two-bit gate is on the i-th qubit of the control register, and the target bit is on the j-th qubit of the target register. Under the path restriction, the two-bit gate can be implemented by a two-bit circuit with a circuit depth and size of O(|ij|), such as Figure 8 shown.

[0113] S704, obtaining at least two second unitary operators for phase shifting the n quantum bits.

[0114] Among them, the second unitary operator is a unitary operator used to phase-shift n qubits.

[0115] In one embodiment, the electronic device may first construct at least two second unitary operators for phase shifting n quantum bits, and then store them; when it is necessary to generate a quantum state preparation circuit, the at least two second unitary operators are obtained.

[0116] Before constructing the second unitary operator, we will explain the contents related to the second unitary operator. First, we define A set that satisfies the following two properties The specific properties are as follows:

[0117] (1) For each gather In finite fields Linearly independent.

[0118] (2) Collection Ability to overwrite collections Right now

[0119] For each r defined on the target register T t The quantum state of a bit:

[0120] in

[0121] That is y (0) and x target same, is with Related linear functions. The following defines disjoint sets

[0122]

[0123] For any gather satisfy and

[0124]

[0125] The second unitary operator is given below Definition: For any

[0126]

[0127] From the above formula, we can get the second unitary operator It has two functions: one is to introduce the phase, and the other is to transition from k-1 step to k step.

[0128] In one embodiment, after determining the second unitary operator, the electronic device may also construct a unitary matrix quantum circuit under path constraints according to the second unitary operator, so as to construct a diagonal unitary matrix quantum circuit using the unitary matrix quantum circuit and unitary matrix quantum circuits corresponding to other unitary operators.

[0129] The construction of the unitary matrix quantum circuit corresponding to the second unitary operator can include two stages: the generation stage and the Gray code cycle stage. The generation stage mainly realizes the circuit construction of the generated unitary operator, which is used to generate the unitary operator in r t The computational basis is converted into a reversible linear transformation on a finite field on qubits; the Gray code loop stage mainly realizes the circuit construction of the Gray code loop operator, which is used to pass r c The Gray code circle corresponding to the n quantum bits phase-shifts the quantum state of the n quantum bits.

[0130] (1) Generation phase

[0131] Implementing the unitary operator in the generation phase satisfy:

[0132]

[0133] Among them, y (k-1) and (k) Respectively, the set T (k-1) and T (k) OK, for

[0134] Can be written as:

[0135]

[0136] because In finite fields is linearly independent, so In finite fields The above is reversible, and the generated unitary operator is defined as:

[0137]

[0138] The matrix-vector multiplication on the right side of the above equation is defined in a finite field Combining equation (9) we can get:

[0139]

[0140] From the above, we can see that by generating the unitary operator The computational basis can be transformed into a finite field Therefore, under the path restriction, the unitary operator is generated The depth is O(n 2 ) is implemented by a two-bit gate circuit. The path restriction means that the two-bit gate acts on two adjacent qubits among the n qubits.

[0141] (2) Gray code circle stage

[0142] In the Gray code cycle stage, the Gray code cycle operator U can be realized GrayCycle ,satisfy:

[0143]

[0144] in, And F k Defined in equation (4). For any i∈[r t ],make Indicates the number of bits is r c i-Gray code circle, and for any i∈[r t ], For any express and Different bit subscripts, let h i1 express and Different bit subscripts. c i-Gray code circle of bits, h ij is defined as follows:

[0145]

[0146] By h ij From the definition of h 1j = k occurs at most Second-rate.

[0147] It should be noted that the Gray code stage contains phases, including:

[0148] 1) Phase 1, The first stage of the phases is implemented by the first rotation gate circuit, which acts on the i-th qubit of the target register. For example, for any i∈[r t ], if the bit string Circuit C 1 Rotation Acts on the i-th bit of the destination register.

[0149] 2) In the stage It consists of two steps:

[0150] In step p.1, The pth stage of the pth stage is implemented by the first two-bit gate circuit. The control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is at the i-th qubit of the target register. For example, for each i∈[r t ], the control bit of the two-bit gate in the first two-bit gate circuit is in the hth position of the control register ip qubits, and the target bit is the i-th bit of the target register T. That is, for each i∈[r t ], if h ip ≤r t , then the dual-bit gate If h ip >r t , then the dual-bit gate

[0151] In step p.2, The pth stage of the pth stage is implemented by the second rotation gate circuit, which acts on the i-th qubit of the target register. For example, for each i∈[r t ],if Revolving door Acts on the i-th quantum bit (labeled 2i) of the target register.

[0152] 3) Stage The first of the The first stage is implemented by the second two-bit gate circuit, and the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is at the i-th qubit of the target register. For example, for each i∈[r t ], the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register i1 qubits, and the target is the i-th qubit of the target register. That is, for each i∈[r t ], if h i1 ≤rt , then the dual-bit gate If h i1 >r t , then the dual-bit gate

[0153] Therefore, in the Gray code cycle stage, the Gray code cycle operator can be Circuit implementation.

[0154] Here, the correctness of the above circuit is proved. For each Defining a Collection

[0155]

[0156] According to equation (6), F k The definition of can be obtained, the set satisfy

[0157] in

[0158]

[0159] Next, verify the use of Implement Gray circle operator U GrayCycle , the Gray circle operator U GrayCycle Please refer to equation (12).

[0160]

[0161] The circuit depth of each stage in the Gray circle stage is analyzed below, where:

[0162] 1) Stage 1 consists of the first rotational gate circuit acting on different qubits in the target register, so it can be implemented in one layer of circuit, that is, the circuit depth is 1.

[0163] 2) In the stage The following different situations are discussed:

[0164] If in stage p h 1p =1, then step p.1 can be implemented by the following first two-bit gate circuit:

[0165]

[0166] Since the path restrictions of each two-bit gate in the first two-bit gate circuit do not intersect, the circuit depth of the first two-bit gate circuit is 1. Step p.2 can be composed of rotation gates acting on different quantum bits in the target register, so it can be implemented in one layer of rotation gate circuits, so the circuit depth of the first rotation gate circuit is 1.

[0167] If in stage p 2≤h 1p ≤τ, then step p.1 can be implemented by the following first two-bit gate circuit:

[0168]

[0169] The two-bit gate circuit The path constraints of each two-bit gate in are disjoint, that is, all two-bit gates in the two-bit gate circuit can be realized at the same time. The distance between the control bit and the target bit of each two-bit gate in is at most O(h 1p ). Since step p.1 consists of the circuit Therefore, the total circuit depth of step p.1 is Step p.2 can be composed of rotating gates acting on different qubits in the target register, so it can be implemented in one layer of rotating gate circuits. Indicates rounding down.

[0170] If in stage p h 1p >τ, since step p.1 can be implemented by the first two-bit gate circuit, according to the circuit implementation of reversible linear transformation under path restriction or multidimensional grid restriction, the depth of step p.1 can be compressed to O(n 2 ). Step p.2 can be composed of rotating gates acting on different bits in the target register, so it can be implemented in one layer of rotating gate circuits.

[0171] 3) Stage It is implemented by the second two-bit gate circuit. It can be seen from the circuit implementation of reversible linear transformation under path restriction or multi-dimensional grid restriction that the circuit depth of this stage can be compressed to O(n 2 ).

[0172] In one embodiment, the electronic device determines the circuit depth of the gate circuit implementing the Gray code circle operator according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit, and the second di-bit gate circuit.

[0173] For example, according to the properties of the Gray code circle, in the stage h 1p At most times, so all The total circuit depth of the stage is Therefore, under the path restriction, the Gray code cycle operator can be represented by a circuit with a depth of Gate circuit implementation.

[0174] It should be pointed out that the above circuit depth is the circuit depth under path constraints, but the circuit depth is also consistent under multi-dimensional grid constraints.

[0175] Therefore, by constructing and combining the circuits of the generation phase and the Gray loop phase, we can obtain the operator Circuit construction under path restriction, that is, under path restriction or multidimensional grid restriction, the second unitary operator The depth can be The quantum circuit can be realized by a single-bit gate (such as a rotating gate) and a two-bit gate.

[0176] S706, determining the quantum bits for replacing the control register and the target register with r c qubits and r t The third unitary operator of qubits.

[0177] Among them, the third The function is to replace the quantum bit of the control register to the first r c qubits, and replace the qubits of the target register with the qubits of the latter r t On quantum bits, that is:

[0178]

[0179] Therefore, under the path restriction or multidimensional grid restriction, the third unitary operator can be represented by a depth of O(n 2 ) is realized by quantum circuits.

[0180] S708, based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The diagonal unitary matrix operators corresponding to the quantum bits generate diagonal unitary matrix quantum circuits.

[0181] In one embodiment, the electronic device obtains a t The fourth unitary operator of the qubits acts on the last r of the input register. t qubits, it will be t The quantum state corresponding to the quantum bit is restored to the input state, that is:

[0182]

[0183] Since the fourth unitary operator is a reversible linear transformation on the computational basis, so the fourth unitary operator can be obtained by implementing the reversible linear transformation in a circuit under path restriction. A two-bit gate circuit.

[0184] After the first unitary operator, the second unitary operator, the third unitary operator and the fourth unitary operator are all realized by the circuit of the object, the diagonal unitary matrix of n quantum bits can be divided into two parts, including the diagonal unitary matrix of the designed circuit and the diagonal unitary matrix of the undesigned circuit. The design can be continued recursively as follows:

[0185] In one embodiment, the electronic device obtains a diagonal unitary matrix operator, which is r c The diagonal unitary matrix of qubits satisfies:

[0186]

[0187] The diagonal unitary matrix operator can be implemented recursively under path constraints or multi-dimensional grid constraints, that is, the diagonal unitary matrix operator is taken as a new diagonal unitary matrix, and the new diagonal unitary matrix is ​​further analyzed recursively to obtain a new first unitary operator, a second unitary operator, a third unitary operator, a fourth unitary operator and a diagonal unitary matrix operator, and then circuits are designed to implement the new first unitary operator, second unitary operator, third unitary operator and fourth unitary operator, and so on, until there is no matrix for which the circuit is not designed.

[0188] Specifically, the electronic device is based on a two-bit gate circuit that implements a first unitary operator, a quantum circuit that implements a second unitary operator, a quantum circuit that implements a third unitary operator, a two-bit gate circuit that implements a fourth unitary operator, and r c The diagonal unitary matrix operator corresponding to the qubits generates a diagonal unitary matrix quantum circuit. The diagonal unitary matrix operator is implemented recursively. Under path restriction or multidimensional grid restriction, the diagonal unitary matrix Λ n can be Figure 5 The realization of a quantum circuit with n-qubits and a circuit depth of O(2 n / n).

[0189] Proof: First, prove the correctness of the circuit framework. First, The first half and the second half of the previous input quantum state |x> can be replaced into the control register and the target register respectively:

[0190]

[0191] Then apply a series of unitary operators The following transformations can be achieved:

[0192]

[0193] Subsequent effects Restore the first and second halves of the input quantum state to their initial positions:

[0194]

[0195] Second action operator The last r t The quantum bits are restored to their initial state:

[0196]

[0197] Finally, recursively implement the diagonal unitary matrix

[0198]

[0199] The above discussion shows that Figure 5 The circuit framework can realize Λ under path constraints n quantum circuits.

[0200] In one embodiment, the electronic device determines the circuit depth of the quantum state preparation circuit according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit corresponding to the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator; wherein the circuit depth is O(2 n / n).

[0201] The following proves that the circuit depth is D(n) = O(2 n / n), there exists a real number α>0, the operator The circuit depth is at most There exists a real number β>0 such that the circuit depth of operator R is at most βn 2 . Therefore, D(n) satisfies the following recursive formula:

[0202]

[0203] According to the above recursive formula, we can get D(n)=O(2 n / n).

[0204] S710, combining each diagonal unitary matrix quantum circuit with a single-bit gate to obtain at least two uniformly controlled gates.

[0205] S712, combining at least two uniform control gates into a quantum state preparation circuit.

[0206] In one embodiment, the electronic device can also detect the circuit depth of the quantum state preparation circuit, and the specific steps include: the electronic device obtains a diagonal unitary matrix; and detects the circuit depth of the quantum state preparation circuit through the diagonal unitary matrix. When it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, a target data vector is obtained; and the quantum state is prepared for the target data vector based on the quantum state preparation circuit.

[0207] For example, when preparing quantum states, the algorithm that needs to be prepared for quantum states is first determined, such as linear equations solution, recommendation system, support vector machine, clustering algorithm and Hamiltonian simulation algorithm. The parameters of the algorithm can be vectorized first, and then the obtained data vector is used as the target data vector to encode the quantum state. For example, the data vector Encoded as quantum states This step is the quantum state preparation, such as Fig. 9 As shown, we can obtain quantum algorithms such as solving quantum linear equations, quantum recommendation systems, quantum support vector machines, quantum clustering algorithms, and Hamiltonian simulation.

[0208] In the above embodiment, the first unitary operator corresponding to the n qubits is determined; the first unitary operator is used to convert r of the n qubits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. c qubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The diagonal unitary matrix operators corresponding to the qubits are used to generate diagonal unitary matrix quantum circuits, thereby effectively reducing the circuit depth of the diagonal unitary matrix quantum circuits. Then, each diagonal unitary matrix quantum circuit is combined with a single-bit gate to obtain at least two uniform control gates; at least two uniform control gates are combined into a quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit, and further effectively reducing the time of quantum state preparation, thereby improving the operating efficiency of quantum computing.

[0209] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0210] Based on the same inventive concept, the embodiment of the present application also provides a device for generating a quantum state preparation circuit for implementing the method for generating a quantum state preparation circuit involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the device for generating one or more quantum state preparation circuits provided below can refer to the limitations of the method for generating a quantum state preparation circuit above, and will not be repeated here.

[0211] In one embodiment, Fig.10 As shown, a device for generating a quantum state preparation circuit is provided, comprising: a first determination module 1002, a first acquisition module 1004, a second determination module 1006, a generation module 1008, a first combination module 1010 and a second combination module 1012, wherein:

[0212] The first determination module 1002 is used to determine the first unitary operator corresponding to the n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2;

[0213] A first acquisition module 1004, configured to acquire at least two second unitary operators for phase shifting the n quantum bits;

[0214] The second determining module 1006 is used to determine the quantum bits of the control register and the quantum bits of the target register to be replaced by r c qubits and r t The third unitary operator of qubits;

[0215] Generating module 1008, for restoring r based on the first unitary operator, the second unitary operator, the third unitary operator, t The fourth unitary operator of qubits and r cThe diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit;

[0216] A first combining module 1010 is used to combine each diagonal unitary matrix quantum circuit with a single-bit gate to obtain at least two uniformly controlled gates;

[0217] The second combining module 1012 is used to combine at least two uniform control gates into a quantum state preparation circuit.

[0218] In one embodiment, under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0219] In one embodiment, the second unitary operator includes a Gray code circle operator and a generating unitary operator; the Gray code circle operator is used to generate a unitary operator by r c The Gray code circle corresponding to the n qubits performs a phase shift on the quantum state of the n qubits; a unitary operator is generated for t On qubits, the computational basis is converted into a reversible linear transformation over a finite field.

[0220] In one embodiment, under path restriction or multi-dimensional grid restriction, the unitary operator is generated by a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; under path restriction or multi-dimensional grid restriction, the Gray code cycle operator is implemented by a circuit depth of The gate circuit is implemented; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0221] In one embodiment, the Gray code cycle operator includes stage; The first stage of the stages is implemented by the first rotation gate circuit, which acts on the i-th quantum bit of the target register; The pth stage of the pth stage is implemented by the first two-bit gate circuit. The control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is the i-th qubit of the target register; or, The pth stage of the stages is implemented by the second rotation gate circuit, and the second rotation gate circuit acts on the i-th quantum bit of the target register; The first of the The first stage is implemented by the second two-bit gate circuit, and the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is at the i-th qubit of the target register; where i∈[r t ,n],h ip and h i1 The subscripts of the bits that differ between adjacent bit strings in an n-bit string sequence, or the subscripts of the bits that differ between the first bit string and the last bit string in an n-bit string sequence.

[0222] In one embodiment, the circuit depth of the first rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the second rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the first two-bit gate circuit under path restriction or multi-dimensional grid restriction is O(n 2 ); The circuit depth of the second two-bit gate circuit under path restriction or multi-dimensional grid restriction is

[0223] In one embodiment, Fig.11 As shown, the device also includes:

[0224] The third determination module 1014 is used to determine the circuit depth of the gate circuit implementing the Gray code circle operator according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit and the second di-bit gate circuit respectively.

[0225] In one embodiment, under path restriction or multi-dimensional grid restriction, the third unitary operator is composed of a circuit with a depth of O(n 2 ) quantum circuit, the fourth unitary operator is implemented by a circuit with depth O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0226] In one embodiment, Fig.11 As shown, the device also includes:

[0227] The fourth determination module 1016 is used to determine the circuit depth of the quantum state preparation circuit according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit corresponding to the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator; wherein the circuit depth is O(2 n / n).

[0228] In one embodiment, Fig.11 As shown, the device also includes:

[0229] A second acquisition module 1018 is used to acquire a diagonal unitary matrix;

[0230] A detection module 1020, configured to detect the circuit depth of the quantum state preparation circuit by using a diagonal unitary matrix;

[0231] The second acquisition module 1018 is further configured to acquire a target data vector when it is determined based on the detection result that the quantum state preparation circuit can realize a diagonal unitary matrix;

[0232] The preparation module 1022 is used to prepare the quantum state of the target data vector based on the quantum state preparation circuit.

[0233] In the above embodiment, the first unitary operator corresponding to the n qubits is determined; the first unitary operator is used to convert r of the n qubits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. c qubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The diagonal unitary matrix operators corresponding to the qubits are used to generate diagonal unitary matrix quantum circuits, thereby effectively reducing the circuit depth of the diagonal unitary matrix quantum circuits. Then, each diagonal unitary matrix quantum circuit is combined with a single-bit gate to obtain at least two uniform control gates; at least two uniform control gates are combined into a quantum state preparation circuit, thereby effectively reducing the circuit depth of the quantum state preparation circuit, and further effectively reducing the time of quantum state preparation, thereby improving the operating efficiency of quantum computing.

[0234] Each module in the generation device of the above-mentioned quantum state preparation circuit can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in an electronic device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0235] In one embodiment, an electronic device is provided. The electronic device may be an industrial intelligent device, and its internal structure diagram may be as follows: Fig.12 As shown. The electronic device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store target data vectors. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for generating a quantum state preparation circuit is implemented.

[0236] Those skilled in the art will understand that Fig.12 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0237] In one embodiment, a quantum chip is provided, comprising a quantum state preparation circuit, wherein the quantum state preparation circuit is implemented by the method for generating a quantum state preparation circuit in the present application.

[0238] In one embodiment, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented: determining a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. cqubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The method comprises the following steps: generating a diagonal unitary matrix operator corresponding to each quantum bit to generate a diagonal unitary matrix quantum circuit; combining each diagonal unitary matrix quantum circuit with a single-bit gate to obtain at least two uniform control gates; and combining at least two uniform control gates into a quantum state preparation circuit.

[0239] In one embodiment, under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0240] In one embodiment, the second unitary operator includes a Gray code circle operator and a generating unitary operator; the Gray code circle operator is used to generate a unitary operator by r c The Gray code circle corresponding to the n qubits performs a phase shift on the quantum state of the n qubits; a unitary operator is generated for t On qubits, the computational basis is converted into a reversible linear transformation over a finite field.

[0241] In one embodiment, under path restriction or multi-dimensional grid restriction, the unitary operator is generated by a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; under path restriction or multi-dimensional grid restriction, the Gray code cycle operator is implemented by a circuit depth of The gate circuit is implemented; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0242] In one embodiment, the Gray code cycle operator includes stage; The first stage of the stages is implemented by the first rotation gate circuit, which acts on the i-th quantum bit of the target register; The pth stage of the pth stage is implemented by the first two-bit gate circuit. The control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is the i-th qubit of the target register; or, The pth stage of the stages is implemented by the second rotation gate circuit, and the second rotation gate circuit acts on the i-th quantum bit of the target register; The first of the The first stage is implemented by the second two-bit gate circuit, and the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is at the i-th qubit of the target register; where i∈[r t ,n],h ip and h i1 The subscripts of the bits that differ between adjacent bit strings in an n-bit string sequence, or the subscripts of the bits that differ between the first bit string and the last bit string in an n-bit string sequence.

[0243] In one embodiment, the circuit depth of the first rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the second rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the first two-bit gate circuit under path restriction or multi-dimensional grid restriction is O(n 2 ); The circuit depth of the second two-bit gate circuit under path restriction or multi-dimensional grid restriction is

[0244] In one embodiment, when the processor executes the computer program, the following steps are further implemented: according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit and the second di-bit gate circuit respectively, the circuit depth of the gate circuit implementing the Gray code circle operator is determined.

[0245] In one embodiment, under path restriction or multidimensional grid restriction, the third unitary operator is composed of a circuit with a depth of O(n 2 ) quantum circuit, the fourth unitary operator is implemented by a circuit with depth O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0246] In one embodiment, when the processor executes the computer program, the following steps are further implemented: according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit corresponding to the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator, the circuit depth of the quantum circuit for the preparation of the quantum state is determined; wherein the circuit depth is O(2 n / n).

[0247] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining a diagonal unitary matrix; detecting the circuit depth of the quantum state preparation circuit through the diagonal unitary matrix; when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining the target data vector; and preparing the quantum state of the target data vector based on the quantum state preparation circuit.

[0248] In one embodiment, a computer-readable storage medium is provided on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: determining a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. c qubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The method comprises the following steps: generating a diagonal unitary matrix operator corresponding to each quantum bit to generate a diagonal unitary matrix quantum circuit; combining each diagonal unitary matrix quantum circuit with a single-bit gate to obtain at least two uniform control gates; and combining at least two uniform control gates into a quantum state preparation circuit.

[0249] In one embodiment, under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0250] In one embodiment, the second unitary operator includes a Gray code circle operator and a generating unitary operator; the Gray code circle operator is used to generate a unitary operator by r c The Gray code circle corresponding to the n qubits performs a phase shift on the quantum state of the n qubits; a unitary operator is generated for t On qubits, the computational basis is converted into a reversible linear transformation over a finite field.

[0251] In one embodiment, under path restriction or multi-dimensional grid restriction, the unitary operator is generated by a circuit with a depth of O(n 2) is realized by a two-bit gate circuit; under path restriction or multi-dimensional grid restriction, the Gray code cycle operator is implemented by a circuit depth of The gate circuit is implemented; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0252] In one embodiment, the Gray code cycle operator includes stage; The first stage of the stages is implemented by the first rotation gate circuit, which acts on the i-th quantum bit of the target register; The pth stage of the pth stage is implemented by the first two-bit gate circuit. The control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is the i-th qubit of the target register; or, The pth stage of the stages is implemented by the second rotation gate circuit, and the second rotation gate circuit acts on the i-th quantum bit of the target register; The first of the The first stage is implemented by the second two-bit gate circuit, and the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is at the i-th qubit of the target register; where i∈[r t ,n],h ip and h i1 The subscripts of the bits that differ between adjacent bit strings in an n-bit string sequence, or the subscripts of the bits that differ between the first bit string and the last bit string in an n-bit string sequence.

[0253] In one embodiment, the circuit depth of the first rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the second rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the first two-bit gate circuit under path restriction or multi-dimensional grid restriction is O(n 2 ); The circuit depth of the second two-bit gate circuit under path restriction or multi-dimensional grid restriction is

[0254] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit and the second di-bit gate circuit respectively, the circuit depth of the gate circuit implementing the Gray code circle operator is determined.

[0255] In one embodiment, under path restriction or multidimensional grid restriction, the third unitary operator is composed of a circuit with a depth of O(n 2 ) quantum circuit, the fourth unitary operator is implemented by a circuit with depth O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0256] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit of the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator, the circuit depth of the quantum circuit of the third unitary operator is determined; wherein the circuit depth is O(2 n / n).

[0257] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: obtaining a diagonal unitary matrix; detecting the circuit depth of the quantum state preparation circuit through the diagonal unitary matrix; when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector; and preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0258] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the following steps: determining a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits into c qubits and r t The quantum bits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; at least two second unitary operators are obtained for phase shifting the n quantum bits; and the quantum bits of the control register and the target register are replaced by r. c qubits and r t The third unitary operator of qubits; based on the first unitary operator, the second unitary operator, and the third unitary operator, used to restore r t The fourth unitary operator of qubits and r c The method comprises the following steps: generating a diagonal unitary matrix operator corresponding to each quantum bit to generate a diagonal unitary matrix quantum circuit; combining each diagonal unitary matrix quantum circuit with a single-bit gate to obtain at least two uniform control gates; and combining at least two uniform control gates into a quantum state preparation circuit.

[0259] In one embodiment, under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0260] In one embodiment, the second unitary operator includes a Gray code circle operator and a generating unitary operator; the Gray code circle operator is used to generate a unitary operator by r c The Gray code circle corresponding to the n qubits performs a phase shift on the quantum state of the n qubits; a unitary operator is generated for t On qubits, the computational basis is converted into a reversible linear transformation over a finite field.

[0261] In one embodiment, under path restriction or multi-dimensional grid restriction, the unitary operator is generated by a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; under path restriction or multi-dimensional grid restriction, the Gray code cycle operator is implemented by a circuit depth of The gate circuit is implemented; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0262] In one embodiment, the Gray code cycle operator includes stage; The first stage of the stages is implemented by the first rotation gate circuit, which acts on the i-th quantum bit of the target register; The pth stage of the pth stage is implemented by the first two-bit gate circuit. The control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is the i-th qubit of the target register; or, The pth stage of the stages is implemented by the second rotation gate circuit, and the second rotation gate circuit acts on the i-th quantum bit of the target register; The first of the The first stage is implemented by the second two-bit gate circuit, and the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is at the i-th qubit of the target register; where i∈[r t ,n],h ip and hi1 The subscripts of the bits that differ between adjacent bit strings in an n-bit string sequence, or the subscripts of the bits that differ between the first bit string and the last bit string in an n-bit string sequence.

[0263] In one embodiment, the circuit depth of the first rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the second rotational gate circuit under path restriction or multi-dimensional grid restriction is 1; the circuit depth of the first two-bit gate circuit under path restriction or multi-dimensional grid restriction is O(n 2 ); The circuit depth of the second two-bit gate circuit under path restriction or multi-dimensional grid restriction is

[0264] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit and the second di-bit gate circuit respectively, the circuit depth of the gate circuit implementing the Gray code circle operator is determined.

[0265] In one embodiment, under path restriction or multidimensional grid restriction, the third unitary operator is composed of a circuit with a depth of O(n 2 ) quantum circuit, the fourth unitary operator is implemented by a circuit with depth O(n 2 ) is realized by a two-bit gate circuit; wherein the path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a linear manner; the multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among n quantum bits arranged in a multi-dimensional grid.

[0266] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit of the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator, the circuit depth of the quantum circuit of the third unitary operator is determined; wherein the circuit depth is O(2 n / n).

[0267] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: obtaining a diagonal unitary matrix; detecting the circuit depth of the quantum state preparation circuit through the diagonal unitary matrix; when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector; and preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0268] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0269] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0270] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0271] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for generating a quantum state preparation circuit, It is characterized in that The method comprises: Determine a first unitary operator corresponding to n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; Obtaining at least two second unitary operators for phase shifting the n quantum bits; Determine the method for replacing the quantum bits of the control register and the quantum bits of the target register with the r c qubits and the r t The third unitary operator of qubits; Based on the first unitary operator, the second unitary operator, the third unitary operator, and the t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit; Combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates; The at least two uniform control gates are combined into a quantum state preparation circuit.

2. The method according to claim 1, It is characterized in that Under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; The path restriction indicates that the two-bit gate circuit acts on two adjacent qubits, and the two adjacent qubits are qubits in the n qubits arranged in a linear manner; The multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multi-dimensional grid.

3. The method according to claim 1, It is characterized in that The second unitary operator includes a Gray code circle operator and a generating unitary operator; The Gray code circle operator is used to pass the r c Gray code circles corresponding to n quantum bits perform phase shifts on the quantum states of the n quantum bits; The generating unitary operator is used to generate the unitary operator in the r t On qubits, the computational basis is converted into a reversible linear transformation over a finite field.

4. The method according to claim 3, It is characterized in that Under path restriction or multidimensional grid restriction, the generating unitary operator is composed of a circuit with depth O(n 2 ) is realized by a two-bit gate circuit; Under path restriction or multidimensional grid restriction, the Gray code cycle operator consists of a circuit depth of Gate circuit implementation; The path restriction indicates that the two-bit gate circuit acts on two adjacent qubits, and the two adjacent qubits are qubits in the n qubits arranged in a linear manner; The multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multi-dimensional grid.

5. The method according to claim 3, It is characterized in that The Gray code circle operator includes stage; Said The first stage of the stages is implemented by a first rotation gate circuit, and the first rotation gate circuit acts on the i-th quantum bit of the target register; Said The pth stage of the pth stage is implemented by a first two-bit gate circuit, the control bit of the two-bit gate in the first two-bit gate circuit is in the hth stage of the control register. ip qubits, and the target is the i-th qubit of the target register; or The pth stage of the stages is implemented by a second rotation gate circuit, and the second rotation gate circuit acts on the i-th quantum bit of the target register; Said The first of the stages The first stage is implemented by a second two-bit gate circuit, in which the control bit of the two-bit gate in the second two-bit gate circuit is in the hth position of the control register. i1 qubits, and the target is the i-th qubit of the target register; Among them, i∈[r t ,n],h ip and h i1 The subscripts representing the different bits between adjacent bit strings in an n-bit string sequence, or the subscripts representing the different bits between the first bit string and the last bit string in the n-bit string sequence.

6. The method according to claim 5, It is characterized in that The circuit depth of the first revolving gate circuit under path restriction or multi-dimensional grid restriction is 1; The circuit depth of the second revolving gate circuit under path restriction or multi-dimensional grid restriction is 1; The circuit depth of the first two-bit gate circuit under path restriction or multi-dimensional grid restriction is O(n 2 ); The circuit depth of the second two-bit gate circuit under path restriction or multi-dimensional grid restriction is:

7. The method according to claim 6, It is characterized in that The method further comprises: The circuit depth of the gate circuit implementing the Gray code circle operator is determined according to the circuit depths corresponding to the first rotational gate circuit, the second rotational gate circuit, the first di-bit gate circuit, and the second di-bit gate circuit respectively.

8. The method according to claim 1, It is characterized in that Under path restriction or multidimensional grid restriction, the third unitary operator is composed of a circuit with a depth of O(n 2 ), the fourth unitary operator is implemented by a quantum circuit with a circuit depth of O(n 2 ) is realized by a two-bit gate circuit; The path restriction indicates that the two-bit gate circuit acts on two adjacent qubits, and the two adjacent qubits are qubits in the n qubits arranged in a linear manner; The multi-dimensional grid restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multi-dimensional grid.

9. The method according to any one of claims 1 to 8, It is characterized in that The method further comprises: The circuit depth of the quantum state preparation circuit is determined according to the circuit depth of the two-bit gate circuit corresponding to the first unitary operator, the circuit depth of the quantum circuit corresponding to the second unitary operator, the circuit depth of the quantum circuit corresponding to the third unitary operator, and the circuit depth of the two-bit gate circuit corresponding to the fourth unitary operator; wherein the circuit depth is O(2 n / n).

10. The method according to claim 9, It is characterized in that The method further comprises: Get the diagonal unitary matrix; Detecting the circuit depth of the quantum state preparation circuit by using the diagonal unitary matrix; When it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector; The quantum state of the target data vector is prepared based on the quantum state preparation circuit.

11. A device for generating a quantum state preparation circuit, It is characterized in that The device comprises: The first determination module is used to determine the first unitary operator corresponding to the n quantum bits; the first unitary operator is used to convert r of the n quantum bits c qubits and r t qubits are encoded into the control register and the target register respectively; n is an integer greater than or equal to 2; A first acquisition module, used to acquire at least two second unitary operators for phase shifting the n quantum bits; The second determining module is used to determine the quantum bits of the control register and the quantum bits of the target register to be replaced by the r c qubits and the r t The third unitary operator of qubits; A generating module for restoring the r based on the first unitary operator, the second unitary operator, the third unitary operator, t The fourth unitary operator of the qubits and the r c The diagonal unitary matrix operator corresponding to the quantum bits generates a diagonal unitary matrix quantum circuit; A first combining module, used for combining each of the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniformly controlled gates; The second combining module is used to combine the at least two uniform control gates into a quantum state preparation circuit.

12. The device according to claim 11, It is characterized in that Under path restriction or multidimensional grid restriction, the first unitary operator is composed of a circuit with a depth of O(n 2 ) is realized by a two-bit gate circuit; The path restriction indicates that the two-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits among the n quantum bits arranged in a linear manner.

13. A quantum chip, comprising a quantum state preparation circuit, It is characterized in that The quantum state preparation circuit is implemented by the method for generating the quantum state preparation circuit according to any one of claims 1 to 10.

14. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, It is characterized in that When the processor executes the computer program, the steps of the method for generating a quantum state preparation circuit according to any one of claims 1 to 10 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the steps of the method for generating a quantum state preparation circuit according to any one of claims 1 to 10 are implemented.

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