Design method for realizing S-box circuit for quantum optimization

By analyzing and dividing the classic implementation structure of S-box, combining quantum logic gate set design quantum optimization implementation, the Toffoli depth and T depth of quantum circuits are optimized, and the problem of resource occupation and speed limitation in large-scale S-boxes in quantum computing is solved, and efficient quantum implementation is achieved.

CN120281467APending Publication Date: 2025-07-08NAT UNIV OF DEFENSE TECH
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Patent Information

Application Number
CN202510701441.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-05-28
Publication Date
2025-07-08

AI Technical Summary

Technical Problem

There is a lack of efficient methods in the prior art to optimize the design of large-scale S-box quantum implementation circuits, especially in quantum computing environments, resulting in limited computing resource occupation and speed.

Method used

By analyzing the classic implementation structure of the S box, dividing nonlinear and linear modules, combining quantum logic gate set design quantum optimization implementation, optimizing the Toffoli depth and T depth of the quantum circuit, using matrix multiplication to represent linear operations and combining the state reset of quantum auxiliary bits to optimize the quantum implementation circuit.

Benefits of technology

It effectively reduces the cost of quantum implementation circuits, improves the quantum implementation efficiency of S-box, saves the consumption of quantum bits and T-gate, and optimizes the circuit depth.

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Abstract

The invention discloses a quantum optimization-oriented design method for realizing an S box circuit, which comprises the following steps of: S1, analyzing linear operation and nonlinear operation in classical implementation of an S box, and dividing a classical implementation structure of the S box; s2, designing quantum implementation of different modules in the classical implementation structure of the S box step by step; and S3, analyzing the combinability of a linear module implementation circuit in the quantum implementation of the S box to optimize the quantum implementation of the S box. The quantum implementation efficiency of the S box in the cryptographic algorithm is effectively improved, and the implementation cost of a related quantum circuit is reduced.
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