Quantum computer operation method, equipment, system and device based on batch processing

Abstract

The embodiment of the invention provides a quantum computer operation method, equipment, system and device based on batch processing, and relates to the technical field of quantum.The method comprises the steps that a plurality of target quantum circuits to be operated currently are obtained; compiling the plurality of target quantum circuits in a first parallel mode to obtain quantum calculation instructions corresponding to the plurality of target quantum circuits, and taking the quantum calculation instructions as target quantum calculation instructions; and the obtained multiple target quantum calculation instructions are sent to a quantum chip, correspondingly, the quantum chip can execute the multiple target quantum calculation instructions, and operation results of the multiple target quantum circuits are obtained. Thus, in the process of using a large number of quantum circuits for calculation, the multiple quantum circuits can be compiled at the same time in a parallel mode, the time consumed for compiling the quantum circuits is shortened, and then the overall calculation efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of quantum technology, and in particular to a method, device, system and apparatus for operating a quantum computer based on batch processing. Background Art

[0002] Quantum circuits are composed of qubits and a series of quantum logic gates. With the rapid development of quantum technology, different quantum circuits can be designed to perform calculations in different application scenarios to solve problems in the corresponding scenarios.

[0003] In related technologies, solving complex problems often requires the use of a large number of quantum circuits. Furthermore, in some hybrid quantum-classical computing scenarios, multiple quantum circuit iterations are required, and each iteration also requires the use of a large number of quantum circuits. Therefore, improving the overall computational efficiency of quantum computing systems using a large number of quantum circuits is a core issue that urgently needs to be addressed. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a method, device, system, and apparatus for operating a quantum computer based on batch processing to improve the overall computational efficiency when performing calculations using a large number of quantum circuits. The specific technical solutions are as follows:

[0005] In a first aspect of the present application, a method for operating a quantum computer based on batch processing is provided, the method comprising:

[0006] Obtain multiple target quantum circuits currently to be run;

[0007] Compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions;

[0008] The obtained multiple target quantum computing instructions are sent to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

[0009] Optionally, before obtaining the multiple target quantum circuits to be run, the method further includes:

[0010] Receive quantum circuits uploaded by the client and cache them;

[0011] The step of obtaining multiple target quantum circuits to be run includes:

[0012] Based on the current working state of the quantum chip, a plurality of target quantum circuits to be currently run are obtained from the currently cached quantum circuits; wherein the working state is idle or non-idle.

[0013] Optionally, the acquiring, based on the current working state of the quantum chip, a plurality of target quantum circuits to be run from currently cached quantum circuits includes:

[0014] If the current working state of the quantum chip is idle, obtaining a first number of quantum circuits from the currently cached quantum circuits as target quantum circuits to be currently run;

[0015] If the current working state of the quantum chip is non-idle, a second number of quantum circuits is obtained from the currently cached quantum circuits as the target quantum circuits to be currently run; wherein the second number is greater than the first number.

[0016] Optionally, the method is applied to a batch processing device, the first number is the product of a specified number and a first coefficient, and the first coefficient is less than 1; the second number is the product of the specified number and a second coefficient, and the second coefficient is greater than 1; the specified number is determined based on the performance of the quantum chip and the maximum number of parallel processing tasks supported by the batch processing device.

[0017] Optionally, the cache space of the quantum chip is used to store quantum computing instructions to be executed; the current working state of the quantum chip is idle, indicating that there are no quantum computing instructions to be executed in the cache space.

[0018] The first coefficient is positively correlated with the number of quantum computing instructions currently being executed by the quantum chip; the second coefficient is positively correlated with the number of quantum computing instructions currently in the cache space.

[0019] Optionally, the receiving and caching of the quantum circuit uploaded by the client includes:

[0020] Receive quantum circuits uploaded by the client;

[0021] Parameter verification is performed on the received quantum circuits in a second parallel manner, and each quantum circuit is cached after passing the verification.

[0022] Optionally, before compiling the multiple target quantum circuits in the first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions, the method further includes:

[0023] performing resource estimation on the plurality of target quantum circuits in a third parallel manner to obtain quantum resources allocated to each target quantum circuit;

[0024] Compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions includes:

[0025] In a first parallel manner, the multiple target quantum circuits are compiled according to the quantum resources allocated to each of the multiple target quantum circuits to obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions.

[0026] Optionally, after sending the obtained multiple target quantum computing instructions to the quantum chip, the method further includes:

[0027] receiving the operation results of the multiple target quantum circuits sent by the quantum chip;

[0028] Send the received operation results to the client.

[0029] Optionally, sending the received operation result to the client includes:

[0030] performing post-processing on the operation results of the plurality of target quantum circuits in a fourth parallel manner;

[0031] Send the post-processing results to the client.

[0032] Optionally, the multiple target quantum circuits are spliced by the client into a quantum computing task for transmission, and the quantum computing task is spliced according to a start instruction, circuit parameters of the multiple target quantum circuits, and an end instruction. The circuit parameters of each target quantum circuit include circuit structure parameters and circuit compilation parameters.

[0033] Optionally, obtaining multiple target quantum circuits to be run currently includes:

[0034] Analyzing the quantum computing task to obtain circuit structure parameters and circuit compilation parameters of each target quantum circuit;

[0035] Restore the circuit structure parameters of each target quantum circuit to obtain multiple target quantum circuits to be operated;

[0036] Compiling the plurality of target quantum circuits in a first parallel manner includes:

[0037] Each target quantum circuit is compiled using a first parallel mode and a circuit compilation parameter of each target quantum circuit.

[0038] Optionally, the multiple target quantum circuits are transmitted by the client separately in the form of a circuit structure parameter set and a circuit compilation parameter set, the number of circuit structure parameters in the circuit structure parameter set is greater than the number of circuit compilation parameters in the circuit compilation parameter set, and each circuit compilation parameter corresponds to at least one circuit structure parameter.

[0039] Optionally, obtaining multiple target quantum circuits to be run currently includes:

[0040] parsing the circuit structure parameter set, determining the circuit structure parameters corresponding to each target quantum circuit from the circuit structure parameter set, and performing restoration based on the circuit structure parameters corresponding to each target quantum circuit to obtain a plurality of target quantum circuits to be currently operated;

[0041] Compiling the plurality of target quantum circuits in a first parallel manner includes:

[0042] parsing the line compilation parameter set to obtain a plurality of line compilation parameters;

[0043] At least one target quantum circuit corresponding to each circuit compilation parameter is compiled in a first parallel manner.

[0044] Optionally, the circuit structure parameters are used to characterize the quantum circuit structure, and the circuit compilation parameters are used to compile the quantum circuit; the circuit structure parameters include at least one of the following: logic gate type, logic gate parameters, number of bits, and logic gate execution timing; the circuit compilation parameters include at least one of the following: bit mapping relationship, optimization requirements, and number of circuit executions.

[0045] Optionally, the adopted parallel method is a single-node multi-thread parallel processing method, or a multi-node parallel processing method.

[0046] A second aspect of the present application provides a batch-processing-based quantum computer operating device, comprising:

[0047] Memory for storing computer programs;

[0048] The processor is configured to implement any of the methods described in the first aspect above when executing a program stored in the memory.

[0049] A third aspect of the present application provides a quantum computer, comprising the device and quantum chip described in the second aspect above; wherein:

[0050] The quantum chip is used to execute the quantum computing instructions received from the device to obtain the operation results of the quantum circuit.

[0051] Optionally, the cache space of the quantum chip is used to store quantum computing instructions received from the device;

[0052] The quantum chip is specifically configured to obtain and execute quantum computing instructions from the cache space when the quantum chip has surplus computing resources.

[0053] Optionally, the quantum chip is also used to send the operation results of the quantum circuit to the device.

[0054] A fourth aspect of the present application provides a batch-processing-based quantum computer operating system, comprising a quantum computer as described in any one of the third aspects above, and a client; wherein:

[0055] The client is used to send multiple quantum circuits to the quantum computer in a single submission or batch submission manner according to the user's instructions.

[0056] In a fifth aspect of the present application, a batch-processing-based quantum computer operation device is provided, the device comprising:

[0057] An acquisition module is used to acquire multiple target quantum circuits currently to be run;

[0058] a compiling module, configured to compile the plurality of target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the plurality of target quantum circuits as target quantum computing instructions;

[0059] The sending module is used to send the obtained multiple target quantum computing instructions to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

[0060] Optionally, the device further includes:

[0061] a cache module, which receives and caches the quantum circuits uploaded by the client before obtaining the multiple target quantum circuits to be run;

[0062] The acquisition module is specifically configured to acquire a plurality of target quantum circuits to be run from the currently cached quantum circuits based on the current working state of the quantum chip; wherein the working state is idle or non-idle.

[0063] Optionally, the acquisition module is specifically configured to, if the current working state of the quantum chip is idle, acquire a first number of quantum circuits from the currently cached quantum circuits as target quantum circuits to be currently run;

[0064] If the current working state of the quantum chip is non-idle, a second number of quantum circuits is obtained from the currently cached quantum circuits as the target quantum circuits to be currently run; wherein the second number is greater than the first number.

[0065] Optionally, the method is applied to a batch processing device, the first number is the product of a specified number and a first coefficient, and the first coefficient is less than 1; the second number is the product of the specified number and a second coefficient, and the second coefficient is greater than 1; the specified number is determined based on the performance of the quantum chip and the maximum number of parallel processing tasks supported by the batch processing device.

[0066] Optionally, the cache space of the quantum chip is used to store quantum computing instructions to be executed; the current working state of the quantum chip is idle, indicating that there are no quantum computing instructions to be executed in the cache space.

[0067] The first coefficient is positively correlated with the number of quantum computing instructions currently being executed by the quantum chip; the second coefficient is positively correlated with the number of quantum computing instructions currently in the cache space.

[0068] Optionally, the cache module is specifically configured to receive a quantum circuit uploaded by a client;

[0069] Parameter verification is performed on the received quantum circuits in a second parallel manner, and each quantum circuit is cached after passing the verification.

[0070] Optionally, the device further includes:

[0071] a resource estimation module configured to, before compiling the multiple target quantum circuits in the first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits and using them as target quantum computing instructions, perform resource estimation on the multiple target quantum circuits in a third parallel manner to obtain quantum resources allocated to each target quantum circuit;

[0072] The compiling module is specifically configured to compile the multiple target quantum circuits in a first parallel manner according to the quantum resources allocated to each of the multiple target quantum circuits, and obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions.

[0073] Optionally, the device further includes:

[0074] A receiving module, configured to receive, after sending the obtained multiple target quantum computing instructions to the quantum chip, the operation results of the multiple target quantum circuits sent by the quantum chip;

[0075] The forwarding module is used to send the received running results to the client.

[0076] Optionally, the forwarding module is specifically configured to post-process the operation results of the multiple target quantum circuits in a fourth parallel manner;

[0077] Send the post-processing results to the client.

[0078] Optionally, the multiple target quantum circuits are spliced by the client into a quantum computing task for transmission, and the quantum computing task is spliced according to a start instruction, circuit parameters of the multiple target quantum circuits, and an end instruction. The circuit parameters of each target quantum circuit include circuit structure parameters and circuit compilation parameters.

[0079] Optionally, the acquisition module is specifically used to parse the quantum computing task to obtain circuit structure parameters and circuit compilation parameters of each target quantum circuit;

[0080] Restore the circuit structure parameters of each target quantum circuit to obtain multiple target quantum circuits to be operated;

[0081] The compiling module is specifically configured to compile each target quantum circuit in a first parallel manner using the circuit compilation parameters of each target quantum circuit.

[0082] Optionally, the multiple target quantum circuits are transmitted by the client separately in the form of a circuit structure parameter set and a circuit compilation parameter set, the number of circuit structure parameters in the circuit structure parameter set is greater than the number of circuit compilation parameters in the circuit compilation parameter set, and each circuit compilation parameter corresponds to at least one circuit structure parameter.

[0083] Optionally, the acquisition module is specifically configured to parse the circuit structure parameter set, determine the circuit structure parameters corresponding to each target quantum circuit from the circuit structure parameter set, and perform restoration based on the circuit structure parameters corresponding to each target quantum circuit to obtain multiple target quantum circuits to be currently operated;

[0084] The compilation module is specifically configured to parse the line compilation parameter set to obtain a plurality of line compilation parameters;

[0085] At least one target quantum circuit corresponding to each circuit compilation parameter is compiled in a first parallel manner.

[0086] Optionally, the circuit structure parameters are used to characterize the quantum circuit structure, and the circuit compilation parameters are used to compile the quantum circuit; the circuit structure parameters include at least one of the following: logic gate type, logic gate parameters, number of bits, and logic gate execution timing; the circuit compilation parameters include at least one of the following: bit mapping relationship, optimization requirements, and number of circuit executions.

[0087] Optionally, the adopted parallel method is a single-node multi-thread parallel processing method, or a multi-node parallel processing method.

[0088] According to a sixth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the methods described in the first aspect is implemented.

[0089] In a seventh aspect of the present application, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute any of the methods described in the first aspect.

[0090] Beneficial effects of the embodiments of the present application:

[0091] The batch-processing-based quantum computer operation method provided in the embodiments of the present application can obtain multiple target quantum circuits to be run; compile the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions; and send the obtained multiple target quantum computing instructions to the quantum chip. In response, the quantum chip can execute the multiple target quantum computing instructions and obtain the operation results of the multiple target quantum circuits. In this way, when using a large number of quantum circuits for calculation, multiple quantum circuits can be compiled simultaneously in a parallel manner, shortening the time consumed by compiling the quantum circuits and thereby improving the overall computing efficiency.

[0092] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0094] Figure 1 A flowchart of a batch-processing-based quantum computer operation method provided in an embodiment of the present application;

[0095] Figure 2 A flowchart of another batch-processing-based quantum computer operation method provided in an embodiment of the present application;

[0096] Figure 3 A schematic diagram of a process for parallel compilation of quantum circuits provided in an embodiment of the present application;

[0097] Figure 4 A flowchart of another batch-processing-based quantum computer operation method provided in an embodiment of the present application;

[0098] Figure 5 A flowchart of another batch-processing-based quantum computer operation method provided in an embodiment of the present application;

[0099] Figure 6 A structural diagram of a batch-processing-based quantum computer operating device provided in an embodiment of the present application;

[0100] Figure 7 A schematic diagram of data flow when a quantum computer performs batch processing on a quantum circuit according to an embodiment of the present application;

[0101] Figure 8 A structural diagram of a batch-processing-based quantum computer operating device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0102] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0103] Quantum circuits, as a manifestation of quantum programs, also known as quantum logic circuits, are the most commonly used general quantum computing model. They represent circuits that perform evolutionary operations on quantum bits in an abstract concept. They are composed of quantum bits, circuits (timelines), and various quantum logic gates. At the end of the quantum circuit, the results of state evolution can be read through quantum measurements.

[0104] After users write a quantum program representing a quantum circuit, they can upload it to a quantum computer. The quantum computer then performs calculations on the quantum circuit based on the program. The entire quantum circuit calculation process involves several steps, including parameter verification, resource estimation, resource scheduling, compilation optimization, chip calculations, and post-processing of the calculated data.

[0105] Solving complex problems often requires the use of a large number of quantum circuits. Furthermore, in some hybrid quantum-classical computing scenarios, multiple quantum circuit iterations are required, and each iteration also requires the use of a large number of quantum circuits. Therefore, improving overall computational efficiency when using a large number of quantum circuits is a core issue that quantum computing systems urgently need to address.

[0106] To address the aforementioned issues, embodiments of the present application provide a method for operating a quantum computer based on batch processing. This method can be applied to an electronic device (referred to herein as a batch processing device). The batch processing device is capable of communicating with a quantum chip in a quantum computer. After obtaining quantum computing instructions corresponding to a quantum circuit based on the methods provided in embodiments of the present application, the batch processing device sends these instructions to the quantum chip. For example, the batch processing device can be integrated into a quantum computer, or it can be a device independent of the quantum computer.

[0107] See also Figure 1 , Figure 1 A flowchart of a method for operating a quantum computer based on batch processing provided in an embodiment of the present application, the method comprising the following steps:

[0108] S101: Acquire multiple target quantum circuits to be run.

[0109] S102: Compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions.

[0110] S103: Sending the obtained multiple target quantum computing instructions to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

[0111] Based on the batch processing-based quantum computer operation method provided in the embodiments of the present application, when using a large number of quantum circuits for calculation, multiple quantum circuits can be compiled simultaneously in a parallel manner, thereby shortening the time consumed in compiling the quantum circuits and thereby improving the overall computing efficiency.

[0112] Regarding step S101, the quantum circuits mentioned in this application can achieve different functions in different scenarios. For example, in the development of new materials, quantum circuits can be used to determine the ground state energy of chemical molecules. In communication scenarios, quantum circuits can be used to achieve encrypted communication.

[0113] The multiple target quantum circuits currently to be run, that is, the quantum circuits that the batch processing device currently needs to compile, can be sent to the batch processing device in real time by the user through the client, or can be selected by the batch processing device from multiple quantum circuits pre-cached.

[0114] With respect to step S102 , one quantum circuit corresponds to one quantum computing instruction.

[0115] The first parallelization method can be a single-node multi-threaded parallel processing method, or a multi-node parallel processing method. That is, the batch processing device can be a single device. Accordingly, after acquiring multiple target quantum circuits, the batch processing device can compile the multiple target quantum circuits in parallel using multiple threads in a thread pool. For example, each thread compiles at least one target quantum circuit.

[0116] Alternatively, a batch processing device can also refer to a processing cluster consisting of multiple nodes, where a node represents a device with computing power. Accordingly, after acquiring multiple target quantum circuits, these target quantum circuits can be compiled in parallel using multiple nodes. For example, at least one thread can be enabled in each node to compile at least one target quantum circuit.

[0117] Understandably, due to performance limitations of the batch processing device, such as the limited number of threads in the thread pool or the limited number of nodes in the processing cluster, to fully utilize the batch processing device's computing resources, the number of target quantum circuits acquired each time must be no less than the maximum number of parallel processing tasks supported by the batch processing device. In this way, the batch processing device can complete the compilation of all target quantum circuits through multiple parallel processing steps.

[0118] In one implementation, the batch processing device processes each acquired target quantum circuit as a batch. Specifically, during each compilation, the batch processing device can send the quantum computing instructions corresponding to the target quantum circuits to the quantum chip after completing the compilation of all target quantum circuits. Accordingly, the quantum chip also processes each acquired quantum computing instruction as a batch.

[0119] In one embodiment, see Figure 2 ,exist Figure 1 On the basis of, before the above step S101, the method may further include:

[0120] Step S104: Receive the quantum circuit uploaded by the client and cache it.

[0121] Accordingly, the above step S101 may include:

[0122] Step S1011: Based on the current working state of the quantum chip, multiple target quantum circuits to be run are obtained from the currently cached quantum circuits.

[0123] The working status is idle or non-idle.

[0124] In an embodiment of the present application, since a user may continuously send a large number of quantum circuits through a client, when a batch processing device receives a quantum circuit uploaded by the client, it may be unable to compile and process the currently received quantum circuit. Therefore, the batch processing device may first cache the received quantum circuits, and then select a quantum circuit from the cached quantum circuits for compilation.

[0125] For example, a batch processing device can pre-set a queue (which can be called a task queue). After receiving the quantum circuit uploaded by the client, the received quantum circuit can be added to the queue. Subsequently, the quantum circuit can be obtained from the queue for compilation.

[0126] When multiple target quantum circuits need to be obtained from the cached quantum circuits, the batch processing device can determine the current working state of the quantum chip to determine the number of target quantum circuits to be obtained from the cached quantum circuits based on the current working state of the quantum chip.

[0127] For example, if the quantum chip currently has a quantum computing instruction being executed, it indicates that the current working state of the quantum chip is non-idle. Conversely, if the quantum chip currently has no quantum computing instruction being executed, it indicates that the current working state of the quantum chip is idle.

[0128] Alternatively, a cache space can be set up for the quantum chip. Since batch processing equipment may continuously send a large number of quantum computing instructions, and the quantum chip's computing resources are limited, when receiving a quantum computing instruction from the batch processing equipment, the quantum chip may not have any remaining computing resources, meaning it may be unable to execute the currently received quantum computing instruction. Therefore, the quantum chip can first cache the received quantum computing instruction, storing it in the cache space. Later, when there are remaining computing resources, the quantum chip can select a quantum computing instruction from the cache space for execution. In this case, if there are currently pending quantum computing instructions in the cache space, the quantum chip's current working state is non-idle. Conversely, if there are currently no pending quantum computing instructions in the cache space, the quantum chip's current working state is idle.

[0129] Based on the above processing, each time a target quantum circuit to be executed is obtained, the current working status of the quantum chip can be taken into account, which can fully utilize the computing performance of the quantum chip, avoid wasting computing resources, and further improve the overall computing efficiency.

[0130] When sending a quantum circuit, the client can also send its configuration information. This information can include the number of quantum circuit measurements and a result correction flag. The result correction flag indicates whether the execution results of the quantum computing instructions corresponding to the quantum circuit should be corrected. Accordingly, the batch processing device can also compile each quantum circuit based on the configuration information. If the client does not define the quantum circuit configuration information, the batch processing device can compile the quantum circuit based on the default configuration information.

[0131] In one embodiment, the above step S104 may include:

[0132] Receive the quantum circuit uploaded by the client; perform parameter verification on the received quantum circuit in a second parallel manner, and cache each quantum circuit after it passes the verification.

[0133] In an embodiment of the present application, after receiving a quantum circuit from a client, the batch processing device may first perform parameter verification on the quantum circuit to determine whether there is any illegal data in the quantum circuit. If not, the quantum circuit may be cached. Otherwise, no caching is performed to avoid subsequent processing errors.

[0134] Regarding the method of performing parameter verification in the second parallel mode, reference may be made to the relevant introduction of compiling based on the first parallel mode in the above embodiment.

[0135] In this way, by performing parameter verification on quantum circuits in parallel, the overall computing efficiency can be further improved.

[0136] In one embodiment, according to the user's instructions, the client can send multiple quantum circuits to the batch processing device through single submission or batch submission.

[0137] If there are multiple quantum circuits to be uploaded, the user can select one quantum circuit to be uploaded at a time in the client and instruct the client to upload it. In this way, through multiple submissions, the client can send the multiple quantum circuits to be uploaded to the batch processing device. This method can be called a single submission method.

[0138] Alternatively, the user can simultaneously select multiple quantum circuits to be uploaded in the client and instruct the client to upload them. The client can then send these multiple quantum circuits to the batch processing device as a whole. In this way, all multiple quantum circuits to be uploaded can be sent to the batch processing device with a single submission. This method is called batch submission.

[0139] See also Figure 3 , Figure 3 A schematic diagram of a process for parallel compilation of quantum circuits provided in an embodiment of the present application.

[0140] The batch processing device can obtain multiple target quantum circuits from the task queue for compilation. In addition, before the first compilation, the batch processing device can also perform preprocessing, including initializing the thread pool, allocating memory space for parallel compilation, and registering exception handling functions.

[0141] Single-circuit compilation involves compiling on a per-thread or per-node basis. The compilation process includes parsing, multi-gate decomposition, mapping, circuit optimization, crosstalk mitigation, and instruction conversion. Ultimately, the corresponding quantum computing instructions for each quantum circuit are generated. These instructions are then packaged in a unified format (i.e., quantum computing instruction integration) and sent to the quantum chip (i.e., the integrated quantum computing instructions). The quantum chip then performs the computation (i.e., executes the quantum computing instructions).

[0142] For each operation in the above-mentioned single-line compilation process, code decoupling can be used to encapsulate it into an independent execution unit to achieve unitized design. This also allows for parallel computing through parallel computing resources to achieve a scalable parallel compilation framework that supports single-node multi-threaded and multi-node multi-threaded parallel compilation scenarios.

[0143] In one embodiment, before step S102, the method may further include:

[0144] Resource estimation is performed on the multiple target quantum circuits in a third parallel manner to obtain quantum resources allocated to each target quantum circuit.

[0145] Accordingly, the above step S102 may include: compiling the multiple target quantum circuits in a first parallel manner according to the quantum resources allocated to each of the multiple target quantum circuits, to obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions.

[0146] In an embodiment of the present application, for each target quantum circuit, the batch processing device may further perform resource estimation, that is, allocate quantum resources (including quantum bits) to the target quantum circuit, and subsequently perform compilation based on the allocated quantum resources.

[0147] Regarding the method of performing resource estimation in the third parallel mode, reference may be made to the related introduction of the compilation based on the first parallel mode in the above embodiment.

[0148] In this way, by estimating the resources of quantum circuits in a parallel manner, the overall computing efficiency can be further improved.

[0149] In one embodiment, see Figure 4 ,exist Figure 3 On the basis of, the above step S1011 may include:

[0150] Step S10111: If the current working state of the quantum chip is idle, a first number of quantum circuits are obtained from the currently cached quantum circuits as the target quantum circuits to be currently run.

[0151] Step S10112: If the current working state of the quantum chip is non-idle, a second number of quantum circuits are obtained from the currently cached quantum circuits as the target quantum circuits to be currently run.

[0152] The second number is greater than the first number.

[0153] In the embodiment of the present application, for the two situations where the current working state of the quantum chip is non-idle and idle, the batch processing device can obtain different numbers of target quantum circuits for compilation.

[0154] If the quantum chip is currently idle, the batch processing device needs to quickly send the quantum computing instructions compiled from the quantum circuit to the quantum chip to fully utilize its computing resources and avoid long wait times. However, since compiling quantum circuits takes a considerable amount of time, the batch processing device can compile a smaller number of target quantum circuits from the currently cached quantum circuits to ensure the quantum chip receives and processes the instructions as quickly as possible.

[0155] Furthermore, since the batch processing device selects multiple target quantum circuits for processing as a batch, the quantum chip can also process the quantum computing instructions corresponding to these target quantum circuits as a batch. Therefore, if the batch processing device selects fewer target quantum circuits for compilation each time, it will lead to unnecessary process consumption. For example, if 200 quantum circuits are processed in five batches, compared to processing them as a batch, four data transfer operations will be generated, which will also affect the resource utilization of the quantum chip.

[0156] Therefore, if the current working state of the quantum chip is non-idle, the batch processing device does not need to send the quantum computing instructions obtained by compiling the quantum circuit to the quantum chip as soon as possible. At the same time, in order to avoid generating a large number of data flow operations, the batch processing device can obtain more target quantum circuits from the currently cached quantum circuits for compilation. In this way, the resource utilization of the quantum chip can be improved.

[0157] Based on the above processing, when the quantum chip is idle, quantum computing instructions can be sent to the quantum chip as quickly as possible, fully utilizing the quantum chip's computing resources and avoiding long wait times. Furthermore, when the quantum chip is busy, it can avoid generating a large number of data transfer operations, thereby further improving overall computing efficiency. Specifically, through the pre-compilation mechanism of the batch processing device, the function of simultaneously compiling quantum circuits and executing quantum computing instructions is achieved. While the quantum chip is executing quantum computing instructions, the batch processing device begins compiling the target quantum circuit to be executed. When the quantum chip completes its current task, it directly retrieves the pre-compiled quantum computing instructions from the cache and begins computing immediately. This allows the compilation time of the quantum circuit to be hidden within the execution time of the quantum circuit, effectively improving the utilization of the quantum chip's computing resources and reducing the overall computing time when a large number of quantum circuits are involved.

[0158] In one embodiment, the first number is the product of the specified number and a first coefficient, and the first coefficient is less than 1; the second number is the product of the specified number and a second coefficient, and the second coefficient is greater than 1; the specified number is determined based on the performance of the quantum chip and the maximum number of parallel processing tasks supported by the batch processing device.

[0159] Among them, the maximum number of parallel processing tasks supported by the batch processing device can be understood as the maximum number of quantum circuits that the batch processing device can process in parallel at the same time.

[0160] In embodiments of the present application, the performance of a quantum chip may include: the storage capacity of the quantum chip's cache space and the quantum chip's computing performance. A larger designated number can be set for a larger quantum chip's cache space; a higher designated number can be set for a higher quantum chip's computing performance; and a larger designated number can be set for a larger maximum number of parallel processing tasks supported by a batch processing device. For example, the designated number can be 200 or 300.

[0161] For each case where the working state of the quantum chip is idle, the first coefficient used in determining the first number may be the same or different; similarly, for each case where the working state of the quantum chip is non-idle, the second coefficient used in determining the second number may be the same or different.

[0162] In one embodiment, the first coefficient is positively correlated with the number of quantum computing instructions currently being executed by the quantum chip; and the second coefficient is positively correlated with the number of quantum computing instructions in the current cache space.

[0163] In an embodiment of the present application, under the premise of ensuring that the first coefficient is less than 1, if the number of quantum computing instructions currently being executed by the quantum chip is smaller, a smaller first coefficient can be set to calculate the first number, so that the batch processing device can complete the compilation as quickly as possible and send the compiled quantum computing instructions to the quantum chip.

[0164] It is understandable that since the batch processing device compiles quantum circuits in parallel, when the quantum chip is in an idle state, it is sufficient to ensure that the calculated minimum first number is not less than the maximum number of parallel processing tasks supported by the batch processing device. In this way, the range of the first coefficient can be determined.

[0165] Correspondingly, on the premise of ensuring that the second coefficient is greater than 1, if the number of quantum computing instructions in the current cache space of the quantum chip is larger, a larger second coefficient can be set to calculate the second number, which can avoid generating more data flow operations as much as possible.

[0166] It is understandable that if the second number is too large, it may cause subsequent quantum chips to wait. Therefore, the time required for a quantum chip to execute the maximum number of quantum computing instructions (i.e., the maximum number of quantum computing instructions that the quantum chip's cache space can store) can be predetermined (this can be called the first time). Based on the time required for the batch processing device to compile a quantum circuit, the maximum second number is determined, so that the time the batch processing device takes to compile this maximum second number of quantum circuits is less than the first time. In this way, the maximum second coefficient can be determined, that is, the range of the second coefficient can be determined.

[0167] Based on the above processing, the first number can be dynamically determined based on the number of quantum computing instructions currently being executed by the quantum chip, and the second number can be dynamically determined based on the number of quantum computing instructions currently in the cache. This allows full utilization of the quantum chip's computing resources, avoiding long wait times for the quantum chip. It also avoids excessive data transfer operations when the quantum chip is not idle, further improving overall computing efficiency.

[0168] In one embodiment, after step S103, the method further includes:

[0169] Step 1: Receive the operating results of multiple target quantum circuits sent by the quantum chip.

[0170] Step 2: Send the received running results to the client.

[0171] In the embodiments of the present application, the quantum chip can execute quantum computing instructions, thereby obtaining the corresponding quantum circuit operation results and sending them to the batch processing device. Correspondingly, the batch processing device can send the operation results to the client.

[0172] For example, after all the quantum computing instructions in each batch are executed, the quantum chip can send the running results of the quantum circuits corresponding to the multiple quantum computing instructions to the batch processing device.

[0173] In one embodiment, step 2 includes: post-processing the operation results of the plurality of target quantum circuits in a fourth parallel manner; and sending the post-processed operation results to the client.

[0174] In an embodiment of the present application, after receiving the operation results, the batch processing device can also post-process the operation results (including denoising the operation results and correcting the operation results), and send the post-processed operation results to the client.

[0175] Regarding the manner of performing post-processing in the fourth parallel manner, reference may be made to the relevant introduction to the compilation based on the first parallel manner in the above embodiment.

[0176] In this way, post-processing the running results in a parallel manner can further improve the overall computing efficiency.

[0177] The parameter verification, resource estimation, compilation, and post-processing introduced in the above embodiments can all be processed in a parallel manner, that is, the above different operations can be encapsulated into independent modules, and single-node multi-threaded or multi-node multi-threaded parallel processing can be performed according to specific business scenarios, which can effectively improve the overall processing efficiency of computing tasks.

[0178] In one embodiment, the batch processing device may also obtain multiple target quantum circuits to be run from the currently cached quantum circuits for processing based on the time consumption of each stage of parameter verification, resource estimation, compilation, and post-processing.

[0179] See also Figure 5 , Figure 5 A flowchart of another batch-based quantum computer operation method provided in an embodiment of the present application.

[0180] Users can upload multiple quantum circuits through the client, either individually or in batches. After receiving the quantum circuits, the batch processing device can perform parameter verification on them in parallel and add the quantum circuits that pass the verification to the task queue.

[0181] Subsequently, based on the quantum chip's operating status, the target quantum circuit can be retrieved from the task queue and resource estimation performed in parallel. The retrieved target quantum circuit can then be compiled in parallel to generate the corresponding quantum computing instructions, which are then sent to the quantum chip. The quantum chip executes the received quantum computing instructions based on its cache space and sends the results of the quantum circuit to the batch processing device. The batch processing device then post-processes the results in parallel and sends them to the client.

[0182] In the above process, for the multiple target quantum circuits obtained this time, if the batch processing device has completed compilation and there is currently no available space in the cache space of the quantum chip, the batch processing device can wait until there is available space in the cache space of the quantum chip and send the compiled quantum computing instructions to the quantum chip. In this way, optimal scheduling of the quantum circuits can be achieved.

[0183] In one embodiment, multiple target quantum circuits are spliced together by a client into a quantum computing task for transmission. The quantum computing task is spliced together according to a start instruction, circuit parameters of multiple target quantum circuits, and an end instruction. The circuit parameters of each target quantum circuit include circuit structure parameters and circuit compilation parameters.

[0184] For example, a quantum computing task may be structured as follows:

[0185] Start command-line structure parameter A-line compilation parameter A-line structure parameter B-line compilation parameter B-...line structure parameter Z-line compilation parameter Z-end command.

[0186] In existing technologies, each quantum circuit is transmitted as a separate quantum computing task, and the transmission structure is as follows:

[0187] Start command-line structure parameter A-line compilation parameter A-end command;

[0188] Start command-line structure parameter B-line compilation parameter B-end command;

[0189] ······

[0190] Start instruction - line structure parameter Z - line compilation parameter Z - end instruction.

[0191] Compared with the existing method in which each quantum circuit is transmitted as a quantum computing task separately, the batch submission method of this application can reduce the number of start instructions and end instructions, thereby reducing the transmission time.

[0192] In the previous embodiment, obtaining multiple target quantum circuits to be run (step S101) includes:

[0193] The quantum computing task is parsed to obtain the circuit structure parameters and circuit compilation parameters of each target quantum circuit; based on the circuit structure parameters of each target quantum circuit, a restoration is performed to obtain multiple target quantum circuits to be run.

[0194] Accordingly, compiling multiple target quantum circuits in a first parallel manner (step S102) includes:

[0195] Each target quantum circuit is compiled using a first parallel mode and a circuit compilation parameter of each target quantum circuit.

[0196] In another embodiment, the multiple target quantum circuits are transmitted by the client separately in the form of a circuit structure parameter set and a circuit compilation parameter set. The number of circuit structure parameters in the circuit structure parameter set is greater than the number of circuit compilation parameters in the circuit compilation parameter set, and each circuit compilation parameter corresponds to at least one circuit structure parameter.

[0197] For example, circuit compilation parameter A corresponds to circuit structure parameter A-circuit structure parameter E, that is, the circuit compilation parameters of quantum circuit A-quantum circuit E are the same; circuit compilation parameter B corresponds to circuit structure parameter F-circuit structure parameter Z, that is, the circuit compilation parameters of quantum circuit F-quantum circuit Z are the same.

[0198] Compared with the previous embodiment, this embodiment can also reduce the number of transmissions of line compilation parameters, avoid repeated transmission of the same line compilation parameters, and reduce transmission time.

[0199] In the previous embodiment, obtaining multiple target quantum circuits to be run (step S101) includes:

[0200] The circuit structure parameter set is parsed, the circuit structure parameters corresponding to each target quantum circuit are determined from the circuit structure parameter set, and restoration is performed based on the circuit structure parameters corresponding to each target quantum circuit to obtain multiple target quantum circuits to be currently operated.

[0201] Accordingly, compiling multiple target quantum circuits in a first parallel manner (step S102) includes:

[0202] The circuit compilation parameter set is parsed to obtain a plurality of circuit compilation parameters; and at least one target quantum circuit corresponding to each circuit compilation parameter is compiled in a first parallel manner.

[0203] In this embodiment, target quantum circuits with the same corresponding circuit compilation parameters are compiled simultaneously, further reducing the circuit compilation time.

[0204] Among them, the circuit structure parameters are used to characterize the quantum circuit structure, and the circuit compilation parameters are used to compile the quantum circuit; the circuit structure parameters include at least one of the following: logic gate type, logic gate parameters, number of bits, and logic gate execution timing; the circuit compilation parameters include at least one of the following: bit mapping relationship, optimization requirements, and number of circuit executions.

[0205] Based on the same inventive concept, the embodiment of the present application also provides a quantum computer operation device based on batch processing, which is also the batch processing device in the above embodiment. Figure 6 , Figure 6 A structural diagram of a batch-processing-based quantum computer operating device provided in an embodiment of the present application includes:

[0206] Memory 601, used for storing computer programs;

[0207] The processor 602 is configured to implement any of the aforementioned batch-processing-based quantum computer operation methods when executing the program stored in the memory 601 .

[0208] Furthermore, the above-mentioned device may further include a communication bus and / or a communication interface, and the processor 602, the communication interface, and the memory 601 communicate with each other via the communication bus.

[0209] The communication bus mentioned in the above devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0210] The communication interface is used for communication between the above devices and other devices.

[0211] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk memory. Alternatively, the memory may be at least one storage device located away from the processor.

[0212] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0213] Based on the same inventive concept, an embodiment of the present application further provides a quantum computer, which includes the batch processing device and quantum chip in the above embodiment; wherein:

[0214] The quantum chip is used to execute the quantum computing instructions received from the batch processing device to obtain the operation results of the quantum circuit.

[0215] In one embodiment, the cache space of the quantum chip is used to store quantum computing instructions received from the batch processing device; the quantum chip is specifically used to obtain and execute quantum computing instructions from the cache space when it has surplus computing resources.

[0216] In one embodiment, the quantum chip is further configured to send the operation results of the quantum circuit to the batch processing device.

[0217] See also Figure 7 , Figure 7 A schematic diagram of data flow when a quantum computer performs batch processing on quantum circuits, provided in an embodiment of the present application.

[0218] The quantum computer in this application may also include a control device, that is, the quantum computer includes Figure 7 The quantum computing hardware includes control devices and quantum chips. Figure 7The classic processing device in the embodiment is the batch processing device in the above embodiment. The classic processing device can be one or more.

[0219] like Figure 7 As shown, a classical processing device can acquire quantum circuits to be run and add them to a task queue. These quantum circuits can be submitted by users via the cloud or created by the classical processing device itself. Before adding a quantum circuit to the task queue, the classical processing device can also perform parameter verification on the quantum circuit in parallel. Accordingly, only quantum circuits that pass verification can be added to the task queue.

[0220] Each time, the classical processing device can retrieve multiple quantum circuits from the task queue, compile them in parallel, obtain the corresponding quantum computing instructions, integrate the multiple quantum computing instructions, and send the integrated quantum computing instructions to the quantum computing hardware. In addition, before the first compilation, the classical processing device can also perform preprocessing (including initializing the thread pool, allocating memory space for parallel compilation, registering exception handling functions, etc.). In the above process, before compiling, the classical processing device can also perform resource estimation on the quantum circuit in parallel, and compile according to the resource estimation results.

[0221] Furthermore, the control device can generate an analog signal representing the quantum logic gate indicated by the quantum computing instruction and send the analog signal to the quantum chip. In response, the quantum chip can apply the received analog signal to the qubit indicated by the quantum computing instruction, thereby applying the quantum logic gate to the qubit, running the quantum circuit and obtaining the result of the quantum circuit operation.

[0222] Classical processing devices can also obtain the operation results of quantum circuits from quantum computing hardware. In addition, classical processing devices can also post-process the operation results in parallel to obtain the final operation results and provide them to users.

[0223] Based on the same inventive concept, an embodiment of the present application further provides a quantum computer operation system based on batch processing, the system comprising the quantum computer in the above embodiment and a client; wherein:

[0224] The client is used to send multiple quantum circuits to the quantum computer in a single submission or batch submission manner according to the user's instructions.

[0225] Based on the same inventive concept, the present application also provides a quantum computer operation device based on batch processing, see Figure 8 , Figure 8This is a structural diagram of a batch-processing-based quantum computer operation device provided in an embodiment of the present application, the device comprising:

[0226] An acquisition module 801 is used to acquire multiple target quantum circuits to be run;

[0227] A compiling module 802 is configured to compile the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions;

[0228] The sending module 803 is used to send the obtained multiple target quantum computing instructions to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

[0229] In one embodiment, the apparatus further comprises:

[0230] a cache module, configured to receive and cache quantum circuits uploaded by a client before acquiring the multiple target quantum circuits to be run;

[0231] The acquisition module 801 is specifically configured to acquire a plurality of target quantum circuits to be run from the currently cached quantum circuits based on the current working state of the quantum chip; wherein the working state is idle or non-idle.

[0232] In one embodiment, the acquisition module 801 is specifically configured to acquire a first number of quantum circuits from currently cached quantum circuits as target quantum circuits to be currently run if the current working state of the quantum chip is idle;

[0233] If the current working state of the quantum chip is non-idle, a second number of quantum circuits is obtained from the currently cached quantum circuits as the target quantum circuits to be currently run; wherein the second number is greater than the first number.

[0234] In one embodiment, the apparatus is applied to a batch processing device, the first number is the product of a specified number and a first coefficient, and the first coefficient is less than 1; the second number is the product of the specified number and a second coefficient, and the second coefficient is greater than 1; the specified number is determined based on the performance of the quantum chip and the maximum number of parallel processing tasks supported by the batch processing device.

[0235] In one embodiment, the cache space of the quantum chip is used to store quantum computing instructions to be executed; the current working state of the quantum chip is idle, which means that there are no quantum computing instructions to be executed in the cache space.

[0236] The first coefficient is positively correlated with the number of quantum computing instructions currently being executed by the quantum chip; the second coefficient is positively correlated with the number of quantum computing instructions currently in the cache space.

[0237] In one embodiment, the cache module is specifically configured to receive a quantum circuit uploaded by a client;

[0238] Parameter verification is performed on the received quantum circuits in a second parallel manner, and each quantum circuit is cached after passing the verification.

[0239] In one embodiment, the apparatus further comprises:

[0240] a resource estimation module configured to, before compiling the multiple target quantum circuits in the first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits and using them as target quantum computing instructions, perform resource estimation on the multiple target quantum circuits in a third parallel manner to obtain quantum resources allocated to each target quantum circuit;

[0241] The compiling module 802 is specifically configured to compile the multiple target quantum circuits in a first parallel manner according to the quantum resources allocated to each of the multiple target quantum circuits, and obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions.

[0242] In one embodiment, the apparatus further comprises:

[0243] A receiving module, configured to receive, after sending the obtained multiple target quantum computing instructions to the quantum chip, the operation results of the multiple target quantum circuits sent by the quantum chip;

[0244] The forwarding module is used to send the received running results to the client.

[0245] In one embodiment, the forwarding module is specifically configured to post-process the operation results of the plurality of target quantum circuits in a fourth parallel manner;

[0246] Send the post-processing results to the client.

[0247] In one embodiment, the multiple target quantum circuits are spliced together by the client into a quantum computing task for transmission. The quantum computing task is spliced together according to a start instruction, circuit parameters of the multiple target quantum circuits, and an end instruction. The circuit parameters of each target quantum circuit include circuit structure parameters and circuit compilation parameters.

[0248] In one embodiment, the acquisition module 801 is specifically configured to parse the quantum computing task and obtain circuit structure parameters and circuit compilation parameters of each target quantum circuit;

[0249] Restore the circuit structure parameters of each target quantum circuit to obtain multiple target quantum circuits to be operated;

[0250] The compiling module 802 is specifically configured to compile each target quantum circuit in a first parallel manner using the circuit compilation parameters of each target quantum circuit.

[0251] In one embodiment, the multiple target quantum circuits are transmitted by the client separately in the form of a circuit structure parameter set and a circuit compilation parameter set. The number of circuit structure parameters in the circuit structure parameter set is greater than the number of circuit compilation parameters in the circuit compilation parameter set, and each circuit compilation parameter corresponds to at least one circuit structure parameter.

[0252] In one embodiment, the acquisition module 801 is specifically configured to parse the circuit structure parameter set, determine the circuit structure parameters corresponding to each target quantum circuit from the circuit structure parameter set, and perform restoration based on the circuit structure parameters corresponding to each target quantum circuit to obtain multiple target quantum circuits to be currently operated.

[0253] The compilation module 802 is specifically configured to parse the line compilation parameter set to obtain a plurality of line compilation parameters;

[0254] At least one target quantum circuit corresponding to each circuit compilation parameter is compiled in a first parallel manner.

[0255] In one embodiment, the circuit structure parameters are used to characterize the quantum circuit structure, and the circuit compilation parameters are used to compile the quantum circuit; the circuit structure parameters include at least one of the following: logic gate type, logic gate parameters, number of bits, and logic gate execution timing; the circuit compilation parameters include at least one of the following: bit mapping relationship, optimization requirements, and number of circuit executions.

[0256] In one embodiment, the parallel processing method used is a single-node multi-thread parallel processing method, or a multi-node parallel processing method.

[0257] In another embodiment provided in the present application, a computer-readable storage medium is further provided, wherein a computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of any of the above-mentioned batch-based quantum computer operation methods are implemented.

[0258] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any batch-based quantum computer operation method in the above embodiments.

[0259] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0260] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0261] Each embodiment in this specification is described in a related manner. Similar portions between embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. In particular, since the device, system, apparatus, quantum computer, computer-readable storage medium, and computer program product embodiments are generally similar to the method embodiments, their descriptions are relatively simplified. For relevant portions, reference can be made to the descriptions of the method embodiments.

[0262] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A method for operating a quantum computer based on batch processing, characterized in that: The method comprises: Obtain multiple target quantum circuits currently to be run; Compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions; The obtained multiple target quantum computing instructions are sent to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

2. The method according to claim 1, characterized in that Before obtaining the multiple target quantum circuits to be currently run, the method further includes: Receive quantum circuits uploaded by the client and cache them; The step of obtaining multiple target quantum circuits to be run includes: Based on the current working state of the quantum chip, a plurality of target quantum circuits to be currently run are obtained from the currently cached quantum circuits; wherein the working state is idle or non-idle.

3. The method according to claim 2, characterized in that The step of obtaining a plurality of target quantum circuits to be run from the currently cached quantum circuits based on the current working state of the quantum chip includes: If the current working state of the quantum chip is idle, obtaining a first number of quantum circuits from the currently cached quantum circuits as target quantum circuits to be currently run; If the current working state of the quantum chip is non-idle, a second number of quantum circuits is obtained from the currently cached quantum circuits as the target quantum circuits to be currently run; wherein the second number is greater than the first number.

4. The method according to claim 3, characterized in that The method is applied to a batch processing device, the first number is the product of a specified number and a first coefficient, and the first coefficient is less than 1; the second number is the product of the specified number and a second coefficient, and the second coefficient is greater than 1; the specified number is determined based on the performance of the quantum chip and the maximum number of parallel processing tasks supported by the batch processing device.

5. The method according to claim 4, characterized in that The cache space of the quantum chip is used to store quantum computing instructions to be executed; the current working state of the quantum chip is idle, which means that there are no quantum computing instructions to be executed in the cache space; The first coefficient is positively correlated with the number of quantum computing instructions currently being executed by the quantum chip; The second coefficient is positively correlated with the number of quantum computing instructions currently in the cache space.

6. The method according to claim 2, characterized in that The receiving and caching of the quantum circuit uploaded by the client includes: Receive quantum circuits uploaded by the client; Parameter verification is performed on the received quantum circuits in a second parallel manner, and each quantum circuit is cached after passing the verification.

7. The method according to claim 1, characterized in that Before compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions, the method further includes: performing resource estimation on the plurality of target quantum circuits in a third parallel manner to obtain quantum resources allocated to each target quantum circuit; Compiling the multiple target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the multiple target quantum circuits as target quantum computing instructions includes: In a first parallel manner, the multiple target quantum circuits are compiled according to the quantum resources allocated to each of the multiple target quantum circuits to obtain quantum computing instructions corresponding to each of the multiple target quantum circuits as target quantum computing instructions.

8. The method according to claim 1, characterized in that After sending the obtained multiple target quantum computing instructions to the quantum chip, the method further includes: receiving the operation results of the multiple target quantum circuits sent by the quantum chip; Send the received operation results to the client.

9. The method according to claim 8, characterized in that The sending of the received operation result to the client includes: performing post-processing on the operation results of the plurality of target quantum circuits in a fourth parallel manner; Send the post-processing results to the client.

10. The method according to claim 1, characterized in that The multiple target quantum circuits are spliced together by the client into a quantum computing task for transmission. The quantum computing task is spliced together according to a start instruction, the circuit parameters of the multiple target quantum circuits, and an end instruction. The circuit parameters of each target quantum circuit include circuit structure parameters and circuit compilation parameters.

11. The method according to claim 10, characterized in that The step of obtaining multiple target quantum circuits to be run includes: Analyzing the quantum computing task to obtain circuit structure parameters and circuit compilation parameters of each target quantum circuit; Restore the circuit structure parameters of each target quantum circuit to obtain multiple target quantum circuits to be operated; Compiling the plurality of target quantum circuits in a first parallel manner includes: Each target quantum circuit is compiled using a first parallel mode and a circuit compilation parameter of each target quantum circuit.

12. The method according to claim 1, characterized in that The multiple target quantum circuits are transmitted by the client in the form of a circuit structure parameter set and a circuit compilation parameter set, respectively. The number of circuit structure parameters in the circuit structure parameter set is greater than the number of circuit compilation parameters in the circuit compilation parameter set, and each circuit compilation parameter corresponds to at least one circuit structure parameter.

13. The method according to claim 12, characterized in that The step of obtaining multiple target quantum circuits to be run includes: parsing the circuit structure parameter set, determining the circuit structure parameters corresponding to each target quantum circuit from the circuit structure parameter set, and performing restoration based on the circuit structure parameters corresponding to each target quantum circuit to obtain a plurality of target quantum circuits to be currently operated; Compiling the plurality of target quantum circuits in a first parallel manner includes: parsing the line compilation parameter set to obtain a plurality of line compilation parameters; At least one target quantum circuit corresponding to each circuit compilation parameter is compiled in a first parallel manner.

14. The method according to any one of claims 10 to 13, characterized in that: The circuit structure parameters are used to characterize the quantum circuit structure, and the circuit compilation parameters are used to compile the quantum circuit. The circuit structure parameters include at least one of the following: logic gate type, logic gate parameters, number of bits, and logic gate execution timing. The circuit compilation parameters include at least one of the following: bit mapping relationship, optimization requirements, and number of circuit executions.

15. The method according to any one of claims 1 to 13, characterized in that The parallel method adopted is a single-node multi-thread parallel processing method, or a multi-node parallel processing method.

16. A quantum computer operating device based on batch processing, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the method according to any one of claims 1 to 15 when executing a program stored in a memory.

17. A quantum computer, characterized in that The quantum computer comprises the device and quantum chip according to claim 16; wherein: The quantum chip is used to execute the quantum computing instructions received from the device to obtain the operation results of the quantum circuit.

18. The quantum computer according to claim 17, characterized in that The cache space of the quantum chip is used to store quantum computing instructions received from the device; The quantum chip is specifically configured to obtain and execute quantum computing instructions from the cache space when the quantum chip has surplus computing resources.

19. The quantum computer according to claim 17, wherein: The quantum chip is also used to send the operation results of the quantum circuit to the device.

20. A quantum computer operating system based on batch processing, characterized in that: The system comprises a quantum computer according to any one of claims 17 to 19, and a client; wherein: The client is used to send multiple quantum circuits to the quantum computer in a single submission or batch submission manner according to the user's instructions.

21. A quantum computer operating device based on batch processing, characterized in that: The device comprises: An acquisition module is used to acquire multiple target quantum circuits currently to be run; a compiling module, configured to compile the plurality of target quantum circuits in a first parallel manner to obtain quantum computing instructions corresponding to the plurality of target quantum circuits as target quantum computing instructions; The sending module is used to send the obtained multiple target quantum computing instructions to the quantum chip, so that the quantum chip executes the multiple target quantum computing instructions and obtains the operation results of the multiple target quantum circuits.

22. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 15 is implemented.

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