Display panel and display device

Abstract

This disclosure relates to a display panel and display device. The display panel includes a first display area, a second display area, a first non-display area, a second non-display area, a third non-display area, and a plurality of pixels. The first and second display areas together constitute an irregularly shaped display panel. The first, second, and third non-display areas are located in the irregular area of ​​the display panel. The width of the first non-display area is 'a', the width of the second non-display area is 'b', and the width of the third non-display area is 'c'. The preset difference is 'm', where |a-b|≤m, |c-b|≤m, and |a-c|≤m. This disclosure improves the consistency of the borders of the irregular areas by reducing the difference in border width in the irregular areas of the display panel, reduces the appearance difference of the borders of the irregularly shaped display panel, and improves the visual experience for users.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In order to match the camera area, some smart devices will have an irregularly shaped display area to make room for the camera. For display panels with irregular areas, the borders of the irregular areas will also have different appearances due to the layout of the peripheral control circuits, thus affecting the user's visual experience. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a display panel and a display device.

[0004] This disclosure provides a display panel, characterized in that the display panel includes a first display area, a second display area, a first non-display area, a second non-display area, a third non-display area, and a plurality of pixels, wherein: the length of the first display area in a first direction is less than the length of the second display area in the first direction, and the first display area and the second display area are adjacent; along a second direction, the first non-display area is located on the side of the first display area away from the second display area; along the first direction, the second non-display area is located on one side of the first display area, and the second non-display area is located between the first non-display area and the third non-display area, and the second non-display area is adjacent to the first non-display area and the third non-display area; along the second direction, the third non-display area is located on the side of the second display area closer to the first display area, and the first direction and the second direction intersect; the width of the first non-display area is a, the width of the second non-display area is b, the width of the third non-display area is c, and the preset difference is m, wherein |ab|≤m, and |cb|≤m, and |ac|≤m.

[0005] Optionally, the widths of the first non-display area, the second non-display area, and the third non-display area are all less than the preset width W.

[0006] Optionally, the preset range of the difference m is 0.08mm≤m≤0.12mm.

[0007] Optionally, the preset width W is in the range of 1.4mm≤W≤1.6mm.

[0008] Optionally, the display panel further includes a fourth non-display area, located along the first direction on the side of the first display area away from the second non-display area; the display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line; the first display area includes a first pixel row extending along the first direction; the first control line is electrically connected to a pixel in the first pixel row, and a first end of the first control line is electrically connected to the first control circuit, and a second end of the first control line is electrically connected to another first control circuit; the second control line is electrically connected to a pixel in the first pixel row, and a first end of the second control line is electrically connected to the second control circuit, and a second end of the second control line is electrically connected to another second control circuit; the first control line and the second control line connect to different transistors in the same pixel, wherein: the fourth non-display area includes the first control circuit and the second control circuit; at least one of the first non-display area, the second non-display area, and the third non-display area includes the first control circuit, and / or, at least one of the first non-display area, the second non-display area, and the third non-display area includes the second control circuit.

[0009] Optionally, the number of first pixel rows in the first display area is greater than or equal to a first preset threshold; the first non-display area and the fourth non-display area include a first control circuit, and the second non-display area, the third non-display area, and the fourth non-display area include a second control circuit; or, the second non-display area and the fourth non-display area include a first control circuit, and the first non-display area, the third non-display area, and the fourth non-display area include a second control circuit; or, the third non-display area and the fourth non-display area include a first control circuit, and the first non-display area, the second non-display area, and the fourth non-display area include a second control circuit.

[0010] Optionally, the number of first pixel rows in the first display area is less than a first preset threshold; the first non-display area and the fourth non-display area include a first control circuit, the fourth non-display area includes a second control circuit, and the second non-display area or the third non-display area includes a second control circuit; or, the second non-display area and the fourth non-display area include a first control circuit, the fourth non-display area includes a second control circuit, and the first non-display area or the third non-display area includes a second control circuit; or, the third non-display area and the fourth non-display area include a first control circuit, the fourth non-display area includes a second control circuit, and the first non-display area or the second non-display area includes a second control circuit.

[0011] Optionally, the first non-display area or the third non-display area includes a first control circuit; the first control line includes a first control line segment located in the first display area and a second control line segment electrically connected to the first control line segment, the first control line segment and the second control line segment intersect in their extending directions, and the second control line segment is connected in series between the first control line segment and the first control circuit located in the first non-display area or the third non-display area; or, the first non-display area or the third non-display area includes a second control circuit; the second control line includes a third control line segment located in the first display area and a fourth control line segment electrically connected to the third control line segment, the third control line segment and the fourth control line segment intersect in their extending directions, and the fourth control line segment is connected in series between the third control line segment and the second control circuit located in the first non-display area or the third non-display area.

[0012] Optionally, the second display area includes a second pixel row, the first control circuit is a scanning control circuit, and the second control circuit is an emission control circuit; the ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is greater than a second preset threshold, and the number of second control lines connected to a second control circuit is greater than or equal to a third preset threshold.

[0013] Optionally, the display panel further includes a fourth non-display area, located along the first direction on the side of the first display area away from the second non-display area; the display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line; the first display area includes a first pixel row extending along the first direction; the first control line is electrically connected to a pixel in the first pixel row, and a first end of the first control line is electrically connected to the first control circuit, and a second end of the first control line is electrically connected to another first control circuit; the second control line is electrically connected to a pixel in the first pixel row, and one end of the second control line is electrically connected to the second control circuit; the first control line and the second control line connect to different transistors in the same pixel, wherein: the second non-display area includes the first control circuit, and the fourth non-display area includes both the first control circuit and the second control circuit.

[0014] Optionally, the second display area includes a second pixel row, the first control circuit is a scanning control circuit, and the second control circuit is an emission control circuit; the ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is greater than a second preset threshold, and the number of second control lines connected to a second control circuit is less than a third preset threshold.

[0015] Optionally, the display panel further includes a fourth non-display area, which is located on the side of the first display area away from the second non-display area along the first direction; the display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line. The first display area includes a first pixel row extending along the first direction. The first control line is electrically connected to the pixels in the first pixel row, and one end of the first control line is electrically connected to the first control circuit. The second control line is electrically connected to the pixels in the first pixel row, and one end of the second control line is electrically connected to the second control circuit. The first control line and the second control line are connected to different transistors in the same pixel, wherein the fourth non-display area includes the first control circuit and the second control circuit.

[0016] Optionally, the second display area includes a second pixel row; the first control circuit is a scan control circuit, and the second control circuit is an emission control circuit; or, the first control circuit is an emission control circuit, and the second control circuit is a scan control circuit; the ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is less than or equal to a second preset threshold, and the number of second control lines connected to a second control circuit is less than a third preset threshold.

[0017] Optionally, it also includes a cathode signal line located in the non-display area, wherein the cathode signal line is disposed in a different layer from the cathode of the pixel, and the cathode signal line is electrically connected to the cathode of the pixel; the first non-display area and the third non-display area include the cathode signal line, and the second non-display area does not include the cathode signal line.

[0018] Optionally, the first non-display area, the second non-display area, and the third non-display area all include cathode signal lines, which are disposed in a different layer from the cathode of the pixel and are electrically connected to the cathode of the pixel; the width of the cathode signal line in the first non-display area is H1, the width of the cathode signal line in the second non-display area is H2, and the width of the cathode signal line in the third non-display area is H3, wherein H2 < H1 and H2 < H3.

[0019] Optionally, the range of the second preset threshold k is 0.4≤k≤0.6.

[0020] Optionally, the range of the third preset threshold l is 3≤l≤5.

[0021] Optionally, the display panel further includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, a first control line, a second control line, a third control line, and a fourth control line, wherein: the first display area includes a first pixel row extending along a first direction; the first control line is electrically connected to a pixel in the first pixel row and is electrically connected to at least one first control circuit; the second control line is electrically connected to a pixel in the first pixel row and is electrically connected to at least one second control circuit; the second display area includes a second pixel row extending along the first direction; the third control line is electrically connected to a pixel in the second pixel row and is electrically connected to at least one third control circuit; the fourth control line is electrically connected to a pixel in the second pixel row and is electrically connected to at least one fourth control circuit; each pixel includes a pixel circuit and a light-emitting element, and the pixel is electrically connected to a first control circuit, a second control circuit, a third control circuit, a third control circuit, a fourth control line, and a fourth control circuit; each pixel includes a pixel circuit and a light-emitting element, and the pixel is electrically connected to a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, a fifth control circuit, a sixth control circuit, a seventh control circuit, a saturation point ... The circuit includes a driving transistor, a threshold compensation transistor, and a light-emitting control transistor. The driving transistor provides a driving signal to the light-emitting element, and the light-emitting control transistor transmits the driving signal to the light-emitting element. The first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. A first control line is connected to the gate of the threshold compensation transistor of the pixel in the first pixel row, and a second control line is connected to the gate of the light-emitting control transistor in the first pixel row. A third control line is connected to the gate of the threshold compensation transistor of the pixel in the second pixel row, and a fourth control line is connected to the gate of the light-emitting control transistor in the second pixel row. There is a gap between the orthographic projection of the first control circuit on the substrate and the orthographic projection of the third control circuit on the substrate. There is also a gap between the orthographic projection of the second control circuit on the substrate and the orthographic projection of the fourth control circuit on the substrate.

[0022] Optionally, when the first control circuit and the second control circuit control the first display area to display a preset image, the third control circuit and the fourth control circuit control the second display area to turn off the screen.

[0023] Based on the same inventive concept, this disclosure also provides a display device, including any of the display panels described above.

[0024] Compared with the prior art, the technical solution provided in this disclosure has the following advantages: by reducing the difference in border width in irregular areas of the display panel, this disclosure improves the consistency of the border in irregular areas, reduces the appearance difference of the border of irregularly shaped display panels, and improves the visual experience of users. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the structure of an electronic device provided for an embodiment of this disclosure;

[0028] Figure 2 A schematic diagram of the structure of a display panel provided for an embodiment of this disclosure;

[0029] Figure 3 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0032] Figure 6 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0033] Figure 7 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0034] Figure 8 A schematic diagram of a pixel circuit provided for an embodiment of this disclosure;

[0035] Figure 9 A schematic diagram of another pixel circuit provided for an embodiment of this disclosure;

[0036] Figure 10 A schematic diagram of another pixel circuit provided for an embodiment of this disclosure;

[0037] Figure 11 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0038] Figure 12 A schematic diagram of another display panel provided in this embodiment of the present disclosure;

[0039] Figure 13 A schematic cross-sectional view of a display panel provided for an embodiment of this disclosure;

[0040] Figure 14This is a schematic diagram of another display panel provided in an embodiment of the present disclosure. Detailed Implementation

[0041] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this disclosure, the solutions of the embodiments of this disclosure will be further described below. It should be noted that, unless otherwise specified, the embodiments and features of the embodiments of this disclosure can be combined with each other.

[0042] Numerous specific details are set forth in the following description to provide a full understanding of the embodiments of this disclosure, but the embodiments of this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments described in the specification are only a part of the embodiments of this disclosure, and not all of them.

[0043] This application provides an irregularly shaped panel, such as... Figure 1 As shown, Figure 1 A foldable electronic device is shown, including a display screen 1 and a camera 2. It can be seen that, to accommodate the camera 2, the display screen 1 has an irregular, non-standard design with a large notch area. This notch area can be used to house the camera 2. Multiple cameras 2 can be used, which can improve the user experience. For an irregularly shaped display panel, the bezels of these irregular areas will also vary in appearance due to the layout of the peripheral control circuitry, resulting in different bezel widths in different areas of the display panel. This can cause noticeable visual differences, or there may be a clear dividing line between the display screen 1 and the camera 2, thus affecting the user's visual experience.

[0044] In view of this, one embodiment of the present disclosure provides a display panel, such as Figure 2 As shown, the display panel includes a first display area 11, a second display area 12, a first non-display area 21, a second non-display area 22, a third non-display area 23, and multiple pixels 100, wherein:

[0045] The length of the first display area 11 in the first direction X is less than the length of the second display area 12 in the first direction X, and the first display area 11 and the second display area 12 are adjacent to each other.

[0046] Specifically, the aforementioned first direction X can be the arrangement direction of pixel rows. The pixel rows adjacent to the first display area 11 and the second display area 12 are aligned on one side. The difference in the number of pixels arranged in the first display area 11 and the second display area 12 along the first direction X is greater than a first quantity, which can be 100, 200, 250~270, or 260. Understandably, in order to have sufficient space to place the camera 2, at the position adjacent to the first display area 11 and the second display area 12, the number of pixels in the last row of the first display area 11 will have a significant difference from the number of pixels in the first row of the second display area 12. In other words, this is equivalent to removing a portion of the pixel columns arranged along the first direction X in the first display area 11. The number of removed pixel columns can be 100, 200, or between 250 and 270.

[0047] like Figure 2 As shown, along the second direction Y, the first non-display area 21 is located on the side of the first display area 11 away from the second display area 12; along the first direction X, the second non-display area 22 is located on one side of the first display area 11, and the second non-display area 22 is located between the first non-display area 21 and the third non-display area 23, and the second non-display area 22 is adjacent to the first non-display area 21 and the second non-display area 22 is adjacent to the third non-display area 23; along the second direction Y, the third non-display area 23 is located on the side of the second display area 12 closer to the first display area 11, and the first direction X intersects with the second direction Y.

[0048] Specifically, the second non-display area 22, located away from the first display area 11, and the third non-display area 23, located away from the second display area 12, include non-display panel components, such as optical components like a camera. In other words, the second non-display area 22 is located between the optical components (e.g., a camera) and the first display area 11. The difference in length between the first display area 11 and the second display area 12 in the first direction X is greater than the length of the aforementioned non-display panel components in the first direction X. Specifically, the first direction X intersects the second direction Y perpendicularly.

[0049] Specifically, such as Figure 2 As shown, the display panel also includes a fourth non-display area 24, a fifth non-display area 25, and a sixth non-display area 26. Along the first direction X, the fourth non-display area 24 is located on the side of the first display area 11 away from the second non-display area 22; the fifth non-display area 25 is located on one side of the second display area 12 and is adjacent to the fourth non-display area 24; the sixth non-display area 26 is located on one side of the second display area 12 and is adjacent to the third non-display area 23. The same principle applies to the accompanying drawings in the following embodiments, and will not be repeated here. Optionally, the fourth non-display area 24, the fifth non-display area 25, and the sixth non-display area 26 have the same width.

[0050] like Figure 2 As shown, the width of the first non-display area 21 is a, the width of the second non-display area 22 is b, the width of the third non-display area 23 is c, and the preset difference is m, where |ab|≤m, |cb|≤m, and |ac|≤m.

[0051] Specifically, the first non-display area 21, the second non-display area 22, and the third non-display area 23 all include a cutting edge and an edge opposite to the cutting edge and adjacent to the first display area 11 or the second display area 12. The width of the first non-display area 21, the second non-display area 22, and the third non-display area 23 can be the shortest distance between the cutting edge and the other edge. Optionally, since the first display area 11 includes multiple pixels 100, and each pixel 100 may include pixel circuits and light-emitting elements, and the multiple pixels 100 are arranged in multiple pixel rows along the second direction Y, as an example, the edge adjacent to the first display area 11 and the second non-display area 22 can be a virtual line formed by connecting the edges of the light-emitting elements closest to the second non-display area 22 in the multiple pixel rows. Optionally, as an example, the edge adjacent to the first display area 11 and the second non-display area 22 can also be a virtual line formed by connecting the edges of the pixel circuits closest to the second non-display area 22. It is understood that the adjacent boundaries between the display area and the non-display area can also be divided by other structures.

[0052] This application improves the consistency of the borders at various locations in the irregular areas by reducing the width difference of the borders in the irregular areas of the display panel (i.e., the first non-display area 21, the second non-display area 22, and the third non-display area 23 mentioned above), thereby reducing the appearance difference of the borders of the irregular display panel and improving the visual experience of the user.

[0053] Optionally, the range of the preset difference m is 0.08mm≤m≤0.12mm, and optionally, m =0.1mm.

[0054] When the preset difference m is around 0.1mm, it is difficult to observe the difference in width of the border area with the naked eye. At the same time, due to process errors during the manufacturing process, there is no need to limit the preset difference m to too small. It is generally between 0.08mm and 0.12mm.

[0055] Optionally, such as Figure 2 As shown, the width a of the first non-display area 21, the width b of the second non-display area 22, and the width c of the third non-display area 23 are all less than or equal to the preset width W.

[0056] By reducing the border width of irregular areas in the display panel, the visual prominence of these irregular borders can be reduced, further enhancing the user's visual experience.

[0057] Optionally, the range of the preset width W is 1.4mm≤W≤1.6mm, and optionally, W=1.5mm.

[0058] When the preset width W is about 1.5mm, the bezel of the display panel will not be very noticeable to the naked eye. At the same time, in order to facilitate the layout of peripheral circuits in the non-display area, there is no need to limit the preset width W to too small.

[0059] Optionally, such as Figure 3 As shown, the display panel also includes a fourth non-display area 24, which is located on the side of the first display area 11 away from the second non-display area 22 along the first direction X.

[0060] The display panel also includes a first control circuit 31, a second control circuit 32, a first control line SL1, and a second control line SL2. The first display area includes a first pixel row 10 extending along a first direction X. The first control line SL1 is electrically connected to the pixels in the first pixel row 10, and its first end is electrically connected to the first control circuit 31, while its second end is electrically connected to another first control circuit 31. The second control line SL2 is electrically connected to the pixels in the first pixel row 10, and its first end is electrically connected to the second control circuit 32, while its second end is electrically connected to another second control circuit 32. The first control line SL1 and the second control line SL2 connect to different transistors in the same pixel, and the signals transmitted by the first control line SL1 and the second control line SL2 are different. In other words, the first control circuit 31 and the second control circuit 32 transmit different signals, such as... Figure 3 As shown, the first control circuit 31 transmits signal STV1 through cascading, and the second control circuit 32 transmits signal STV2 through cascading. The following implementation methods are the same and will not be described again. Wherein:

[0061] The fourth non-display area 24 includes a first control circuit 31 and a second control circuit 32;

[0062] At least one of the first non-display area 21, the second non-display area 22, and the third non-display area 23 includes a first control circuit 31, and / or at least one of the first non-display area 21, the second non-display area 22, and the third non-display area 23 includes a second control circuit 32.

[0063] Specifically, the first control circuit 31 provides a first control signal to each pixel in the first pixel row 10 through the first control line SL1, and the second control circuit 32 provides a second control signal to each pixel in the first pixel row 10 through the second control line SL2. One control line connects to two control circuits, meaning the two control circuits transmit control signals from both ends of the control line to the control line, thereby providing control signals for a row of pixels. This control method is called bilateral drive control. Bilateral drive control can improve the transmission effect of the first control line SL1 and reduce the voltage drop (IR-drop) of the first control line SL1 along the first direction X. It is understandable that bilateral drive control can also improve the transmission effect of the second control line SL2 and reduce the voltage drop (IR-drop) of the second control line SL2 along the first direction X. When both the first and second control signals need to be provided through bilateral drive control, the border area of ​​the irregular region needs to be the same as the border area of ​​the regular region (i.e., the fourth non-display area 24), that is, to simultaneously accommodate both the first control circuit 31 and the second control circuit 32. Figure 3 As shown, the first end of the first control line SL1 is electrically connected to the first control circuit 31, the second end of the first control line SL1 is electrically connected to another first control circuit 31, the first end of the second control line SL2 is electrically connected to the second control circuit 32, and the second end of the second control line SL2 is electrically connected to another second control circuit 32. The first control circuit 31 connected to the first end of the first control line SL1 is located in the fourth non-display area 24, and the second control circuit 32 connected to the first end of the second control line SL2 is also located in the fourth non-display area 24. If the first control circuit 31, which is electrically connected to the second end of the first control line SL1, and the second control circuit 32, which is electrically connected to the second end of the second control line SL2, are both located in the second non-display area 22 opposite to the fourth non-display area 24, it will inevitably lead to an increase in the width of the second non-display area 22. Moreover, the width of the second non-display area 22 will be significantly greater than the width of the first non-display area 21 and the third non-display area 23. Therefore, the above embodiment utilizes the first non-display area 21 and / or the third non-display area 23 and / or the second non-display area 22 to share the first control circuit 31 and the second control circuit 32 that need to be set, which can reduce the width difference of the border of the irregular area in the display panel, further improve the consistency of the border of the irregular area, and further improve the visual experience of the user.

[0064] Figure 3 The wiring shown to identify the cascaded connection of the first control circuit 31 and the second control circuit 32 is not intended to limit the wiring in the display panel to be the same as the wiring shown in the figure in a specific implementation; it is merely an example. The following embodiments are similar and will not be described again. Optionally, as Figure 3 and or Figure 4 As shown, the first control circuit 31 and the second control circuit 32 can be arranged alternately in the second direction Y.

[0065] Optionally, such as Figure 3 As shown, the first control line SL1 includes a first control line segment SL101 located in the first display area 11 and a second control line segment SL102 electrically connected to the first control line segment SL101. The extension directions of the first control line segment SL101 and the second control line segment SL102 intersect. Specifically, the extension direction of the first control line segment SL101 is the X direction, and the extension direction of the second control line segment SL102 is the Y direction. The second control line segment SL102 is connected in series between the first control line segment SL101 and the first control circuit 31 located in the first non-display area 21 or the third non-display area 23. Alternatively, the second control line SL2 includes a third control line segment SL103 located in the first display area 11 and a fourth control line segment SL104 electrically connected to the third control line segment SL103. The extension directions of the third control line segment SL103 and the fourth control line segment SL104 intersect. Specifically, the extension direction of the third control line segment SL103 is the X direction, and the extension direction of the fourth control line segment SL104 is the Y direction. The fourth control line segment SL104 is connected in series between the third control line segment SL103 and the second control circuit 32 located in the first non-display area 21 or the third non-display area 23.

[0066] Specifically, such as Figure 3 As shown, when the first control circuit 31 or the second control circuit 32 is located in the first non-display area 21 or the third non-display area 23, the control lines can be routed directly from the first display area 11 and / or the second display area 12 to the first non-display area 21 or the third non-display area 23 through the intersecting first control line segment SL101 and second control line segment SL102, without passing through the second non-display area 22. This eliminates the need to set up control line routing in the second non-display area 22 to connect the second end of the first control line SL1 to the first control circuit 31 located in the first non-display area 21 or the third non-display area 23, and also eliminates the need to set up control line routing in the second non-display area 22 to connect the second end of the second control line SL2 to the second control circuit located in the first non-display area 21 or the third non-display area 23. This reduces the number of control line routings in the second non-display area 22, further reducing the space occupied by the control line routing in the second non-display area 22, thereby further reducing the width of the second non-display area 22.

[0067] To more clearly demonstrate the positions of the first non-display area 21, the second non-display area 22, the third non-display area 23, and the fourth non-display area 24 relative to the first display area 11, Figure 3The first display area 11 and its surrounding area have been enlarged, and portions of the second display area 12, the fifth non-display area 25, and the sixth non-display area 26 have been omitted accordingly. The control circuits in the fifth non-display area 25 and the sixth non-display area 26 used to provide control signals to the pixels in the second display area 12 have also been omitted. This does not mean that... Figure 3 In the illustrated embodiment, the complete second display area 12, third non-display area 23, fourth non-display area 24, and corresponding control circuits are not present. The accompanying drawings for the following embodiments are similar and will not be repeated. Furthermore, to clearly demonstrate the positions of the first control circuit 31 and the second control circuit 32 within the first non-display area 21, second non-display area 22, third non-display area 23, and / or fourth non-display area 24, the following are... Figure 3 The widths of the first non-display area 21, the second non-display area 22, and the third non-display area 23 are enlarged in proportion to the size of the first display area 11. This does not mean that the actual product size is the same as the attached figure. The same applies to the attached figure in the following embodiments, and will not be repeated.

[0068] Optionally, such as Figure 4 As shown, the extension direction of the edge of the first display area 11 near the second non-display area 22 intersects the first direction, meaning the edge of the first display area 11 near the second non-display area 22 is an inclined edge. The second non-display area 22 includes a first control circuit 31, which is inclined relative to the first direction X. Optionally, the first control circuit 31 may include a first output transistor (not shown in the figure), with an angle A between the virtual extension line of the channel of the first output transistor and the inclined edge, where 45° ≤ A ≤ 90°. The second non-display area 22 includes a second control circuit 32, which is inclined relative to the first direction X. Optionally, the second control circuit 32 may include a second output transistor (not shown in the figure), with an angle B between the virtual extension line of the channel of the second output transistor and the inclined edge, where 45° ≤ B ≤ 90°. It is understood that the transistor channel may include polysilicon or oxide semiconductor (e.g., indium gallium zinc oxide).

[0069] Optionally, the cutting edge of the second non-display area 22 has a first angle α with the first direction X, 45°≤ α≤90°, that is, the edge of the first display area 11 near the irregular area is inclined. The first control line SL1 and the second control line SL2 connected to the first control circuit 31 and the second control circuit 32 in the second non-display area 22 also have a second angle with the first direction X. In addition, the circuit traces in the first control circuit 31 and the second control circuit 32 in the second non-display area 22 also have a second angle β with the first direction X, 45°≤ β≤90°. Specifically, the second angle β is the same as the first angle α. Considering the influence of factors such as process error, there will be a certain error between the second angle β and the first angle α. If the difference between the two is within the error range, it can be considered that the second angle β and the first angle α are the same. When the second non-display area 22 is tilted, the first control circuit 31, the second control circuit 32, and the corresponding control lines are also tilted to match the second non-display area 22. This can further reduce the space occupied by the first control circuit 31 and the second control circuit 32 in the second non-display area 22, thereby further reducing the width of the second non-display area 22.

[0070] Optionally, when the number of first pixel rows 10 in the first display area 11 is greater than or equal to a first preset threshold, the first non-display area 21 and the fourth non-display area 24 include a first control circuit 31, and the second non-display area 22, the third non-display area 23 and the fourth non-display area 24 include a second control circuit 32; or, the second non-display area 22 and the fourth non-display area 24 include a first control circuit 31, and the first non-display area 21, the third non-display area 23 and the fourth non-display area 24 include a second control circuit 32; or, the third non-display area 23 and the fourth non-display area 24 include a first control circuit 31, and the first non-display area 21, the second non-display area 22 and the fourth non-display area 24 include a second control circuit 32.

[0071] When there are many pixel rows in the first display area 11, it means that there are also many first control circuits 31 and second control circuits 32 connected to the pixel rows. Therefore, it is necessary to use the first non-display area 21, the third non-display area 23 and the second non-display area 22 to share the first control circuit 31 and the second control circuit 32 that need to be set, thereby reducing the width difference of the border of the irregular area in the display panel, further improving the consistency of the border of the irregular area, and further improving the visual experience of the user.

[0072] Specifically, in order to facilitate the routing of control lines, such as Figure 5As shown, when the number of first pixel rows 10 in the first display area 11 is greater than or equal to a first preset threshold, optionally, the second non-display area 22 and the fourth non-display area 24 include a first control circuit 31, and the first non-display area 21, the third non-display area 23, and the fourth non-display area 24 include a second control circuit 32. A portion of the first control circuit 31 is disposed in the fourth non-display area 24, and the other portion is entirely disposed in the second non-display area 22. The first control line SL1 can be routed in a conventional manner (i.e., the manner in which it is routed to the first control circuit 31 located in the second non-display area 22). For the above embodiment, only the routing of the second control line SL2 to the second control circuit 32 needs to be changed.

[0073] Optionally, when the number of first pixel rows 10 in the first display area 11 is less than a first preset threshold, the first non-display area 21 and the fourth non-display area 24 include a first control circuit 31, the fourth non-display area 24 includes a second control circuit 32, and the second non-display area 22 or the third non-display area 23 includes a second control circuit 32; or, the second non-display area 22 and the fourth non-display area 24 include a first control circuit 31, the fourth non-display area 24 includes a second control circuit 32, and the first non-display area 21 or the third non-display area 23 includes a second control circuit 32; or, the third non-display area 23 and the fourth non-display area 24 include a first control circuit 31, the fourth non-display area 24 includes a second control circuit 32, and the first non-display area 21 or the second non-display area 22 includes a second control circuit 32.

[0074] When the number of pixel rows in the first display area 11 is small, it means that the number of first control circuits 31 and second control circuits 32 connected to the pixel rows is also small. Therefore, the first control circuit 31 and second control circuit 32 that need to be set can be shared by the three non-display areas at the same time, thereby reducing the width difference of the border of irregular areas in the display panel and simplifying the wiring.

[0075] Specifically, in order to facilitate the routing of control lines, such as Figure 6 or Figure 7As shown, when the number of first pixel rows 10 in the first display area 11 is less than a first preset threshold, optionally, the second non-display area 22 and the fourth non-display area 24 include a first control circuit 31, the fourth non-display area 24 includes a second control circuit 32, and the first non-display area 21 or the third non-display area 23 includes a second control circuit 32. A portion of the first control circuit 31 is disposed in the fourth non-display area 24, and the other portion is entirely disposed in the second non-display area 22. The first control line SL1 can be routed in a conventional manner (i.e., the manner in which it is routed to the first control circuit 31 located in the second non-display area 22). For the above embodiment, only the routing of the second control line SL2 to the second control circuit 32 needs to be changed.

[0076] The purpose of setting the first preset threshold is only to distinguish the number of pixel rows in the first display area 11 and to provide different implementation methods based on the number of pixel rows in the first display area 11. The specific value of the first preset threshold is not limited here.

[0077] Optionally, the second display area 12 includes a second pixel row 20, the first control circuit 31 is a scanning control circuit, and the second control circuit 32 is an emission control circuit.

[0078] The ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is greater than a second preset threshold, and the number of second control lines SL2 connected to a second control circuit 32 is greater than or equal to a third preset threshold.

[0079] like Figure 8 As shown, a pixel includes a pixel circuit and a light-emitting element (OLED, Organic Light-Emitting Diode). The pixel circuit includes a driving transistor M1, a threshold compensation transistor M4, and light-emitting control transistors M2 and M3. The driving transistor M1 provides a driving signal to the light-emitting element, and the light-emitting control transistors M2 and M3 transmit the driving signal to the light-emitting element. The first terminal of the threshold compensation transistor M4 is connected to the second terminal of the driving transistor M1, and the second terminal of the threshold compensation transistor M4 is connected to the gate of the driving transistor M1. The threshold compensation transistor M4 provides threshold compensation for the driving transistor M1 by providing the voltage from the first terminal of the driving transistor M1 to the gate. Specifically, the pixel circuit also includes a storage capacitor Cst.

[0080] Specifically, the scan control circuit described above provides a scan signal SP to turn the threshold compensation transistor M4 on or off, and the emission control circuit described above provides an emission signal EM to turn the light-emitting control transistors M2 and M3 on or off. If the driving capability of the scan signal SP is insufficient, the driving transistor M1 cannot obtain sufficient threshold compensation, which will affect the subsequent provision of driving signals to the light-emitting element OLED. Therefore, the scan driving circuit that provides the scan signal SP has a high driving capability requirement. So, if the ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is large, it means that the number of pixels in the first pixel row 10 needs to be driven is large, and the scan signal SP needs to be provided through bilateral driving. The emission signal EM is used to enable the power supply signal VDD to be provided to the driving transistor M1 and to enable the driving signal to be provided to the light-emitting element OLED. The driving capability requirement is not high. Therefore, when a set of emission control circuits needs to drive multiple rows of pixels, the emission signal EM can be provided through bilateral driving.

[0081] Specifically, Figure 8 The transistors shown are all P-type transistors, which can be LTPS (Low Temperature Poly-Silicon) transistors. In specific implementations, Figure 8 The transistors in the transistors can be partially or completely replaced with N-type transistors, and can be IGZO (Indium Gallium Zinc Oxide) transistors.

[0082] Optionally, when the pixel circuit includes an N-type transistor and the gate of the N-type transistor is electrically connected to the drive transistor M1, the first control circuit 31 can be a circuit for controlling the N-type transistor, and the second control circuit 32 can be an emission control circuit. In this case, the first control line can be set to double-sided driving, and the second control line can be set to single-sided driving. That is, both the first and second ends of the first control line are electrically connected to the first control circuit 31, and the first control circuit 31 electrically connected to the first end of the first control line is located in the fourth non-display area. The first control circuit 31 electrically connected to the second end of the first control line can be located in the first non-display area, the second non-display area, or the third non-display area. The first end of the second control line is electrically connected to the second control circuit 32, and the second control circuit 32 is located in the fourth non-display area.

[0083] To further illustrate the pixel circuit in the above embodiments, Figure 9 and Figure 10 The pixel circuits and light-emitting elements in two more specific implementations are given respectively. Specifically, Figure 9In this embodiment, the pixel circuit includes a driving transistor T1, a threshold compensation transistor T4, light-emitting control transistors T2 and T3, a data writing transistor T5, a reset transistor T7 and T6, and a storage capacitor Cst. The functions of the driving transistor T1, threshold compensation transistor T4, light-emitting control transistors T2 and T3, and storage capacitor Cst in the circuit can be found in [reference needed]. Figure 8 In this implementation, the driving transistor M1, threshold compensation transistor M4, light-emitting control transistors M2 and M3, and data writing transistor T5 are used to write the data signal Vdata to the driving transistor T1. The reset transistor T7 is used to reset the gate voltage of the driving transistor T1, and the reset transistor T6 is used to reset the anode voltage of the LED. Specifically, Figure 9 The transistor in the illustrated embodiment can be an LTPS transistor.

[0084] Specifically, Figure 10 In this embodiment, the pixel circuit includes a driving transistor T8, a threshold compensation transistor T11, light-emitting control transistors T9 and T10, a data writing transistor T12, a reset transistor T13 and T14, a storage capacitor Cst, and a capacitor C1. The functions of the driving transistor T8, threshold compensation transistor T11, light-emitting control transistors T9 and T10, and storage capacitor Cst in the circuit can be found in [reference needed]. Figure 8 The functions of the driving transistor M1, threshold compensation transistor M4, light-emitting control transistors M2 and M3, data writing transistor T12, and reset transistors T13 and T14 in the implementation embodiment can be found in the following reference: Figure 9 The implementation method uses data writing transistor T5, reset transistors T7 and T6. Specifically, Figure 10 The transistor in the illustrated embodiment can be an IGZO transistor.

[0085] Optionally, the range of the second preset threshold k is 0.4≤k≤0.6, or k=0.5. The second preset threshold in the following embodiments is similar and will not be repeated.

[0086] Optionally, the range of the third preset threshold l is 3≤l≤5, or l=4. The third preset threshold in the following embodiments is similar and will not be repeated.

[0087] Optionally, the second display area 12 includes a second pixel row 20, the first control circuit 31 is an emission control circuit, and the second control circuit 32 is a scanning control circuit. The ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is greater than a second preset threshold, and the number of first control lines SL1 connected to one of the first control circuits 31 is greater than or equal to a third preset threshold.

[0088] Optionally, such as Figure 11As shown, the display panel also includes a fourth non-display area 24, which is located on the side of the first display area 11 away from the second non-display area 22 along the first direction X.

[0089] The display panel also includes a first control circuit 31, a second control circuit 32, a first control line SL1, and a second control line SL2. The first display area 11 includes a first pixel row 10 extending along a first direction X. The first control line SL1 is electrically connected to the pixels in the first pixel row 10, and a first end of the first control line SL1 is electrically connected to the first control circuit 31, while a second end of the first control line SL1 is electrically connected to another first control circuit 31. The second control line SL2 is electrically connected to the pixels in the first pixel row 10, and one end of the second control line SL2 is electrically connected to the second control circuit 32. The first control line SL1 and the second control line SL2 connect to different transistors in the same pixel, wherein:

[0090] The second non-display area 22 includes a first control circuit 31, and the fourth non-display area 24 includes the first control circuit 31 and the second control circuit 32.

[0091] Specifically, Figure 11 The second control line SL2 shown is connected to only one second control circuit 32. That is, one control circuit transmits control signals from one end of the control line to the control line, thereby providing control signals for a row of pixels. This control method is single-sided drive control. Although single-sided drive cannot improve the transmission effect of the second control line SL2, when the pixel does not have high requirements for driving capability, single-sided drive can save the area of ​​the border area occupied by the control circuit while meeting the driving requirements. When the second control circuit 32 is single-sided drive, in order to reduce the area of ​​the irregular border area occupied by the control circuit, the second control circuit 32 is only set in the fourth non-display area 24. At the same time, in order to facilitate the routing of control lines, the first control circuit 31 of the double-sided drive is directly set in the second non-display area 22 opposite to the fourth non-display area 24.

[0092] Optionally, the second display area 12 includes a second pixel row 20, the first control circuit 31 is a scanning control circuit, and the second control circuit 32 is an emission control circuit.

[0093] The ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is greater than a second preset threshold, and the number of second control lines SL2 connected to a second control circuit 32 is less than a third preset threshold.

[0094] If the ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is large, it means that the first pixel row 10 needs to drive a large number of pixels, and the scanning signal SP needs to be provided by bilateral driving. When a set of emission control circuits does not need to drive multiple rows of pixels, in order to reduce the border area and save manufacturing costs, the emission signal EM can be provided by single-sided driving.

[0095] Optionally, the second display area 12 includes a second pixel row 20, the first control circuit 31 is an emission control circuit, and the second control circuit 32 is a scanning control circuit. The ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is greater than a second preset threshold, and the number of first control lines SL1 connected to one of the first control circuits 31 is less than a third preset threshold.

[0096] Optionally, such as Figure 12 As shown, the display panel also includes a fourth non-display area 24, which is located on the side of the first display area 11 away from the second non-display area 22 along the first direction X.

[0097] The display panel also includes a first control circuit 31, a second control circuit 32, a first control line SL1, and a second control line SL2. The first display area 11 includes a first pixel row 10 extending along a first direction X. The first control line SL1 is electrically connected to the pixels in the first pixel row 10, and one end of the first control line SL1 is electrically connected to the first control circuit 31. The second control line SL2 is electrically connected to the pixels in the first pixel row 10, and one end of the second control line SL2 is electrically connected to the second control circuit 32. The first control line SL1 and the second control line SL2 connect to different transistors in the same pixel, wherein:

[0098] The fourth non-display area 24 includes a first control circuit 31 and a second control circuit 32.

[0099] Specifically, Figure 12 The first control line SL1 shown is connected to only one first control circuit 31, and the second control line SL2 is connected to only one second control circuit 32. In order to avoid the control circuits occupying the area of ​​the irregular area border, the first control circuit 31 and the second control circuit 32 are only located in the fourth non-display area 24.

[0100] Optionally, the second display area 12 includes a second pixel row 20, the first control circuit 31 is a scanning control circuit, and the second control circuit 32 is a transmission control circuit; or, the first control circuit 31 is a transmission control circuit and the second control circuit 32 is a scanning control circuit.

[0101] The ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is less than or equal to a second preset threshold, and the number of second control lines SL2 connected to a second control circuit 32 is less than a third preset threshold.

[0102] If the ratio of the number of pixels in the first pixel row 10 to the number of pixels in the second pixel row 20 is small, it means that the number of pixels that need to be driven in the first pixel row 10 is small. In order to reduce the border area and save manufacturing costs, the above scanning signal SP can be provided by single-sided driving. When a set of emission control circuits does not need to drive multiple rows of pixels, in order to reduce the border area and save manufacturing costs, the above emission signal EM can be provided by single-sided driving.

[0103] Optionally, the aforementioned display panel also includes cathode signal lines located in the non-display area. Figure 13 The diagram shows a partial cross-sectional structure of the display panel, in which the cathode signal line 201 and the pixel cathode 202 are disposed on different layers, and the cathode signal line 201 and the pixel cathode 202 are electrically connected. Specifically, the cathode signal line 201 is electrically connected to the pixel cathode 202 through a metal layer 203, which can be a connecting line on the same layer as the pixel anode.

[0104] The first non-display area 21 and the third non-display area 23 include cathode signal lines, while the second non-display area 22 does not include cathode signal lines.

[0105] Related technologies involve laying cathode signal lines in the non-display area of ​​the display panel and providing cathode voltage (PVEE) to the cathode in the pixel through these lines. Typically, the cathode signal lines are relatively wide, thus occupying a portion of the non-display area. By eliminating the cathode signal lines in the second non-display area 22, the reduction in... Figure 1 The bezel area between the display screen 1 and the camera 2 shown in the diagram avoids a noticeable dividing line between them, thus improving the user's visual experience. Furthermore, since the first non-display area 21 and the third non-display area 23 have conventionally laid cathode signal lines, and specifically, the fourth non-display area 24 also has conventionally laid cathode signal lines, the cathode voltage PVEE can be transmitted to the cathode of each pixel in the first display area 11 through the first non-display area 21, the third non-display area 23, and the fourth non-display area 24. Therefore, removing some cathode signal lines will not significantly affect the cathode voltage VSS drop.

[0106] Specifically, such as Figure 13As shown, the display panel further includes an electrical insulating layer 204, a substrate 205, a first insulating layer 206, a second insulating layer 207, a third insulating layer 208, a pixel definition layer 209, a common electrode layer 210, an inorganic insulating layer 211, an organic insulating layer 212, an encapsulation film 213, a control signal line 214, a device metal layer 215, and a support pillar structure 216. The cathode 202 of the pixel is electrically connected to the metal layer 203 through a via 220 on the pixel definition layer 209, thereby being electrically connected to the cathode signal line 201. The materials of the first insulating layer 206, the second insulating layer 207, and the third insulating layer 208 can be organic or inorganic insulating materials. The first insulating layer 206 can be a gate insulating layer GI, an interlayer dielectric insulating layer IMD and / or an interlayer dielectric layer ILD, the second insulating layer 207 can be a passivation layer PV and a protective adhesive layer BPL, the third insulating layer 208 can be a planarization layer PLN, the inorganic insulating layer 211 can be a chemical vapor deposition layer CVD, and the inorganic insulating layer 212 can be an organic layer IJP. Figure 13 Only structures relevant to the inventive concept of this disclosure are shown; the aforementioned display panel may also include... Figure 13 Other membrane structures, not shown, will not be described in detail.

[0107] Optionally, the first non-display area 21, the second non-display area 22, and the third non-display area 23 all include cathode signal lines, such as... Figure 11 As shown, the cathode signal line 201 and the pixel cathode 202 are disposed in different layers, and the cathode signal line 201 and the pixel cathode 202 are electrically connected. Specifically, the cathode signal line 201 is electrically connected to the pixel cathode 202 through the metal layer 203.

[0108] The width of the cathode signal line in the first non-display area 21 is H1, the width of the cathode signal line in the second non-display area 22 is H2, and the width of the cathode signal line in the third non-display area 23 is H3, wherein H2 < H1 and H2 < H3.

[0109] Related technologies involve laying cathode signal lines in the non-display area of ​​the display panel and providing a cathode voltage VSS to the cathode in the pixel through these lines. Consequently, the cathode signal lines occupy a portion of the non-display area. By reducing the width of the cathode signal lines in the second non-display area 22, it is possible to reduce... Figure 1 The bezel area between the display screen 1 and the camera 2 shown in the figure avoids a clear dividing line between the display screen 1 and the camera 2 to a certain extent, thereby improving the user's visual experience.

[0110] Optionally, such as Figure 14As shown, the display panel also includes a first control circuit 31, a second control circuit 32, a third control circuit 33, a fourth control circuit 34, a first control line SL1, a second control line SL2, a third control line SL3, and a fourth control line SL4, as follows. Figure 14 As shown, the first control circuit 31 transmits signal STV1 in a cascaded manner, the second control circuit 32 transmits signal STV2 in a cascaded manner, the third control circuit 33 transmits signal STV3 in a cascaded manner, and the fourth control circuit 34 transmits signal STV4 in a cascaded manner, wherein:

[0111] The first display area 11 includes a first pixel row 10 extending along a first direction X. A first control line SL1 is electrically connected to the pixels in the first pixel row 10 and is also electrically connected to at least one first control circuit 31. A second control line SL2 is electrically connected to the pixels in the first pixel row 10 and is also electrically connected to at least one second control circuit 32. The second display area 12 includes a second pixel row 20 extending along a first direction X. A third control line SL3 is electrically connected to the pixels in the second pixel row 20 and is also electrically connected to at least one third control circuit 33. A fourth control line SL4 is electrically connected to the pixels in the second pixel row 20 and is also electrically connected to at least one fourth control circuit 34.

[0112] like Figure 8 As shown, a pixel includes a pixel circuit and an OLED light-emitting element. The pixel circuit includes a driving transistor M1, a threshold compensation transistor M4, and light-emitting control transistors M2 and M3. The driving transistor M1 provides a driving signal to the light-emitting element, and the light-emitting control transistors M2 and M3 transmit the driving signal to the light-emitting element. The first terminal of the threshold compensation transistor M4 is connected to the second terminal of the driving transistor M1, and the second terminal of the threshold compensation transistor M4 is connected to the gate of the driving transistor M1. The threshold compensation transistor M4 provides threshold compensation for the driving transistor M1 by providing the voltage of the first terminal of the driving transistor M1 to the gate.

[0113] The first control line SL1 is connected to the gate of the threshold compensation transistor M4 of the pixel in the first pixel row 10. The second control line SL2 is connected to the gate of the light emission control transistors M2 and M3 in the first pixel row 10. The third control line SL3 is connected to the gate of the threshold compensation transistor M4 of the pixel in the second pixel row 20. The fourth control line SL4 is connected to the gate of the light emission control transistors M2 and M3 in the second pixel row 20.

[0114] There is a gap between the orthographic projection of the first control circuit 31 on the substrate and the orthographic projection of the third control circuit 33 on the substrate; there is a gap between the orthographic projection of the second control circuit 32 on the substrate and the orthographic projection of the fourth control circuit 34 on the substrate.

[0115] When the pixels in the display panel are working, there are scanning and light-emitting phases. The scanning phase includes the process of using the threshold compensation transistor M4 to provide threshold compensation for the driving transistor M1 in the above embodiment. The light-emitting phase includes the process of using the driving transistor M1 to provide a driving signal to the light-emitting element, and using the light-emitting control transistors M2 and M3 to transmit the driving signal to the light-emitting element. The pixel completes the display of one frame after one scanning phase and one light-emitting phase. In the above embodiments, the first display area 11 and the second display area 12 are controlled by a first control circuit 31, a second control circuit 32, a third control circuit 33, and a fourth control circuit 34, respectively. Furthermore, there is a gap between the orthographic projection of the first control circuit 31 / second control circuit 32 on the substrate and the orthographic projection of the third control circuit 33 / fourth control circuit 34 on the substrate, indicating that the first control circuit 31 / second control circuit 32 and the third control circuit 33 / fourth control circuit 34 are not cascaded. There are no signal lines directly connecting the first control circuit 31 and the third control circuit 33, nor are there signal lines directly connecting the second control circuit 32 and the fourth control circuit 34. That is, the pixels in the first display area 11 and the pixels in the second display area 12 can be driven and controlled separately to display different images, thereby improving the flexibility of the display panel.

[0116] Optionally, when the first control circuit 31 and the second control circuit 32 control the first display area 11 to display a preset image, the third control circuit 33 and the fourth control circuit 34 control the second display area 12 to turn off the screen.

[0117] In practice, by controlling the first display area 11 and the second display area 12 separately, UI icons such as time, battery level, and network status can be displayed in the first display area 11 when the second display area 12 is off. This fully utilizes the information displayed on the screen, and by controlling the pixels in areas that do not need to be displayed to not receive the control signals transmitted by the corresponding control lines, the screen in areas that do not need to be displayed can be turned off, thus achieving energy saving.

[0118] Specifically, the aforementioned display panel also includes a master control circuit (not shown in the accompanying drawings). The master control circuit is electrically connected to the first control circuit 31, the second control circuit 32, the third control circuit 33, and / or the fourth control circuit 34 in the above embodiments via signal lines, and provides a control signal Vcontrol to the first control circuit 31, the second control circuit 32, the third control circuit 33, and / or the fourth control circuit 34. The first control circuit 31, the second control circuit 32, the third control circuit 33, and / or the fourth control circuit 34 provide control signals to the first pixel row 10 and the second pixel row 20 in response to the control signal Vcontrol.

[0119] Specifically, the aforementioned display panel also includes dummy pixels. Dummy pixels are typically located around regular pixels, and their internal circuitry is identical to that of regular pixels. They serve only to match the regular pixels. For example, dummy pixels can be used to generate the reference voltage required by regular pixels, thus eliminating the need for a separate reference voltage generation circuit that occupies the area of ​​the display panel.

[0120] Based on the same inventive concept, corresponding to the display panel in any of the above embodiments, one embodiment of this application also provides a display device, which includes the display panel in any of the above embodiments.

[0121] The aforementioned display device can be installed in an electronic device, for example... Figure 1 The folding electronic device shown, or other electronic devices that can utilize irregularly shaped display panels.

[0122] The display device of the above embodiments includes the corresponding display panel in any of the foregoing embodiments and has the beneficial effects of the corresponding embodiments, which will not be repeated here.

[0123] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

[0124] The foregoing description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described above, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, The display panel includes a first display area, a second display area, a first non-display area, a second non-display area, a third non-display area, multiple pixels, and cathode signal lines, wherein: The cathode signal line is disposed in a different layer from the cathode of the pixel, and the cathode signal line is electrically connected to the cathode of the pixel; The length of the first display area in the first direction is less than the length of the second display area in the first direction, and the first display area is adjacent to the second display area; Along the second direction, the first non-display area is located on the side of the first display area away from the second display area; along the first direction, the second non-display area is located on one side of the first display area, the second non-display area is located between the first non-display area and the third non-display area, and the second non-display area is adjacent to the first non-display area and the third non-display area; along the second direction, the third non-display area is located on the side of the second display area closer to the first display area, and the first direction intersects the second direction; The width of the first non-display area is a, the width of the second non-display area is b, the width of the third non-display area is c, and the preset difference is m, where |ab|≤m, |cb|≤m, and |ac|≤m; The first non-display area and the third non-display area include the cathode signal line, while the second non-display area does not include the cathode signal line; or, The first non-display area, the second non-display area, and the third non-display area all include cathode signal lines. The width of the cathode signal line in the first non-display area is H1, the width of the cathode signal line in the second non-display area is H2, and the width of the cathode signal line in the third non-display area is H3, wherein H2 < H1 and H2 < H3.

2. The display panel according to claim 1, characterized in that, The widths of the first non-display area, the second non-display area, and the third non-display area are all less than the preset width W.

3. The display panel according to claim 1, characterized in that, The range of the preset difference m is 0.08mm ≤ m ≤ 0.12mm.

4. The display panel according to claim 2, characterized in that, The preset width W is in the range of 1.4mm ≤ W ≤ 1.6mm.

5. The display panel according to claim 1, characterized in that, The display panel further includes a fourth non-display area, which is located on the side of the first display area away from the second non-display area along the first direction; The display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line. The first display area includes a first pixel row extending along a first direction. The first control line is electrically connected to a pixel in the first pixel row, and a first end of the first control line is electrically connected to the first control circuit, and a second end of the first control line is electrically connected to another first control circuit. The second control line is electrically connected to a pixel in the first pixel row, and a first end of the second control line is electrically connected to the second control circuit, and a second end of the second control line is electrically connected to another second control circuit. The first control line and the second control line connect to different transistors in the same pixel, wherein: The fourth non-display area includes the first control circuit and the second control circuit; At least one of the first non-display area, the second non-display area, and the third non-display area includes the first control circuit, and / or at least one of the first non-display area, the second non-display area, and the third non-display area includes the second control circuit.

6. The display panel according to claim 5, characterized in that, The number of the first pixel rows in the first display area is greater than or equal to a first preset threshold; The first non-display area and the fourth non-display area include the first control circuit, and the second non-display area, the third non-display area, and the fourth non-display area include the second control circuit; or, The second non-display area and the fourth non-display area include the first control circuit, and the first non-display area, the third non-display area, and the fourth non-display area include the second control circuit; or, The third non-display area and the fourth non-display area include the first control circuit, and the first non-display area, the second non-display area and the fourth non-display area include the second control circuit.

7. The display panel according to claim 5, characterized in that, The number of the first pixel rows in the first display area is less than a first preset threshold; The first non-display area and the fourth non-display area include the first control circuit, the fourth non-display area includes the second control circuit, and the second non-display area or the third non-display area includes the second control circuit; or, The second non-display area and the fourth non-display area include the first control circuit, the fourth non-display area includes the second control circuit, and the first non-display area or the third non-display area includes the second control circuit; or, The third non-display area and the fourth non-display area include the first control circuit, the fourth non-display area includes the second control circuit, and the first non-display area or the second non-display area includes the second control circuit.

8. The display panel according to claim 5, characterized in that, The first non-display area or the third non-display area includes the first control circuit; The first control line includes a first control line segment located in the first display area and a second control line segment electrically connected to the first control line segment. The first control line segment and the second control line segment extend in opposite directions. The second control line segment is connected in series between the first control line segment and the first control circuit located in the first non-display area or the third non-display area; or... The first non-display area or the third non-display area includes the second control circuit; The second control line includes a third control line segment located in the first display area and a fourth control line segment electrically connected to the third control line segment. The third control line segment and the fourth control line segment extend in opposite directions. The fourth control line segment is connected in series between the third control line segment and the second control circuit located in the first non-display area or the third non-display area.

9. The display panel according to claim 5, characterized in that, The second display area includes a second pixel row, the first control circuit is a scanning control circuit, and the second control circuit is an emission control circuit; The ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is greater than a second preset threshold, and the number of second control lines connected to a second control circuit is greater than or equal to a third preset threshold.

10. The display panel according to claim 1, characterized in that, The display panel further includes a fourth non-display area, which is located on the side of the first display area away from the second non-display area along the first direction; The display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line. The first display area includes a first pixel row extending along a first direction. The first control line is electrically connected to a pixel in the first pixel row, and a first end of the first control line is electrically connected to the first control circuit, and a second end of the first control line is electrically connected to another first control circuit. The second control line is electrically connected to a pixel in the first pixel row, and one end of the second control line is electrically connected to the second control circuit. The first control line and the second control line connect to different transistors in the same pixel, wherein: The second non-display area includes the first control circuit, and the fourth non-display area includes the first control circuit and the second control circuit.

11. The display panel according to claim 10, characterized in that, The second display area includes a second pixel row, the first control circuit is a scanning control circuit, and the second control circuit is an emission control circuit; The ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is greater than a second preset threshold, and the number of second control lines connected to one of the second control circuits is less than a third preset threshold.

12. The display panel according to claim 1, characterized in that, The display panel further includes a fourth non-display area, which is located on the side of the first display area away from the second non-display area along the first direction; The display panel further includes a first control circuit, a second control circuit, a first control line, and a second control line. The first display area includes a first pixel row extending along a first direction. The first control line is electrically connected to a pixel in the first pixel row, and one end of the first control line is electrically connected to the first control circuit. The second control line is electrically connected to a pixel in the first pixel row, and one end of the second control line is electrically connected to the second control circuit. The first control line and the second control line are connected to different transistors in the same pixel, wherein: The fourth non-display area includes the first control circuit and the second control circuit.

13. The display panel according to claim 12, characterized in that, The second display area includes a second pixel row; The first control circuit is a scanning control circuit, and the second control circuit is a transmission control circuit; or, the first control circuit is a transmission control circuit, and the second control circuit is a scanning control circuit. The ratio of the number of pixels in the first pixel row to the number of pixels in the second pixel row is less than or equal to a second preset threshold, and the number of second control lines connected to a second control circuit is less than a third preset threshold.

14. The display panel according to any one of claims 9, 11, or 13, characterized in that, The range of the second preset threshold k is 0.4≤k≤0.

6.

15. The display panel according to any one of claims 9, 11, or 13, characterized in that, The range of the third preset threshold l is 3≤l≤5.

16. The display panel according to claim 1, characterized in that, The display panel further includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, a first control line, a second control line, a third control line, and a fourth control line, wherein: The first display area includes a first pixel row extending along a first direction, the first control line is electrically connected to the pixels in the first pixel row, and the first control line is electrically connected to at least one first control circuit, the second control line is electrically connected to the pixels in the first pixel row, and the second control line is electrically connected to at least one second control circuit; The second display area includes a second pixel row extending along the first direction, the third control line is electrically connected to the pixels in the second pixel row and is electrically connected to at least one of the third control circuits, the fourth control line is electrically connected to the pixels in the second pixel row and is electrically connected to at least one of the fourth control circuits; The pixel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor, a threshold compensation transistor, and a light-emitting control transistor. The driving transistor provides a driving signal to the light-emitting element, and the light-emitting control transistor transmits the driving signal to the light-emitting element. The first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor. The first control line is connected to the gate of the threshold compensation transistor of the pixel in the first pixel row, and the second control line is connected to the gate of the light emission control transistor in the first pixel row. The third control line is connected to the gate of the threshold compensation transistor of the pixel in the second pixel row, and the fourth control line is connected to the gate of the light emission control transistor in the second pixel row. There is a gap between the orthographic projection of the first control circuit on the substrate and the orthographic projection of the third control circuit on the substrate; There is a gap between the orthographic projection of the second control circuit on the substrate and the orthographic projection of the fourth control circuit on the substrate.

17. The display panel according to claim 16, characterized in that, When the first control circuit and the second control circuit control the first display area to display a preset image, the third control circuit and the fourth control circuit control the second display area to turn off the screen.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

Images