Method, system, and electronic device for handling interrupts and storage medium

Abstract

Embodiments of the present application provide a kind of interrupt processing method, system and electronic equipment and storage medium, wherein the method comprises: monitoring target interrupt derived from network card;Get the first quantity of current unprocessed target interrupt, the second quantity of CPU core currently used to process target interrupt and the total quantity of CPU core in virtual machine;According to the first quantity, the second quantity and the total quantity, CPU core is scheduled, and the current unprocessed target interrupt is processed using the CPU core after scheduling.The embodiments of the present application improve load balancing, reduce network delay, improve system throughput and dynamic adaptation capability, etc., can optimize interrupt processing process, improve system performance and network reliability.

Description

Technical Field

[0001] This invention relates to the field of cloud computing technology, and in particular to an interrupt handling method, an interrupt handling system, an electronic device, and a computer-readable storage medium. Background Technology

[0002] With the rapid development of Internet technology, cloud computing has become an indispensable and important technology. Virtualization technology in cloud computing breaks through the boundaries of time and space, allowing it to penetrate into various application scenarios.

[0003] Software Defined Wide Area Network (SDWAN), as a typical key enterprise-level service of Communications Technology (CT) cloud, places high demands on the cloud's network processing capabilities. In the conventional configuration of cloud resource pools, network card interrupts are handled by the Central Processing Unit (CPU) core 0 (the first logical core of the CPU) by default. For CT cloud SDWAN services, the network performance provided by the network card depends entirely on the CPU's processing power, thus placing high demands on the CPU.

[0004] When there are many interrupts originating from the network card, all of these interrupts need to be processed by CPU0 core. At this time, CPU0 core has a high load, causing interrupts to remain unprocessed for extended periods, resulting in network latency and even packet loss. Meanwhile, other CPU cores may be idle, leading to inefficient resource allocation. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide an interrupt handling method, an interrupt handling system, an electronic device, and a computer-readable storage medium that overcome or at least partially solve the above problems.

[0006] To address the aforementioned issues, this invention discloses an interrupt handling method, comprising: detecting a target interrupt originating from a network interface card; obtaining a first number of currently unprocessed target interrupts, a second number of CPU cores currently used to process the target interrupts, and the total number of CPU cores within a virtual machine; scheduling CPU cores according to the first number, the second number, and the total number, and using the scheduled CPU cores to process the currently unprocessed target interrupts.

[0007] Optionally, scheduling CPU cores based on the first quantity, the second quantity, and the total quantity includes: when the first quantity is less than the second quantity, obtaining latency data of the network card and scheduling CPU cores based on the latency data; when the first quantity is greater than or equal to the second quantity, if the second quantity is equal to the total quantity, obtaining latency data of the network card and scheduling CPU cores based on the latency data; when the first quantity is greater than or equal to the second quantity, if the second quantity is less than the total quantity, obtaining packet loss data of the network card and adjusting the second quantity based on the packet loss data.

[0008] Optionally, scheduling CPU cores based on the latency data includes: if the latency data does not meet a preset first service requirement, obtaining the utilization rate of each CPU core in the virtual machine; and scheduling the CPU cores based on each utilization rate.

[0009] Optionally, scheduling CPU cores based on each utilization rate includes: selecting the lowest utilization rate from the various utilization rates; if the lowest utilization rate is greater than or equal to a first threshold, keeping the second number unchanged; if the lowest utilization rate is less than the first threshold, selecting at least one CPU core with a utilization rate less than a second threshold from the various CPU cores, where the first threshold is greater than the second threshold; and using the selected at least one CPU core to cancel the processing of bound target interrupts and process target interrupts waiting to be bound to CPU cores.

[0010] Optionally, the process of handling target interrupts waiting to be bound to CPU cores includes: rebinding the target interrupt with the longest waiting time to be bound to a selected CPU core, and using the selected CPU core to process the newly bound target interrupt.

[0011] Optionally, adjusting the second quantity based on the packet loss data includes: adjusting the second quantity if the packet loss data does not meet a preset second service requirement.

[0012] Optionally, adjusting the second quantity includes: if the difference between the first quantity and the second quantity is less than the difference between the total quantity and the second quantity, then adjusting the second quantity to the first quantity; if the difference between the first quantity and the second quantity is greater than or equal to the difference between the total quantity and the second quantity, then adjusting the second quantity to the total quantity.

[0013] Optionally, the method further includes: if the first quantity is greater than the total quantity, and the utilization rate of the CPU core corresponding to the currently unprocessed target interrupt is greater than the third threshold for a first time period, then all CPU cores are used to prioritize processing the target interrupt with the shortest expected processing time or the least CPU usage among all current target interrupts.

[0014] This invention also discloses an interrupt handling system, comprising: an interrupt monitoring module for detecting target interrupts originating from a network interface card; a quantity acquisition module for acquiring a first quantity of currently unprocessed target interrupts, a second quantity of CPU cores currently used to process the target interrupts, and a total quantity of CPU cores within a virtual machine; and a CPU core scheduling module for scheduling CPU cores according to the first quantity, the second quantity, and the total quantity, and using the scheduled CPU cores to process the currently unprocessed target interrupts.

[0015] Optionally, the CPU core scheduling module includes: a core scheduling module, configured to acquire latency data of the network card and schedule CPU cores according to the latency data when the first quantity is less than the second quantity; the core scheduling module is further configured to acquire latency data of the network card and schedule CPU cores according to the latency data when the first quantity is greater than or equal to the second quantity and the second quantity is equal to the total quantity; and a second quantity adjustment module, configured to acquire packet loss data of the network card and adjust the second quantity according to the packet loss data when the first quantity is greater than or equal to the second quantity and the second quantity is less than the total quantity.

[0016] Optionally, the core scheduling module includes: a utilization acquisition module, used to acquire the utilization of each CPU core in the virtual machine if the latency data does not meet the preset first service requirement; and a scheduling module, used to schedule the CPU cores according to each utilization.

[0017] Optionally, the scheduling module includes: a utilization filtering module, configured to filter out the lowest utilization rate from the various utilization rates; a second quantity holding module, configured to keep the second quantity unchanged if the lowest utilization rate is greater than or equal to a first threshold; a core selection module, configured to select at least one CPU core with a utilization rate less than a second threshold from the various CPU cores if the lowest utilization rate is less than the first threshold, wherein the first threshold is greater than the second threshold; and a core processing module, configured to use the selected at least one CPU core to cancel the processing of bound target interrupts and process target interrupts waiting to be bound to CPU cores.

[0018] Optionally, the core processing module is used to re-bind the target interrupt with the longest waiting time to the selected CPU core to at least one selected CPU core, and use the selected at least one CPU core to process the newly bound target interrupt.

[0019] Optionally, the second quantity adjustment module is used to adjust the second quantity if the lost packet data does not meet the preset second service requirements.

[0020] Optionally, the second quantity adjustment module is configured to adjust the second quantity to the first quantity if the difference between the first quantity and the second quantity is less than the difference between the total quantity and the second quantity; and to adjust the second quantity to the total quantity if the difference between the first quantity and the second quantity is greater than or equal to the difference between the total quantity and the second quantity.

[0021] Optionally, the system further includes a priority processing module, configured to, if the first quantity is greater than the total quantity, and the utilization rate of the CPU core corresponding to the currently unprocessed target interrupt is greater than a third threshold for a first time period, then utilize all CPU cores to prioritize processing the target interrupt with the shortest expected processing time or the least CPU usage among all current target interrupts.

[0022] This invention also discloses an electronic device, including: one or more processors; and one or more machine-readable media storing instructions thereon, which, when executed by the one or more processors, cause the electronic device to perform the interrupt handling method as described above.

[0023] This invention also discloses a computer-readable storage medium storing a computer program that causes a processor to execute the interrupt handling method described above.

[0024] The embodiments of the present invention have the following advantages:

[0025] The interrupt handling scheme provided in this embodiment of the invention detects that the current interrupt is a target interrupt originating from the network card; obtains a first number of unprocessed target interrupts, a second number of CPU cores used to process the target interrupts, and a total number of CPU cores; and then schedules the CPU cores according to the first number, the second number, and the total number so as to use the scheduled CPU cores to process the unprocessed target interrupts.

[0026] This invention schedules CPU cores based on a first number, a second number, and a total number, distributing interrupt handling tasks to idle or low-load CPU cores to achieve load balancing. This avoids excessive load on CPU0 cores and effectively utilizes system resources. Because load balancing is achieved, all interrupts originating from the network card are no longer concentrated on CPU0 cores. Network card interrupts can be promptly allocated to suitable CPU cores, accelerating network card interrupt processing. This significantly reduces network latency, improves system response performance, and reduces the possibility of packet loss. By rationally scheduling CPU cores to handle interrupt tasks, system resources can be utilized more effectively, fully leveraging the parallel processing capabilities of multi-core processors. When some CPU cores are idle, they can take over handling some interrupt tasks, thereby improving system throughput and overall performance. The system can monitor and schedule interrupt load in real time, thus possessing dynamic adaptability. Whether the interrupt load is a sustained peak or a sudden increase, the system can adjust according to the current situation to maintain efficient interrupt handling capabilities. This dynamic adaptability makes the system more resilient and able to adapt to network traffic under different load conditions.

[0027] Overall, the embodiments of the present invention optimize the interrupt handling process and improve system performance and network reliability through improvements in load balancing, reducing network latency, increasing system throughput and dynamic adaptability. Attached Figure Description

[0028] Figure 1 This is a flowchart of the steps of an interrupt handling method according to an embodiment of the present invention;

[0029] Figure 2 This is a flowchart illustrating a solution for handling network card interruptions within a virtual machine according to an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram illustrating the processing interaction of a network card interrupt according to an embodiment of the present invention;

[0031] Figure 4 This is a structural block diagram of an interrupt handling system according to an embodiment of the present invention. Detailed Implementation

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] This invention aims to address the problem in the background art where network card interrupts are concentrated on CPU0 cores, leading to load imbalance, network latency, and packet loss. This invention achieves load balancing by real-time monitoring of interrupt sources and the number of unprocessed interrupts, and using scheduling strategies to distribute interrupt tasks to appropriate CPU cores. This allows network interrupts to be processed faster, reducing the risk of network latency and packet loss. Simultaneously, by fully utilizing idle CPU cores, this invention also improves system throughput and overall performance. Furthermore, it possesses dynamic adaptability, capable of adjusting scheduling strategies in real-time to adapt to network traffic under different load conditions. These improvements effectively optimize the interrupt handling process, enhancing system performance and network reliability.

[0034] Reference Figure 1 The diagram illustrates a flowchart of an interrupt handling method according to an embodiment of the present invention. The interrupt handling method specifically includes the following steps:

[0035] Step 101: A target interrupt originating from the network card was detected.

[0036] In embodiments of the present invention, interrupts originating from the network interface card (NIC) are monitored in real time or periodically. It should be noted that in these embodiments, interrupts originating from the NIC are referred to as NIC interrupts or target interrupts. When a target interrupt is detected, CPU core scheduling is performed for that interrupt. When no target interrupt is detected, or when a non-target interrupt is detected (e.g., a hardware interrupt from a peripheral device such as a keyboard or hard drive, or a software interrupt from a process or code), no further processing is performed.

[0037] In embodiments of the present invention, if a target interrupt is detected, CPU cores can be bound to the target interrupt sequentially according to a preset CPU core order, and a CPU core scheduling detection mechanism can be initiated simultaneously. Due to varying CPU core resource occupancy, processing capabilities, and network card interrupt handling difficulties, multiple network card interrupts may remain unprocessed. To expedite the processing of network card interrupts, a CPU core scheduling detection mechanism can be initiated upon detecting a network card interrupt. This eliminates the need for real-time monitoring of CPU core scheduling, reducing unnecessary waste of monitoring resources. Furthermore, initiating the CPU core scheduling detection mechanism upon receiving a new network card interrupt avoids the problem of highly unreasonable CPU core bindings between periodic monitoring sessions, which significantly increases the difficulty of CPU core scheduling.

[0038] Step 102: Obtain the first number of unprocessed target interrupts, the second number of CPU cores currently used to process target interrupts, and the total number of CPU cores in the virtual machine.

[0039] In embodiments of the present invention, the number of currently unprocessed target interrupts is referred to as the first quantity A, and the number of CPU cores currently used to process the target interrupts is referred to as the second quantity B. The currently unprocessed target interrupts may include, but are not limited to, network card interrupts that have just been assigned to CPU cores for processing, and network card interrupts that have been processed by CPU cores for a period of time but have not yet been completed. The CPU cores currently used to process the target interrupts are determined according to actual business needs, and are CPU cores assigned to network card interrupts and used to process network card interrupts.

[0040] In an embodiment of the present invention, the second quantity B has an initial value, which can be set according to actual business needs. After the CPU core scheduling detection mechanism is started, the second quantity B can be adjusted within the range of [0, C], where C represents the total number of CPU cores in the virtual machine.

[0041] Step 103: Schedule the CPU cores according to the first quantity, the second quantity and the total quantity, and use the scheduled CPU cores to process the target interrupts that have not yet been processed.

[0042] In embodiments of the present invention, a scheduling strategy can be formulated based on a first quantity, a second quantity, and a total quantity to determine how to allocate interrupt tasks to CPU cores. The specific strategy can be designed according to actual conditions; for example, algorithms such as round-robin, load balancing, or priority can be used. During the scheduling process, unprocessed target interrupt tasks are allocated to available CPU cores according to the scheduling strategy. This ensures that network card interrupts are processed in a distributed manner, avoiding excessive concentration on a single CPU core. The scheduled CPU cores will then process the interrupt tasks assigned to them, thereby improving overall processing efficiency.

[0043] The interrupt handling scheme provided in this embodiment of the invention detects a target interrupt originating from the network card; obtains a first number of currently unprocessed target interrupts, a second number of CPU cores currently used to process the target interrupts, and the total number of CPU cores in the virtual machine; and then schedules the CPU cores according to the first number, the second number, and the total number, and uses the scheduled CPU cores to process the currently unprocessed target interrupts.

[0044] This invention schedules CPU cores based on a first quantity, a second quantity, and a total quantity, distributing interrupt handling tasks to idle or low-load CPU cores to achieve load balancing. This avoids excessive load on CPU0 cores and effectively utilizes system resources. Because load balancing is achieved, all interrupts originating from the network card are no longer concentrated on CPU0 cores. Network card interrupts can be promptly allocated to suitable CPU cores, accelerating network card interrupt processing. This significantly reduces network latency, improves system response performance, and reduces the possibility of packet loss. By rationally scheduling CPU cores to handle interrupt tasks, system resources can be utilized more effectively, fully leveraging the parallel processing capabilities of multi-core processors. When some CPU cores are idle, they can take over handling some interrupt tasks, thereby improving system throughput and overall performance. The system can monitor and schedule interrupt load in real time, thus possessing dynamic adaptability. Whether the interrupt load is a sustained peak or a sudden increase, the system can adjust according to the current situation to maintain efficient interrupt handling capabilities. This dynamic adaptability makes the system more resilient and able to adapt to network traffic under different load conditions.

[0045] Overall, the embodiments of the present invention optimize the interrupt handling process and improve system performance and network reliability through improvements in load balancing, reducing network latency, increasing system throughput and dynamic adaptability.

[0046] In one exemplary embodiment of the present invention, one method of scheduling CPU cores based on a first quantity, a second quantity, and a total quantity is to compare the first quantity with the second quantity and schedule the CPU cores based on the comparison result between the first quantity and the second quantity.

[0047] (1) If the first quantity is less than the second quantity, obtain the network card's latency data and schedule the CPU cores according to the latency data.

[0048] The first quantity is less than the second quantity, meaning the number of currently unprocessed network interface card (NIC) interrupts is less than the number of CPU cores currently used to handle NIC interrupts. In this case, the number of CPU cores currently used to handle NIC interrupts is sufficient to provide processing services for the NIC interrupts. Therefore, it can be further determined whether the CPU cores associated with each NIC interrupt can efficiently handle the corresponding NIC interrupt. This is achieved by detecting the current latency data of the NIC to determine whether CPU core scheduling is necessary. Latency data typically refers to the time required for data transmission or processing in a network. It is obtained by measuring the transmission delay between the sender and receiver. Latency data can be used to evaluate network performance, monitor network congestion, and optimize the performance of network applications. Here are some common examples of latency data: Round-Trip Time (RTT): The time it takes for data to travel from the sender to the receiver and receive an acknowledgment signal. It is one of the most commonly used units of latency measurement and is typically used to evaluate network latency performance. Network Transmission Latency: The time required for data to travel in a network. It includes the transmission time from the sender to routers, switches, and other network devices, and the transmission time from these devices to the receiver. Network transmission latency is typically affected by factors such as network congestion, bandwidth limitations, and distance. Application latency refers to the time required for a specific application to process data. For example, in real-time audio and video calls, latency measures the time difference between sending audio and video data and the recipient playing it. Lower application latency is crucial for applications such as real-time communication, gaming, and streaming media. Processing latency refers to the time required for data to be processed on computing devices. It includes the time data is processed on the CPU, memory, and other hardware components. Processing latency is typically related to factors such as system load, processing power, and algorithm complexity. The specific types of latency data and their application areas vary. By measuring and analyzing latency data, network performance can be evaluated and optimized to provide a better user experience and system responsiveness.

[0049] In practical applications, during the scheduling of CPU cores based on latency data, it can be determined whether the latency data meets a preset first service requirement. For example, the first service requirement is latency data of less than 20 milliseconds lasting for 3 minutes. If the latency data does not meet the first service requirement, the utilization rate of each CPU core within the virtual machine is obtained, and CPU cores are scheduled based on each utilization rate. When the latency data does not meet the first service requirement, it indicates that among the CPU cores bound to each network card interrupt, there are CPU cores that cannot efficiently handle the corresponding network card interrupts. Therefore, the current utilization rate of all CPU cores within the virtual machine (C utilization rates) can be obtained, and CPU cores can be scheduled based on each utilization rate.

[0050] When scheduling CPU cores based on each utilization rate, the lowest utilization rate can be selected from among the various utilization rates. The lowest utilization rate can comprehensively represent the current operating status of all CPU cores within the virtual machine. The lower the lowest utilization rate, the higher the probability that there are many idle CPU cores among the CPU cores; the higher the lowest utilization rate, the lower the probability that there are many idle CPU cores among the CPU cores. The lowest utilization rate is compared with a first threshold. If the lowest utilization rate is greater than or equal to the first threshold, the second number remains unchanged. If the lowest utilization rate is greater than or equal to the first threshold, it means that all CPU cores are in a relatively busy state. For example, if the utilization rate of all CPU cores is above 80% (example of the first threshold), and there are no CPU cores available for scheduling, then the second number B can remain unchanged, and the second number B CPU cores are still used to handle interrupts from the network card. If the lowest utilization rate is less than the first threshold, it means that there are relatively idle CPU cores among the CPU cores. At least one CPU core with a utilization rate less than the second threshold is selected from among the CPU cores, and then the selected at least one CPU core is used to cancel the processing of the bound target interrupt and process the target interrupt waiting to be bound to the CPU core. The first threshold is greater than the second threshold, which can be a fixed value or a lower utilization rate set based on the actual utilization rate. Selecting at least one CPU core with a utilization rate less than the second threshold can be understood as selecting one or more CPU cores with the lowest utilization rate.

[0051] This invention utilizes latency data for CPU core scheduling, allowing for flexible adjustment of CPU core allocation to meet service latency requirements. By acquiring the utilization rate of each CPU core and identifying the lowest utilization rate, the CPU cores of the entire system can be comprehensively considered and scheduled. This enables global optimization, resulting in more balanced utilization of each CPU core and full utilization of system resources. A second quantity B, representing the number of CPU cores currently used for interrupt processing, can be dynamically adjusted based on a comparison between the lowest utilization rate and a first threshold. When the lowest utilization rate is less than the first threshold, at least one CPU core with a utilization rate lower than the second threshold is selected to process the target interrupt waiting to be bound to the CPU core. This dynamic adjustment rationally allocates processing resources based on real-time CPU core utilization. The first and second thresholds can be set according to specific utilization conditions, making the solution more flexible and scalable, adaptable to different system environments and load requirements.

[0052] While each network interface card (NIC) interrupt is waiting to be bound to a CPU core, the waiting time for each interrupt can be recorded. During the process of handling the target interrupt waiting to be bound to a CPU core using at least one selected CPU core, the target interrupt with the longest waiting time can be newly bound to the selected at least one CPU core, and the newly bound target interrupt can be handled by the selected at least one CPU core. Then, the latency data of the NIC is reacquired, and it is determined whether the newly acquired latency data meets the first service requirement. If the newly acquired latency data does not meet the first service requirement, a new utilization rate is obtained, and CPU cores are scheduled according to the new utilization rate. This process is repeated, acquiring new latency data again and determining whether the new acquired latency data meets the first service requirement, until the newly acquired latency data meets the first service requirement; if the newly acquired latency data meets the first service requirement, the process ends.

[0053] This invention, through recording the waiting time of each network card interrupt waiting for binding to a CPU core, can identify the target interrupt with the longest waiting time and bind it to at least one selected CPU core for processing. This method prioritizes processing interrupt tasks with longer waiting times, thereby reducing the waiting time of network card interrupts and improving overall latency performance. After at least one selected CPU core processes the newly bound target interrupt, a step is performed to determine whether the latency data meets the first service requirement. If the latency data still does not meet the first service requirement, the next round of scheduling and processing continues. This step-by-step improvement strategy can continuously optimize the interrupt handling process until the preset first service requirement is met. Recording and considering the waiting time of each interrupt and dynamically scheduling based on this makes the solution flexible and iteratively optimized, enabling continuous improvement of interrupt handling according to actual conditions and gradually enhancing system performance and efficiency.

[0054] If the delayed data meets the primary business requirement, no further processing will be performed.

[0055] (2.1) If the first quantity is greater than or equal to the second quantity, and the second quantity is equal to the total quantity, it means that there is no room for adjustment in the second quantity. In this case, the latency data of the network card is obtained, and the CPU core is scheduled according to the latency data. It should be noted that the execution process of scheduling the CPU core according to the latency data can refer to the relevant content of step (1) above, and will not be repeated here.

[0056] (2.2) If the first quantity is greater than or equal to the second quantity, and the second quantity is less than the total quantity, then obtain the packet loss data of the network card and adjust the second quantity according to the packet loss data.

[0057] If the first number is greater than or equal to the second number, meaning the number of currently unprocessed network interface card (NIC) interrupts is greater than or equal to the number of CPU cores currently used to process NIC interrupts, then the number of CPU cores currently used to process NIC interrupts is insufficient to provide processing services for NIC interrupts. If the second number is less than the total number, it indicates that not all CPU cores in the virtual machine are used to process NIC interrupts, meaning the second number B has room for adjustment. Therefore, further packet loss data of the NIC can be obtained to determine whether the second number B CPU cores are capable of handling the first number A NIC interrupts. Packet loss data refers to the number of data packets lost during network transmission. Packet loss data is commonly used to assess network quality, detect network congestion, and troubleshoot problems. Here are some common examples of packet loss data: Packet loss due to network congestion: In the case of network congestion, packet loss occurs when network devices (such as routers and switches) cannot process and forward all arriving data packets in a timely manner. This may be due to insufficient network bandwidth, excessive network device load, or sudden network traffic bursts. For example, when the data traffic on the network exceeds the capacity of the network link, data packets may be dropped to alleviate network congestion. Packet loss due to signal interference: In wireless communication, signal interference can lead to packet loss. This interference can originate from other wireless devices, physical obstacles, electromagnetic interference, etc. For example, in a wireless network, when the signal quality between a device and the wireless router is poor, packets may be lost during transmission. Packet loss due to poor link quality: In some cases, poor network link quality can lead to packet loss. For example, in a wired network, damaged cables, loose connections, or equipment malfunctions can cause packet loss. Packet loss due to network faults and errors: Faults and errors in the network, such as router malfunctions, misconfigurations, and transmission errors, can also lead to packet loss. These problems usually require troubleshooting and network maintenance to resolve. Packet loss data is crucial for assessing network reliability and performance. By monitoring and analyzing packet loss data, problems in the network can be identified, and appropriate measures can be taken to improve network quality, optimize data transmission, and enhance user experience.

[0058] One implementation method for adjusting the second quantity based on packet loss data is as follows: if the packet loss data does not meet the preset second service requirements, the second quantity is adjusted. If the current network card packet loss data does not meet the second service requirements, it means that using the current second quantity of B CPU cores to handle the first quantity of A network card interrupts will result in a large number of packet losses, affecting the accuracy and efficiency of data transmission, thus significantly impacting the service. Therefore, the current second quantity of B CPU cores is not capable of handling the first quantity of A network card interrupts, and the second quantity B needs to be adjusted until the network card packet loss data meets the second service requirements.

[0059] Adjusting the second quantity can be done by comparing the difference AB between the first quantity A and the second quantity B with the difference CB between the total quantity C and the second quantity B, and then determining how to adjust the second quantity B based on the comparison results.

[0060] If AB is less than CB, meaning there are enough CPU cores to handle the first number A network card interrupts, then the second number B can be adjusted to the first number A. After this adjustment, the network card latency data can be reacquired, and the process can be repeated to determine if the new latency data meets the first service requirement. If the new latency data does not meet the first service requirement, a new utilization rate is obtained, and CPU cores are scheduled based on this new utilization rate. This process is repeated again, acquiring new latency data and determining if it meets the first service requirement, until the new latency data does meet the first service requirement. If the new latency data does meet the first service requirement, the process ends.

[0061] If AB is greater than or equal to CB, meaning there are insufficient CPU cores to handle the first number A network card interrupts, then the second number B can be adjusted to the total number C. Since the number of CPU cores is still less than the number of network card interrupts, it's necessary to reacquire network card latency data and determine if the newly acquired latency data meets the first service requirement. If it doesn't, a new utilization rate is obtained, and CPU cores are scheduled based on this rate. This process repeats until the newly acquired latency data meets the first service requirement. If the newly acquired latency data does meet the first service requirement, the process ends.

[0062] This invention determines how to adjust the second quantity B by comparing the difference AB between the first quantity A and the second quantity B, and the difference CB between the total quantity C and the second quantity B. This allows for dynamic adjustment of the number of CPU cores currently used to handle the target interrupt based on actual conditions, better meeting interrupt handling requirements. When all CPU cores are sufficient to handle all network card interrupts, the second quantity B is adjusted to the first quantity A to fully utilize all available CPU cores. When the number of CPU cores is insufficient to handle all network card interrupts, the second quantity B is adjusted to the total quantity C to maximize the system's processing capacity. Based on the adjusted second quantity B, other steps (such as determining whether the delay data meets the first service requirement) are re-executed. This allows for iterative optimization, gradually optimizing the interrupt handling process through multiple adjustments and executions to achieve better performance and effectiveness.

[0063] It should be noted that in practical applications, there is no situation where the second quantity is greater than the total quantity.

[0064] In an exemplary embodiment of the present invention, if the first quantity A is greater than the total quantity C, and the utilization rate of the CPU core corresponding to the currently unprocessed target interrupt meets a preset condition, then all CPU cores are used to prioritize processing the target interrupt with the shortest expected processing time or the least CPU usage among all current target interrupts. The preset condition can be that the utilization rate is greater than a third threshold for a continuous first time period, for example, the utilization rate reaches 90% (example of the third threshold) and lasts for 5 minutes (example of the first time period).

[0065] In this embodiment of the invention, when the first quantity A (the number of currently unprocessed network card interrupts) is greater than the total quantity C (the total number of CPU cores in the virtual machine), if the utilization rate of the CPU cores corresponding to the currently unprocessed target interrupts meets a preset condition (e.g., utilization rate reaches 90% for 5 minutes), then all CPU cores can be used to simultaneously process the target interrupt with the shortest expected processing time or the least CPU usage among all current target interrupts. This improves processing efficiency and allows for the rapid processing of a large number of interrupt tasks. The utilization of CPU cores is determined by setting preset conditions (e.g., utilization rate reaches 90% for 5 minutes). This allows for intelligent scheduling of CPU cores, avoiding the allocation of tasks to fully loaded cores and prioritizing cores with lower utilization rates. This intelligent scheduling fully utilizes system resources and improves overall processing efficiency. By prioritizing the processing of target interrupts with the shortest expected processing time or the least CPU usage, these interrupts can be processed quickly, reducing processing time and freeing up CPU resources for processing other interrupt tasks. This improves system performance and response speed, ensuring that each interrupt task is processed in a timely manner.

[0066] Based on the above description of an embodiment of an interrupt handling method, a solution for handling network card interrupts within a virtual machine is described below. (Refer to...) Figure 2 The diagram illustrates a flowchart of a virtual machine network card interruption handling scheme according to an embodiment of the present invention.

[0067] Step 201: Monitor for interruptions.

[0068] Step 202: Determine whether the currently detected interrupt is a network card interrupt.

[0069] If the currently detected interrupt is a network card interrupt, then proceed to step 203; if the currently detected interrupt is not a network card interrupt, then no CPU core adjustment will be performed.

[0070] Step 203: Perform network card interrupt scheduling detection.

[0071] Step 204: Obtain the number of unprocessed network card interrupts (A) in the virtual machine, the number of CPU cores currently bound to the network card for handling network card interrupts (B), and the total number of CPU cores in the virtual machine (C).

[0072] Step 205: Determine whether quantity B is greater than quantity A.

[0073] If quantity B is greater than quantity A, proceed to step 206; if quantity B is not greater than quantity A, proceed to step 210.

[0074] Step 206: Obtain the network card's latency data.

[0075] Step 207: Determine whether the delayed data meets the first business requirement.

[0076] If the delayed data meets the first business requirement, no CPU core adjustment will be performed; if the delayed data does not meet the first business requirement, step 208 will be executed.

[0077] Step 208: Obtain the utilization of all CPU cores and determine the minimum utilization.

[0078] If the minimum utilization rate is not less than the first threshold, the quantity B does not need to be adjusted. If the minimum utilization rate is less than the first threshold, proceed to step 209.

[0079] Step 209: Bind the network card interrupt with the longest queue time to at least one CPU core with the lowest utilization.

[0080] The longest queue time mentioned above is the waiting time for the bound CPU core. The newly bound network card interrupt is processed by at least one CPU core with the lowest utilization, and then step 206 is executed.

[0081] Step 210: Determine whether quantity B is less than quantity C.

[0082] If quantity B is not less than quantity C, proceed to step 206; if quantity B is less than quantity C, proceed to step 211.

[0083] Step 211: Obtain packet loss data from the network card.

[0084] Step 212: Determine whether the lost packet data meets the second business requirement.

[0085] If the lost packet data meets the second business requirement, no CPU core adjustment will be performed; if the lost packet data does not meet the second business requirement, step 213 will be executed.

[0086] Step 213: Determine whether AB is less than CB.

[0087] If AB is less than CB, proceed to step 214; if AB is not less than CB, proceed to step 215.

[0088] Step 214: Adjust quantity B to quantity A.

[0089] Step 215: Adjust quantity B to quantity C. Then proceed to step 206.

[0090] Reference Figure 3 This diagram illustrates an interaction diagram of network card interrupt handling according to an embodiment of the present invention. The interaction process of network card interrupt involves the server, network card, and CPU.

[0091] The server uses a detection mechanism to monitor network card (NIC) interrupts in real time or periodically. The server detects NIC interrupts originating from the NIC. The server calculates the number of unprocessed NIC interrupts (A, e.g., 5), the number of CPU cores currently used to process NIC interrupts (B, e.g., 6), and the total number of CPU cores within the virtual machine (C, e.g., 7) from the CPU. When A is less than B, the server obtains latency data (e.g., 60%) from the NIC. If the latency data does not meet business requirements (30%), the server obtains the utilization rate of each CPU core (e.g., 50%, 40%, and 30%) from the CPU. The server determines the minimum utilization rate (30%). When the first threshold is 20%, the minimum utilization rate is not less than the first threshold, and the server still processes NIC interrupts with B (6) CPU cores. When the first threshold is 40%, the minimum utilization rate is less than the first threshold, and the server selects at least one CPU core with the lowest utilization rate (two CPU cores with utilization rates of 40% and 30%). The NIC interrupt with the longest queue time is processed using at least one CPU core with the lowest utilization rate.

[0092] This invention first designs a corresponding adjustment strategy for the second quantity B when there is adjustable space, so that the second quantity B can be adjusted when the adjustment conditions are met. Secondly, when there is no adjustable space for the second quantity B, a corresponding CPU core scheduling strategy is designed, so that CPU core scheduling can be performed when the CPU core scheduling conditions are met. This invention provides a stable and reliable forwarding environment for high-traffic virtual machines from multiple perspectives, avoiding data transmission anomalies and packet loss. Furthermore, it eliminates the need for maintenance personnel to subjectively adjust the second quantity B and perform CPU core scheduling, saving labor costs.

[0093] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0094] Reference Figure 4 The diagram illustrates a structural block diagram of an interrupt handling system according to an embodiment of the present invention. Specifically, the interrupt handling system may include the following modules.

[0095] Interrupt monitoring module 41 is used to detect target interrupts originating from the network card;

[0096] The quantity acquisition module 42 is used to acquire the first number of target interrupts that have not yet been processed, the second number of CPU cores currently used to process target interrupts, and the total number of CPU cores in the virtual machine.

[0097] CPU core scheduling module 43 is used to schedule CPU cores according to the first quantity, the second quantity and the total quantity, and use the scheduled CPU cores to process the target interrupt that has not yet been processed.

[0098] In an exemplary embodiment of the present invention, the CPU core scheduling module 43 includes:

[0099] The core scheduling module is used to obtain the latency data of the network card when the first quantity is less than the second quantity, and to schedule the CPU cores according to the latency data.

[0100] The core scheduling module is further configured to, when the first quantity is greater than or equal to the second quantity, if the second quantity is equal to the total quantity, obtain the latency data of the network card and schedule the CPU cores according to the latency data;

[0101] The second quantity adjustment module is used to obtain packet loss data of the network card if the second quantity is less than the total quantity when the first quantity is greater than or equal to the second quantity. The second quantity is then adjusted according to the packet loss data.

[0102] In an exemplary embodiment of the present invention, the core scheduling module includes:

[0103] The utilization acquisition module is used to acquire the utilization rate of each CPU core in the virtual machine if the latency data does not meet the preset first business requirement.

[0104] The scheduling module is used to schedule CPU cores based on the utilization rate of each core.

[0105] In an exemplary embodiment of the present invention, the scheduling module includes:

[0106] The utilization rate filtering module is used to filter out the lowest utilization rate from the various utilization rates;

[0107] The second quantity maintenance module is used to maintain the second quantity unchanged if the minimum utilization rate is greater than or equal to the first threshold.

[0108] The core selection module is used to select at least one CPU core whose utilization is less than a second threshold from among the CPU cores if the minimum utilization is less than the first threshold, wherein the first threshold is greater than the second threshold.

[0109] The core processing module is used to cancel the processing of bound target interrupts using at least one selected CPU core, and to process target interrupts waiting to be bound to a CPU core.

[0110] In an exemplary embodiment of the present invention, the core processing module is configured to re-bind the target interrupt with the longest waiting time to a selected CPU core, and process the newly bound target interrupt using the selected CPU core.

[0111] In an exemplary embodiment of the present invention, the second quantity adjustment module is used to adjust the second quantity if the lost packet data does not meet the preset second service requirements.

[0112] In an exemplary embodiment of the present invention, the second quantity adjustment module is configured to adjust the second quantity to the first quantity if the difference between the first quantity and the second quantity is less than the difference between the total quantity and the second quantity; and to adjust the second quantity to the total quantity if the difference between the first quantity and the second quantity is greater than or equal to the difference between the total quantity and the second quantity.

[0113] In one exemplary embodiment of the present invention, the system further includes:

[0114] The priority processing module is configured to, if the first quantity is greater than the total quantity, and the utilization rate of the CPU core corresponding to the currently unprocessed target interrupt is greater than the third threshold for a first time period, use all CPU cores to prioritize processing the target interrupt with the shortest expected processing time or the least CPU usage among all the current target interrupts.

[0115] As the system implementation is basically similar to the method implementation, it is described in a relatively simple way. For relevant details, please refer to the description of the method implementation.

[0116] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0118] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0121] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0122] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0123] The interrupt handling method and interrupt handling system provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An interrupt handling method, characterized in that, The method includes: An interrupt originating from the network interface card was detected. Get the first number of target interrupts that are currently not processed, the second number of CPU cores currently used to process target interrupts, and the total number of CPU cores in the virtual machine; The CPU cores are scheduled according to the first quantity, the second quantity and the total quantity, and the scheduled CPU cores are used to process the target interrupts that have not yet been processed. The step of scheduling CPU cores based on the first quantity, the second quantity, and the total quantity includes: If the first quantity is less than the second quantity, obtain the latency data of the network card, and schedule the CPU cores according to the latency data; If the first quantity is greater than or equal to the second quantity, and if the second quantity is equal to the total quantity, then the latency data of the network card is obtained, and the CPU core is scheduled according to the latency data. If the first quantity is greater than or equal to the second quantity, and the second quantity is less than the total quantity, then the packet loss data of the network card is obtained, and the second quantity is adjusted according to the packet loss data.

2. The method according to claim 1, characterized in that, The step of scheduling CPU cores based on the latency data includes: If the latency data does not meet the preset first business requirement, then obtain the utilization rate of each CPU core in the virtual machine; CPU cores are scheduled based on the utilization rate of each core.

3. The method according to claim 2, characterized in that, The scheduling of CPU cores based on the utilization rate of each core includes: The lowest utilization rate is selected from all the aforementioned utilization rates; If the minimum utilization rate is greater than or equal to the first threshold, then the second quantity remains unchanged; If the minimum utilization rate is less than the first threshold, then at least one CPU core with a utilization rate less than the second threshold is selected from among the CPU cores, where the first threshold is greater than the second threshold. Use at least one selected CPU core to cancel the processing of the bound target interrupt and process the target interrupt waiting to be bound to the CPU core.

4. The method according to claim 3, characterized in that, The processing of target interrupts waiting to be bound to CPU cores includes: The target interrupt that has been waiting for the longest time is re-attached to at least one selected CPU core, and the newly-attached target interrupt is processed by at least one selected CPU core.

5. The method according to claim 1, characterized in that, The step of adjusting the second quantity based on the packet loss data includes: If the lost packet data does not meet the preset second service requirement, the second quantity will be adjusted.

6. The method according to claim 1 or 5, characterized in that, The adjustment of the second quantity includes: If the difference between the first quantity and the second quantity is less than the difference between the total quantity and the second quantity, then the second quantity is adjusted to the first quantity; If the difference between the first quantity and the second quantity is greater than or equal to the difference between the total quantity and the second quantity, then the second quantity is adjusted to the total quantity.

7. The method according to claim 1, characterized in that, The method further includes: If the first number is greater than the total number, and the utilization rate of the CPU core corresponding to the currently unprocessed target interrupt is greater than the third threshold for a continuous first time period, then all CPU cores are used to prioritize processing the target interrupt with the shortest expected processing time or the least CPU usage among all current target interrupts.

8. An interrupt handling system, characterized in that, The system includes: The interrupt monitoring module is used to detect target interrupts originating from the network card; The quantity acquisition module is used to acquire the first number of target interrupts that have not yet been processed, the second number of CPU cores currently used to process target interrupts, and the total number of CPU cores in the virtual machine. The CPU core scheduling module is used to schedule CPU cores according to the first number, the second number and the total number, and use the scheduled CPU cores to process the target interrupt that has not yet been processed. The CPU core scheduling module includes: The core scheduling module is used to obtain the latency data of the network card when the first quantity is less than the second quantity, and to schedule the CPU cores according to the latency data. The core scheduling module is further configured to, when the first quantity is greater than or equal to the second quantity, if the second quantity is equal to the total quantity, obtain the latency data of the network card and schedule the CPU cores according to the latency data; The second quantity adjustment module is used to obtain packet loss data of the network card if the second quantity is less than the total quantity when the first quantity is greater than or equal to the second quantity. The second quantity is then adjusted according to the packet loss data.

9. An electronic device, characterized in that, include: One or more processors; and One or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, cause the electronic device to perform the interrupt handling method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The stored computer program causes the processor to execute the interrupt handling method as described in any one of claims 1 to 7.

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