Display substrate and display device

Abstract

A display substrate and a display device are disclosed. The display substrate includes a first display area and a second display area. The first display area includes a first light-emitting unit group and a first pixel circuit group connected to the first light-emitting unit group. The second display area includes a second light-emitting unit group and a second pixel circuit group connected to the second light-emitting unit group. The light-emitting unit group includes a light-emitting unit, and the light-emitting unit includes a first electrode and a second electrode. The second pixel circuit group includes a first pixel circuit unit. The first pixel circuit unit includes at least a first pixel circuit and a second pixel circuit. At least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the second electrode of the same light-emitting unit. Driving one light-emitting unit to emit light through at least two pixel circuits in the second display area of ​​the display substrate can achieve a more uniform full-screen visual display effect.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202011356201.7, filed on November 27, 2020, entitled "Display Substrate and Display Device". Technical Field

[0002] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0003] With people's ever-increasing pursuit of visual effects in display products, narrow bezels and even full-screen displays have become a new trend in the development of OLED display products. As the screen-to-body ratio of many mobile phones has gradually and steadily increased, full-screen displays have become the current trend. The front-facing camera is key to the design of a full-screen display. To achieve a higher screen-to-body ratio, display products with notch screens, waterdrop screens, and punch-hole screens have emerged. These full-screen forms increase the screen-to-body ratio by sacrificing the phone's appearance. Therefore, the under-display camera design can both maintain the phone's appearance and improve the screen-to-body ratio. An under-display camera refers to a front-facing camera located below the screen but not affecting the screen's display function. When the front-facing camera is not in use, the screen above the camera can still display images normally. From an appearance perspective, an under-display camera has no camera hole, truly achieving a full-screen display effect. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate and a display device.

[0005] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate including a first display area and a second display area, the first display area including a plurality of first light-emitting unit groups and a plurality of first pixel circuit groups respectively connected to the plurality of first light-emitting unit groups, the second display area including a plurality of second light-emitting unit groups and a plurality of second pixel circuit groups respectively connected to the plurality of second light-emitting unit groups, each light-emitting unit group including a plurality of light-emitting units, each light-emitting unit including a first electrode, a light-emitting layer and a second electrode disposed along a direction perpendicular to the substrate, the second electrode being located on the side of the light-emitting layer facing the substrate; a plurality of reset power signal lines extending along a first direction and located between the second electrode and the substrate; and a plurality of data lines located on the side of the plurality of reset power signal lines away from the substrate and extending along a second direction, the second direction intersecting the first direction. Each pixel circuit group includes multiple pixel circuits, and the second pixel circuit group includes multiple first pixel circuit units. Each first pixel circuit unit includes at least a first pixel circuit and a second pixel circuit. At least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the second electrode of the same light-emitting unit. Each pixel circuit includes a data writing transistor, a driving transistor, and a first reset control transistor. The first electrode of the first reset control transistor is connected to the reset power signal line, and the second electrode of the first reset control transistor is connected to the second electrode. The first electrode of the data writing transistor is connected to the second electrode of the driving transistor. The display substrate also includes multiple first connection portions. At least a portion of the first connection portions has its first end connected to the second electrode of the data writing transistor of the first pixel circuit. The second end of the at least a portion of the first connection portions is connected to the second electrode of the data writing transistor of the second pixel circuit, so that at least two data writing transistors of the first pixel circuit unit are connected to the same data line. At least a portion of the first connection portion is located between the second electrode of the data writing transistor in the first pixel circuit and the first electrode of the first reset control transistor.

[0006] For example, in an embodiment of this disclosure, the substrate further includes a third display area, the second display area including a plurality of third pixel circuit groups, the third display area including a plurality of third light-emitting unit groups, the plurality of third light-emitting unit groups being respectively connected to the plurality of third pixel circuit groups, and the density of the plurality of second light-emitting unit groups being less than the density of the plurality of first light-emitting unit groups, the density of the plurality of third light-emitting unit groups being less than the density of the plurality of first light-emitting unit groups; the third pixel circuit group including a plurality of second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit being configured to be electrically connected to the second electrode of the same light-emitting unit; a first end of a portion of the first connection portion is connected to the second electrode of the data writing transistor of the third pixel circuit, and a second end of the portion of the first connection portion is connected to the second electrode of the data writing transistor of the fourth pixel circuit so that at least two data writing transistors of the second pixel circuit unit are connected to the same data line, the first connection portion being located between the second electrode of the data writing transistor in the third pixel circuit and the first electrode of the first reset control transistor.

[0007] For example, in embodiments of this disclosure, each pixel circuit further includes a threshold compensation transistor, the first terminal of which is connected to the first terminal of the driving transistor, the second terminal of which is connected to the gate of the driving transistor, and the first connection portion is located between the second terminal of the threshold compensation transistor and the first terminal of the first reset control transistor in the first pixel circuit.

[0008] For example, in embodiments of this disclosure, each pixel circuit further includes: a second connection portion and a third connection portion disposed on the same layer as the data line, the second connection portion being configured to connect the second electrode of the threshold compensation transistor and the gate of the driving transistor, the third connection portion being configured to connect the first electrode of the first reset control transistor and the reset power supply signal line, and in the first pixel circuit, the distance in the second direction between the edges of the second connection portion and the third connection portion that are close to each other is 7 to 12 micrometers so that the first connection portion is disposed between the second connection portion and the third connection portion.

[0009] For example, in an embodiment of this disclosure, the display substrate further includes: a plurality of power signal lines, disposed on the same layer as the data lines and extending along the second direction. The first connection portion is located on a different layer from the data lines and extends along a third direction perpendicular to the substrate, with each first connection portion overlapping the data lines and the power signal lines.

[0010] For example, in an embodiment of this disclosure, the first connection portion and the reset power signal line are located on the same layer.

[0011] For example, in an embodiment of this disclosure, each pixel circuit further includes: a fourth connection portion disposed on the same layer as the data line, the fourth connection portion being configured to connect the first connection portion and the second pole of the data writing transistor, wherein in at least one of the pixel circuit units of the first pixel circuit unit and the second pixel circuit unit, the fourth connection portion of one pixel circuit has a gap with the adjacent data line, and the fourth connection portion of the other pixel circuit is integrally formed with the data line.

[0012] For example, in an embodiment of this disclosure, the display substrate further includes: a plurality of cover portions disposed in the same layer as the first connection portion; each threshold compensation transistor includes two gates and an active semiconductor layer located between the two gates; along the third direction, the cover portions overlap with the active semiconductor layer between the two gates, the data line, and the power signal line. The orthographic projection of the cover portion overlapping with the active semiconductor layer on a first straight line extending along the first direction overlaps with the orthographic projection of the first connection portion on the first straight line; the orthographic projection of the fourth connection portion on a second straight line extending along the second direction overlaps with the orthographic projection of the cover portion on the second straight line.

[0013] For example, in an embodiment of this disclosure, the first connecting portion includes a main connecting portion extending along the first direction and two ends located at both ends of the main connecting portion and extending along the second direction. The two ends are respectively connected to two fourth connecting portions in at least one of the pixel circuit units of the first pixel circuit unit and the second pixel circuit unit. The orthographic projection of the two ends on the second straight line overlaps with the orthographic projection of the covering portion on the second straight line.

[0014] For example, in an embodiment of this disclosure, along the second direction, the distance between the main body connection portion and the first electrode of the threshold compensation transistor in the first pixel circuit is greater than the distance between the main body connection portion and the first electrode of the first reset control transistor in the first pixel circuit.

[0015] For example, in embodiments of this disclosure, each pixel circuit further includes a first light-emitting control transistor and a fifth connection portion disposed on the same layer as the data line. The first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the light-emitting unit located in the first display area and the second display area is electrically connected to the second electrode of the first light-emitting control transistor through the fifth connection portion.

[0016] For example, in an embodiment of this disclosure, the second electrode of each of the light-emitting units in the second light-emitting unit group includes a main electrode and a connecting electrode, wherein the connecting electrode is configured to be directly electrically connected to the fifth connecting portion to be electrically connected to the second electrode of at least two first light-emitting control transistors of the first pixel circuit unit.

[0017] For example, in an embodiment of this disclosure, the display substrate further includes: a plurality of transparent traces located between the second electrode and the film layer containing the data line, each of the transparent traces extending along the first direction. The transparent traces are configured to connect the second electrode of the light-emitting unit in the third light-emitting unit group and the fifth connection portion, such that the second electrode of each light-emitting unit in the third light-emitting unit group is electrically connected to the second electrode of at least two first light-emitting control transistors of the second pixel circuit unit in the third pixel circuit group.

[0018] For example, in an embodiment of this disclosure, the plurality of first pixel circuit groups are arranged in an array along the first direction and the second direction; along the first direction, the plurality of second pixel circuit groups and the plurality of third pixel circuit groups are alternately arranged, and along the second direction, the plurality of second pixel circuit groups and the plurality of third pixel circuit groups are alternately arranged, and a column of second pixel circuit groups and third pixel circuit groups arranged along the second direction is connected to different data lines.

[0019] For example, in an embodiment of this disclosure, the display substrate further includes: a scan signal line extending along the first direction and located between the reset power signal line and the substrate; a reset control signal line extending along the first direction and disposed on the same layer as the scan signal line; and a light emission control signal line extending along the first direction and disposed on the same layer as the scan signal line. The pixel circuit of each sub-pixel further includes a storage capacitor, a second light-emitting control transistor, and a second reset transistor. The gate of the data writing transistor is electrically connected to the scan signal line; the first terminal of the storage capacitor is electrically connected to the power supply signal line, and the second terminal of the storage capacitor is electrically connected to the gate of the driving transistor; the gate of the threshold compensation transistor is electrically connected to the scan signal line; the gate of the first reset transistor is electrically connected to the reset control signal line; the first terminal of the second reset transistor is electrically connected to the reset power supply signal line, the second terminal of the second reset transistor is electrically connected to the gate of the driving transistor, and the gate of the second reset transistor is electrically connected to the reset control signal line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line; the first terminal of the second light-emitting control transistor is electrically connected to the power supply signal line, the second terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor, and the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line.

[0020] For example, in embodiments of this disclosure, each of the light-emitting unit groups includes a first color light-emitting unit, a second color light-emitting unit pair, and a third color light-emitting unit. The first color light-emitting unit and the third color light-emitting unit are arranged along the second direction. The second color light-emitting unit pair includes two second color light-emitting units arranged along the second direction. The first color light-emitting unit and the second color light-emitting unit pair are arranged along the first direction.

[0021] Another embodiment of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 This is a partial planar structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure;

[0024] Figure 2 for Figure 1 The pixel circuit equivalent diagram of at least one of the second pixel circuit group and the third pixel circuit group shown;

[0025] Figure 3A This is a partial planar structure diagram of the active semiconductor layer of the pixel circuit in the second display area provided according to an embodiment of the present disclosure;

[0026] Figure 3B This is a schematic diagram of the active semiconductor layer and the first conductive layer stacked in the second display area according to an embodiment of the present disclosure;

[0027] Figure 3C This is a partial planar structural diagram of the second conductive layer within the second display area provided according to an embodiment of the present disclosure;

[0028] Figure 3D This is a schematic diagram showing the stacked active semiconductor layer, first conductive layer, and second conductive layer in the second display area according to an embodiment of the present disclosure;

[0029] Figure 3E This is a partial planar structural diagram of the source / drain metal layer of the second display area provided according to an embodiment of the present disclosure;

[0030] Figure 3F This is a schematic diagram showing the stacked structure of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layer in the second display area according to an embodiment of this disclosure;

[0031] Figure 4A This is a schematic diagram showing the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area according to an embodiment of this disclosure;

[0032] Figure 4B for Figure 4A A schematic layer structure diagram of one light-emitting unit;

[0033] Figure 4C for Figure 4A The diagram shows the positional relationship between the second light-emitting unit group and the via in the second display area.

[0034] Figure 5A This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the first display area and the second display area according to an embodiment of this disclosure;

[0035] Figure 5B for Figure 5A A schematic diagram of the membrane structure where the data cable connection part is located is shown;

[0036] Figure 5C for Figure 5A A schematic diagram of the membrane structure where the data line is located is shown;

[0037] Figure 5D for Figure 1 A partial plan view of the first and second display areas in the display substrate shown;

[0038] Figure 5E This is a partial plan view of a first display area and a second display area in a display substrate provided according to another example of an embodiment of the present disclosure;

[0039] Figure 6 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the edge areas of the first display area and the third display area according to an embodiment of this disclosure;

[0040] Figure 7 This is a schematic diagram of the second electrode of the light-emitting unit group located in the first display area according to an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of the second electrode of the light-emitting unit group located at the non-edge of the second display area according to an embodiment of the present disclosure;

[0042] Figure 9 This is a schematic diagram of the second electrode of the light-emitting unit group located in the third display area according to an embodiment of the present disclosure;

[0043] Figure 10 A schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups at the boundary of the second display area and the first display area according to an embodiment of this disclosure; and

[0044] Figure 11 This is a schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups at the boundary of the second display area and the first display area according to an embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0047] In their research, the inventors of this application discovered that in current organic light-emitting diode display devices using under-display camera designs, the display brightness and current of the low-density display area (L area) are at least half that of the high-density display area (H area), which affects the display effect.

[0048] This disclosure provides a display substrate and a display device. The display substrate includes a substrate, a first display area, and a second display area. The first display area includes a plurality of first light-emitting unit groups and a plurality of first pixel circuit groups respectively connected to the plurality of first light-emitting unit groups. The second display area includes a plurality of second light-emitting unit groups and a plurality of second pixel circuit groups respectively connected to the plurality of second light-emitting unit groups. The density of the plurality of second light-emitting unit groups is less than the density of the plurality of first light-emitting unit groups. Each light-emitting unit group includes a plurality of light-emitting units. Each light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode disposed along a direction perpendicular to the substrate. The second electrode is located on the side of the light-emitting layer facing the substrate. A plurality of reset power signal lines extend along a first direction and are located between the second electrode and the substrate. A plurality of data lines are located on the side of the plurality of reset power signal lines away from the substrate and extend along a second direction, which intersects the first direction. Each pixel circuit group includes multiple pixel circuits, and the second pixel circuit group includes multiple first pixel circuit units. Each first pixel circuit unit includes at least a first pixel circuit and a second pixel circuit. At least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the second electrode of the same light-emitting unit. Each pixel circuit includes a data writing transistor, a driving transistor, and a first reset control transistor. The first electrode of the first reset control transistor is connected to a reset power signal line, and the second electrode of the first reset control transistor is connected to the second electrode. The first electrode of the data writing transistor is connected to the second electrode of the driving transistor. The display substrate also includes multiple first connection portions. At least a portion of the first connection portions has its first end connected to the second electrode of the data writing transistor of the first pixel circuit, and at least a portion of the first connection portions has its second end connected to the second electrode of the data writing transistor of the second pixel circuit, so that at least two data writing transistors of the first pixel circuit unit are connected to the same data line. At least a portion of the first connection portion is located between the second electrode of the data writing transistor in the first pixel circuit and the first electrode of the first reset control transistor. In the display substrate provided in this embodiment, at least two pixel circuits in the second display area drive the same light-emitting unit to emit light, which can increase the current and brightness of the light-emitting unit in the second display area and achieve a more uniform full-screen visual display effect.

[0049] The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0050] Figure 1 This is a schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure. Figure 1As shown, the display substrate includes a substrate 10. The display substrate includes a first display area 100 and a second display area 200. For example, the display substrate also includes a third display area 300. For example, the second display area 200 is located around the third display area 300, for example, on both sides of the third display area 300 along the X direction, and the first display area 100 is located around the second display area 200 and the third display area 300. For example, the second display area 200 and the third display area 300 are located at the edges of the display areas, that is, the display substrate includes the display areas and the peripheral areas surrounding the display areas, and the edges of the second display area 200 and the third display area 300 away from the first display area 100 are connected to the peripheral areas. That is, the first display area 100 is only located on one side of the third display area 300 along the Y direction. For example, the third display area 300 can be rectangular, with two edges extending along the Y direction respectively connecting to the second display areas 200 located on both sides thereon, one edge extending along the X direction connecting to the peripheral area, and the other edge connecting to the first display area 100. For example, the second display area 200 is located between the first display area 100 and the third display area 300 arranged along the X direction, and one of the two edges of the second display area 200 extending along the X direction is connected to the peripheral area, and the other edge is connected to the first display area 100.

[0051] like Figure 1 As shown, the first display area 100 includes a plurality of first light-emitting unit groups 110 and a plurality of first pixel circuit groups 120 respectively connected to the plurality of first light-emitting unit groups 110. For example, a first light-emitting unit group 110 can be connected to a first pixel circuit group 120 to drive the first light-emitting unit group 110 to emit light. The first light-emitting unit groups 110 and the first pixel circuit groups 120 that drive the first light-emitting unit groups 110 to emit light are both located in the first display area 100.

[0052] like Figure 1As shown, the second display area 200 includes multiple second light-emitting unit groups 210 and multiple second pixel circuit groups 220, with each of the multiple second light-emitting unit groups 210 connected to the multiple second pixel circuit groups 220. For example, the second display area 200 also includes multiple third pixel circuit groups 230. For example, one second light-emitting unit group 210 can be connected to one second pixel circuit group 220 to drive the second light-emitting unit group 210 to emit light. Both the second light-emitting unit group 210 and the second pixel circuit group 220 that drives the second light-emitting unit group 210 to emit light are located in the second display area 200. For example, the third display area 300 includes multiple third light-emitting unit groups 310, with each of the multiple third light-emitting unit groups 310 connected to the multiple third pixel circuit groups 230. That is, the third light-emitting unit groups 310 located in the third display area 300 and the third pixel circuit groups 230 located in the second display area 200 are connected, and the third light-emitting unit groups 310 and the third pixel circuit groups 230 that drive the third light-emitting unit groups 310 to emit light are located in different display areas. For example, as... Figure 1 As shown, the central area 301 of the third display area 300 is only provided with a transparent third light-emitting unit group 310, and no non-transparent pixel circuit group is provided. This central area 301 can be used as an under-screen camera area, which can have a high light transmittance to realize the camera function, and can also realize light emission by connecting with the pixel circuit group of other areas without affecting the display function of the screen.

[0053] like Figure 1 As shown, the density of the multiple second light-emitting unit groups 210 is less than the density of the multiple first light-emitting unit groups 110. For example, the density of the multiple third light-emitting unit groups 310 is less than the density of the multiple first light-emitting unit groups 110. Since the density (i.e., pixel density) of the light-emitting unit groups in the under-display camera area (the central area of ​​the third display area) is lower than the density of the light-emitting unit groups in the normal display area (the first display area), the camera can be positioned below a low-pixel-density area that allows more light to pass through. The statement "the density of both the multiple second light-emitting unit groups 210 and the multiple third light-emitting unit groups 310 is less than the density of the multiple first light-emitting unit groups 110" means that the number of second light-emitting unit groups is less than the number of first light-emitting unit groups in the same area.

[0054] For example, the first display area 100 is the main display area and has a high resolution (PPI, Pixel Per Inch), meaning that the first display area 100 has a high density of sub-pixels for display. Each sub-pixel includes a light-emitting unit and a pixel circuit that drives the light-emitting unit. The third display area 300 allows light incident from the display side of the display substrate to pass through the display substrate and reach the back side of the display substrate, thereby enabling the normal operation of components such as sensors located on the back side of the display substrate. This disclosure is not limited to this; for example, the third display area 300 may also allow light emitted from the back side of the display substrate to pass through the display substrate and reach the display side of the display substrate. The third display area 300 and the second display area 200 also include multiple sub-pixels for display. However, since the pixel circuit of a sub-pixel is generally opaque, in order to improve the light transmittance of the central area 301 of the third display area 300, the light-emitting unit of the sub-pixel in the third display area 300 can be physically separated from the pixel circuit that drives the light-emitting unit. For example, with the light-emitting unit group in the third display area 300 (e.g., Figure 1 The pixel circuits connected to the third display area 300 (shown in the boxes) can be located in the second display area 200, thus occupying part of the space in the second display area 200. The remaining space in the second display area 200 is used to set the pixels of the second display area 200 (including the second pixel circuit group 220 and the second light-emitting unit group 210). For example, each point in the second display area 200 filling a box represents a pixel. At this time, the pixels in the second display area 200 and the third pixel circuit group 230 connected to the third light-emitting unit group 310 in the third display area 300 are arrayed in the second display area 200. As a result, the resolution of the third display area 300 and the second display area 200 is lower than the resolution of the first display area 100, that is, the density of pixels arranged in the third display area 300 and the second display area 200 for display is lower than the pixel density of the first display area 100.

[0055] Figure 2 for Figure 1 The equivalent diagrams of pixel circuit pairs in the second and third pixel circuit groups are shown. Figure 2As shown, each pixel circuit group includes multiple pixel circuits 600. The second pixel circuit group 220 includes multiple first pixel circuit units 610, each first pixel circuit unit 610 including at least a first pixel circuit 611 and a second pixel circuit 612. For example, a first pixel circuit unit 610 may include two pixel circuits, then the first pixel circuit unit 610 may be referred to as a pixel circuit pair 610. The embodiments of this disclosure schematically show that the first pixel circuit unit includes two pixel circuits, but are not limited thereto, and may also include three or more pixel circuits. For example, each light-emitting unit group includes multiple light-emitting units, the first pixel circuit group 120 includes multiple pixel circuits, each pixel circuit is configured to be connected to a light-emitting unit to drive the light-emitting unit to emit light; the second pixel circuit group 220 includes multiple pixel circuit pairs 610, each pixel circuit pair 610 of the second pixel circuit group 220 is configured to be connected to a light-emitting unit to drive the light-emitting unit to emit light.

[0056] For example, a third pixel circuit group comprises more than 230 second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be connected to the same light-emitting unit to drive the light-emitting unit to emit light. For example, a second pixel circuit unit may include two pixel circuits, then the second pixel circuit unit may also be referred to as a pixel circuit pair 610. The embodiments of this disclosure schematically show that the second pixel circuit unit includes two pixel circuits, but are not limited thereto, and may also include three or more pixel circuits.

[0057] For example, the display substrate also includes reset power signal lines, data lines, scan signal lines, power signal lines, reset control signal lines, and light emission control signal lines located on the substrate. Figure 2 As shown, each pixel circuit 600 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first terminal of the threshold compensation transistor T2 is connected to the first terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3. The first terminal of the first reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the first reset control transistor T7 is connected to the light-emitting unit. The first terminal of the data writing transistor T4 is connected to the second terminal of the driving transistor T3. For example, as... Figure 2As shown, the pixel circuit of each sub-pixel also includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of storage capacitor C is electrically connected to the power supply signal line, and the second terminal of storage capacitor C is electrically connected to the gate of driving transistor T3; the gate of threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the gate of first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset; the first terminal of second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, the second terminal of second reset transistor T1 is electrically connected to the gate of driving transistor T3, and the gate of second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset; the gate of first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first terminal of second light-emitting control transistor T5 is electrically connected to the power supply signal line, the second terminal of second light-emitting control transistor T5 is electrically connected to the second terminal of driving transistor T3, and the gate of second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The aforementioned power signal line refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0058] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, increasing the flexibility of the pixel circuit control.

[0059] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0060] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same; that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0061] For example, such as Figure 2 As shown, when the display substrate is working, in the first stage of image display, the second reset transistor T1 is turned on to initialize the voltage of node N1. In the second stage, the same data signal Data is stored in the two N1 nodes of the two pixel circuits 600 through two connected data writing transistors T4, and two driving transistors T3 and two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4. In the third light-emitting stage, the second light-emitting control transistor T5, driving transistor T3 and first light-emitting control transistor T6 in the two pixel circuits 600 (i.e., the pixel circuit pair 610 composed of the first pixel circuit 611 and the second pixel circuit 612) are all turned on to transmit the same data signal to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits 600 are connected and jointly drive the same light-emitting unit 20 to emit light, which can achieve the purpose of increasing current and brightness.

[0062] It should be noted that, in the embodiments of this disclosure, the pixel circuit of the sub-pixel can be, in addition to being, Figure 2 Besides the 7T1C (seven transistors and one capacitor) structure shown, other structures with different numbers of transistors can also be used, such as 7T2C, 6T1C, 6T2C, or 9T2C structures. This disclosure does not limit the specific implementation of these structures. The goal is simply to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to enable them to jointly drive the same light-emitting unit to emit light.

[0063] Figure 3A This is a partial planar structure diagram of the active semiconductor layer of the pixel circuit in the second display area provided according to an embodiment of this disclosure. (See diagram below.) Figure 3AAs shown, the active semiconductor layer 3100 can be formed by patterning semiconductor material. The active semiconductor layer 3100 can be used to fabricate the active layers of the aforementioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of each transistor in each sub-pixel, and the active layer pattern and doped region pattern of each transistor in the same pixel circuit are integrally formed.

[0064] It should be noted that the active layer may include an integrally formed low-temperature polycrystalline silicon layer. The source and drain regions can be made conductive through doping to achieve electrical connections between the various structures. That is, the active semiconductor layer of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern. The active layers of different transistors are separated by doped structures.

[0065] For example, the active semiconductor layer 3100 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0066] Figure 3B This is a schematic diagram of the active semiconductor layer and the first conductive layer stacked in the second display area according to an embodiment of the present disclosure. The display substrate includes a gate insulating layer located on the side of the active semiconductor layer away from the substrate, for insulating the active semiconductor layer 3100 from the subsequently formed first conductive layer 3200 (i.e., the gate metal layer). Figure 3B The first conductive layer 3200 of the display substrate is shown. The first conductive layer 3200 is disposed on the gate insulating layer, thereby insulating it from the active semiconductor layer 3100. The first conductive layer 3200 may include the second terminal CC2 of capacitor C, multiple scan signal lines 430 extending along a first direction (X direction in the figure), multiple reset control signal lines 440, multiple light emission control signal lines 450, and the gates of a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0067] For example, such as Figure 3BAs shown, the gate of the data writing transistor T3 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 can be a dual-gate thin-film transistor. The first gate of the threshold compensation transistor T2 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100, and the second gate of the threshold compensation transistor T2 can be the portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100. Figure 3B As shown, the gate of the driving transistor T1 can be the second terminal CC2 of the capacitor C.

[0068] It should be noted that, Figure 3B The dashed rectangles in the diagram illustrate the overlapping portions of the first conductive layer 3200 and the active semiconductor layer 3100. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In embodiments of this disclosure, to distinguish transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode, and the other as the second electrode. Therefore, in embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0069] For example, such as Figure 3B As shown, the scan signal line 430, reset control signal line 440, and light emission control signal line 450 are arranged along the second direction (Y direction). The scan signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450. In this embodiment, the first direction and the second direction are intersecting directions, for example, the first direction is perpendicular to the second direction. In this embodiment, the first direction and the second direction can be interchanged.

[0070] For example, in the second direction, the second terminal CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between scan signal line 430 and light emission control signal line 450. The protruding structure P protruding from scan signal line 430 is located on the side of scan signal line 430 away from light emission control signal line 450.

[0071] For example, a first insulating layer is formed on the first conductive layer 3200 to insulate the first conductive layer 3200 from the subsequently formed second conductive layer 3300.

[0072] Figure 3C This is a partial planar structural diagram of the second conductive layer within the second display area according to an embodiment of the present disclosure. Figure 3D This is a schematic diagram showing the stacked structure of the active semiconductor layer, the first conductive layer, and the second conductive layer in the second display area according to an embodiment of this disclosure. Figures 3C to 3D As shown, the second conductive layer 330 includes a first electrode CC1 of capacitor C and multiple reset power signal lines 410 extending along a first direction. The first electrode CC1 of capacitor C and the second electrode CC2 of capacitor C at least partially overlap to form capacitor C.

[0073] like Figures 3C to 3D As shown, the display substrate provided in this embodiment further includes a plurality of first connection portions 510. At least a portion of the first connection portions 510 has its first end connected to the second pole of the data writing transistor T4 of the first pixel circuit 611 in the first pixel circuit unit (for example, the first end of the first connection portion 510 and the second pole of the data writing transistor T4 of the first pixel circuit 611 in the first pixel circuit unit can be directly connected or electrically connected through a conductive layer transition layer). The second end of the first connection portion 510 is connected to the second pole of the data writing transistor T4 of the second pixel circuit 612 in the first pixel circuit unit so that at least two data writing transistors T4 of the first pixel circuit unit are connected to the same data line. Along the second direction, at least a portion of the first connection portion 510 is located between the second pole of the data writing transistor T2 in the first pixel circuit 611 and the first pole of the first reset control transistor T7.

[0074] In this embodiment of the disclosure, the second pole of the data writing transistor of at least two pixel circuits in the second display area is connected through the first connection portion to drive a light-emitting unit to emit light. This can increase the current and brightness of the light-emitting unit in the second display area. For example, the current and brightness of the light-emitting unit in the second display area can be increased to 1.8 to 2 times that when driven by a single pixel circuit. This solves the problem of low current and brightness in the second display area and achieves a more uniform full-screen visual display effect.

[0075] For example, a first terminal of a portion of the first connection portion 510 is connected to the second terminal of the data write transistor T4 of the third pixel circuit in the second pixel circuit unit, and a second terminal of the first connection portion 510 is connected to the second terminal of the data write transistor T4 of the fourth pixel circuit in the second pixel circuit unit, so that at least two data write transistors T4 of the second pixel circuit unit are connected to the same data line, and along the second direction, the first connection portion 510 is located between the second terminal of the data write transistor T2 in the third pixel circuit and the first terminal of the first reset control transistor T7. For ease of subsequent description, the first pixel circuit unit and the second pixel circuit unit in this disclosure are collectively referred to as a pixel circuit pair, and the two pixel circuits included in each pixel circuit unit are both referred to as the first pixel circuit and the second pixel circuit, that is, the third pixel circuit in the second pixel circuit unit can be referred to as the first pixel circuit, and the fourth pixel circuit in the second pixel circuit unit can be referred to as the second pixel circuit.

[0076] For example, along the second direction, the first connection portion 510 is located between the second pole of the threshold compensation transistor T3 and the first pole of the first reset control transistor T7 in the first pixel circuit 611.

[0077] For example, the first connection part 510 is disposed on the same layer as the reset power signal line 410.

[0078] For example, a second insulating layer is formed on the second conductive layer 3300 to insulate the second conductive layer 3300 from the subsequently formed source-drain metal layer 3400.

[0079] For example, Figure 3E This is a partial planar structural diagram of the source / drain metal layer of the second display area provided according to an embodiment of the present disclosure. Figure 3F This is a schematic diagram showing the stacked structure of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layer in the second display area according to an embodiment of this disclosure. Figures 3E to 3F As shown, the source-drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along a second direction. The data line 420 is electrically connected to the second terminal of the data writing transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line 460 is electrically connected to the first terminal of the second light-emitting control transistor T5 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line 460 and the data line 420 are alternately arranged along a first direction. The power signal line 460 is electrically connected to the first terminal CC1 of the capacitor C through a via penetrating the second insulating layer.

[0080] For example, a passivation layer and a planarization layer can be provided on the side of the source / drain metal layer 3400 away from the substrate to protect the source / drain metal layer 3400.

[0081] For example, Figures 3D to 3F The illustration schematically shows a portion of the pixel circuits in the second pixel circuit group 220 and a portion of the pixel circuits in the third pixel circuit group 230. This embodiment schematically shows that both the second pixel circuit group 220 and the third pixel circuit group 230 include pixel circuit pairs. Each pixel circuit pair includes a first pixel circuit 611 and a second pixel circuit 612 arranged along a first direction. The second terminals of the data writing transistors T4 of the two pixel circuits in each pixel circuit pair are connected via a first connection portion 510 to drive the same light-emitting unit to emit light. This embodiment is not limited to this; for example, only the second pixel circuit group or only the third pixel circuit group may include the aforementioned pixel circuit pairs.

[0082] For example, such as Figures 3D to 3F As shown, the second pixel circuit group 220 and the third pixel circuit group 230 may include eight pixel circuits arranged in two rows, i.e., four pixel circuit pairs arranged in a two-dimensional array. The first pixel circuit group does not include the aforementioned pixel circuit pairs (not shown), but only includes four pixel circuits arranged in a two-dimensional array. In the first pixel circuit group, each of two adjacent pixel circuits arranged along a first direction drives a light-emitting unit to emit light, and the two data write transistors in these two adjacent pixel circuits are independent of each other and connected to different data lines. The layout difference between the first pixel circuit group and the second pixel circuit group in this embodiment mainly lies in whether a first connection portion is provided, and the position of the second electrode of the data write transistor connected to the first connection portion.

[0083] For example, such as Figures 3D to 3FAs shown, the display substrate provided in this embodiment can adopt a quarter-high resolution (QHD). However, since the distance along the second direction between the second electrode of the threshold compensation transistor and the first electrode of the first reset control transistor in each pixel circuit designed with this resolution is very small, for example, less than 2 micrometers, or for example, 1.4 to 1.8 micrometers, it is difficult to set the first connection portion between the second electrode of the two data write transistors (data input nodes) of the pixel circuit pair and the first electrode of the threshold compensation transistor and the first electrode of the first reset control transistor. Since the pixel size in QHD resolution products is generally smaller than the pixel size in full-screen resolution (FHD) products, in this embodiment, the pixel circuit with QHD resolution is designed into the pixel pitch with FHD resolution, thereby increasing the distance along the second direction between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 in each pixel circuit, so as to ensure that the data input nodes of the two pixel circuits of the pixel circuit pair are connected by a hole through the first connection portion.

[0084] For example, such as Figures 3D to 3F As shown, relative to a display substrate, its second display area includes multiple light-emitting units and multiple pixel circuits connected one-to-one with the multiple light-emitting units. In the case where dummy pixel circuits that are not connected to any light-emitting units are set between adjacent pixel circuits, in this embodiment of the present disclosure, a first connecting part is used to connect the dummy pixel circuits and the pixel circuits that connect the light-emitting units in the second display area. This can effectively utilize the dummy pixel circuits while minimizing changes to the overall structure of the pixel circuits, thereby increasing the current and brightness of the light-emitting units in the second display area (and at least one of the third display areas), and achieving a more uniform full-screen visual display effect.

[0085] For example, the distance between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7 along the second direction is 7 to 12 micrometers so that a first connection portion 510 is provided between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0086] For example, such as Figures 3A to 3FAs shown, each pixel circuit further includes a second connection portion 520 and a third connection portion 530 disposed on the same layer as the data line 420. The second connection portion 520 is configured to connect the second terminal of the threshold compensation transistor T2 and the gate of the driving transistor T3. The third connection portion 530 is configured to connect the first terminal of the first reset control transistor T7 and the reset power supply signal line 410. For example, one end of the second connection portion 520 is electrically connected to the second terminal of the threshold compensation transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the second connection portion 520 is electrically connected to the gate of the driving transistor T3 (i.e., the second terminal CC2 of capacitor C) through a via penetrating the first insulating layer and the second insulating layer. One end of the third connection portion 530 is electrically connected to the reset power supply signal line 410 through a via penetrating the second insulating layer. The other end of the third connection portion 530 is electrically connected to the first terminal of the first reset control transistor T7 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0087] For example, such as Figures 3A to 3F As shown, in the first pixel circuit 611, the distance in the second direction between the adjacent edges of the second connecting portion 520 and the third connecting portion 530 is 7 to 12 micrometers so that the first connecting portion 510 is disposed between the second connecting portion 520 and the third connecting portion 530. For example, in the first pixel circuit 611, the distance in the second direction between the adjacent edges of the second connecting portion 520 and the third connecting portion 530 can be 8 to 11 micrometers.

[0088] For example, such as Figures 3A to 3F As shown, the first connection portion 510 and the data line 420 are located on different layers and are perpendicular to the substrate in a third direction. Each first connection portion 510 overlaps with the data line 420 and the power signal line 460. For example, a data line 420 and a power signal line 460 are provided between the two data writing transistors T4 included in the pixel circuit pair 610, and the first connection portion 510 connecting the two data writing transistors T4 overlaps with both the data line 420 and the power signal line 460.

[0089] For example, such as Figures 3A to 3FAs shown, each pixel circuit also includes a fourth connection portion 540 disposed on the same layer as the data line 420. The fourth connection portion 540 is configured to connect the first connection portion 510 and the second terminal of the data writing transistor T4. The fourth connection portion 540 of one of the pixel circuit pairs 610 (e.g., the second pixel circuit 612) has a gap between it and the adjacent data line 420. The fourth connection portion 540 of the other pixel circuit pair 610 (e.g., the first pixel circuit 611) is integrated with the data line 420 to achieve that the pixel circuit pair 610 is connected to only one data line 420. In the above statement "the fourth connection portion 540 has a gap between it and the adjacent data line 420," "adjacent data line" means that there are no other data lines between the fourth connection portion 540 and the data line 420.

[0090] For example, such as Figure 1 , Figures 3A to 3F As shown, multiple first pixel circuit groups 120 are arranged in an array along a first direction and a second direction. Along the first direction, multiple second pixel circuit groups 220 and multiple third pixel circuit groups 230 are alternately arranged, and along the second direction, multiple second pixel circuit groups 220 and multiple third pixel circuit groups 230 are alternately arranged, and the second pixel circuit groups 220 and third pixel circuit groups 230 are connected to different data lines 420.

[0091] For example, a straight line extending along the first direction passes through the second terminals of the two data write transistors in a pixel circuit pair, and the entire first connection portion extends along the first direction. For example, different pixel circuit groups connect to different data lines, so the length of the first connection portion along the first direction in different pixel circuit groups can be different. For example, in the same pixel circuit group, the length of the first connection portion along the first direction in different pixel circuit pairs can also be different.

[0092] For example, such as Figure 3EAs shown, the fourth connecting portion 540 integrated with the data line 420 is designated as the first sub-part 541, and the fourth connecting portion 540 spaced from the adjacent data line 420 is designated as the second sub-part 542. Taking a second pixel circuit group comprising eight pixel circuits arranged in an array (four pixel circuits arranged along the row direction and two pixel circuits arranged along the column direction) as an example, in the second pixel circuit group, two first sub-parts 541 are arranged along the second direction (e.g., in one column), and two second sub-parts 542 are arranged along the second direction (e.g., in one column), with the first sub-parts 541 and second sub-parts 542 alternating in the first direction (e.g., in the row direction). Similarly, the arrangement of the first and second sub-parts in the third pixel circuit group is the same as that in the second pixel circuit group. For the second and third pixel circuit groups that alternate along the second direction, the first sub-parts in the second pixel circuit group and the second sub-parts in the third pixel circuit group are located in different columns so that the second pixel circuit group and the third pixel circuit group are connected to different data lines.

[0093] Since there are no pixel circuit pairs in the first pixel circuit group, the fourth connection part of each of the two adjacent pixel circuits arranged along the first or second direction in the first pixel circuit group is integrated with the data line to realize the electrical connection between each pixel circuit and the corresponding data line.

[0094] For example, such as Figures 3A to 3F As shown, the display substrate also includes a plurality of cover portions S disposed on the same layer as the first connection portion 510. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and an active semiconductor layer 3100 located between the two gates. Along the third direction, the cover portions S overlap with the active semiconductor layer 3100 between the two gates, the data line 420, and the power signal line 460.

[0095] For example, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is off. This makes it susceptible to voltage fluctuations due to surrounding lines, which can affect the leakage current of the threshold compensation transistor T2 and consequently its luminous brightness. To maintain a stable voltage in the active semiconductor layer between the two channels of the threshold compensation transistor T2, a capacitor is formed between the cover portion S and the active semiconductor layer between the two channels of the threshold compensation transistor T2. The cover portion S can be connected to the power signal line 460 to obtain a constant voltage, thus ensuring a stable voltage for the floating active semiconductor layer. The overlap between the cover portion S and the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 also prevents the active semiconductor layer between the two gates from being illuminated and altering its characteristics, such as preventing voltage changes in this portion of the active semiconductor layer to prevent crosstalk. For example, the power signal line 460 can be electrically connected to the cover portion S through a via penetrating the second insulating layer to provide a constant voltage to the cover portion S.

[0096] For example, the orthographic projection of the cover portion S overlapping with the active semiconductor layer on a first straight line extending in the first direction overlaps with the orthographic projection of the first connecting portion 510 on the first straight line, and the orthographic projection of the fourth connecting portion 540 on a second straight line extending in the second direction overlaps with the orthographic projection of the cover portion S on the second straight line. Thus, in order to maintain a distance from the cover portion S disposed in the same layer, the first connecting portion 510 is configured as a non-linear type, such as a broken line type.

[0097] For example, such as Figures 3A to 3F As shown, the first connecting portion 510 includes a main connecting portion 511 extending along a first direction and two end portions 512 located at both ends of the main connecting portion 511 and extending along a second direction. The two end portions 512 are respectively connected to the two fourth connecting portions 540 of the pixel circuit pair 610. The orthographic projections of the two end portions 512 on the second straight line overlap with the orthographic projections of the cover portion S on the second straight line. Thus, the main connecting portion and the two end portions form a zigzag shape to maintain a distance from the cover portion.

[0098] For example, in the second direction, the distance between the cover portion S and the second electrode of the threshold compensation transistor T2 is less than the distance between the cover portion S and the first electrode of the first reset control transistor T7, that is, the cover portion S is closer to the threshold compensation transistor T2. Therefore, for ease of design and to maintain a certain distance between the first connection portion 510 and the cover portion S, the first connection portion 510 is set to be closer to the first electrode of the first reset transistor T7, that is, in the Y direction, the distance between the main body connection portion 511 and the second electrode of the threshold compensation transistor T2 in the first pixel circuit 611 is greater than the distance between the main body connection portion 511 and the first electrode of the first reset control transistor T7 in the first pixel circuit 611.

[0099] For example, Figure 4A This is a schematic diagram showing the connection relationship between the second light-emitting unit group and the second pixel circuit group in the second display area according to an embodiment of this disclosure. Figure 4B for Figure 4A A schematic layer structure diagram of one light-emitting unit. (See diagram below.) Figures 1 to 4B As shown, each light-emitting unit group includes multiple light-emitting units 20. For example, each light-emitting unit group includes a first-color light-emitting unit 201, a second-color light-emitting unit pair 202, and a third-color light-emitting unit 203. The first-color light-emitting unit 201 and the third-color light-emitting unit 203 are arranged along a second direction. The second-color light-emitting unit pair 202 includes two second-color light-emitting units arranged along the second direction. There are also first light-emitting unit blocks 202-1 and second light-emitting unit blocks 202-2. The first-color light-emitting unit 201 and the second-color light-emitting unit pair 202 are arranged along a first direction. For example, the orthographic projection of the second electrode of the first-color light-emitting unit 201 onto a straight line extending along the Y direction overlaps with the orthographic projection of the second electrode of the first light-emitting unit block 202-1 onto that straight line; the orthographic projection of the second electrode of the third-color light-emitting unit 203 onto that straight line overlaps with the orthographic projection of the interval between the second electrodes of the two second-color light-emitting units onto that straight line. For example, the orthographic projection of the main electrode of the third color light-emitting unit 203 (described later) onto a straight line extending in that direction does not overlap with the orthographic projection of the main electrodes of the two second color light-emitting units onto the same straight line.

[0100] For example, each light-emitting unit 20 includes a first electrode 21, a light-emitting layer 23, and a second electrode 22 sequentially disposed along a direction perpendicular to the substrate 10. The second electrode 22 is located on the side of the light-emitting layer 13 facing the substrate 10. The display substrate also includes a pixel-defining layer 24, which includes an opening for defining the light-emitting area of ​​a sub-pixel. This opening exposes the second electrode 22 of the light-emitting unit 20. When the light-emitting layer 23 of a subsequent light-emitting unit 20 is formed in the opening of the pixel-defining layer 24, the light-emitting layer 23 contacts the second electrode 22, thereby driving the light-emitting layer 23 to emit light to form an effective light-emitting area. Here, "effective light-emitting area" can refer to a two-dimensional planar region parallel to the substrate. It should be noted that, due to process reasons, the size of the opening of the pixel-defining layer away from the substrate is slightly larger than that of the opening near the substrate, or it gradually increases in size from the side near the substrate to the side away from the substrate. Therefore, the size of the effective light-emitting area may be slightly different from the size of different positions of the opening of the pixel-defining layer, but the overall shape and size of the area are basically the same. For example, the orthographic projection of the effective light-emitting area on the substrate roughly coincides with the orthographic projection of the corresponding pixel-defining layer opening on the substrate. For example, the orthographic projection of the effective light-emitting area on the substrate falls entirely within the orthographic projection of the corresponding pixel-defining layer opening on the substrate, and the two are similar in shape, with the projected area of ​​the effective light-emitting area on the substrate being slightly smaller than the projected area of ​​the corresponding pixel-defining layer opening on the substrate.

[0101] For example, the first color emitting unit can be one of a red emitting unit and a blue emitting unit, the third color emitting unit is the other of a red emitting unit and a blue emitting unit, and the second color emitting unit pair is a green emitting unit pair. This disclosure schematically shows that the first color emitting unit is a red emitting unit and the second color emitting unit is a green emitting unit.

[0102] For example, such as Figures 1 to 4BAs shown, each pixel circuit also includes a fifth connection portion 550 disposed on the same layer as the data line 420. The second electrode 22 of the light-emitting unit 20 located in the first display area 100 and the second display area 200 can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion 550. For example, in the first display area 100, the second electrode of each light-emitting unit 20 in the first light-emitting unit group 110 can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion 550 of the corresponding pixel circuit 600 in the first pixel circuit group 120. In the second display area 200, the second electrode of each light-emitting unit 20 in the second light-emitting unit group 210 can be directly electrically connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion 550 of the corresponding pixel circuit 600 in the second pixel circuit group 220. For example, in the second display area 200, the second electrode of each light-emitting unit 20 in the second light-emitting unit group 210 can be connected to the fifth connection portion 550 through the passivation layer and the first via 561 in the planarization layer.

[0103] For example, such as Figures 1 to 4B As shown, the second pixel circuit group 220 includes multiple pixel circuit pairs 610. The second electrode 22 of each light-emitting unit 20 in the second light-emitting unit group 210 includes a main electrode and a connecting electrode. The shape of the main electrode is basically the same as the shape of the effective light-emitting area of ​​each light-emitting unit 20. The connecting electrode is configured to be directly electrically connected to the fifth connecting part 550 to be electrically connected to the second electrode of the two first light-emitting control transistors T6 of the pixel circuit pair 610.

[0104] For example, such as Figures 1 to 4B As shown, the display substrate also includes multiple transparent traces 700 located between the second electrode 22 and the film layer containing the data line 420, each transparent trace 700 extending along a first direction. For example, the third pixel circuit group 230 includes multiple pixel circuit pairs 610, and the transparent traces 700 are configured to connect the second electrode 22 of the light-emitting unit 20 in the third light-emitting unit group 310 and the fifth connection portion 550 so that the second electrode 22 of each light-emitting unit 20 in the third light-emitting unit group 310 is electrically connected to the second electrode of the two first light-emitting control transistors T6 of the pixel circuit pair 610 in the third pixel circuit group 230.

[0105] For example, in the second display area 200, the transparent trace 700 is electrically connected to the fifth connection portion 550 in the third pixel circuit group 230 through the passivation layer and the second via 562 in the planarization layer; in the third display area 300, the second electrode 22 of the light-emitting unit 20 is connected to the transparent trace 700 through the third insulating layer located between the transparent trace 700 and the second electrode 22, thereby realizing the connection with the pixel circuit 600 in the second display area 200.

[0106] For example, Figure 4C for Figure 4A The diagram shows the positional relationship between the second light-emitting unit group and the vias in the second display area. Figure 4A and Figure 4C As shown, a first via group 5610 is formed by multiple first vias 561 connecting a second light-emitting unit group 210 and a second pixel circuit group 220, and a second via group 562 is formed by multiple second vias 562 connecting a third light-emitting unit group 310 and a third pixel circuit group 230. Along a first direction, the multiple first via groups 5610 and multiple second via groups 5620 are arranged alternately; along a second direction, the multiple first via groups 5610 and multiple second via groups 5620 are arranged alternately. Compared to the case where both the second and third light-emitting unit groups are connected to the fifth connection portion through a transparent trace film layer, in this embodiment, the second electrode of the light-emitting unit in the second light-emitting unit group is directly connected to the fifth connection portion, while the second electrode of the light-emitting unit in the third light-emitting unit group is connected to the fifth connection portion through a transparent trace. This allows for more space to be allocated to the transparent trace, preventing signal crosstalk.

[0107] For example, Figure 5D for Figure 1 A partial plan view of the first and second display areas in the display substrate shown. Figure 1 and Figure 5D As shown, in one embodiment of this disclosure, a first display area 100 and a second display area 200 in a display substrate include a plurality of pixel circuits 030 arranged along a first direction and a second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. The plurality of pixel circuits 030 located in the first display area 100 include a plurality of first sub-pixel circuits 031, and the plurality of pixel circuits 030 located in the second display area 200 include a plurality of second sub-pixel circuits 032. A plurality of first light-emitting units (i.e., the three colors of light-emitting units included in the first light-emitting unit group 110, such as R, G1, G2, and B shown in the figure) in the first display area 100 are connected to the plurality of first sub-pixel circuits 031 in a one-to-one correspondence. Each second light-emitting unit (i.e., the three colors of light-emitting units included in the second light-emitting unit group 210, such as R, G1, G2, and B shown in the figure) in the second display area 200 is connected to at least two second sub-pixel circuits 032.

[0108] For example, such as Figure 1 As shown, the first display area 100 and the second display area 200 are connected in the Y direction (i.e., the direction of extension of the data cable). The third display area 300 includes a central area 301 and an edge area 302 surrounding the central area 301, and the edge area 302 of the third display area 300 is connected to the first display area 100 in the Y direction. For example, Figure 1The diagram schematically shows that the third display area 300 is rectangular in shape, and the central area 301 of the third display area 300 is circular in shape. The edge area 302 is the area located within the rectangle excluding the central circular area. This embodiment is not limited to this; the shapes of the central and edge areas of the third display area can be set according to actual product requirements.

[0109] For example, such as Figure 1 As shown, both the central area 301 and the edge area 302 of the third display area 300 are provided with third light-emitting unit groups 310. Multiple third light-emitting unit groups 310 located in the third display area 300 are electrically connected to multiple third pixel circuit groups 230 in the second display area 200 via transparent traces 700 to drive the third light-emitting unit groups 310 to emit light. The central area 301 of the third display area 300 only has light-emitting unit groups and no pixel circuit groups, thereby reducing the metal coverage area and achieving higher light transmittance. The edge area 302 of the third display area 300, in addition to having light-emitting unit groups, also has a light-blocking structure so that the third display area 300 forms a light-transmitting area (i.e., the central area 301) with a preset shape. For example, in this embodiment of the present disclosure, the light-blocking structure disposed in the edge region 302 of the third display area 300 can be a plurality of dummy pixel circuit groups 320. The plurality of dummy pixel circuit groups 320 include a portion located between the third light-emitting unit group 310 and the substrate, and a portion located between adjacent third light-emitting unit groups 310. Each dummy pixel circuit group 320 is not connected to any light-emitting unit group and is only a floating pixel circuit. For example, the edge region 302 is a ring-shaped wiring region. For example, the data lines, scan signal lines, power signal lines, reset control lines, light-emitting control signal lines, reset power signal lines, etc., connecting the third pixel circuit group are all located in the ring-shaped wiring region.

[0110] For example, such as Figure 1 As shown, the third light-emitting unit group 310 in the third display area 300 can be controlled in a left-right half-control manner, with the third pixel circuit groups 230 in the two second display areas 200 that are symmetrical about the center line extending along the Y direction of the third display area 300 being controlled separately. For example, the third light-emitting unit group 310 located to the left of the center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the left of the center line, and the third light-emitting unit group 310 located to the right of the center line is controlled by the third pixel circuit group 230 in the second display area 200 located to the right of the center line. The traces used to drive the light-emitting units in the circular central area 301 are arranged in a dense manner in the edge area 302, so that the circular central area 301, which serves as the under-screen display area, can have a maximum area.

[0111] For example, such as Figure 1As shown, the first display area 100 and the second display area 200 include a plurality of pixel circuits arranged along a first direction and a second direction to form a plurality of pixel circuit columns 32 and a plurality of pixel circuit rows 31. For example, the edge area 302 of the third display area 300 includes a plurality of dummy pixel circuits 034 arranged along a first direction and a second direction to form a plurality of dummy pixel circuit columns and a plurality of dummy pixel circuit rows. Here, the dummy pixel circuits in the third display area 300 are also referred to as pixel circuits. Although the dummy pixel circuits are not connected to any light-emitting unit, their structure can be roughly the same as the pixel circuit structure of other areas, for example, all including a 7T1C (i.e., seven transistors and one capacitor) structure. For example, multiple data lines 420 extending along the Y direction are respectively connected to the plurality of pixel circuit columns 32.

[0112] For example, such as Figures 1 to 4A As shown, each pixel circuit column 32 includes a pixel circuit column group consisting of four adjacent columns. Each pixel circuit column group includes a first pixel circuit column 321, a second pixel circuit column 322, a third pixel circuit column 323, and a fourth pixel circuit column 324 arranged sequentially along the X direction (i.e., the direction intersecting with the extension direction of the data line 420). The first pixel circuit column 321, the second pixel circuit column 322, the third pixel circuit column 323, and the fourth pixel circuit column 324 within the first display area 100 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged sequentially along the X direction. At least some of the pixel circuits in the first pixel circuit column 321, at least some of the pixel circuits in the second pixel circuit column 322, at least some of the pixel circuits in the third pixel circuit column 323, and at least some of the pixel circuits in the fourth pixel circuit column 324 in the second display area 200 are respectively connected to the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 arranged sequentially along the X direction.

[0113] For example, such as Figures 1 to 4A As shown, within the second display area 200, in at least one pixel circuit column group, the data output terminals (i.e., the fourth connection portion 540) of two pixel circuits located in the same pixel circuit row 31 and located in the first pixel circuit column 321 and the second pixel circuit column 322 are electrically connected to form a first pixel circuit pair 601, and the data output terminals (i.e., the fourth connection portion 540) of two pixel circuits 600 located in the same pixel circuit row 31 and located in the third pixel circuit column 323 and the fourth pixel circuit column 324 are electrically connected to form a second pixel circuit pair 602. This embodiment of the present disclosure is illustrated by example where each pixel circuit column group in the second display area includes a first pixel circuit pair and a second pixel circuit pair, but it is not limited to this and can be configured according to actual product requirements.

[0114] For example, such as Figures 1 to 4AThe first display area 100, the second display area 200, and the third display area 300 each include multiple light-emitting units 20. The multiple light-emitting units 20 in the first display area 100 are respectively connected to multiple pixel circuits 600 of the first display area 100. The multiple light-emitting units 20 in the second display area 200 are respectively connected to a portion of the pixel circuits 600 of the second display area 200, and the multiple light-emitting units 20 in the third display area 300 are respectively connected to another portion of the pixel circuits 600 of the second display area 200. That is, in the second display area 200, the light-emitting units 20 in the second light-emitting unit group 210 are connected to the pixel circuits 600 in the second pixel circuit group 220; and in the third display area 300, the light-emitting units 20 in the third light-emitting unit group 310 are connected to the pixel circuits 600 in the third pixel circuit group 230 of the second display area 200. This embodiment of the present disclosure schematically shows that the second display area includes only the second pixel circuit group and the third pixel circuit group, but is not limited thereto. Depending on factors such as space design requirements in the product, the second display area may also include other pixel circuit groups, such as dummy pixel circuit groups (not connected to the light-emitting unit), etc.

[0115] For example, such as Figures 1 to 4A As shown, the second pixel circuit group 220 and the third pixel circuit group 230 in the second display area 200 both include a first pixel circuit pair 601 and a second pixel circuit pair 602. In the second display area 200 and the third display area 300, multiple light-emitting units 20 are respectively connected to multiple first pixel circuit pairs 601 and multiple second pixel circuit pairs 602 in the second display area 200.

[0116] For example, in the embodiments of this disclosure, the light-emitting unit provided in the first display area can be called the first light-emitting unit, the light-emitting unit provided in the second display area can be called the second light-emitting unit, and the light-emitting unit provided in the third display area can be called the third light-emitting unit.

[0117] Because the second pixel circuit group 220 and the third pixel circuit group 230 are arranged alternately in both the X and Y directions, and the second pixel circuit group 220 and the third pixel circuit group 230 arranged in the same column along the Y direction are connected to different data lines 420, some pixel circuits in the first pixel circuit column 321 located in the second display area 200 are connected to the first data line 421. For example, the pixel circuits in the second pixel circuit group 220 located in the first pixel circuit column 321 are connected to the first data line 421, while the pixel circuits in the third pixel circuit group 230 located in the first pixel circuit column 321 are not connected to the first data line 421. Similarly, some pixel circuits in the second pixel circuit column 322 located in the second display area 200 are connected to the second data line 422. For example, the pixel circuits in the third pixel circuit group 230 located in the second pixel circuit column 322 are connected to the second data line 422, while the pixel circuits in the second pixel circuit group 220 located in the second pixel circuit column 322 are not connected to the second data line 422. Some pixel circuits in the third pixel circuit column 323 located within the second display area 200 are connected to the third data line 423. For example, the pixel circuits in the third pixel circuit group 230 within the third pixel circuit column 323 are connected to the third data line 423, while the pixel circuits in the second pixel circuit group 220 within the third pixel circuit column 323 are not connected to the third data line 423. Some pixel circuits in the fourth pixel circuit column 324 located within the second display area 200 are connected to the fourth data line 424. For example, the pixel circuits in the second pixel circuit group 220 within the fourth pixel circuit column 324 are connected to the fourth data line 424, while the pixel circuits in the third pixel circuit group 230 within the fourth pixel circuit column 324 are not connected to the fourth data line 424.

[0118] For example, such as Figures 1 to 4A As shown, multiple first pixel circuit pairs 601 connected to multiple light-emitting units 20 of the second display area 200 are connected to the first data line 421, multiple second pixel circuit pairs 602 connected to multiple light-emitting units 20 of the second display area 200 are connected to the fourth data line 424, multiple first pixel circuit pairs 601 connected to multiple light-emitting units 20 of the third display area 300 are connected to the second data line 422, and multiple second pixel circuit pairs 601 connected to multiple light-emitting units 20 of the third display area 300 are connected to the third data line 423.

[0119] For example, in the second pixel circuit group 220, two pixel circuits in the first pixel circuit pair 601 are connected to the first data line 421, and two pixel circuits in the second pixel circuit pair 602 are connected to the fourth data line 424. In the third pixel circuit group 230, two pixel circuits in the first pixel circuit pair 601 are connected to the second data line 422, and two pixel circuits in the second pixel circuit pair 602 are connected to the third data line 423.

[0120] For example, such as Figures 1 to 4A As shown, the first pixel circuit pair 601, which is connected to the first color light-emitting unit 201 and the third color light-emitting unit 203 in the second light-emitting unit group 210, is connected to the first data line 421, and the second pixel circuit pair 602, which is connected to the second color light-emitting unit pair 202 in the second light-emitting unit group 210, is connected to the fourth data line 424.

[0121] Figure 5A This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the first display area and the second display area according to an embodiment of this disclosure. Figure 5B for Figure 5A A schematic diagram of the membrane structure where the data line connection part is located, as shown. Figure 5C for Figure 5A A schematic diagram of the membrane structure where the data line is located, as shown. Figures 1 to 5DAs shown, at the boundary between the first display area 100 and the second display area 200, i.e., at the interval between the first sub-pixel circuit 031 and the second sub-pixel circuit 032, the second data line 422, the third data line 423, and the fourth data line 424, which are connected to at least one pixel circuit group, are disconnected to form a first break 4201. The first data line 421 remains continuous without a break. That is, the portion of the second data line 422 located in the second display area 200 is not connected to the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200. Similarly, the portion of the third data line 423 located in the second display area 200 is not connected to the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200; and the portion of the fourth data line 424 located in the second display area 200 is not connected to the portion located in the first display area 100 at the boundary between the first display area 100 and the second display area 200. The second data line 422 is located at the end 4221 of the first display area 100 near the second display area 200, and is connected to the end 4241 of the fourth data line 424 located in the second display area 200 near the first display area 100 via the data line connector 560. The data line connector 560 passes through the first break 4201 of the third data line 423. Here, the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 can refer to a continuous data line, such as the first data line 421 being a continuous data line; or they can refer to non-continuous data lines connected to the same column of pixel circuits, such as the second data line 422, the third data line 423, and the fourth data line 424. Thus, the second data line 422 connected to the first sub-pixel circuit and the second data line 423 connected to the second sub-pixel circuit are configured to transmit different signals; the third data line 423 connected to the first sub-pixel circuit and the third data line 423 connected to the second sub-pixel circuit are configured to transmit different signals; and the fourth data line 424 connected to the first sub-pixel circuit and the fourth data line 424 connected to the second sub-pixel circuit are configured to transmit different signals.

[0122] For example, the second data line 422 connected to the first sub-pixel circuit 031 and the second data line 422 connected to the second sub-pixel circuit 032 are configured to transmit different signals; the third data line 423 connected to the first sub-pixel circuit 031 and the third data line 423 connected to the second sub-pixel circuit 032 are configured to transmit different signals; and the fourth data line 424 connected to the first sub-pixel circuit 031 and the fourth data line 424 connected to the second sub-pixel circuit 032 are configured to transmit different signals. Although in this application, data lines located on the same straight line in the first and second display areas are all referred to as second data lines, third data lines, or fourth data lines, second data lines (third data lines or fourth data lines) located in different display areas are configured to transmit different signals.

[0123] For example, this embodiment of the present disclosure schematically shows that the endpoint of the second data line in the first display area near the second display area is connected to the endpoint of the fourth data line in the second display area near the first display area through a data line connection portion. However, it is not limited to this. The endpoint of the second data line in the first display area near the second display area can also be connected to the endpoint of the third data line in the second display area near the first display area through a data line connection portion.

[0124] In this embodiment of the disclosure, the pixel circuit located in the first display area is called the first sub-pixel circuit, the pixel circuit connected to the light-emitting unit located in the second display area is called the second sub-pixel circuit, and the pixel circuit connected to the light-emitting unit located in the third display area is called the third sub-pixel circuit.

[0125] For example, such as Figure 5A As shown, in this embodiment of the present disclosure, a plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include a first color light-emitting unit and a third color light-emitting unit; a plurality of light-emitting units 20 connected to the second pixel circuit column 322 in the first display area 100 include a pair of second color light-emitting units; a plurality of light-emitting units 20 connected to the third pixel circuit column 323 in the first display area 100 include a first color light-emitting unit and a third color light-emitting unit; and a plurality of light-emitting units 20 connected to the fourth pixel circuit column 324 in the first display area 100 include a pair of second color light-emitting units.

[0126] In this embodiment, data signals are transmitted via data lines from the source driver integrated circuit located on the side of the first display area away from the second display area to the pixel circuits in the first and second display areas. The data signal transmitted to a pixel circuit connected to a color-emitting unit in the second display area should be the same as the data signal transmitted to a pixel circuit connected to the same color-emitting unit in the first display area. Therefore, when the same row of pixel circuits in the first display area is connected to the same data line, and a pair of pixel circuits in the second display area is connected to the same data line, it is easy for the data signal transmitted to a pixel circuit connected to a first color-emitting unit in the first display area to be the same as the data signal transmitted to a pair of pixel circuits connected to a pair of second color-emitting units in the second display area, resulting in a mismatch between the data signals in the first and second display areas.

[0127] For example, in the first display area 100, each first light-emitting unit group 110 includes a first color light-emitting unit, a second color light-emitting unit pair, and a third color light-emitting unit. Each second color light-emitting unit pair includes a first light-emitting unit block and a second light-emitting unit block. The first color light-emitting unit and the third color light-emitting unit are arranged in a direction parallel to the extension direction of the data line (Y direction). The first light-emitting unit block and the second light-emitting unit block are arranged in the Y direction. The first color light-emitting unit and the second color light-emitting unit pair are arranged in the X direction intersecting the Y direction. In two adjacent first light-emitting unit groups, the first color light-emitting unit points to the third color light-emitting unit in opposite directions. That is, the light-emitting units connected to the four pixel circuits in the pixel circuit column group located near the second display area in the first display area are, in order, the first color light-emitting unit, the first light-emitting unit block, the third color light-emitting unit, and the second light-emitting unit block. And the four light-emitting units connected to the second row of pixel circuits in the pixel circuit column group located near the second display area in the first display area are, in order, the third color light-emitting unit, the second light-emitting unit block, the first color light-emitting unit, and the first light-emitting unit block. Therefore, the arrangement of the first and third color light-emitting units connected to the pixel circuits of the first and third pixel circuit columns is different, and the arrangement of the first and second light-emitting unit blocks connected to the pixel circuits of the second and fourth pixel circuit columns is different. The data signals transmitted by the data lines are related to the arrangement of the corresponding color light-emitting units, and both the first and second display areas should transmit matching data signals according to the above-mentioned light-emitting unit arrangement.

[0128] For example, such as Figures 1 to 5AAs shown, the plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the second display area 200 include alternating first-color light-emitting units 201 and third-color light-emitting units 203. The light-emitting unit connected to the pixel circuit of the first pixel circuit column 321 located in the second display area 200 near the first display area 100 is, for example, the third-color light-emitting unit 203. The plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include alternating first-color light-emitting units and third-color light-emitting units. The light-emitting unit connected to the pixel circuit of the first pixel circuit column 321 located in the first display area 100 near the second display area 200 is the first-color light-emitting unit. Therefore, the pixel circuit in the row of pixel circuits closest to the second display area in the first display area and connected to the first data line is connected to the first color light-emitting unit, and the pixel circuit in the row of pixel circuits closest to the first display area in the second display area and connected to the same first data line is connected to the third color light-emitting unit. The arrangement of the light-emitting units matches the data signal transmitted by the first data line, so the first data line can remain connected at the junction of the first display area and the second display area without needing to be disconnected at the junction of the two display areas.

[0129] For example, such as Figures 1 to 5A As shown, the plurality of second-color light-emitting unit pairs 202 connected to the fourth pixel circuit column 324 in the second display area 200 include alternating first light-emitting unit blocks 202-1 and second light-emitting unit blocks 202-2. For example, the light-emitting unit connected to the pixel circuit of the fourth pixel circuit column 324 located in the second display area 200 near the first display area 100 is the second light-emitting unit block 202-2. Similarly, the plurality of second-color light-emitting unit pairs connected to the fourth pixel circuit column 324 in the first display area 100 include alternating first light-emitting unit blocks and second light-emitting unit blocks. The light-emitting unit connected to the pixel circuit of the fourth pixel circuit column 324 located in the first display area 100 near the second display area 200 is also a second light-emitting unit block. Therefore, if the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the second display area in the first display area and the light-emitting unit connected to the pixel circuit of the row of pixel circuits near the first display area in the second display area and the light-emitting unit of the same type are the same light-emitting unit, then the data signal of the fourth data line connected to the fourth pixel circuit column in the first display area and the data signal of the fourth data line connected to the fourth pixel circuit column in the second display area do not match. Therefore, the fourth data line should be disconnected at the junction of the first display area and the second display area.

[0130] For example, such as Figures 1 to 5AAs shown, the multiple pairs of second color light-emitting units connected to the second pixel circuit column 322 in the first display area 100 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the light-emitting unit connected to the pixel circuit of the second pixel circuit column 322 located in the row of the first display area 100 near the second display area 200 is the first light-emitting unit block. Therefore, when the data signal of the fourth data line connected to the fourth pixel circuit column of the second display area matches the data signal of the second data line connected to the second pixel circuit column of the first display area, the portion of the second data line located in the first display area and the portion located in the second display area are disconnected at the boundary between the two display areas. The second data line located in the first display area is connected to the fourth data line located in the second display area via a data line connection portion to satisfy the unified algorithm processing of the integrated circuit (IC) in the first and second display areas.

[0131] In this embodiment of the present disclosure, at the junction of the first display area and the second display area, the second data line, the third data line and the fourth data line are disconnected, and the end of the second data line located in the first display area near the second display area is connected to the end of the fourth data line located in the second display area near the first display area through the data line connection part, thereby ensuring the matching of the data signal transmitted from the data line to the light-emitting unit in the first display area with the data signal transmitted from the data line to the light-emitting unit in the second display area.

[0132] For example, such as Figures 5A to 5C As shown, the data line connector 560 and the multiple data lines 420 are located on different layers. For example, along a direction perpendicular to the substrate, the data line connector 560 overlaps with the power signal line 460. Since the data line connector needs to pass through the first break of the third data line and the two power signal lines to connect the endpoints of the second and fourth data lines, the data line connector needs to be located on a different layer from the data lines.

[0133] For example, such as Figures 5A to 5C As shown, the data line connector 560 and the reset power signal line 410 are located on the same layer for ease of design.

[0134] For example, such as Figures 5A to 5C As shown, a data line connection portion 560 is provided between the second terminal of the threshold compensation transistor T2 and the first terminal of the first reset control transistor T7 in the two pixel circuits of the first pixel circuit row 31 adjacent to the second pixel circuit row 200 in the first display area 100 and located in the third pixel circuit column 323 and the fourth pixel circuit column 324.

[0135] In this embodiment of the disclosure, the junction of the first display area 100 and the second display area 200 refers to the interval between the first terminal of the first reset transistor and the second terminal of the data write transistor in a row of pixel circuits 31 that is close to the second display area 200 in the first display area 100.

[0136] For example, in a row of pixel circuits 31 adjacent to the second display area 200 in the first display area 100, the distance between the second electrode of the threshold compensation transistor T2 and the second electrode of the first reset control transistor T7 in the second direction is 7 to 12 micrometers so that a data line connection portion 560 is provided between the second electrode of the threshold compensation transistor T2 and the first electrode of the first reset control transistor T7.

[0137] For example, in the pixel circuit of the first display area 100, the distance between the edges of the second connection portion 520 and the third connection portion 530 that are close to each other in the second direction is 7 to 12 micrometers so that a data line connection portion 560 is provided between the second connection portion 520 and the third connection portion 530. In this embodiment of the present disclosure, although the first connection portion and the data line connection portion are respectively provided in the second display area and the boundary between the first display area and the second display area, by adjusting the distance between the second electrode of the threshold compensation transistor of the pixel circuit and the first electrode of the first reset control transistor, the first connection portion and the data line connection portion can both be provided in a larger space reserved between the second electrode of the threshold compensation transistor of the pixel circuit and the first electrode of the first reset control transistor to prevent interference with other signals.

[0138] For example, Figure 6 This is a schematic diagram of a portion of the pixel circuit structure at the boundary between the edge areas of the first display area and the third display area according to an embodiment of this disclosure. For example, as... Figure 6As shown, the multiple dummy pixel circuit columns in the third display area include groups of four adjacent dummy pixel circuit columns. Each group of dummy pixel circuit columns includes a first dummy pixel circuit column 0341, a second dummy pixel circuit column 0342, a third dummy pixel circuit column 0343, and a fourth dummy pixel circuit column 0344 arranged sequentially along the second direction. At least a portion of the dummy pixel circuits 0344 in the first dummy pixel circuit column 0341, at least a portion of the dummy pixel circuits 0344 in the second dummy pixel circuit column 0342, and at least a portion of the dummy pixel circuits 0344 in the third dummy pixel circuit column 0344... At least a portion of the dummy pixel circuit 034 of 43 and at least a portion of the dummy pixel circuit 0344 of the fourth dummy pixel circuit array are connected to the first data line 421, the second data line 422, the third data line 423 and the fourth data line 424 arranged sequentially along the second direction, respectively. At the interval between the dummy pixel circuit 034 and the first pixel circuit 031 (for example, at the junction of the edge area 302 of the third display area 300 and the first display area 100), the third data line 423 and the fourth data line 424 are disconnected to form a second break 4202.

[0139] For example, the first dummy pixel circuit column 0341, the second dummy pixel circuit column 0342, the third dummy pixel circuit column 0343 and the fourth dummy pixel circuit column 0344 mentioned above can also be referred to as the first pixel circuit column, the second pixel circuit column, the third pixel circuit column and the fourth pixel circuit column, respectively.

[0140] For example, such as Figures 1 to 6 As shown, the pixel circuit pair connected to the first color light-emitting unit and the third color light-emitting unit in the third light-emitting unit group 310 can be one of the first pixel circuit pair 601 and the second pixel circuit pair 602, and the pixel circuit pair connected to the second color light-emitting unit pair in the third light-emitting unit group 310 can be the other of the first pixel circuit pair 601 and the second pixel circuit pair 602.

[0141] For example, a pixel circuit pair connected to the first color light-emitting unit and the third color light-emitting unit of the third light-emitting unit group 310 can be connected to one of the second data line 422 and the third data line 423, and a pixel circuit pair connected to the first light-emitting unit block and the second light-emitting unit block of the third light-emitting unit group 310 can be connected to the other of the second data line 422 and the third data line 423. For example, a pixel circuit pair connected to the first color light-emitting unit and the third color light-emitting unit of the third light-emitting unit group 310 can be connected to the third data line 423, and a pixel circuit pair connected to the first light-emitting unit block and the second light-emitting unit block of the third light-emitting unit group 310 can be connected to the second data line 422. Because the second data line and the third data line are disconnected at the boundary between the first display area and the second display area, the pixel circuit connected to the third light-emitting unit group cannot receive a matching data signal from the data line in the first display area connected to the second display area. Therefore, in this embodiment of the present disclosure, a first data line and a second data line, which are continuous at the junction of the edge area of ​​the third display area and the first display area, are respectively connected to the pixel circuit pairs connected to the first light-emitting unit block and the second light-emitting unit block of the third light-emitting unit group 310, as well as the pixel circuit pairs connected to the first color light-emitting unit and the third light-emitting unit of the third light-emitting unit group 310, so as to realize the input of matching data signals to the pixel circuits connected to the third light-emitting unit group, and to satisfy the unified algorithm processing of the integrated circuit in the first display area and the third display area.

[0142] For example, the plurality of light-emitting units connected to the third pixel circuit column 323 of the second display area 200 in the third display area 300 include alternating first-color light-emitting units and third-color light-emitting units, and the light-emitting units connected to the pixel circuits of the first row of the second display area 200 away from the first display area 100 and the third pixel circuit column 323 are third-color light-emitting units. The plurality of light-emitting units 20 connected to the first pixel circuit column 321 in the first display area 100 include alternating first-color light-emitting units and third-color light-emitting units, and the data line connected to the pixel circuits of the first-color light-emitting units in the row of the third display area 300 close to the first display area 100 is a first data line.

[0143] For example, the plurality of light-emitting units connected to the second pixel circuit column 322 of the second display area 200 in the third display area 300 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the light-emitting unit connected to the pixel circuit in the first row of the second display area 200 away from the first display area 100 and in the second pixel circuit column 322 is the second light-emitting unit block. The plurality of light-emitting units 20 connected to the second pixel circuit column 322 in the first display area 100 include alternating first light-emitting unit blocks and second light-emitting unit blocks, and the data line connected to the pixel circuit of the first light-emitting unit block in the row of the third display area 300 close to the first display area 100 is the second data line. Therefore, the data signals on the first and second data lines in the area where the edge areas of the first and third display areas meet are matched with the data signals on the third and second data lines in the second display area, respectively. However, the data signals transmitted by the third and fourth data lines in the area where the edge areas of the first and third display areas meet do not match the data signals on the third and second data lines in the second display area. Thus, at the boundary between the edge area of ​​the third display area and the first display area, the first and second data lines remain connected, while the third and fourth data lines are disconnected.

[0144] For example, such as Figures 1 to 6 As shown, the display substrate also includes a peripheral region 303 located on the side of the third display area 300 away from the first display area 100, a first data line 421 located in the edge region 302 of the third display area 300 bypasses the central region 301 to connect to one of the second data line 422 and the third data line 423 of the second display area 200 in the peripheral region 303, and the second data line 422 located in the edge region 302 of the third display area 300 bypasses the central region 301 to connect to the other of the second data line 422 and the third data line 423 of the second display area 200 in the peripheral region 303.

[0145] For example, an embodiment of this disclosure schematically shows that a first data line 421 located in the edge area 302 of the third display area 300 bypasses the center area 301 to connect to a third data line 423 in the peripheral area 303 of the second display area 200, and a second data line 422 located in the edge area 302 of the third display area 300 bypasses the center area 301 to connect to a second data line 422 in the peripheral area 303 of the second display area 200, thereby facilitating the routing of data lines in the third and second display areas.

[0146] For example, such as Figures 1-6As shown, another embodiment of this disclosure provides a display substrate including a first display area 100 and a second display area 200. The first display area 100 includes a plurality of first light-emitting units 110-1 and a plurality of first sub-pixel circuits 031. The plurality of first light-emitting units 110-1 includes adjacent rows of first light-emitting units 110-11 and second light-emitting units 110-12. Each row of light-emitting units is connected to a corresponding row of first sub-pixel circuits 031. The second display area 200 includes a plurality of second light-emitting units 120-1 and a plurality of second sub-pixel circuits 032. The plurality of second light-emitting units 120-1 includes adjacent rows of third light-emitting units 120-11 and fourth light-emitting units 120-12. Each row of light-emitting units in the second display area 200 is connected to a row of first sub-pixel circuit pairs 032-1. Each row of first sub-pixel circuit pairs 032-1 includes two adjacent rows of second sub-pixel circuits 032.

[0147] For example, such as Figures 1-6 As shown, the display substrate also includes multiple first sub-data lines 4210, multiple second sub-data lines 4220, multiple third sub-data lines 4230, and multiple fourth sub-data lines 4240 extending along the second direction. Each first sub-data line 4210 is connected to each first light-emitting unit column 110-11, each second sub-data line 4220 is connected to each second light-emitting unit column 110-12, each third sub-data line 4230 is connected to each third light-emitting unit column 120-11, and each fourth sub-data line 4240 is connected to each fourth light-emitting unit column 120-12. The second direction intersects with the first direction.

[0148] For example, such as Figures 1-6 As shown, the arrangement direction of the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12 is the same as that of the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12. A column of first sub-pixel circuits 031 connected to the first light-emitting unit column 110-11 and a column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column. The first sub-data line 4210 and the third sub-data line 4230 are a continuous data line extending along the second direction. The two columns of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 and the column of first sub-pixel circuits 031 connected to the second light-emitting unit column 110-12 are located in different columns. The second sub-data line 4220 and the fourth sub-data line 4240 are connected through a data line connection part 560, and the extension direction of the data line connection part 560 intersects with the second direction.

[0149] The first sub-data line 4210, the second sub-data line 4220, the third sub-data line 4230, and the fourth sub-data line 4240 here have different meanings from the first data line 421, the second data line 422, the third data line 423, and the fourth data line 424 in the above embodiments. Here, the first sub-data line 4210 refers only to the data line in the first data line 421 in the above embodiments that connects to the pixel circuit in the first display area. Here, the second sub-data line 4220 refers only to the data line in the second data line 422 in the above embodiments that connects to the pixel circuit in the first display area. Here, the third sub-data line 4230 refers only to the data line in the first data line 421 in the above embodiments that connects to the pixel circuit in the second display area. Here, the fourth sub-data line 4240 refers only to the data line in the fourth data line 424 in the above embodiments that connects to the pixel circuit in the second display area.

[0150] At the junction of the pixel circuits in the first display area and the second display area, the second sub-data line and the fourth sub-data line are disconnected, and the second sub-data line and the fourth sub-data line are connected through the data line connector, thereby ensuring the matching of the data signal transmitted from the data line to the light-emitting unit in the first display area and the data signal transmitted from the data line to the light-emitting unit in the second display area.

[0151] For example, such as Figures 1-6 As shown, a column of first sub-pixel circuits 031 connected to the second light-emitting unit column 110-12 and another column of second sub-pixel circuits 032 connected to the third light-emitting unit column 120-11 are located in the same column.

[0152] For example, such as Figures 1-6 As shown, the first display area 100 also includes a fifth light-emitting unit column 110-13 and a sixth light-emitting unit column 110-14 arranged adjacent to each other. The first light-emitting unit column 110-11, the second light-emitting unit column 110-12, the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14 are arranged repeatedly along the first direction, and the third light-emitting unit column 120-11 and the fourth light-emitting unit column 120-12 are arranged alternately along the first direction.

[0153] For example, such as Figures 1-6 As shown, the display substrate also includes multiple fifth sub-data lines 4250 and multiple sixth sub-data lines 4260 extending along the second direction. Each fifth sub-data line 4250 is connected to each fifth light-emitting unit column 110-13, and each sixth sub-data line 4260 is connected to each sixth light-emitting unit column 110-14.

[0154] For example, such as Figures 1-6As shown, a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column. A column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and another column of second sub-pixel circuits 032 connected to the fourth light-emitting unit column 120-12 are located in the same column. There is a gap between the sixth sub-data line 4260 or the fifth sub-data line 4250 and the fourth sub-data line 4240. Figure 5D The illustration schematically shows that the pixel circuit connected to the sixth sub-data line 4260 and the pixel circuit connected to the fourth sub-data line 4240 are located in the same column, with a gap between them. However, this is not a limitation; when the pixel circuit connected to the fourth sub-data line and the pixel circuit connected to the fifth sub-data line are located in the same column, a gap is also provided between them. Here, the fifth sub-data line 4250 refers only to the data line in the third data line 423 of the above embodiment that connects to the pixel circuit in the first display area, and the sixth sub-data line 4260 refers to the data line in the fourth data line 424 of the above embodiment that connects to the pixel circuit in the first display area.

[0155] For example, Figure 5E This is a partial plan view of a first display area and a second display area in a display substrate provided according to another example of an embodiment of the present disclosure. Figure 5E The example shown is the same as Figure 5D The difference in the example shown is the arrangement of the pixels. Figure 5D The pixel arrangement in the example shown is GGRB. Figure 5E The pixel arrangement in the example shown is real RGB. Figure 5EAs shown, every six RGB light-emitting units in the first display area 100 constitute one repeating cycle. The data line 420 connecting the first column of R light-emitting units in the first display area 100 and the data line 420 connecting the first column of R light-emitting units in the second display area 200 are the same continuous data line; there is a gap between the data line 420 connecting the second column of G light-emitting units in the first display area 100 and the data line 420 connecting the second column of R light-emitting units in the second display area 200, and the data line 420 connecting the second column of G light-emitting units in the first display area 100 is connected to the data line 420 connecting the third column of G (or fourth column of G) light-emitting units in the second display area 200 via a data line connector 560; there is a gap between the data line 420 connecting the third column of B light-emitting units in the first display area 100 and the data line 420 connecting the third column of G light-emitting units in the second display area 200. The data lines 420 connected to the third column B light-emitting units of the first display area 100 are connected to the data lines 420 connected to the fifth column B (or sixth column B) light-emitting units of the second display area 200 via the data line connection part 560; there is a gap between the data lines 420 connected to the fourth column G light-emitting units of the first display area 100 and the data lines 420 connected to the fourth column G light-emitting units of the second display area 200; there is a gap between the data lines 420 connected to the fifth column R light-emitting units of the first display area 100 and the data lines 420 connected to the fifth column B light-emitting units of the second display area 200; there is a gap between the data lines 420 connected to the sixth column G light-emitting units of the first display area 100 and the data lines 420 connected to the sixth column B light-emitting units of the second display area 200. The embodiments disclosed herein are not limited to the above-described connections. As long as one R light-emitting unit in the first display area and one R light-emitting unit in the second display area are connected to the same data line, one B light-emitting unit in the first display area and one B light-emitting unit in the second display area are connected to the same data line, and one G light-emitting unit in the first display area and one G light-emitting unit in the second display area are connected to the same data line, it is acceptable.

[0156] For example, such as Figures 1-6 As shown, the first display area 100 includes a plurality of first sub-light-emitting unit groups 1-1 and a plurality of second sub-light-emitting unit groups 1-2 arranged alternately along a first direction and a second direction. The first sub-light-emitting unit group 1-1 includes light-emitting units in the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12. The second sub-light-emitting unit group 1-2 includes light-emitting units in the fifth light-emitting unit column 110-13 and the sixth light-emitting unit column 110-14. The second display area 200 includes a plurality of third sub-light-emitting unit groups 1-3.

[0157] For example, such as Figures 1-6As shown, each sub-light-emitting unit group includes a first-color light-emitting unit R, a pair of second-color light-emitting units G1 and G2, and a third-color light-emitting unit B. The first-color light-emitting unit R and the third-color light-emitting unit B are arranged along a second direction. The pair of second-color light-emitting units G1 and G2 includes two second-color light-emitting units arranged along the second direction. The first-color light-emitting unit R and the second-color light-emitting unit pairs G1 and G2 are arranged along a first direction. The arrangement direction of the first-color light-emitting unit R and the third-color light-emitting unit B in the first sub-light-emitting unit group 1-1 is opposite to that in the second sub-light-emitting unit group 1-2. The relative position distribution of each light-emitting unit in the first sub-light-emitting unit group 1-1 is the same as that in the third sub-light-emitting unit group 1-3. This embodiment of the present disclosure illustrately uses a red light-emitting unit as the first color light-emitting unit, a green light-emitting unit pair as the second color light-emitting unit pair, and a blue light-emitting unit as the third color light-emitting unit, but it is not limited to this. For example, the first color light-emitting unit can be a blue light-emitting unit, the second color light-emitting unit pair can be a green light-emitting unit pair, and the third color light-emitting unit can be a red light-emitting unit. For example, the first color light-emitting unit can be a green light-emitting unit, the second color light-emitting unit pair can be a red light-emitting unit pair, and the third color light-emitting unit can be a blue light-emitting unit.

[0158] For example, such as Figures 1-6 As shown, the substrate also includes a third display area 300, and the second display area 200 includes a plurality of third sub-pixel circuits 033. The third display area 300 includes a plurality of third light-emitting units 130-1. The plurality of third light-emitting units 130-1 include a seventh light-emitting unit column 130-11 and an eighth light-emitting unit column 130-12 arranged adjacent to each other. The arrangement direction of the first light-emitting unit column 110-11 and the second light-emitting unit column 110-12 is the same as the arrangement direction of the seventh light-emitting unit column 130-11 and the eighth light-emitting unit column 130-12. Each light-emitting unit column in the third display area 300 is connected to a column of second sub-pixel circuit pairs 033-1. Each column of second sub-pixel circuit pairs 033-1 includes two adjacent columns of third sub-pixel circuits 033.

[0159] For example, such as Figures 1-6 As shown, the display substrate also includes multiple seventh sub-data lines 4270 and multiple eighth sub-data lines 4280 extending along the second direction. Each seventh sub-data line 4270 is connected to each seventh light-emitting unit column 130-11, and each eighth sub-data line 4280 is connected to each eighth light-emitting unit column 130-12.

[0160] For example, such as Figures 1-6As shown, at least one of the seventh sub-data line 4270 and the eighth sub-data line 4280 is disposed between the third sub-data line 4230 and the fourth sub-data line 4240. Here, the seventh sub-data line 4270 refers only to the data line in the second data line 422 of the above embodiment that connects to the pixel circuit in the second display area, and the eighth sub-data line 4280 refers to the data line in the third data line 423 of the above embodiment that connects to the pixel circuit in the second display area.

[0161] For example, such as Figures 1-6 As shown, the seventh sub-data line 4270 and the eighth sub-data line 4280 are both disposed between the third sub-data line 4230 and the fourth sub-data line 4240, and a gap is provided between the eighth sub-data line 4280 and the fifth sub-data line 4250 to provide a data line connection part 560.

[0162] For example, the eighth sub-data line 4280 and the fifth sub-data line 4250 have a break at the interval between the pixel circuit of the first display area and the pixel circuit of the second display area, and the connecting part 560 is provided at the break.

[0163] For example, such as Figures 1-6 As shown, multiple third sub-pixel circuits 033 are configured with multiple fourth sub-light-emitting unit groups 1-4. The relative position distribution of each light-emitting unit in each fourth sub-light-emitting unit group 1-4 is the same as the relative position distribution of each light-emitting unit in the third sub-light-emitting unit group 1-3. The first sub-pixel circuit pair 032-1 connected to the third sub-light-emitting unit group 1-3 and the second sub-pixel circuit pair 033-1 connected to the fourth light-emitting unit group 1-4 are arranged alternately along the first direction and the second direction.

[0164] For example, such as Figures 1-6 As shown, the third display area 300 includes a central area 301 and an edge area 302 surrounding the central area 301. The edge area 302 includes a plurality of dummy pixel circuits arranged along a first direction and a second direction to form a plurality of dummy pixel circuit columns 320-1 and a plurality of dummy pixel circuit rows 320-2.

[0165] For example, such as Figures 1-6 As shown, the multiple virtual pixel circuit columns 320-1 in the third display area 300 include virtual pixel circuit column groups 3201 composed of four adjacent columns. Each virtual pixel circuit column group 3201 includes a first virtual pixel circuit column 0341, a second virtual pixel circuit column 0342, a third virtual pixel circuit column 0343 and a fourth virtual pixel circuit column 0344 arranged sequentially along the first direction.

[0166] For example, such as Figures 1-6As shown, the display substrate also includes a first dummy data line 431, a second dummy data line 432, a third dummy data line 433, and a fourth dummy data line 434. The first dummy data line 431 is connected to the first dummy pixel circuit column 0341, the second dummy data line 432 is connected to the second dummy pixel circuit column 0342, the third dummy data line 433 is connected to the third dummy pixel circuit column 0343, and the fourth dummy data line 434 is connected to the fourth dummy pixel circuit column 0344.

[0167] For example, such as Figures 1-6 As shown, a column of first sub-pixel circuits 031 and a column of first dummy pixel circuits 0341 connected to the first light-emitting unit column 110-11 are located in the same column; a column of first sub-pixel circuits 031 and a column of second dummy pixel circuits 0342 connected to the second light-emitting unit column 110-12 are located in the same column; a column of first sub-pixel circuits 031 connected to the fifth light-emitting unit column 110-13 and a column of third dummy pixel circuits 0343 are located in the same column; and a column of first sub-pixel circuits 031 connected to the sixth light-emitting unit column 110-14 and a column of fourth dummy pixel circuits 0344 are located in the same column. The two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are consecutive data lines, or the two data lines connected to the second light-emitting unit group 1-2 and the corresponding two dummy data lines are consecutive data lines. Figure 6 The diagram schematically shows that the two data lines connected to the first light-emitting unit group 1-1 and the corresponding two dummy data lines are two continuous data lines.

[0168] For example, such as Figures 1-6 As shown, the display substrate also includes a peripheral area 400 located on the side of the third display area 300 away from the first display area 100. Two dummy data lines connected to the first light-emitting unit group 1-1 or the second light-emitting unit group 1-2 bypass the central area 301 to connect the seventh sub-data line 4270 and the eighth sub-data line 4280 in the peripheral area 400, respectively.

[0169] For example, such as Figures 1-6 As shown, the first dummy data line 431 and the first sub-data line 4210 are a continuous data line, the second dummy data line 432 and the second sub-data line 4220 are a continuous data line, there is a gap between the third dummy data line 433 and the fifth sub-data line 4250, and there is a gap between the fourth dummy data line 434 and the sixth sub-data line 4260.

[0170] For example, such as Figures 1-6 As shown, the first dummy data line 431 bypasses the central area 301 to connect to the seventh sub-data line 4270 in the peripheral area 400, and the second dummy data line bypasses the central area to connect to the eighth data line in the peripheral area.

[0171] For example, Figure 7 This is a schematic diagram of the second electrode of the light-emitting unit group located in the first display area according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of the second electrode of the light-emitting unit group located at the non-edge of the second display area according to an embodiment of the present disclosure. Figure 9 This is a schematic diagram of the second electrode of the light-emitting unit group located in the third display area according to an embodiment of the present disclosure. Figures 1 to 9 As shown, the second electrode 22 of each light-emitting unit 20 includes a main electrode 22-1 and a connecting electrode 22-2. The shape of the main electrode 22-1 is substantially the same as the shape of the effective light-emitting area of ​​each light-emitting unit 20. The connecting electrode 22-2 is configured to be electrically connected to the second electrode of the first light-emitting control transistor T6 of the pixel circuit via a fifth connecting portion 550. Each light-emitting unit group located in the display area includes multiple light-emitting units of different colors. For example, each light-emitting unit group includes a first color light-emitting unit 201, a pair of second color light-emitting units 202, and a third color light-emitting unit 203.

[0172] For example, such as Figures 1 to 9 As shown, the area of ​​the main electrode 22-1 of a color-emitting unit located in at least one of the non-edge region of the second display area 200 and the third display area 300 is larger than the area of ​​the main electrode 22-1 of the light-emitting unit 20 located in the first display area 100 and having the same color as the aforementioned color-emitting unit. The area of ​​the main electrode of each color-emitting unit is related to the area of ​​its effective light-emitting area. In this embodiment of the present disclosure, by setting the area of ​​the main electrode of a color-emitting unit located in at least one of the non-edge region of the second display area and the third display area to be larger than the area of ​​the main electrode of the light-emitting unit located in the first display area and having the same color as the aforementioned color-emitting unit, the area of ​​the effective light-emitting area of ​​the color-emitting unit located in at least one of the non-edge region of the second display area and the third display area can be designed to be larger than the area of ​​the effective light-emitting area of ​​the light-emitting unit located in the first display area and having the same color as the aforementioned color-emitting unit.

[0173] In this embodiment, since the density of the light-emitting unit groups in the second and third display areas is less than that in the first display area, by setting the area of ​​the main electrode in at least one of the light-emitting units in the second and third display areas to be greater than the area of ​​the main electrode in the light-emitting unit in the first display area, the area of ​​the effective light-emitting area of ​​the light-emitting unit of one color located in the non-edge area of ​​the second display area and at least one of the third display areas is designed to be greater than the area of ​​the effective light-emitting area of ​​the light-emitting unit located in the first display area and having the same color as the aforementioned light-emitting unit. This can increase the brightness of at least one of the second and third display areas while ensuring the lifespan of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0174] For example, the embodiments of this disclosure schematically show that in the non-edge area of ​​the second display area 200 and the third display area 300, the area of ​​the main electrode 22-1 of a color light-emitting unit is larger than the area of ​​the main electrode 22-1 of the light-emitting unit 20 in the first display area 100 that has the same color as the aforementioned color light-emitting unit. This makes the area of ​​the effective light-emitting area of ​​the color light-emitting unit in the non-edge area of ​​the second display area and the third display area larger than the area of ​​the effective light-emitting area of ​​the light-emitting unit in the first display area that has the same color as the aforementioned color light-emitting unit. As a result, the brightness of the second and third display areas can be increased while ensuring the lifespan of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0175] For example, in one embodiment of this disclosure, each light-emitting unit in the first, second, and third display areas is connected to a pixel circuit. That is, each light-emitting unit in the second and third display areas may not be connected to a pixel circuit, but only to a single pixel circuit. In this case, the density of the light-emitting unit groups in the second and third display areas is less than that in the first display area. By setting the area of ​​the main electrode in at least one of the light-emitting units in the second and third display areas to be larger than the area of ​​the main electrode in the light-emitting unit in the first display area, the area of ​​the effective light-emitting area of ​​a light-emitting unit of one color located in the non-edge area of ​​the second display area and at least one of the light-emitting units in the third display area is designed to be larger than the area of ​​the effective light-emitting area of ​​a light-emitting unit of the same color as the aforementioned light-emitting unit located in the first display area, the display effect of each display area can be made as uniform as possible.

[0176] For example, in another embodiment of this disclosure, each pixel circuit group includes multiple pixel circuits, and at least one of the second pixel circuit group and the third pixel circuit group in the second display area includes multiple pixel circuit pairs. The two pixel circuits in each pixel circuit pair are configured to be electrically connected to the second electrode of the same light-emitting unit. For example, both the second pixel circuit group and the third pixel circuit group in the second display area include multiple pixel circuit pairs. Each pixel circuit pair in the second pixel circuit group is connected to each light-emitting unit in the second light-emitting unit group, and each pixel circuit pair in the third pixel circuit group is connected to each light-emitting unit in the third light-emitting unit group. The density of the light-emitting unit groups in the second and third display areas is lower than that in the first display area. By combining the design of the pixel circuits connected to the light-emitting units in the second and third display areas as pixel circuit pairs with the design of the area of ​​the main electrode in the light-emitting units in the second and third display areas being larger than that in the light-emitting units in the first display area, the current and brightness of the light-emitting units in the second and third display areas can be increased by 1.8 to 2 times that under pixel circuit driving conditions, while ensuring the lifespan of the light-emitting materials in the light-emitting units. This solves the problem of low current and brightness in the second and third display areas and achieves a more uniform full-screen visual display effect.

[0177] For example, such as Figures 1 to 9 As shown, each light-emitting unit group includes a first color light-emitting unit 201. The area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in at least one of the non-edge region of the second display area 200 and the third display area 300 to the area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in the first display area 100 is 1.5 to 2.5. For example, each light-emitting unit group includes a first color light-emitting unit 201. The area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in at least one of the non-edge region of the second display area 200 and the third display area 300 to the area ratio of the main electrode 2011 of each first color light-emitting unit 201 located in the first display area 100 is 1.9 to 2.1.

[0178] For example, the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 located in the non-edge area of ​​the second display area 200 and at least one of the third display area 300 is 2 times the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 located in the first display area 100.

[0179] For example, such as Figures 1 to 9As shown, the main electrode 2011 and the effective light-emitting area of ​​the first color light-emitting unit 201 located in each display area are both hexagonal. The area of ​​the connecting electrode 2012 of the non-edge first color light-emitting unit 201 located in the second display area 200 can be larger than the area of ​​the connecting electrode 2012 of the first color light-emitting unit 201 located in the first display area 100 to achieve connection with the pixel circuit pair.

[0180] For example, such as Figures 1 to 9 As shown, the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5 compared to the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 located in the first display area 100. For example, the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.9 to 2.1 compared to the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 located in the first display area 100.

[0181] For example, the area of ​​the effective light-emitting area of ​​each second color light-emitting unit pair 202 in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the effective light-emitting area of ​​each second color light-emitting unit pair 202 in the first display area 100.

[0182] For example, such as Figures 1 to 9 As shown, the area of ​​the main electrode 2021-1 of each first light-emitting unit block 202-1 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5 of the area of ​​the main electrode 2021-1 of each first light-emitting unit block 202-1 located in the first display area 100. For example, the area of ​​the main electrode 2021-2 of each second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5 of the area of ​​the main electrode 2021-2 of each second light-emitting unit block 202-2 located in the first display area 100 is 1.5 to 2.5 of the area of ​​the main electrode 2021-2 of the second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5 of the area of ​​the main electrode 2021-2 of the second light-emitting unit block 202-2 located in the first display area 100. For example, the area of ​​the main electrode 2021-1 of each first light-emitting unit block 202-1 located in at least one of the non-edge region of the second display area 200 and the third display area 300 is 1.9 to 2.1 compared with the area of ​​the main electrode 2021-1 of each first light-emitting unit block 202-1 located in the first display area 100. For example, the area of ​​the main electrode 2021-2 of each second light-emitting unit block 202-2 located in at least one of the non-edge region of the second display area 200 and the third display area 300 is 1.9 to 2.1 compared with the area of ​​the main electrode 2021-2 of each second light-emitting unit block 202-2 located in the first display area 100 is 1.9 to 2.1.

[0183] For example, the area of ​​the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the non-edge region of the second display area 200 is larger than the area of ​​the connection electrode 2022-1 of each first light-emitting unit block 202-1 located in the first display area 100. Similarly, the area of ​​the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the non-edge region of the second display area 200 is larger than the area of ​​the connection electrode 2022-2 of each second light-emitting unit block 202-2 located in the first display area 100 to facilitate connection with the pixel circuit.

[0184] For example, the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and at least one of the third display area 300 is 1.5 to 2.5 compared to the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100. For example, the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and at least one of the third display area 300 is 1.9 to 2.1 compared to the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100.

[0185] For example, the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the main electrode 2031 of each third color light-emitting unit 203 located in the first display area 100. For example, the area of ​​the effective light-emitting area of ​​each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 and the third display area 300 is 2 times the area of ​​the effective light-emitting area of ​​each third color light-emitting unit 203 located in the first display area 100.

[0186] For example, the area of ​​the connection electrode 2032 of each third color light-emitting unit 203 located in the non-edge area of ​​the second display area 200 is larger than the area of ​​the connection electrode 2032 of each third color light-emitting unit 203 located in the first display area 100 to achieve connection with the pixel circuit pair.

[0187] For example, the main electrode and the effective light-emitting area of ​​the third color light-emitting unit in each display area are both hexagonal in shape.

[0188] For example, such as Figure 8 and Figure 9As shown, the second electrode of the light-emitting unit in the second display area is directly connected to the pixel circuit, so the area of ​​the connecting electrode of the light-emitting unit in the second display area is relatively large. However, the second electrode of the light-emitting unit in the third display area is connected to the pixel circuit of the second display area through a transparent trace, so the area of ​​the connecting electrode of the light-emitting unit in the third display area can be set to be relatively small.

[0189] For example, Figure 10 This is a schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups at the boundary of the second display area and the first display area according to an embodiment of this disclosure. Figures 1 to 10 As shown, the shape and area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the row of light-emitting units adjacent to the first display area 100 in the Y direction of the second display area 200 are approximately the same as the shape and area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the first display area 100. In this embodiment, the shape and area of ​​the main electrode of each first color light-emitting unit in the two rows of light-emitting units adjacent to each other in the Y direction of the second display area are set to be approximately the same. That is, the area of ​​the main electrode of the first color light-emitting unit located at the edge of the second display area is designed to be different from the area of ​​the main electrode of the first color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0190] For example, such as Figures 1 to 10 As shown, the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 in the row of light-emitting units adjacent to the first display area 100 in the first direction in the second display area 200 is 0.9 to 1.1 times the area of ​​the main electrode 2021 of each second color light-emitting unit pair 202 in the first display area 100. In this embodiment, the area of ​​the main electrode of each second color light-emitting unit in two rows of light-emitting units adjacent to each other in the Y direction in the second display area is set to be approximately the same. That is, the area of ​​the main electrode of the second color light-emitting unit located at the edge of the second display area is designed to be different from the area of ​​the main electrode of the second color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the second color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0191] For example, such as Figures 1 to 10As shown, the shape of the main electrode 2021 of the two second color sub-pixels included in the second color sub-pixel pair 202 in the first display area 100 is different from the shape of the two main electrodes 2021 of each second color light-emitting unit pair 202 in the second display area 200 that is adjacent to the first display area 100 in the first direction.

[0192] In this embodiment of the disclosure, the size of the pixel limiting layer gap (PDL gap) between two adjacent light-emitting units in the non-edge region of the second display area is approximately the same as the size of the PDL gap between two adjacent light-emitting units in the edge region of the second display area, so as to ensure the uniformity of the image light displayed in the second display area.

[0193] For example, such as Figures 1 to 10 As shown, the main electrodes 2021 of the two second color sub-pixels in the second color sub-pixel pair 202 within the first display area 100 are both pentagonal in shape. Each pentagon includes a first side 1 extending along the X direction, two second sides 2 extending along the Y direction, and two third sides 3 connected to the two second sides 2. The two third sides 3 intersect to form sharp corners, and the two sharp corners of the main electrodes 2021 of the two second color sub-pixels are close to each other. The main electrodes 2021 of each second color light-emitting unit pair 202 in the row of light-emitting unit groups adjacent to the first display area 100 in the Y direction in the second display area 200 include a fourth side 4 extending along the X direction, two fifth sides 5 extending along the Y direction, two sixth sides 6 connected to the two fifth sides 5, and a seventh side 7 connecting the two sixth sides 6. The two seventh sides 7 of the main electrodes 2021 of the two second color sub-pixels are close to each other.

[0194] For example, such as Figures 7 to 10 As shown, the length of the second side 2 of the main electrode 2021 of the second color light-emitting unit in the first display area 100 is less than the length of the fifth side 5 of the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200, so as to ensure that the area of ​​the main electrode of the second color light-emitting unit in the first display area is approximately equal to the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area.

[0195] For example, such as Figures 7 to 10As shown, when the area of ​​the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of ​​the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure that the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or the third color light-emitting unit) and the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or the third color light-emitting unit) in the non-edge area of ​​the second display area 200 are not parallel to the center line connecting the two main electrodes of each pair of second color light-emitting units in the row of light-emitting units adjacent to the first display area 100 in the first direction.

[0196] When the area of ​​the main electrode 2021 of the second color light-emitting unit at the edge of the second display area 200 is set to be the same as the area of ​​the main electrode 2021 of the second color light-emitting unit in the first display area 100, in order to ensure that the PDL gap between the second color light-emitting unit at the edge of the second display area 200 and the first color light-emitting unit (or the third color light-emitting unit) is the same as the PDL gap between the second color light-emitting unit and the first color light-emitting unit (or the third color light-emitting unit) in the non-edge area of ​​the second display area 200, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area 200 is a pentagon including sharp corners, which would spatially conflict with the connection electrode of the first color light-emitting unit (or the third color light-emitting unit). Therefore, the shape of the main electrode of the second color light-emitting unit at the edge of the second display area no longer includes sharp corners. At this point, in order to ensure that the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area is approximately the same as the area of ​​the main electrode of the second color light-emitting unit in the first display area, it is necessary to compensate for the shape of the main electrode of the second color light-emitting unit at the edge of the second display area, that is, to add two sixth sides 6 and a seventh side 7 connecting the two sixth sides 6, so as to achieve that the area of ​​the main electrode of the second color light-emitting unit at the edge of the second display area is equal to the area of ​​the second color light-emitting unit in the first display area without spatial conflict.

[0197] For example, such as Figures 1 to 10As shown, the shape and area of ​​the main electrode 2031 of each third color light-emitting unit 203 in the row of light-emitting units adjacent to the first display area 100 in the Y direction of the second display area 200 are approximately the same as those of the main electrode 2031 of each third color light-emitting unit 203 in the first display area 100. In this embodiment, the shape and area of ​​the main electrode of each third color light-emitting unit in the two rows of light-emitting units adjacent to the first display area in the Y direction of the second display area are set to be approximately the same. That is, the area of ​​the main electrode of the third color light-emitting unit located at the edge of the second display area is designed to be different from the area of ​​the main electrode of the third color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the third color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0198] For example, Figure 11 This is a schematic diagram of the second electrode of each light-emitting unit in two rows of light-emitting unit groups at the boundary of the second display area and the first display area according to an embodiment of this disclosure. Figure 11 As shown, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the second color light-emitting unit pairs 202 are located on the side of the first color light-emitting unit 201 and the third color light-emitting unit 203 closer to the first display area 100. The area and shape of the main electrode 2021 of each second color light-emitting unit pair 202 in this row of light-emitting unit units are approximately the same as the area and shape of the main electrode 2021 of each second color light-emitting unit pair 202 in the first display area 100. In this embodiment, the shape and area of ​​the main electrodes of each second color light-emitting unit pair in two rows of light-emitting unit groups adjacent to each other in the X direction in the second display area are set to be approximately the same. That is, the area of ​​the main electrode of the second color light-emitting unit pair located at the edge of the second display area is designed to be different from the area of ​​the main electrode of the second color light-emitting unit pair located in the non-edge area of ​​the second display area. This can increase the brightness of most of the second color light-emitting unit pairs in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0199] For example, a third pixel circuit group is provided between two adjacent second light-emitting unit groups arranged along the Y direction, thus no light-emitting unit group is provided at the interval between two adjacent second light-emitting unit groups arranged along the Y direction. In the first display area 100, a gap is provided between two adjacent first light-emitting unit groups in a column of multiple first light-emitting unit groups close to the second display area 200 in the X direction. This gap includes a first pixel circuit group not connected to the light-emitting unit group, and along the X direction, this first pixel circuit group and the light-emitting unit group in a column of second light-emitting unit groups adjacent to the first display area 100 are located on the same straight line. Therefore, the brightness distribution of the first and second display areas in the X direction can be balanced.

[0200] For example, such as Figure 11 As shown, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the area of ​​the main electrode 2011 of each first color light-emitting unit 201 is 1.5 to 2.5 times the area of ​​the main electrode 2011 of each first color light-emitting unit 201 in the first display area 100. For example, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 is 2 times the area of ​​the effective light-emitting area of ​​each first color light-emitting unit 201 in the first display area 100. In this embodiment of the disclosure, while ensuring that the main electrodes of the light-emitting units in a row of light-emitting units adjacent to the first display area in the X direction do not conflict in space, the shape and area of ​​the main electrode of the first color light-emitting unit located at the edge of the second display area are approximately the same as the shape and area of ​​the main electrode of the first color light-emitting unit located in the non-edge area of ​​the second display area. This can increase the brightness of most of the first color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing the main electrodes of the two rows of light-emitting units from conflicting in space.

[0201] For example, such as Figure 11 As shown, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the area of ​​the main electrode 2031 of each third-color light-emitting unit 203 is 1.5 to 2.5 times the area of ​​the main electrode 2031 of each third-color light-emitting unit 203 in the first display area 100. For example, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the area of ​​the main electrode 2031 of each third-color light-emitting unit 203 is 1.9 to 2.1 times the area of ​​the main electrode 2031 of each third-color light-emitting unit 203 in the first display area 100.

[0202] For example, in a row of light-emitting units adjacent to the first display area 100 in the X direction in the second display area 200, the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit 203 is 2 times the area of ​​the effective light-emitting area of ​​each third-color light-emitting unit 203 in the first display area 100. In this embodiment, while ensuring that the main electrodes of the light-emitting units in the row of light-emitting units adjacent to the first display area in the X direction in the second display area do not conflict spatially, the shape and area of ​​the main electrodes of the third-color light-emitting units located at the edge of the second display area are approximately the same as those of the main electrodes of the third-color light-emitting units located in the non-edge area of ​​the second display area. This can increase the brightness of most of the third-color light-emitting units in the second display area to achieve a uniform full-screen display effect while preventing spatial conflict between the main electrodes of the two rows of light-emitting units.

[0203] Another embodiment of this disclosure provides a display device including any of the above-described display substrates.

[0204] In an example of the display device provided in this disclosure, two pixel circuits in the second display area drive a light-emitting unit to emit light, which can increase the current and brightness of the light-emitting unit in at least one of the second and third display areas, thereby achieving a more uniform full-screen visual display effect.

[0205] In an example of an embodiment of this disclosure, a display device is provided in which the area of ​​the main electrode in at least one of the light-emitting units in the second display area and the third display area is set to be greater than the area of ​​the main electrode in the light-emitting unit in the first display area. This makes the area of ​​the effective light-emitting area of ​​a light-emitting unit of a certain color located in the non-edge area of ​​the second display area and at least one of the third display areas larger than the area of ​​the effective light-emitting area of ​​a light-emitting unit of the same color as the light-emitting unit located in the first display area. This increases the brightness of at least one of the second and third display areas while ensuring the lifespan of the light-emitting material of the light-emitting unit, thereby achieving a more uniform full-screen visual display effect.

[0206] In an example of the display device provided in this disclosure, by designing the data lines at the junction of the first display area and the second display area, as well as the boundary between the first display area and the third display area, the unified algorithm processing of the integrated circuit (IC) in the first display area and the second display area can be satisfied.

[0207] The following points need to be explained:

[0208] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0209] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0210] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area. The first display area includes a plurality of first light-emitting unit groups and a plurality of first pixel circuit groups respectively connected to the plurality of first light-emitting unit groups. The second display area includes a plurality of second light-emitting unit groups and a plurality of second pixel circuit groups respectively connected to the plurality of second light-emitting unit groups. Each light-emitting unit group includes a plurality of light-emitting units. Each light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode disposed along a direction perpendicular to the substrate. The second electrode is located on the side of the light-emitting layer facing the substrate. Multiple reset power signal lines are located between the second electrode and the substrate. Multiple data lines are located on the side of the multiple reset power signal lines away from the substrate, and the extension direction of the data lines intersects with the extension direction of the reset power signal lines. Each pixel circuit group includes multiple pixel circuits, the second pixel circuit group includes multiple first pixel circuit units, each first pixel circuit unit includes at least a first pixel circuit and a second pixel circuit, and at least two pixel circuits in the first pixel circuit unit are configured to be electrically connected to the second electrode of the same light-emitting unit. Each pixel circuit includes a data writing transistor, a driving transistor, and a first reset control transistor. The first terminal of the first reset control transistor is connected to the reset power supply signal line, and the second terminal of the first reset control transistor is connected to the second electrode. The first terminal of the data writing transistor is connected to the second terminal of the driving transistor. The display substrate further includes a plurality of first connection portions, at least a portion of the first connection portions having a first end connected to the second terminal of the data writing transistor of the first pixel circuit, and the at least a portion of the first connection portions having a second end connected to the second terminal of the data writing transistor of the second pixel circuit so that at least two data writing transistors of the first pixel circuit unit are connected to the same data line, and at least a portion of the first connection portion is located between the second terminal of the data writing transistor in the first pixel circuit and the first terminal of the first reset control transistor. Each of the light-emitting unit groups includes a first color light-emitting unit, a second color light-emitting unit pair, and a third color light-emitting unit. The first color light-emitting unit and the third color light-emitting unit are arranged along the extension direction of the data line. The second color light-emitting unit pair includes two second color light-emitting units arranged along a second direction. The first color light-emitting unit and the second color light-emitting unit pair are arranged along the extension direction of the reset power signal line.

2. The display substrate according to claim 1, wherein, The substrate further includes a third display area, the second display area includes a plurality of third pixel circuit groups, the third display area includes a plurality of third light-emitting unit groups, the plurality of third light-emitting unit groups are respectively connected to the plurality of third pixel circuit groups, and the density of the plurality of second light-emitting unit groups is less than the density of the plurality of first light-emitting unit groups, and the density of the plurality of third light-emitting unit groups is less than the density of the plurality of first light-emitting unit groups. The third pixel circuit group includes a plurality of second pixel circuit units, each second pixel circuit unit including at least a third pixel circuit and a fourth pixel circuit, and at least two pixel circuits in the second pixel circuit unit are configured to be electrically connected to the second electrode of the same light-emitting unit. A first end of a portion of the first connection is connected to the second terminal of the data writing transistor of the third pixel circuit, and a second end of the portion of the first connection is connected to the second terminal of the data writing transistor of the fourth pixel circuit so that at least two data writing transistors of the second pixel circuit unit are connected to the same data line. The first connection is located between the second terminal of the data writing transistor in the third pixel circuit and the first terminal of the first reset control transistor.

3. The display substrate according to claim 2, wherein, Each pixel circuit further includes a threshold compensation transistor, the first terminal of which is connected to the first terminal of the driving transistor, and the second terminal of which is connected to the gate of the driving transistor. The first connection portion is located between the second terminal of the threshold compensation transistor and the first terminal of the first reset control transistor in the first pixel circuit.

4. The display substrate according to claim 3, wherein, Each pixel circuit further includes a second connection portion and a third connection portion disposed on the same layer as the data line. The second connection portion is configured to connect the second terminal of the threshold compensation transistor and the gate of the driving transistor, and the third connection portion is configured to connect the first terminal of the first reset control transistor and the reset power supply signal line. In the first pixel circuit, the distance between the edges of the second connecting portion and the third connecting portion that are close to each other in the second direction is 7 to 12 micrometers so that the first connecting portion is disposed between the second connecting portion and the third connecting portion.

5. The display substrate according to claim 3, further comprising: Multiple power signal lines are arranged on the same layer as the data lines and extend along the second direction. The first connection portion and the data line are located on different layers, and along a third direction perpendicular to the substrate, each of the first connection portions overlaps with the data line and the power signal line.

6. The display substrate according to claim 5, wherein, The first connection part and the reset power signal line are located on the same layer.

7. The display substrate according to claim 5, wherein, Each pixel circuit further includes a fourth connection portion disposed on the same layer as the data line, the fourth connection portion being configured to connect the first connection portion and the second electrode of the data write transistor. In at least one of the pixel circuit units, the first pixel circuit unit and the second pixel circuit unit, the fourth connection portion of one pixel circuit is spaced apart from the adjacent data line, and the fourth connection portion of the other pixel circuit is integrally formed with the data line.

8. The display substrate according to claim 7, further comprising: Multiple covering portions are disposed on the same layer as the first connecting portion. Each threshold compensation transistor includes two gates and an active semiconductor layer located between the two gates. Along the third direction, the covering portions overlap with the active semiconductor layer between the two gates, the data lines, and the power signal lines. The reset power signal line extends along a first direction, and the data line extends along a second direction. The orthographic projection of the cover portion overlapping the active semiconductor layer on a first straight line extending along the first direction overlaps with the orthographic projection of the first connecting portion on the first straight line, and the orthographic projection of the fourth connecting portion on a second straight line extending along the second direction overlaps with the orthographic projection of the cover portion on the second straight line.

9. The display substrate according to claim 8, wherein, The first connecting portion includes a main connecting portion extending along the first direction and two end portions located at both ends of the main connecting portion and extending along the second direction. The two end portions are respectively connected to two fourth connecting portions in at least one of the pixel circuit units of the first pixel circuit unit and the second pixel circuit unit. The orthographic projection of the two end portions on the second straight line overlaps with the orthographic projection of the covering portion on the second straight line.

10. The display substrate according to claim 9, wherein, Along the second direction, the distance between the main body connection portion and the first electrode of the threshold compensation transistor in the first pixel circuit is greater than the distance between the main body connection portion and the first electrode of the first reset control transistor in the first pixel circuit.

11. The display substrate according to any one of claims 8-10, wherein, Each pixel circuit further includes a first light-emitting control transistor and a fifth connection portion disposed on the same layer as the data line. The first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor. The second electrode of the light-emitting unit located in the first display area and the second display area is electrically connected to the second electrode of the first light-emitting control transistor through the fifth connection portion.

12. The display substrate according to claim 11, wherein, The second electrode of each of the light-emitting units in the second light-emitting unit group includes a main electrode and a connecting electrode. The connecting electrode is configured to be directly electrically connected to the fifth connecting portion to be electrically connected to the second electrode of at least two first light-emitting control transistors of the first pixel circuit unit.

13. The display substrate according to claim 11, further comprising: Multiple transparent traces are located between the second electrode and the film layer containing the data line, and each transparent trace extends along the first direction. The transparent trace is configured to connect the second electrode of the light-emitting unit in the third light-emitting unit group and the fifth connection portion so that the second electrode of each light-emitting unit in the third light-emitting unit group is electrically connected to the second electrode of at least two first light-emitting control transistors of the second pixel circuit unit in the third pixel circuit group.

14. The display substrate according to claim 13, wherein, The plurality of first pixel circuit groups are arranged in an array along the first direction and the second direction; Along the first direction, the plurality of second pixel circuit groups and the plurality of third pixel circuit groups are alternately arranged; along the second direction, the plurality of second pixel circuit groups and the plurality of third pixel circuit groups are alternately arranged; and a column of second pixel circuit groups and third pixel circuit groups arranged along the second direction is connected to different data lines.

15. The display substrate according to claim 11, further comprising: A scan signal line extends along the first direction and is located between the reset power signal line and the substrate. The reset control signal line extends along the first direction and is disposed on the same layer as the scan signal line; as well as The light emission control signal line extends along the first direction and is disposed on the same layer as the scanning signal line. The pixel circuit of each sub-pixel further includes a storage capacitor, a second light-emitting control transistor, and a second reset transistor; The gate of the data writing transistor is electrically connected to the scan signal line; The first terminal of the storage capacitor is electrically connected to the power signal line, and the second terminal of the storage capacitor is electrically connected to the gate of the driving transistor. The gate of the threshold compensation transistor is electrically connected to the scan signal line; The gate of the first reset transistor is electrically connected to the reset control signal line; The first terminal of the second reset transistor is electrically connected to the reset power supply signal line, the second terminal of the second reset transistor is electrically connected to the gate of the driving transistor, and the gate of the second reset transistor is electrically connected to the reset control signal line. The gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line; The first terminal of the second light-emitting control transistor is electrically connected to the power signal line, the second terminal of the second light-emitting control transistor is electrically connected to the second terminal of the driving transistor, and the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line.

16. A display device comprising the display substrate according to any one of claims 1-15.

Images