Variable modulation scheme for memory device access or operation

Abstract

This application relates to a variable modulation scheme for accessing or operating a memory device. The device can switch between different modulation schemes for communication based on one or more operating parameters associated with the device or components thereof. The modulation scheme may involve amplitude modulation in which different levels of a signal represent different data values. For example, the device may use a first modulation scheme that uses two levels to represent data and a second modulation scheme that uses four levels to represent data. In one instance, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power saving is required.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on August 30, 2018, with application number 201811006077.4, entitled "Variable modulation scheme for accessing or operating a memory device".

[0003] Cross-reference

[0004] This patent application claims priority to U.S. Patent Application No. 15 / 977,808, filed May 11, 2018, entitled "Variable Modulation Scheme for Memory Device Access or Operation," by Hasbun et al., which in turn claims the benefit and priority to U.S. Provisional Patent Application No. 62 / 567,011, filed October 2, 2017, and assigned to the assignee, entitled "Variable Modulation Scheme," and each of the above applications is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to variable modulation schemes for accessing or operating memory devices. Background Technology

[0006] The following discussion generally pertains to the use of signaling in memory devices. Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of memory cells.

[0007] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time, even without external power. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless periodically refreshed by an external power source. FeRAM can use a similar device architecture to volatile memory, but it is non-volatile due to the use of ferroelectric capacitors as storage devices.

[0008] Generally, improvements to memory devices can include increasing memory cell density, increasing read / write speed, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Summary of the Invention

[0009] Describe a method. The method may include: communicating at a first frequency using a first signal modulated with a first modulation scheme having a first number of levels; determining operating parameters associated with a host coupled to a memory controller; selecting a second modulation scheme, different from the first modulation scheme, having a second number of levels different from the first number of levels, based at least in part on the determined operating parameters; and communicating using a second signal modulated with the second modulation scheme.

[0010] Another method is described. The method may include: receiving a first data set in a first number of bit streams; generating a first signal having a first number of levels by a memory controller based at least in part on the first number of bit streams including the first data set; receiving a second data set in a second number of bit streams; determining, at least in part on the received second data set, operating parameters associated with a host coupled to the memory controller; and generating a second signal having a second number of levels based at least in part on the second number of bit streams including the second data set and the determined operating parameters, wherein the second number of levels differs from the first number of levels.

[0011] Describe an apparatus. The apparatus may include a memory die and a memory controller. The memory controller may be configured to: transmit a first signal to the memory die, wherein the first signal is modulated using a first modulation scheme having a first number of levels; determine operating parameters associated with the apparatus; select a second modulation scheme different from the first modulation scheme based at least in part on the determined operating parameters; and transmit a second signal to the memory die based at least in part on the selected second modulation scheme, wherein the second signal is modulated using a second modulation scheme having a second number of levels different from the first number of levels.

[0012] Describe another device. The device may include: means for transmitting a first signal to a memory die, wherein the first signal is modulated using a first modulation scheme having a first number of levels; means for determining operating parameters associated with the device; means for selecting a second modulation scheme, different from the first modulation scheme, at least in part based on the determined operating parameters; and means for transmitting a second signal to the memory die, at least in part based on the selected second modulation scheme, wherein the second signal is modulated using a second modulation scheme having a second number of levels, different from the first number of levels.

[0013] Describe another device. The device may include a first driver in electronic communication with a data bus. The device may also include a memory controller configured to: transmit a first signal on the data bus using the first driver, the first signal having a signal strength corresponding to one of a first number of levels representing a first data set; determine operating parameters associated with the device; and transmit a second signal on the data bus, at least in part based on the determined operating parameters, the second signal having a signal strength corresponding to one of a second number of levels representing a second data set, the second number of levels being different from the first number of levels.

[0014] Describe another device. The device may include: means for transmitting a first signal on a data bus using a first driver, the first signal having a signal strength corresponding to one of a first number of levels representing a first data set; means for determining operating parameters associated with the device; and means for transmitting a second signal on the data bus, at least in part based on the determined operating parameters, the second signal having a signal strength corresponding to one of a second number of levels representing a second data set, the second number of levels being different from the first number of levels. Attached Figure Description

[0015] Figure 1Examples of memory devices that support variable modulation schemes according to embodiments of the present invention are described.

[0016] Figure 2 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0017] Figure 3 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0018] Figure 4 Examples of diagrams illustrating a variable modulation scheme according to an embodiment of the present invention are provided.

[0019] Figure 5 Examples of diagrams illustrating a variable modulation scheme according to an embodiment of the present invention are provided.

[0020] Figure 6 Examples of memory devices that support variable modulation schemes according to embodiments of the present invention are described.

[0021] Figure 7 Examples of memory devices that support variable modulation schemes according to embodiments of the present invention are described.

[0022] Figure 8 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0023] Figure 9 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0024] Figure 10 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0025] Figure 11 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0026] Figure 12 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0027] Figure 13 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0028] Figure 14 Examples of circuits supporting variable modulation schemes according to embodiments of the present invention are described.

[0029] Figure 15 Examples of waveform diagrams illustrating a variable modulation scheme according to an embodiment of the present invention are provided.

[0030] Figure 16Examples of waveform diagrams illustrating a variable modulation scheme according to an embodiment of the present invention are provided.

[0031] Figure 17 Examples of waveform diagrams illustrating a variable modulation scheme according to an embodiment of the present invention are provided.

[0032] Figure 18 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0033] Figure 19 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0034] Figure 20 Examples of memory devices that support variable modulation schemes according to embodiments of the present invention are described.

[0035] Figure 21 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0036] Figure 22 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0037] Figure 23 An example of a block diagram illustrating a variable modulation scheme according to an embodiment of the present invention.

[0038] Figure 24 Examples of systems that support variable modulation schemes according to embodiments of the present invention are described.

[0039] Figure 25 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0040] Figure 26 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0041] Figure 27 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention.

[0042] Figure 28 An example of a process flowchart illustrating a variable modulation scheme according to an embodiment of the present invention. Detailed Implementation

[0043] The device can dynamically switch between two or more modulation schemes based on one or more operating parameters determined by the device to access or operate the memory. The device can also optionally switch from using one frequency (e.g., pulse rate) to using a different frequency based on parameters. Combinations of modulation schemes and frequencies can be selected to adapt to, take into account, or otherwise satisfy the operating parameters.

[0044] In some systems, a device may use a single modulation scheme to communicate with the memory die, but can switch between a discrete number of frequencies to meet bandwidth requirements or comply with power or other constraints. Because higher frequencies provide greater bandwidth, the device can increase the frequency when bandwidth requirements are high and decrease the frequency when bandwidth requirements are low. Similarly, because lower frequencies consume less power, the device can increase the frequency when the available power supply is high and decrease the frequency when the available power supply is low. Therefore, the device can select frequencies that provide sufficient bandwidth at adequate power consumption levels.

[0045] However, in some cases, the frequency at which the device is designed to communicate may not provide the target (e.g., required, sufficient) bandwidth and / or power consumption (or power savings). For example, the device may be designed to communicate at different frequencies (e.g., multiple frequencies, N frequencies), but the two lowest frequencies may not provide sufficient bandwidth to meet the target bandwidth, while a third frequency may consume too much power to meet power constraints. Therefore, the device may need to choose between operating with insufficient bandwidth or consuming excessive power, either of which could impair communication or operation.

[0046] According to the techniques described herein, a device can switch between frequencies and modulation schemes when accessing or operating memory. Because different modulation schemes offer different bandwidths and consume different amounts of power, selecting between modulation schemes allows the device to more closely match target metrics, needs, or requirements. For example, the device can select a combination of modulation scheme and frequency such that the provided bandwidth and power consumption (and other possible or additional factors) are adapted to the device's operating parameters (e.g., bandwidth, power). Operating parameters may include other aspects associated with the operation of the device, such as the startup of high-data-rate applications and the temperature of one or more components of the device, etc.

[0047] The features of this disclosure described above are further described below in the context of exemplary memory devices and various other components. Specific examples of memory devices supporting multi-symbol signaling are described. These and other features of this disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts involving multi-symbol signaling.

[0048] Figure 1 An example system 100 including a memory device according to various embodiments of the present disclosure is illustrated. System 100 may also be referred to as an electronic memory device. System 100 may be configured to dynamically switch between multiple modulation schemes and frequencies. System 100 may include multiple memory dies 105 and a memory controller 110. Memory dies 105 may be coupled to memory controller 110 using one or more internal signal paths 115. Each internal signal path 115 may be configured to transmit internal signals representing data (e.g., binary symbol signals, multi-symbol signals) between memory controller 110 and one or more of memory dies 105. In some embodiments, internal signal paths 115 may be used to transmit and receive internal signals within a semiconductor package and among various components therein.

[0049] In some cases, system 100 includes computing device 120, such as a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU)) or system-on-a-chip (SoC). System 100 including computing device 120 may be a subsystem of a larger system (e.g., a laptop computer, server, personal computing device, smartphone, personal computer). In any case, computing device 120 may exchange information with memory controller 110 using signals transmitted via first signal path 125.

[0050] The memory die 105 may contain multiple memory cells (such as...) Figure 2 The images and references shown Figure 2 As described, the memory cells can be programmed to store different logical states. For example, each memory cell can be programmed to store one or more logical states (e.g., logic '0', logic '1', logic '00', logic '01', logic '10', logic '11'). The memory cells of memory die 105 can use any number of memory technologies to store data, including DRAM, FeRAM, PCM, 3DXP memory, NAND memory, NOR memory, or combinations thereof. In some cases, the first memory die 105 of system 100 can use a first memory technology (e.g., NAND flash memory), and the second memory die 105 of system 100 can use a second memory technology different from the first memory technology (e.g., FeRAM).

[0051] In some cases, the memory die 105 may be an instance of a two-dimensional (2D) array of memory cells. Alternatively, the memory die 105 may be an instance of a three-dimensional (3D) array, wherein multiple 2D arrays having multiple memory cells are formed on top of each other. Compared to a 2D array, this configuration can increase the number of memory cells that can be formed on a single die or substrate. In turn, this can reduce manufacturing costs or improve the performance of the memory array, or both. Each level of the array may be positioned such that the memory cells in each level can be substantially aligned with each other, thereby forming a memory cell stack. In some cases, the memory dies 105 may be stacked directly on top of each other. In other cases, one or more of the memory dies 105 may be positioned away from a stack of memory dies (e.g., in different memory stacks).

[0052] Memory die 105 may include one or more vias 130 (e.g., through-silicon vias (TSVs)). In some cases, the one or more vias 130 may be part of an internal signal path 115 and perform a similar function. The vias 130 can be used to enable communication between memory dies 105, for example, when memory dies 105 are stacked on top of each other. Some vias 130 can be used to facilitate communication between memory controller 110 and at least some of the memory dies 105. In some cases, a single via 130 may be coupled to multiple memory dies 105. In some cases, each memory die 105 may include a via 130.

[0053] The memory controller 110 can control the operation (e.g., read, write, rewrite, refresh, clear) of memory cells in the memory die 105 via one or more various components (e.g., row decoder, column decoder, sensing component). In some cases, the row decoder, column decoder, or sensing component, or some combination thereof, may be located in the same location as the memory controller 110. The memory controller 110 may generate row and column address signals to activate the desired word lines and digital lines. In other instances, the memory controller 110 may control various voltages or currents, or both, used during the operation of the system 100. For example, the memory controller 110 may apply a discharge voltage to the word lines or digital lines after accessing one or more memory cells. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may differ for the various operations discussed relative to the operating system 100. Furthermore, one, more, or all memory cells within the memory die 105 may be accessed simultaneously. For example, multiple or all memory cells in memory die 105 can be accessed simultaneously during a reset operation, in which multiple or all memory cells can be set to a single logic state (e.g., logic '0').

[0054] In some cases, the memory controller 110 may be integrated as part of the computing device 120. For example, the processor of the computing device 120 may execute one or more processes, operations, or programs configured to control various aspects of the system 100 or to initiate various operations or actions. In some cases, the memory controller 110 may be integrated as part of a buffer in a stack of memory dies 105. For example, the memory controller 110 may be an example of a semiconductor die that may execute one or more processes, operations, or programs configured to control various aspects of the system 100 or to initiate various operations or actions.

[0055] The memory controller 110 may include a multi-symbol signal component 135 configured to transmit multi-symbol signals within the system 100 (i.e., signals modulated using an M-ary modulation scheme, where M is greater than or equal to 3) (e.g., internal signals transmitted on internal signal path 115) and / or multi-symbol signals having other components (e.g., external signals transmitted on first signal path 125). The memory controller 110 may control the multi-symbol signal component 135 such that different signals are modulated using modulation schemes, frequencies, or different combinations of both. For example, the memory controller 110 may control the multi-symbol signal component 135 such that a first signal sent to the memory die 105 is modulated using a first modulation scheme (e.g., a modulation scheme having a first number of levels), and a second signal sent to the memory die 105 is modulated using a second modulation scheme (e.g., a modulation scheme with a different number of levels than the first modulation scheme). The memory controller 110 may also communicate with the multi-symbol signal component 135 to transmit signals at the same or different frequencies. The modulation scheme and the frequency of the transmitted signal can be based on one or more operating parameters associated with system 100.

[0056] In some cases, the memory controller 110 may be configured to simultaneously transmit binary symbol signals and multi-symbol signals. Features and functions associated with transmitting multi-symbol signals and binary symbol signals can be implemented in devices and contexts other than memory storage devices. For example, features of the functions described herein can be implemented in personal computing devices, laptops, servers, portable communication devices, or combinations thereof.

[0057] Figure 2 Examples of circuit 200 according to various embodiments of the present disclosure are shown. Circuit 200 may illustrate an example of memory cell 205, which may be part of one or more memory dies 105. Circuit 200 may include memory cell 205 coupled to digital line 210 and voltage source 215.

[0058] Memory cell 205 can implement any type of memory technology (e.g., DRAM, FeRAM, PCM, NAND, NOR). Therefore, some aspects of circuitry 200 can be based on the memory technology implemented by memory cell 205. For example, if memory cell 205 is a FeRAM memory cell, then voltage source 215 can be an instance of a board or a board line coupled to a board driver. If memory cell 205 is a DRAM memory cell, then voltage source 215 can be an instance of ground or dummy ground. Those skilled in the art will understand and appreciate the differences between memory cells 205 and different memory technologies.

[0059] Memory cell 205 may include capacitor 220 and selection component 225. In some cases, capacitor 220 may be or include a resistor-type device, as in the case of a PCM memory cell. Memory cell 205 may store charge representing programmable states in capacitor 220; for example, charged and uncharged capacitors may represent two logic states respectively. DRAM memory cells may include capacitors with a dielectric material as the insulating material. For example, the dielectric material may have linear or parapolar polarization characteristics, and ferroelectric memory cells may include capacitors with a ferroelectric material as the insulating material. In examples where the storage medium includes FeRAM, different charges on the ferroelectric capacitors may represent different logic states.

[0060] The memory cells 205 of the memory die 105 can be accessed using various combinations of word lines 230 and digital lines 210 in certain types of memory technologies, board lines, or combinations thereof (e.g., during read operations, write operations, or other operations). In some cases, some memory cells 205 may share access lines (e.g., digital lines, word lines, board lines) with other memory cells. For example, digital lines 210 may be shared by memory cells 205 in the same column, and word lines 230 may be shared by memory cells in the same row. In some cases, board lines may be shared by memory cells in the same segment, block, one or more decks. As described above, various states can be stored by charging and discharging the capacitors 220 of the memory cells 205.

[0061] The stored state of capacitor 220 in memory cell 205 can be read or sensed by operating various components. Capacitor 220 may be electrically connected to digital line 210. When select component 225 is deactivated, capacitor 220 may be disconnected from digital line 210, and when select component 225 is activated, capacitor 220 may be coupled to digital line 210 (e.g., via word line 230). In some instances, activating select component 225 may be referred to as selecting memory cell 205. In some cases, select component 225 may be a transistor, and its operation may be controlled by applying a voltage to the transistor gate, wherein the voltage value is greater than the transistor's threshold value. Word line 230 may activate select component 225 based on instructions received from memory controller 110. For example, memory controller 110 may control the bias of word line 230 to selectively activate / deactivate select component 225, thereby connecting capacitor 220 of memory cell 205 to digital line 210.

[0062] In some instances, the change in voltage of digital line 210 depends on the intrinsic capacitance of the digital line. That is, when charge flows through digital line 210, a finite amount of charge can be stored in digital line 210, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance can depend on the physical characteristics of the digital line, including its dimensions. Digital line 210 can connect multiple memory cells in memory die 105, therefore digital line 210 can have a length that produces a non-negligible capacitance (e.g., approximately picofarads (pF)). The resulting voltage of digital line 210 can then be compared with a reference voltage using sensing component 240 to determine the logic state stored in the memory cell. Other sensing methods can be used. Sensing component 240 can be coupled to digital line 210.

[0063] Sensing component 240 may include various transistors or amplifiers for detecting and amplifying signal differences, a process known as latching. Sensing component 240 may include a sensing amplifier that receives and compares the voltages of digital line 210 and reference line 245, where the voltage of reference line 245 may be a reference voltage. The output of the sensing amplifier may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison result. For example, if the voltage of the digital line is higher than that of the reference line, then the output of the sensing amplifier may be driven to a positive supply voltage.

[0064] In some cases, the sense amplifier can drive the digital line to the supply voltage. The sensing component 240 can then latch the output of the sense amplifier and / or the voltage of the digital line 210, which can be used to determine the state stored in the memory cell (e.g., logic '1'). Alternatively, for example, if the voltage of the digital line 210 is lower than that of the reference line 245, the sense amplifier output can be driven to a negative or ground voltage. The sensing component 240 can similarly latch the sense amplifier output to determine the state stored in the memory cell 205 (e.g., logic '0'). The latched logic state of the memory cell 205 can then be output to the memory controller 110, for example, using one or more internal signal paths 115 or vias 130.

[0065] To write to a memory cell, a voltage can be applied to capacitor 220 of memory cell 205. Various methods can be used to write to memory cell 205. In one example, select component 225 can be activated via word line 230 to electrically connect capacitor 220 to digital line 210. A voltage can be applied to capacitor 220 by controlling the voltage of the first cell board (e.g., via voltage source 215) and the voltage of the second cell board (e.g., via digital line 210). To write logic '0', the cell board can be high (e.g., the voltage level can be increased above a predetermined voltage for 'high'). That is, a positive voltage can be applied to the board line, and the cell bottom can be low (e.g., dummy ground or a negative voltage applied to the digital line). The reverse process can be performed to write logic '1', where the cell board is low and the cell bottom is high.

[0066] According to the techniques described herein, different combinations of modulation schemes and frequencies can be used to transmit different signals. The modulation scheme used to modulate the signal may affect the number of memory cells 205 selected to receive the signal. For example, more memory cells 205 can be selected to receive a signal modulated using a modulation scheme with a higher number of levels compared to a signal modulated using a modulation scheme with a lower number of levels. This is because a modulation scheme with a higher number of levels can transmit a larger amount of data than a modulation scheme with a lower number of levels. In some cases, more memory cells 205 can be selected to receive the signal by increasing the page size of the memory die. Conversely, fewer memory cells 205 can be selected to receive the signal (e.g., a signal modulated using a modulation scheme with a lower number of levels) by decreasing the page size of the memory die.

[0067] Figure 3Examples of circuit 300 according to various embodiments of the present disclosure are shown. Circuit 300 may include one or more internal signal paths 315-a to 315-N, said internal signal paths coupling at least one memory die 305 to a memory controller 310. Internal signal paths 315 may be configured to transmit multi-symbol signals 320 or binary symbol signals 325, or both. In some cases, a first internal signal path 315-a may be dedicated to transmitting a first signal type (e.g., multi-symbol signal 320). In some cases, a second internal signal path 315-b may be dedicated to transmitting a different second signal type (e.g., binary symbol signal 325). In some cases, internal signal paths 315 may include one or more vias or TSVs, or may transmit through one or more vias or TSVs. Memory die 305 may be referenced. Figure 1 An example of memory die 105 is described. Memory controller 310 may be referenced. Figure 1 An example of the described memory controller 110. Signal path 315 may be referenced. Figure 1 An example of the described signal path 115.

[0068] Memory devices can use multi-symbol signaling to increase the amount of information transmitted within a given bandwidth of frequency resources (e.g., internal signals may be instances of multi-symbol signals). In some cases, memory controller 310 may be configured to select a modulation scheme (e.g., binary symbol or multi-symbol) applied to the signal based on one or more parameters. Such parameters may include power consumption parameters of the memory device, performance requirements of applications implemented using the memory device, other parameters, or combinations thereof.

[0069] In binary symbol signal 325, the modulation scheme includes two symbols (e.g., two voltage levels) representing at most two logic states (e.g., logic state '0' or logic state '1'). In multi-symbol signal 320, the modulation scheme may include a larger library of symbols that can represent three or more logic states. For example, if multi-symbol signal 320 is modulated using a modulation scheme containing four unique symbols, then multi-symbol signal 320 can be used to represent at most four logic states: '00', '01', '10', and '11'. Therefore, multiple bits of data can be contained within a single symbol, thereby increasing the amount of data transmitted using a given bandwidth.

[0070] The multi-symbol signal 320 can be any signal modulated using a modulation scheme that includes three or more unique symbols representing data (e.g., two or more bits of data). The modulation scheme modulates an M-ary signal, where M represents the number of unique symbols (e.g., level, or other conditions or combinations of conditions that may exist in the modulation scheme). The multi-symbol signal 320 can be an instance of any M-ary modulation scheme where M is greater than or equal to 3. In some cases, the multi-symbol signal 320 or the multi-symbol modulation scheme may be referred to as a non-binary signal or a non-binary modulation scheme. Examples of multi-symbol (or M-ary) modulation schemes associated with multi-symbol signals may include (but are not limited to) pulse amplitude modulation (PAM) schemes, quadrature amplitude modulation (QAM) schemes, quadrature phase shift keying (QPSK) schemes, and so on.

[0071] The binary symbol signal 325 can be any signal modulated using a modulation scheme that includes two unique symbols representing one bit of data. The binary symbol signal 325 can be an example of an M-ary modulation scheme, where M equals 2. Examples of binary symbol modulation schemes associated with binary symbol signals include (but are not limited to) Non-Return-to-Zero (NRZ), unipolar coding, bipolar coding, Manchester coding, PAM2, and so on.

[0072] In some cases, the modulation schemes for various signals can be amplitude modulation schemes that encode information in terms of the signal's amplitude (or level) (e.g., voltage amplitude or current amplitude), such as PAM4 and / or NRZ. The symbols of the modulation scheme can be referred to as levels, amplitudes, or signal strengths. For example, a first level of a signal can represent '00', a second level can represent '01', a third level can represent '10', and a fourth level can represent '11'. In some cases, a single symbol of an amplitude modulation scheme can be a constant level applied during the duration of a single symbol or two or more levels applied during the duration of a single symbol. The features described herein can be used in conjunction with other types of modulation schemes, such as phase modulation schemes, phase shift keying modulation schemes, frequency shift keying modulation schemes, amplitude shift keying modulation schemes, discontinuous keying (OOK) modulation schemes, orthogonal frequency division multiplexing (OFDM) modulation schemes, spread spectrum modulation schemes, time-based modulation schemes, or combinations thereof. Therefore, the symbol or level of the modulation scheme can be related to signal parameters other than amplitude (e.g., phase, time, frequency).

[0073] In some instances, multi-symbol signaling schemes contain symbols spaced by a smaller voltage difference (or other variable signal parameter measurement) than the symbols in binary symbol signaling schemes. In some instances, the smaller voltage spacing makes the multi-symbol signal 320 more susceptible to errors caused by noise and other factors. However, the voltage spacing of the symbols in the multi-symbol signal 320 can be amplified by increasing the peak-to-peak transmit power of the transmitted signal. But in some cases, such an increase in peak-to-peak transmit power may be impossible or difficult due to fixed supply voltage, fixed signal power requirements, or other factors. Therefore, to implement multi-level signaling, the transmitter can utilize greater power and / or the receiver may be more susceptible to an increased error rate compared to the binary symbol signal 325. Despite this smaller voltage difference and related aspects, multi-level signaling facilitates different and advantageous implementation schemes. For example, given a limited amount of communication resources, multi-level signaling can transmit more information than binary level signals.

[0074] Furthermore, using different multilevel signaling schemes allows the device to achieve target communication or operational metrics. Multilevel signals with a large number of levels provide more bandwidth than multilevel signals with a smaller number of levels. However, transmitting a multilevel signal with a large number of levels may also consume more power than transmitting a multilevel signal with a smaller number of levels. Therefore, the device can select several levels from the multilevel signal to provide the target bandwidth or maintain it within the target power consumption level.

[0075] In some cases, the features and functions associated with transmitting the multi-symbol signal 320 and the binary symbol signal 325 may be implemented in devices and contexts other than memory storage devices. For example, features of the functions described herein may be implemented in personal computing devices, laptops, servers, portable communication devices, or combinations thereof.

[0076] Figures 4 to 6 A memory device configured to transmit data using binary symbol signals, multi-symbol signals, or combinations thereof is illustrated. The memory device may include a computing device electrically coupled to a semiconductor package comprising several semiconductor dies stacked on top of each other. The computing device may exchange information with a host via a first signal path using a binary symbol signal encoded with a modulation scheme containing two symbols (e.g., two voltage levels) representing one bit of data. The computing device may generate a multi-symbol signal encoded with a modulation scheme containing three or more symbols representing more than one bit of data based on the received binary symbol signal. The computing device may transmit the multi-symbol signal to other semiconductor dies within the semiconductor package via a set of internal signal paths (e.g., TSVs). Reference Figures 4 to 6 The described features and / or functions may be compared with those in the reference. Figures 1 to 3 and Figures 7 to 22 Other features and / or combinations of functions of the described memory device.

[0077] Figure 4 An exemplary diagram 401, voltage driver 402, and current driver 403 are shown illustrating memory system interfaces and associated exemplary circuitry according to various embodiments of the present disclosure. A memory controller 405 may receive a first signal 410 from a computing device 120-a and process the information contained in the first signal 410 to generate a second signal 415. The memory controller 405 may be used as a reference. Figure 1 Examples of the described memory controller 110. In some instances, the first signal 410 may be a binary symbol signal configured with two levels. In some instances, the first signal 410 may be encoded using a modulation scheme containing two unique symbols representing a bit of data.

[0078] In some instances, the second signal 415 may be a multi-symbol signal using a modulation scheme that includes three or more unique symbols representing more than one bit of data. In some instances, the first signal 410 may be encoded using an NRZ modulation scheme, and the second signal 415 may be encoded using a PAM scheme. An example of a second signal 415 encoded using a PAM scheme is provided for reference. Figure 3 The described configuration has four PAM4 signals with different signal levels.

[0079] In some instances, the memory controller 405 may be located within a semiconductor package 480, which may be electrically coupled to a computing device 120-a located outside the semiconductor package 480. The computing device 120-a may be a system-on-a-chip (SoC) or a processor (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The semiconductor package 480 may contain other semiconductor dies (which may also be referred to as semiconductor chips, not shown) electrically coupled to the memory controller 405, such as memory chips employing DRAM, NAND, FeRAM, or 3DXP technologies. In some instances, a second signal 415 may be used to send and receive encoded information within the semiconductor package 480 and among its various components.

[0080] The memory controller 405 may include a voltage driver 402 configured to generate a second signal 415 based on the receipt of a first signal 410. The voltage driver 402 may be a reference. Figure 1This describes a portion of the multi-symbol signal component 135. The first signal 410 may include a first signal 410-a corresponding to the first bit (e.g., the least significant bit (LSB)) of the first signal 410. In some instances, the first signal 410-a may be connected to an input of the 1X complementary metal-oxide-semiconductor (CMOS) branch 420. Furthermore, the first signal 410 may include a first signal 410-b corresponding to the second bit (e.g., the most significant bit (MSB)) of the first signal 410.

[0081] In some instances, the first signal 410-b may be connected to the input of the 2X CMOS branch 430. The 1X CMOS branch 420 may be connected to the 1X voltage node 421, while the 2X CMOS branch 430 may be connected to the 2X voltage node 431. The description in voltage driver 402 indicates whether 1X or 2X represents the voltage value supplied to the CMOS branch as an operating voltage. For example, the 2X CMOS branch 430 may be connected to the 2X voltage node 431 having a voltage approximately twice that of the 1X voltage node 421 (e.g., 0.8V) (e.g., 1.6V). The output nodes of the 1X CMOS branch 420 and the 2X CMOS branch 430 may be connected to generate a second signal 415-a. Voltage driver 402 may generate the second signal 415-a associated with four voltage levels, which can be determined by four different combinations of the first signals 410-a and 410-b, such as 00, 01, 10, or 11.

[0082] The memory controller 405 may include a current driver 403 configured to generate a second signal 415 based on the receipt of a first signal 410. The current driver 403 may be a reference. Figure 1 This describes a portion of the multi-symbol signal component 135. The first signal 410 may include a first signal 410-c corresponding to the first bit (e.g., the least significant bit (LSB)) of the first signal 410. In some instances, the first signal 410-c may be connected to the gate of a 1X n-type MOS (NMOS) device 440. Furthermore, the first signal 410 may include a first signal 410-d corresponding to the second bit (e.g., the most significant bit (MSB)) of the first signal 410. In some instances, the first signal 410-d may be connected to the gate of a 2X NMOS device 450.

[0083] The description 1X or 2X in current driver 403 indicates the current value that the NMOS device can conduct. For example, 2X NMOS device 450 can conduct approximately twice the current (e.g., 500 microamps, μA) that 1X NMOS device 440 can conduct (e.g., 250 microamps, μA). The drain nodes of 1X NMOS device 440 and 2X NMOS device 450 are connected to generate a second signal 415-b in the form of a current flowing through resistive load 460. Resistive load 460 may represent the equivalent resistance of the circuitry connected to the drain nodes of 1X NMOS device 440 and 2X NMOS device 450. Current driver 403 can generate the second signal 415-b associated with four current levels, which can be determined by four different combinations of first signals 410-c and 410-d, such as 00, 01, 10, or 11.

[0084] The specific configurations depicted in voltage driver 402 and current driver 403, such as LSB signal 410-a connected to 1X CMOS branch 420 and MSB signal 410-b connected to 2X CMOS branch 430 in voltage driver 402, or LSB signal 410-c connected to 1X NMOS device 440 and MSB signal 410-b connected to 2X NMOS device 450 in current driver 403, may represent possible examples to illustrate the function of memory controller 405, which may be configured to generate a second signal 415 comprising four signal levels (e.g., voltage amplitude or current amplitude).

[0085] Other circuit configurations may generate a second signal 415 comprising four signal levels based on the receipt of a first signal 410 comprising two signal levels. For example, in some instances, the NMOS device 440 or 450 (e.g., an NMOS transistor) may be replaced by a p-type MOS (PMOS) transistor. Furthermore, different circuitry may be used to generate a second signal 415 comprising at least three or more different signal levels, such that the second signal 415 encodes more than one bit of data. Additionally, the voltage driver 402 and current driver 403 may include other circuit components (e.g., each CMOS branch 420 or 430 may include a resistor network or other circuit elements (not shown)) to generate a robust second signal 415, thereby mitigating various problems (e.g., jitter, distortion, width reduction, and openness of the second signal 415).

[0086] The second signal 415 can be modulated using a modulation scheme comprising at least three levels to encode more than one bit of information. The second signal 415 can be used to transmit and receive encoded information in various portions within a semiconductor package 480, which may contain semiconductor dies or chips (e.g., memory chips using DRAM, NAND, FeRAM, or 3DXP memory technologies, or combinations thereof). Because the second signal 415 represents more than one bit of information, the number of interconnects (e.g., through-silicon vias (TSVs)) between two semiconductor dies within the semiconductor package 480 can be reduced.

[0087] In some instances, the second signal 415 can be modulated such that a single level of the second signal 415 represents two bits of information (e.g., 00, 01, 10, or 11), and the number of TSVs carrying the second signal 415 can be reduced to half the number of TSVs carrying a second signal representing one bit of information (e.g., 0 or 1). By reducing the number of TSVs, the die area occupied by the TSVs can also be reduced. Furthermore, various circuitry associated with the TSVs (e.g., receivers, drivers) can be removed.

[0088] For example, a semiconductor package containing several memory chips connected via internal interconnects (e.g., TSVs) can be configured to have an external pin connected to a first number of interconnects (e.g., eleven TSVs). The metal traces between the external pin and the first number of interconnects can become a significant source of parasitic components (e.g., resistance and capacitance). A second signal 415 representing two bits of information can reduce the number of interconnects (e.g., from eleven TSVs to six TSVs), and the resulting reduction in parasitic components can improve the performance of the memory system containing the semiconductor package.

[0089] Figure 5 An exemplary diagram 501 shows a memory system interface and associated exemplary circuitry according to various embodiments of the present disclosure, and a serial-to-parallel converter 502. A memory controller 505 may be referenced. Figure 4 An example of a memory controller 405 is described. The first signal 510 and the second signal 515 may be referenced. Figure 4 Examples of the first signal 410 and the second signal 415 described herein. A serializer / serializer converter 520 may receive the first signal 510 from the computing device 120-b and generate a deserialization signal 525. In some cases, the serializer / serializer converter 520 may be referred to as a SerDes function block. A memory controller 505 may receive the deserialization signal 525 to generate the second signal 515. In some instances, the memory controller 505 may include the serializer / serializer converter 520.

[0090] Serializer / serial-to-parallel converter 520 may include serial-to-parallel converter 502 to generate a deserialization signal 525 based on the received first signal 510. Serial-to-parallel converter 502 may include comparators 530-a and 530-b and a multiplexer 540. Serial-to-parallel converter 502 may operate with a two-phase clock system, wherein a first clock signal 545-a may be associated with a first comparator 530-a, and a second clock signal 545-b may be associated with a second comparator 530-b. In some instances, each comparator 530-a and 530-b may be supplied with a first signal 510-a and a Vref signal 550. The Vref signal 550 may provide a reference voltage for comparators 530-a and 530-b to generate an output by comparing the Vref signal 550 and the first signal 510-a.

[0091] In some instances, comparator 530-a may be configured to acquire information contained in the even-numbered bits of the first signal 510-a on the rising edge of the first clock signal 545-a. Furthermore, comparator 530-b may be configured to acquire information contained in the odd-numbered bits of the first signal 510-a on the rising edge of the second clock signal 545-b. Subsequently, multiplexer 540 may compare the output signals of comparators 530-a and 530-b to generate a deserialization signal 525-a.

[0092] The specific configuration depicted in serial-to-parallel converter 502, such as using a two-phase clock system to deserialize odd and even bits, can represent an example used to illustrate the function of serializer / serial-to-parallel converter 520. Other circuit configurations may produce a deserialization signal 525 with a 2:1 deserialization factor. For example, a single-phase clock system can be used to acquire odd bits at the rising edge of a single clock signal, while even bits can be acquired at the falling edge of a single clock signal. Furthermore, different circuits can be used to generate a deserialization signal 525 with a serialization factor other than 2:1 (e.g., 4:1 or 8:1).

[0093] Figure 6 Figure 601 illustrates an exemplary memory system according to various embodiments of the present disclosure. Figure 601 shows a memory controller 605 located within a semiconductor package 680. The memory controller 605 may be used as a reference. Figure 4 and 5 Examples of memory controllers 405 or 505 are described. A semiconductor package 680 may be used as a reference. Figure 4 and 5 Examples of semiconductor packages 480 or 580 are described. In some cases, the memory controller 605 may also include reference... Figure 5 The serializer / serial-to-parallel converter 520 is described. The memory controller 605 can receive a first signal 610 from the computing device 120-c.

[0094] In some cases, computing device 120 may be referred to as host device. First signal 610 may be a reference. Figure 4 and 5 Examples of the described first signal 410 or 510. In some cases, the first signal 610 may be a binary signal containing two signal levels. In some cases, the first signal 610 may be encoded using a modulation scheme containing two unique symbols representing one bit of data. The memory controller 605 may generate a second signal 620 based on information from the first signal 610 from the computing device 120-c. The second signal 620 may be a reference. Figure 4 and 5 Examples of the described second signal 415 or 515. In some cases, the second signal 620 can be encoded using a PAM scheme. In some cases, the second signal 620 can be a PAM4 signal configured with four signal levels.

[0095] In some cases, the semiconductor package 680 may include one or more memory dies 625 (which may also be referred to as chips, semiconductor chips, and / or semiconductor dies) positioned above the memory controller 605. The memory die 625 may be referenced. Figure 1 Examples of memory dies 105 are described. Individual dies in memory dies 625, 626 may employ different memory technologies, such as DRAM, NAND, FeRAM, 3DXP, or combinations thereof. In some cases, different dies may employ memory technologies different from those of other dies in the memory stack. In some instances, semiconductor package 680 may contain a first number of memory dies 625 (e.g., eight memory dies).

[0096] Memory die 625 may be electrically coupled to memory controller 605 and stacked directly on top of each other. In some cases, memory die 625 may comprise a memory die having its own package different from semiconductor package 680. In some cases, memory die 625 may comprise one or more dies having a set of TSVs 621 to relay the second signal 620. In other words, memory die 625 may relay the second signal 620 via a set of TSVs 621. In some instances, the topmost memory die of memory 625 (e.g., memory die 625-n) may not have a TSV when it does not need to relay the second signal 620 further (in the absence of repeater 607 and the second set of memory dies 626). In some instances, each memory die in memory die 625 may contain a receiver (not shown) configured to receive and decode the second signal 620.

[0097] When the memory controller 605 transmits the second signal 620 via a set of TSVs 621, the memory controller 605 may send a chip enable (CE) signal to the memory die 625. The CE signal indicates a target memory die (e.g., 625-a, or any of the memory dies 625 depicted in FIG. 601) that receives the second signal 620. In some instances, the memory controller 605 may send the CE signal directly to the target memory die. When the target memory die (e.g., memory die 625-a) receives the CE signal, the target memory die (e.g., memory die 625-a) may activate its receiver to receive the second signal 620 and decode the information contained therein.

[0098] Other memory dies (e.g., memory dies 625 other than 625-a) may not activate their receivers to avoid the power consumption associated with activating them. In some instances, the CE signal may be encoded, for example, using a PAM scheme. In these cases, one or more memory dies 625 may include another receiver configured to decode the CE signal to determine whether they are intended to receive the second signal 620. Once the target memory die (e.g., memory die 625-a) determines that it is intended to receive the second signal 620, it may activate its receiver configured to receive the second signal 620 and decode the information contained therein.

[0099] Figure 601 further illustrates a repeater 607 and a second set of memory dies 626 located in the same position within a semiconductor package 680. The repeater 607 and the second set of memory dies 626 may be positioned above a first set of memory dies 625. The second set of memory dies 626 (e.g., memory dies 626-a to 626-m) may be one or more memory chips or dies employing the same or different memory technologies, such as DRAM, NAND, FeRAM, 3DXP, or combinations thereof. In some cases, memory dies 626 may include one or more dies having a set of TSVs 622 to relay a multi-level signal containing a second signal 620. In some instances, the topmost memory die (e.g., memory die 626-m) may not contain a TSV when it is not necessary to relay the signal further. In some instances, each memory die in the memory dies 626 may include a receiver (not shown) configured to receive and decode signals.

[0100] The repeater 607 mitigates problems associated with the vertical distance traveled by the second signal 620. In some cases, this problem may be referred to as the Z-height limitation problem. The Z-height limitation problem can occur when a first number of memory dies 625 (e.g., eight memory dies) form a vertical distance that may be long enough to cause degradation of the second signal 620 received at the next memory die (e.g., memory die 626-a in the absence of repeater 607). Therefore, decoding of the second signal 620 may fail due to degradation of the second signal 620 (e.g., at memory die 626-a in the absence of repeater 607). In some instances, after traveling the vertical distance associated with the first number of memory dies 625, jitter, distortion, and reduced-amplitude extended rise and fall times may contribute to the degradation of the second signal 620.

[0101] Repeater 607 can be electrically coupled to a first set of memory dies 625 via a first set of TSVs 621 and to a second set of memory dies 626 via a second set of TSVs 622. Repeater 607 can be configured to receive a second signal 620 via the first set of TSVs 621 and retransmit the second signal 620 to the second set of memory dies 626 positioned above the first set of memory dies 625 via the second set of TSVs 622. Repeater 607 may be referred to as a retransmission driver based on its signal retransmission function. In some instances, the first set of memory dies 625 may be referred to as the first layer, and the second set of memory dies 626 may be referred to as the second layer.

[0102] As described above, in some instances, a first number of memory dies 625 may include a first set of TSVs 621 through which the second signal 620 can be relayed. Furthermore, in some instances, a second number of memory dies 626 may include a second set of TSVs 622 through which the second signal 620 can be relayed. A memory controller 605, referred to as the primary master, is configured to communicate with a repeater 607 when the memory controller 605 sends the second signal 620 to the second number of memory dies 626. In some instances, a set of pass-through TSVs (not shown) may be used to directly couple the memory controller 605 and the repeater 607. The pass-through TSVs may be configured with structural features different from the first set of TSVs 621 or the second set of TSVs 622 (e.g., smaller three-dimensional dimensions and fewer in number) because the signal characteristics between the repeater 607 and the memory controller 605 are relatively simpler in the absence of various circuits associated with the first or second set of TSVs.

[0103] The memory controller 605 can be restricted from accessing the memory dies 625 in the first layer when transmitting the second signal 620 to the second number of memory dies 626 in the second layer. This restriction stems from the fact that a first set of TSVs 621 associated with the first number of memory dies 625 can be used to relay the second signal 620 to the second number of memory dies 626 in conjunction with a repeater 607 that receives and retransmits the second signal 620. In other words, access to the first number of memory dies 625 in the first layer and access to the second number of memory dies 626 in the second layer can be performed in a time-division manner.

[0104] In some instances, during a first time duration, memory controller 605 may access a first number of memory dies 625 in the first layer, while a second number of memory dies 626 in the second layer are isolated. During a second time duration following the first time duration, memory controller 605 (e.g., a primary master controller) cooperates with repeater 607 (e.g., a re-driver) to access the second number of memory dies 626 in the second layer via a first set of TSVs 621 and a second set of TSVs 622, while the first number of memory dies 625 in the first layer are isolated.

[0105] Figure 601 further illustrates a third group of TSVs 623 located in the same position within the semiconductor package 680. The third group of TSVs 623 can be electrically coupled to the memory controller 605 and the repeater 607. Figure 6 A single representation of the third set of TSVs 623 is shown to enhance the visibility and clarity of the depicted features. Additional configurations are envisioned. The third set of TSVs 623 may alleviate problems associated with the time-division multiplexing of access to a first number of memory dies 625 in the first layer and a second number of memory dies 626 in the second layer. The memory controller 605 may generate a signal 620-a to be transmitted via the third set of TSVs 623. Signal 620-a may be considered a modified instance of the second signal 620 because it bypasses the first number of memory dies 625.

[0106] For example, signal 620-a may be identical to the second signal 620, except that signal 620-a may be less susceptible to degradation associated with the second signal 620 that passes through the first number of memory dies 625. The third set of TSVs 623 may be configured with structural features of the first set of TSVs 621 or the second set of TSVs 622 (e.g., similar three-dimensional dimensions and number). The memory controller 605 may be configured to communicate with the repeater 607 when the memory controller 605 transmits signal 620-a to the second number of memory dies 626 via the third set of TSVs 623. Furthermore, the repeater 607 may be configured to receive signal 620-a via the third set of TSVs 623 and retransmit signal 620-a to the second number of memory dies 626 via the second set of TSVs 622.

[0107] In some instances, the addition of a third set of TSVs 623 enables the memory controller 605 to access a first number of memory dies 625 and a second number of memory dies 626 simultaneously, or at least during partially overlapping periods. In other words, the memory controller 605 can operate independently of the second number of memory dies in the second layer when sending the second signal 620 to the first number of memory dies 625 in the first layer. Simultaneously, or at least during partially overlapping periods, the memory controller 605 (e.g., a primary controller) cooperates with a repeater 607 (e.g., a re-driver) to access the second number of memory dies 626 in the second layer due to the presence of a third set of TSVs 623 that simultaneously relays signal 620-a and the second signal 620. Therefore, the configuration depicted in FIG. 601 can support an expansion of memory capacity in both the first and second layers to improve the performance of the memory system.

[0108] Figures 7 to 8 This diagram illustrates a memory device configured to transmit one or more binary symbol signals and / or one or more multi-symbol signals using dedicated signal paths within the memory device for transmitting specific types of signals (e.g., binary symbol signals or multi-symbol signals). The memory device can transmit data over numerous channels within the memory device using binary or multi-level signaling, such as NRZ and PAM. Signals can be transmitted via different dedicated signal paths, which can improve read and write times, reduce power consumption, and / or increase the reliability of the memory device. Reference Figures 7 to 8 The described features and / or functions may be compared with those in reference. Figures 1 to 6 and Figures 9 to 22 Other features and / or combinations of functions of the described memory device.

[0109] Figure 7 Example memory device 700 according to various embodiments of the present disclosure is shown. Memory device 700 may be as described in reference... Figure 1An example of the described system 100. The memory device 700 may include a memory controller 705, a first memory die 710, a second memory die 715, and a host 740. In some instances, the memory controller 705 may include an encoder 745 and a path selection component 750. In other instances, the first memory die 710 may be coupled to the memory controller 705 via a first signal path 720 and a second signal path 725.

[0110] The second memory die 715 can be coupled to the memory controller 705 via the third signal path 730 and the fourth signal path 735. In some embodiments, the first signal path 720, the second signal path 725, the third signal path 730, and the fourth signal path 735 can be as described in the reference. Figure 1 This describes a particular example of the internal signal path 115. In other examples, the first memory die 710 and the second memory die 715 may be as described in the reference. Figure 1 The described memory die 105 is a particular example. Alternatively or alternatively, for example, the memory controller 705 may be as referenced. Figure 1 The described memory controller 110 is an example. In other examples, the host 740 may be as shown in the reference. Figure 1 An example of the computing device 120 described.

[0111] The first memory die 710 may include one or more memory cells (not specified), which may be referred to as the multiple memory cells of the first memory die 710. In some instances, the memory controller 705 may transmit one or more signals to the multiple memory cells of the memory die 710 via a first signal path 720 and a second signal path 725. For example, the first signal path 720 may be coupled to the memory controller 705 and the first memory die 710 and may be configured to transmit multi-level signals to the first memory die 710. Alternatively or alternatively, for example, the second signal path 725 may be coupled to the memory controller 705 and the first memory die 710 and may be configured to transmit binary symbol signals to the first memory die 710.

[0112] In other instances, each of the first signal path 720 and the second signal path 725 can be configured to transmit a multi-level signal or a binary symbol signal to the first memory die 710. In some instances, each of the signal paths can be configured to transmit a dedicated signal type. For example, the first signal path 720 and the second signal path 725 can be configured to transmit a binary symbol signal. In other instances, the third signal path 730 and the fourth signal path 735 can be configured to transmit a multi-level signal. In other instances, any one of the first signal path 720, the second signal path 725, the third signal path 730, and the fourth signal path 735 can be configured to transmit a binary symbol signal or a multi-level signal.

[0113] The memory die 715 may contain one or more memory cells (e.g., as referenced). Figure 2 As described, these may be referred to as a plurality of memory cells of a second memory die 715. In some instances, the memory controller 705 may transmit one or more signals to the plurality of memory cells of the memory die 710 via a third signal path 730 and a fourth signal path 735. For example, the third signal path 730 may be coupled to the memory controller 705 and the second memory die 715 and may be configured to transmit a multi-level signal to the second memory die 715. Alternatively or alternatively, for example, the fourth signal path 735 may be coupled to the memory controller 705 and the second memory die 715 and may be configured to transmit a binary symbol signal to the second memory die 715. In other instances, each of the third signal path 730 and the fourth signal path 735 may be configured to transmit a multi-level signal or a binary symbol signal to the second memory die 710.

[0114] In some instances, path selection component 750 may facilitate the selection of one or more paths. For example, path selection component 750 may select a first signal path 720 to transmit signals to a first memory die 710. In other instances, path selection component 750 may select a third signal path 730 to transmit signals to a second memory die 715. In any instance, path selection component 750 may select one or more signal paths based on signal type (e.g., binary symbol signal), data type being transmitted (e.g., control data), or the availability of the channel used for data transmission.

[0115] In an additional example, each of the first memory die 710 and the second memory die 715 may receive a multi-level or binary symbol signal in response to a CE signal (e.g., chip enable). For example, the memory controller 705 may transmit a CE signal to one of the first memory die 710 or the second memory die 715. Upon receiving the CE signal, one of the first memory die 710 or the second memory die 715 may instruct the memory controller 705 to transmit a multi-level or binary symbol signal.

[0116] In some instances, memory device 700 may include a bus binary symbol signal configured to transmit a multi-level signal or a binary-level signal along any of the signal paths. When transmitting the multi-level signal or binary symbol signal, the bus or memory controller 705 may transmit the signal based on the timing of a system clock. In some instances, the system clock may be associated with (e.g., integrated with) the memory controller 705. In other instances, the system clock may be external to the memory controller 705. For example, the memory controller 705 may transmit a multi-level signal, a binary-level signal, or both during the rising edge, falling edge, or both of the system clock.

[0117] Specific data can be transmitted in each of the multi-level signal and the binary symbol signal. For example, the multi-level signal may contain control data, while the binary level signal may contain metadata. In other instances, the multi-level signal may contain metadata, while the binary level signal may contain control data. In other instances, the multi-level signal may contain either metadata or control data, while the binary symbol signal may contain either metadata or control data. In other instances, either the multi-level signal or the binary symbol signal may contain stored data. The stored data may correspond to one or more memory cells of the first memory die 710 or the second memory die 715. In some instances, one or both of the metadata and control data may be transmitted to one or more memory devices or one or more stacks of a single memory device. In other instances, one or both of the metadata and control data may be redundantly stored in more than one memory device. For example, one or both of the metadata and control data may be stored in a NAND device as long-term backup data and may be transmitted simultaneously to both the NAND device and the DRAM device.

[0118] In any configuration, multilevel signals and binary symbol signals can be transmitted simultaneously by memory controller 705. For example, at least a portion of the multilevel signal can be transmitted to first memory die 710, while at least a portion of the binary symbol signal can be transmitted to second memory die 715. Signals can be transmitted such that a portion or all of each signal is transmitted at the same time—for example, during the rising edge of the system clock of memory controller 705.

[0119] Each of the multilevel and binary level signals can be modulated using a modulation scheme. In some instances, the multilevel and binary level signals can be modulated using an encoder 745. For example, the multilevel signal can be modulated using a pulse amplitude modulation (PAM) scheme, while the binary symbol signal can be modulated using a non-return-to-zero (NRZ) scheme. In a PAM modulation scheme, the multilevel signaling can include PAM4 signaling, PAM8 signaling, etc. In this modulation scheme, for example, data (e.g., control data or metadata) can be encoded in terms of the signal amplitude. An amplitude or a single symbol can represent one bit of data. In other instances, an amplitude or a single symbol can represent two or more bits of data.

[0120] For example, a signal can be demodulated by detecting its amplitude level over a given time period. In another instance, a binary level signal can be modulated using a dual-level amplitude modulation scheme (e.g., an NRZ modulation scheme). In such an instance, a logic "1" can be represented by a first voltage level (e.g., a positive voltage), and a logic "0" can be represented by a second voltage level (e.g., a negative voltage). In other instances, a dual-level amplitude modulation scheme can include non-return-to-zero (NRZ(L)), non-return-to-zero inverted (NRZ(I)), non-return-to-zero marker (NRZ(M)), non-return-to-zero space (NRZ(S)), or non-return-to-zero change (NRZ(C)) modulation schemes.

[0121] Figure 8 Example process flowchart 800 is shown, illustrating various embodiments of the present disclosure. Process flowchart 800 may illustrate, as referenced... Figure 7 The described memory device 700 implements one or more operations. Process flowchart 800 may include operations implemented by memory controller 805, memory die 810, and memory die 815. In some instances, memory controller 805, memory die 810, and memory die 815 may be instances of memory controller 705, memory die 710, and memory die 715, as referenced... Figure 1 As described. In other instances, memory die 810 and memory die 815 may be referred to as first memory die 810 and second memory die 815, respectively.

[0122] At block 820, memory controller 805 can identify first data to be transferred to first memory die 810. For example, first memory die 810 may contain one or more memory cells, which may be referred to as a plurality of memory cells. In some instances, first memory die 810 may contain ferroelectric memory cells, dynamic random access memory cells, NAND memory cells, NOR memory cells, or combinations thereof. The first data may contain, for example, metadata or control data, and can be transmitted via, as referenced... Figure 1 The described host computing device 120 is provided to the memory controller 805.

[0123] In other instances, data can be stored via, as referenced... Figure 1 The described host computing device 120 is provided to a memory controller 805. In some instances, stored data may be associated with one or more memory cells of a first memory die 810 or a second memory die 815. After identifying the first data, the memory controller 805 may determine the modulation scheme of the data at block 825. (Refer to the above...) Figure 7 As described, the first data can be modulated using a multi-symbol modulation scheme (e.g., PAM) or a binary symbol modulation scheme (e.g., NRZ) that can correspond to multi-level and binary symbol signals, respectively.

[0124] At block 830, memory controller 805 can select a signal path for transmitting the first data. The signal path may be, for example, as shown in reference [reference needed]. Figure 7 One of the described first signal path 720, second signal path 725, third signal path 730, or fourth signal path 735. Also refer to... Figure 7 The signal path may be a wire in a through-silicon via (TSV). Once the signal path is selected, the memory controller 805 can transmit a first signal modulated using a modulation scheme to the first memory die 810 via transmit 235. In some cases, the memory controller 805 may select the signal path. The memory controller 805 may recognize one or more capabilities (e.g., bandwidth) of the signal path or the availability of the signal path for transmission.

[0125] For example, memory controller 805 can identify the type of signal that can be transmitted using a signal path. If the signal path is configured to transmit the type of signal requested to be transmitted (e.g., the signal is a multi-symbol signal, and the signal path is configured to transmit multi-symbol signals), then memory controller 805 can select the given signal path. In some cases, the availability of the signal path (e.g., bandwidth) may also be considered when selecting the signal path. In other instances, the signal path may be selected by memory controller 805 based on the type of signal being transmitted (e.g., a binary symbol signal). When transmitting the first signal, memory controller 805 may transmit the first signal based on the timing of the system clock. In some instances, the system clock may be associated with memory controller 805 (e.g., integrated). In other instances, the system clock may be external to memory controller 805. For example, memory controller 805 may transmit the first signal during the rising edge of the system clock, the falling edge of the system clock, or both.

[0126] For example, the memory controller 805 can identify control data to be transferred to the first memory die 810. After identifying the control data, the memory controller 805 can select a PAM modulation scheme to encode the control data in the multi-symbol signal, and can select a first signal path 720 (as per reference). Figure 7 The signal path 720 is used to transmit a multi-symbol signal encoded with control data. The selection of signal path 720 may be based at least in part on the determination of the PAM modulation scheme. In some instances, the selection of a different signal path (e.g., a third signal path 730) may be based at least in part on the selection of a different modulation scheme (e.g., an NRZ modulation scheme). In any instance, the memory controller 805 may use the first signal path (e.g., signal path 720) to transmit a first signal modulated using the PAM modulation scheme to the first memory die 810.

[0127] In another example, memory controller 805 may identify second data at block 840. The second data may contain, for example, metadata or control data, and may be provided to memory controller 805 via a host (not shown). In other examples, the second data may contain storage data that can be associated with either first memory die 810 or second memory die 815. In some examples, the second data may be of the same data type as the identified first data; in other examples, the second data may be of a different data type (e.g., metadata) than the identified first data. After identifying the second data, memory controller 805 may determine the modulation scheme of the data at block 845. As described above, the second data may be modulated using a multi-symbol modulation scheme (e.g., PAM4) or a binary symbol modulation scheme (e.g., NRZ modulation).

[0128] At block 850, memory controller 805 can select a signal path for transmitting the second data. The signal path may be, for example, as shown in reference [reference needed]. Figure 7 One of the described first signal path 720, second signal path 725, third signal path 730, or fourth signal path 735. Also described above, the signal path can be a wire in the TSV. In some instances, the type of the signal path can be the same as the type of the signal path used to transmit the first signal; in other instances, the type of the signal path can be different from the type of the signal path used to transmit the first signal.

[0129] Once a signal path is selected, at block 850, the memory controller 805 can transmit a second signal modulated using a modulation scheme to the first memory die 810 using the predetermined signal path. This can be done via transmit 855. When transmitting the second signal, the memory controller 805 can transmit the first signal based on the timing of the system clock. For example, the memory controller 805 can transmit the second signal during the rising edge of the system clock, the falling edge of the system clock, or both. In other instances, the memory controller 805 can transmit the first and second signals simultaneously. For example, at least a portion of the first signal can be transmitted to the first memory die 810, while at least a portion of the second signal can be transmitted to the second memory die 815 simultaneously. Signals can be transmitted such that a portion or all of each signal is transmitted at the same time—for example, during the rising edge of the system clock of the memory controller 805.

[0130] For example, the memory controller 805 can identify second control data to be transferred to the first memory die 810. After identifying the second control data, the memory controller 805 can determine the NRZ modulation scheme of the second control data and can select, for example, a second signal path 725 (as shown in the reference). Figure 7 (As described) to transmit control data. The selection of signal path 725 may be based at least in part on the determination of the NRZ modulation scheme. Therefore, memory controller 805 may use the second signal path (e.g., signal path 720) to transmit a second signal modulated using the NRZ modulation scheme to the first memory die 810.

[0131] In another example, by transmitting 860, the memory controller 805 can transmit a first signal to the second memory die 815. For example, the second memory die 815 may contain one or more memory cells, which may be referred to as a plurality of memory cells. In some examples, the plurality of memory cells of the second memory die 815 may contain memory cells of a different type than those of the first memory die 810.

[0132] As an example above, the first data may include control data and may be modulated using a multi-symbol modulation scheme. The first data may, for example, be transmitted via a third signal path (e.g., as referenced). Figure 7 The first data is transmitted to the second memory die 815 via the described signal path 730. However, in other instances, the first data may contain different types of data and / or be modulated using an NRZ modulation scheme. In either case, the modulation scheme may be at least partially based on the data type of the first data (e.g., control data). The first data may then be transmitted via, for example, through a different signal path (e.g., as described in reference 730). Figure 7 The fourth signal path (735) described herein is transmitted to the second memory die 815.

[0133] Alternatively or alternatively, for example, the memory controller 805 may transmit a second signal to the second memory die 815 via transmitter 865. As an example above, the second data may contain metadata and may be modulated using an NRZ modulation scheme. The second data may, for example, be transmitted via a fourth signal path (e.g., as referenced). Figure 1 The second data is transmitted to the second memory die 815 via the described signal path 735. However, in other instances, the second data may contain different types of data and / or be modulated using a PAM modulation scheme. In either case, the modulation scheme may be at least partially based on the data type of the first or second data (e.g., control data). The second data may then be transmitted via, for example, a different signal path (e.g., as described in reference 735). Figure 1 The third signal path (730) described is transmitted to the second memory die 815.

[0134] Figures 9 to 13 A memory device configured to support both multi-symbol signaling and binary symbol signaling is illustrated, and the memory device can utilize various signaling modes to adjust the data transfer rate or reduce the output pin count (e.g., reduce the number of active output pins in the signaling scheme). In some cases, the memory device may include a memory array coupled to a buffer, wherein the buffer is coupled to a multiplexer configured to output a group of bits comprising more than one bit, such as a bit pair. Additionally, the multiplexer may be coupled to a driver, wherein the driver may be configured to generate a symbol representing the group of bits. The symbol may represent an integer number of bits (e.g., a PAM4 symbol representing two bits) or a non-integer number of bits (e.g., a PAM3 symbol representing more than one but less than two bits). The symbol representing the group of bits may be output on an output pin of the memory device. Reference Figures 9 to 13 The described features and / or functions may be compared with those in reference. Figures 1 to 8 and Figures 14 to 22 Other features and / or combinations of functions of the described memory device.

[0135] Figure 9 Example circuit 900 according to various embodiments of the present disclosure is shown. Circuit 900 may include memory array 905, output circuit 935, and output pin 925. Output circuit 935 may include buffer 910, multiplexer 915, and driver 920.

[0136] Memory array 905 can store data and may include multiple memory cells, which may be volatile memory cells, non-volatile memory cells, or a combination thereof. Memory array 905 may include one or more memory dies (e.g., reference...). Figure 1 The memory die 905 is described. In some instances, the memory array 905 may be coupled to the output circuitry 935, and may be directly or indirectly coupled to the buffer 910 within the output circuitry 935. For example, the memory array 905 may be coupled to a data bus, and the buffer 910 may also be coupled to the data bus. The data bus may be a serial or parallel data bus. Other components not shown in circuitry 900 may also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0137] Data stored in memory array 905 can be sensed or read by one or more memory sensing components, and buffer 910 can store bits reflecting the data stored in memory array 905 for a certain time length before supplying such bits to multiplexer 915. Buffer 910 may contain several logically or physically distinct parts—for example, one or more logically or physically distinct buffers may be contained within buffer 910. For example, buffer 910 may contain at least one first buffer and a second buffer. The buffers contained in buffer 910 may be instances of first-in-first-out (FIFO) buffers.

[0138] Buffer 910 can, for example, simultaneously supply multiple bits to multiplexer 915 via a parallel interface. For instance, in some instances, buffer 910 can simultaneously supply eight bits to multiplexer 915. Alternatively, buffer 910 can intermittently supply bits to multiplexer 915. For example, buffer 910 can supply one set of bits to multiplexer 915 and wait for several clock cycles before supplying the next set of bits to multiplexer 915, the number of clock cycles between sets of bits being at least partially based on the number of clock cycles required for multiplexer 915 to process or at least partially process the previous set of bits.

[0139] Multiplexer 915 can also be referred to as serializer in some cases. It can receive multiple sets of bits from buffer 910, such as bits output simultaneously by buffer 910, and can output the received bits sequentially. Therefore, multiplexer 915 can act as a parallel-to-serial converter—for example, multiplexer 915 can receive parallel bits from buffer 910 and output the corresponding serial bits.

[0140] In some cases, multiplexer 915 may comprise several logically or physically distinct parts—for example, one or more logically or physically distinct multiplexers may be included within multiplexer 915. The parts of multiplexer 915 may be arranged in parallel with each other, in series with each other, or in some other cascaded manner (e.g., as multiple stages of multiplexing). For example, as shown in circuit 900, multiplexer 915 may include a first multiplexer 915-a, a second multiplexer 915-b, and a third multiplexer 915-c. Multiplexer 915-a may be an example of a first multiplexer that can be configured to process bits output from a first buffer in buffer 910.

[0141] Multiplexer 915-b may be an example of a second multiplexer configurable to process bits output from the second buffer in buffer 910. In some instances, both first multiplexer 915-a and second multiplexer 915-b can serialize the same number of bits. For example, both first multiplexer 915-a and second multiplexer 915-b may be four-to-one multiplexers (e.g., both can receive four bits through four parallel inputs and cascade those four bits through a single serial output), and thus collectively include an eight-to-two multiplexer. The third multiplexer 915-c can be a two-to-one multiplexer that serializes the corresponding outputs of the first multiplexer 915-a and the second multiplexer 915-b, so that the first multiplexer 915-a, the second multiplexer 915-b, and the third multiplexer 915-c together act as an eight-to-one multiplexer. For example, multiplexer 915-c can receive one bit of information from multiplexer 915-a and one bit of information from multiplexer 915-b through different parallel inputs, and output those two bits in series through a single serial output. In some cases, buffer 910 can supply bits to multiplexer 915 and then wait for a predetermined number of clock cycles before supplying additional bits to multiplexer 915.

[0142] In some instances, multiplexer 915 may be coupled to driver 920. Driver 920 may also be coupled to output pin 925. Driver 920 may be configured to receive bits from multiplexer 915, generate a symbol representing each bit received from multiplexer 915, and supply such symbol to output pin 925. For example, driver 920 may be a two-level signal driver and may generate a symbol for each bit output by multiplexer 915 and supply the symbol to output pin 925. In some cases, two-level signal drivers use non-return-to-zero (NRZ) modulation schemes, single-pole coded modulation schemes, bipolar coded modulation schemes, Manchester coded modulation schemes, PAM2 modulation schemes, etc., to encode data.

[0143] In some cases, the memory array 905 may be coupled to multiple circuits 900. For example, the memory array 905 may be coupled to eight circuits 900, and those eight circuits 900 may be configured together to output eight two-level signal symbols (commonly representing eight bits of information stored in the memory array 905) at each rising edge, each falling edge, or each rising and falling edge of a clock signal. These may be examples of x8 (or byte mode) two-level signal operation modes. As another example, the memory array 905 may be coupled to sixteen circuits 900, and those sixteen circuits 900 may be configured together to output sixteen two-level signal symbols (commonly representing sixteen bits of information stored in the memory array 905) at each rising edge, each falling edge, or each rising and falling edge of a clock signal. These may be examples of x16 two-level signal operation modes. Those skilled in the art will appreciate that other numbers of circuits 900 may be used in two-level signal operation modes.

[0144] Figure 10 Example circuit 1000 according to various embodiments of the present disclosure is shown. Circuit 1000 may include memory array 1005, output circuit 1035 and output pin 1025. Output circuit 1035 may include buffer 1010, multiplexer 1015 and driver 1020.

[0145] Memory array 1005 can store data and may include multiple memory cells, which may be volatile memory cells, non-volatile memory cells, or a combination thereof. In some instances, memory array 1005 may be coupled to output circuitry 1035 and may be directly or indirectly coupled to buffer 1010 within output circuitry 1035. For example, memory array 1005 may be coupled to a data bus, and buffer 1010 may also be coupled to the data bus. The data bus may be a serial or parallel data bus. Other components not shown in circuitry 1000 may also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0146] Data stored in memory array 1005 can be sensed or read by one or more memory sensing components, and buffer 1010 can store bits reflecting the data stored in memory array 1005 for a certain time length before supplying such bits to multiplexer 1015. Buffer 1010 may contain several logically or physically different parts—for example, one or more logically or physically different buffers may be contained within buffer 1010. For example, buffer 1010 may contain at least a first buffer 1010-a and a second buffer 1010-b.

[0147] Buffers 1010-a and 1010-b may be instances of FIFO buffers. The first buffer 1010-a can process bits corresponding to data stored in a first portion of the memory array 1005, and the second buffer 1010-b can process bits corresponding to data stored in a second portion of the memory array 1005. In some cases, the first portion of the memory array 1005 may be closer to buffer 1010 than the second portion of the memory array 1005. Buffer 1010 may, for example, simultaneously supply multiple bits to multiplexer 1015 via a parallel interface. In some cases, the first buffer 1010-a and the second buffer 1010-b can process bits corresponding to data stored in the same part of the memory array 1005, including data stored in the same memory cell within the memory array 1005 (for example, the memory cell can be a memory cell that supports the storage of non-binary symbols, such as a four-level NAND memory cell that can be programmed into one of four logic states, and the first buffer 1010-a can process the first bit, the second buffer 1010-b can process the second bit, and the first and second bits together represent the data stored in the memory cell).

[0148] For example, in some instances, buffer 1010 may simultaneously supply eight bits to multiplexer 1015. Alternatively, buffer 1010 may supply bits to multiplexer 1015 intermittently. For instance, buffer 1010 may supply one set of bits to multiplexer 1015 and wait for several clock cycles before supplying the next set of bits to multiplexer 1015, the number of clock cycles between sets of bits being at least partially based on the number of clock cycles required for multiplexer 1015 to process or at least partially process the previous set of bits.

[0149] Multiplexer 1015 can receive multiple sets of bits from buffer 1010 through a certain number of parallel inputs, such as bits simultaneously output by buffer 1010, and can output the received bits through a different number of parallel outputs. In some cases, multiplexer 1015 can output bits through a smaller number of parallel outputs than the number of parallel inputs through which multiplexer 1015 receives bits from buffer 1010. For example, multiplexer 1015 can simultaneously receive eight bits from buffer 1010 and output those bits through two parallel outputs—for example, as bit pairs. Bit pairs can represent data stored in memory array 1005. Therefore, multiplexer 1015 can act as a partial parallel-to-serial converter or a partial serializer.

[0150] In some cases, multiplexer 1015 may comprise several logically or physically distinct parts—for example, one or more logically or physically distinct multiplexers may be included within multiplexer 1015. The parts of multiplexer 1015 may be arranged in parallel with each other, in series with each other, or in some other cascaded manner (e.g., as multiple stages of multiplexing). For example, as shown in circuit 1000, multiplexer 1015 may include a first multiplexer 1015-a and a second multiplexer 1015-b.

[0151] The first multiplexer 1015-a may be an example of a multiplexer configurable to process bits output from the first buffer 1010-a. The second multiplexer 1015-b may be an example of a multiplexer configurable to process bits output from the second buffer 1010-b. The first multiplexer 1015-a may output the first bit of a bit group (e.g., a bit pair) to driver 1020, and the second multiplexer 1015-b may output the second bit of a bit group (e.g., a bit pair) to driver 1020. The first multiplexer 1015-a may process the first bit of a bit pair output from the first buffer 1010-a, while the second multiplexer 1015-b may process the second bit of a bit pair output from the second buffer 1010-b.

[0152] In some instances, the first bit of a bit pair may represent data stored in a first portion of memory array 1005. The second bit of the bit pair may represent data stored in a second portion of memory array 1005, which is different from the first portion of memory array 1005. In some cases, the first portion of memory array 1005 may be closer to buffer 1010 than the second portion of memory array 1005. Buffer 1010 may, for example, supply multiple bits simultaneously to multiplexer 1015 via a parallel interface.

[0153] In some cases, the first bit and the second bit in a bit pair may represent data stored in the same part of the memory array 1005, including data stored in the same memory cell within the memory array 1005 (for example, the memory cell may be a memory cell that supports the storage of non-binary symbols, such as a four-level NAND memory cell that can be programmed into one of four logic states, and the first buffer 1010-a can process the first bit, the second buffer 1010-b can process the second bit, and the first and second bits together represent the data stored in the memory cell).

[0154] In some instances, the first multiplexer 1015-a and the second multiplexer 1015-b may each be instances of a quad-to-one multiplexer, and the first multiplexer 1015-a and the second multiplexer 1015-b may therefore collectively comprise an octet-to-two multiplexer. Those skilled in the art will appreciate that the multiplexer 1015 can be configured to output groups comprising more than two bits (e.g., via more than two parallel outputs).

[0155] In some instances, multiplexer 1015 may be coupled to driver 1020. Driver 1020 may also be coupled to output pin 1025. Driver 1020 may be configured to receive each group of bits (e.g., bit pairs) from multiplexer 1015, generate a symbol representing each group of bits received from multiplexer 1015, and supply such symbol to output pin 1025. For example, driver 1020 may receive one bit from a bit pair from multiplexer 1015-a and another bit from a bit pair from multiplexer 1015-b, generate a symbol representing the bit pair, and supply the symbol representing the bit pair to output pin 1025.

[0156] In some cases, driver 1020 may be a pulse amplitude modulation (PAM) driver, and the symbol representing the bit pair may be a multi-symbol signal (e.g., PAM4) symbol. In other cases, driver 1020 may receive multiple groups of bits including more than two bits (e.g., three, four, five, six, seven, or eight bits) from multiplexer 1015, and driver 1020 may generate symbols, each representing more than two bits. For example, driver 1020 may receive multiple groups of three bits from multiplexer 1015 and generate multi-symbol signal symbols (e.g., PAM8 symbols) representing each group of bits.

[0157] In some cases, the memory array 1005 may be coupled to multiple circuits 1000. For example, the memory array 1005 may be coupled to several circuits 1000 (in some cases, eight circuits), and these circuits 1000 may be configured together to output a similar number of multi-symbol signal symbols at each rising edge of a clock signal, each falling edge of a clock signal, or both rising and falling edges of a clock signal. For example, each circuit 1000 may output symbols of a multi-level modulation scheme, where a symbol represents two bits of data. If there are eight circuits 1000, then these eight symbols will collectively represent sixteen bits of data stored in the memory array 1005.

[0158] These can be examples of x8 multi-symbol signaling operation modes. As another example, the memory array 1005 can be coupled to sixteen circuits 1000, and those sixteen circuits can be collectively configured to output sixteen multi-symbol signal symbols (e.g., collectively representing sixteen PAM4 symbols of 32 bits of information stored in the memory array 1005) at each rising edge of a clock signal, each falling edge of a clock signal, or both rising and falling edges of a clock signal. These can be examples of x16 multi-symbol signaling operation modes. Those skilled in the art will appreciate that other numbers of additional circuits 1000 can be utilized in multi-symbol signaling operation modes.

[0159] In some instances, circuit 1000 can operate at the same symbol rate (which may also be referred to as baud rate) as circuit 900, while providing twice the output data rate of circuit 900. In some instances, circuit 1000 can operate at half the symbol rate (which may also be referred to as baud rate) of circuit 900, while providing the same output data rate per pin (which may also be referred to as bandwidth per pin) as circuit 900. Therefore, circuit 1000 can advantageously provide the same data rate per pin as circuit 900, while allowing a reduction in the symbol rate (e.g., allowing a reduction in the clock rate that determines the symbol rate), which can improve the reliability, robustness, or power consumption of circuit 1000 and the system or circuitry coupled to the system.

[0160] In some instances, circuit 1000 can be obtained by disabling or bypassing the third multiplexer 915-c of circuit 900. Driver 1020 includes both a multi-symbol signal driver and a binary symbol signal driver, and can be configured to generate multi-symbol signal symbols for each group of bits received from multiplexer 1015 and binary symbol signal symbols for each bit received from multiplexer 1015.

[0161] Figure 11 Example circuit 1100 according to various embodiments of the present disclosure is shown. Circuit 1100 may include memory array 1105, output circuit 1135, and output pin 1125. Output circuit 1135 may include buffer 1110, multiplexer 1115, and driver 1120. Circuit 1100 may illustrate one or more aspects of circuit 900 or circuit 1000.

[0162] Memory array 1105 can store data and may include multiple memory cells, which may be volatile memory cells, non-volatile memory cells, or a combination thereof. In some instances, memory array 1105 may be coupled to output circuitry 1135 and may be directly or indirectly coupled to buffer 1110 within output circuitry 1135. For example, memory array 1105 may be coupled to a data bus, and buffer 1110 may also be coupled to the data bus. The data bus may be a serial or parallel data bus. Other components not shown in circuitry 1100 may also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0163] Data stored in memory array 1105 can be sensed or read by one or more memory sensing components, and buffer 1110 can store bits reflecting the data stored in memory array 1105 for a certain period of time before supplying such bits to multiplexer 1115. Buffer 1110 may contain several logically or physically different bits—for example, one or more logically or physically different buffers may be contained within buffer 1110.

[0164] For example, buffer 1110 may include at least a first buffer 1110-a and a second buffer 1110-b. Buffers 1110-a and 1110-b may be instances of FIFO buffers. The first buffer 1110-a may process bits corresponding to data stored in a first portion of memory array 1105, and the second buffer 1110-b may process bits corresponding to data stored in a second portion of memory array 1105. In some cases, the first portion of memory array 1105 may be closer to buffer 1110 than the second portion of memory array 1105. In some cases, the first buffer 1110-a and the second buffer 1110-b can process bits corresponding to data stored in the same part of the memory array 1105, including data stored in the same memory cell within the memory array 1105 (for example, the memory cell can be a memory cell that supports the storage of non-binary symbols, such as a four-level NAND memory cell that can be programmed into one of four logic states, and the first buffer 1110-a can process the first bit, the second buffer 1110-b can process the second bit, and the first and second bits together represent the data stored in the memory cell).

[0165] Buffer 1110 can simultaneously supply multiple bits to multiplexer 1115, for example, via a parallel interface. Alternatively, buffer 1110 can supply bits to multiplexer 1115 intermittently. For example, buffer 1110 can supply one set of bits to multiplexer 1115 and wait for several clock cycles before supplying the next set of bits to multiplexer 1115, the number of clock cycles between sets of bits being at least partially based on the number of clock cycles required for multiplexer 1115 to process or at least partially process the previous set of bits.

[0166] Multiplexer 1115 can receive multiple sets of bits from buffer 1110 through a certain number of parallel inputs, such as bits simultaneously output by buffer 1110, and can output the received bits through a different number of parallel outputs. In some cases, multiplexer 1115 can output bits through a smaller number of parallel outputs than the number of parallel inputs through which multiplexer 1115 receives bits from buffer 1110. For example, multiplexer 1115 can simultaneously receive sixteen bits from buffer 1110 and output those bits through two parallel outputs—for example, as bit pairs. Bit pairs can represent data stored in memory array 1105. Therefore, multiplexer 1115 can act as a partial parallel-to-serial converter or a partial serializer.

[0167] In some cases, multiplexer 1115 may comprise several logically or physically distinct parts—for example, one or more logically or physically distinct multiplexers may be included within multiplexer 1115. The parts of multiplexer 1115 may be arranged in parallel with each other, in series with each other, or in some other cascaded manner (e.g., as multiple stages of multiplexing). For example, as shown in circuit 1100, multiplexer 1115 may include a first multiplexer 1115-a, a second multiplexer 1115-b, a third multiplexer 1115-c, a fourth multiplexer 1115-d, a fifth multiplexer 1115-e, and a sixth multiplexer 1115-f.

[0168] Multiplexer 1115-a may be an example of a first multiplexer configurable to process bits output from the first buffer 1110-a in buffer 1110. Multiplexer 1115-b may be an example of a second multiplexer configurable to process additional bits output from the first buffer 1110-a in buffer 1110. In some instances, both the first multiplexer 1115-a and the second multiplexer 1115-b can serialize the same number of bits. For example, both the first multiplexer 1115-a and the second multiplexer 1115-b can be quad-to-one multiplexers (e.g., both can receive four bits through four parallel inputs and cascade those four bits through a single serial output), and thus collectively comprise an octa-to-two multiplexer. The third multiplexer 1115-c can be a two-to-one multiplexer, such that the first multiplexer 1115-a, the second multiplexer 1115-b, and the third multiplexer 1115-c together act as an eight-to-one multiplexer. For example, the third multiplexer 1115-c can receive one bit of information from the first multiplexer 1115-a and one bit of information from the second multiplexer 1115-b through different parallel inputs, and output those two bits in series through a single serial output.

[0169] In some instances, multiplexer 1115 may additionally include a fourth multiplexer 1115-d, a fifth multiplexer 1115-e, and a sixth multiplexer 1115-f. Multiplexer 1115-d may be an instance of a first multiplexer configurable to process bits output from the second buffer 1110-b in buffer 1110. Multiplexer 1115-e may be an instance of a second multiplexer configurable to process bits output from the second buffer 1110-b in buffer 1110. In some instances, both the fourth multiplexer 1115-d and the fifth multiplexer 1115-e can serialize the same number of bits.

[0170] For example, the fourth multiplexer 1115-d and the fifth multiplexer 1115-e can both be 4-to-1 multiplexers (e.g., both can receive four bits through four parallel inputs and output those four bits in series through a single serial output), and thus collectively constitute an 8-to-2 multiplexer. The sixth multiplexer 1115-f can be a 2-to-1 multiplexer such that the fourth multiplexer 1115-d, the fifth multiplexer 1115-e, and the sixth multiplexer 1115-f collectively act as an 8-to-1 multiplexer. For example, the sixth multiplexer 1115-f can receive one bit of information from the fourth multiplexer 1115-d and one bit of information from the fifth multiplexer 1115-e through different parallel inputs, and output those two bits in series through a single serial output.

[0171] Therefore, multiplexer 1115 can function as a sixteen-to-two multiplexer comprising two octet multiplexers arranged in parallel, wherein each octet multiplexer processes bits from a different portion of buffer 1110. Those skilled in the art will appreciate that multiplexer 1115 can be configured to output groups comprising more than two bits (e.g., via more than two parallel outputs).

[0172] In some instances, multiplexer 1115 may be coupled to driver 1120. Driver 1120 may also be coupled to output pin 1125. Driver 1120 may be configured to receive each group of bits—e.g., bit pairs—from multiplexer 1115, generate a symbol representing each group of bits received from multiplexer 1115, and supply such symbol to output pin 1125. For example, driver 1120 may receive one bit from a bit pair from a third multiplexer 1115-c and another bit from a bit pair from a sixth multiplexer 1115-f, generate a symbol representing the bit pair, and supply the symbol representing the bit pair to output pin 1125.

[0173] In some cases, driver 1120 may be a multi-symbol signal driver, and the symbol representing a bit pair may be a multi-symbol signal symbol. In other cases, driver 1120 may receive multiple groups of bits comprising more than two bits from multiplexer 1115, and driver 1120 may generate symbols, each representing more than two bits. For example, driver 1120 may receive multiple groups of three bits from multiplexer 1115 and generate multi-symbol signal symbols (e.g., PAM8 symbols) representing each group of bits.

[0174] In some cases, memory array 1105 may be coupled to multiple circuits 1100. For example, memory array 1105 may be coupled to eight circuits 1100, and those eight circuits may be configured together to output eight multi-symbol signal symbols (e.g., eight PAM4 symbols representing sixteen bits of information stored in memory array 1105) at each rising edge of a clock signal, each falling edge of a clock signal, or both rising and falling edges of a clock signal. These may be additional instances of x8 multi-symbol signal operation modes.

[0175] As another example, the memory array 1105 may be coupled to sixteen circuits 1100, and those sixteen circuits may be configured collectively to output sixteen multi-symbol signal symbols (e.g., collectively representing sixteen PAM4 symbols of 32 bits of information stored in the memory array 1105) at each rising edge of a clock signal, each falling edge of a clock signal, or both rising and falling edges of a clock signal. These may be additional examples of x16 multi-symbol signaling operation modes. Those skilled in the art will appreciate that other numbers of additional circuits 1100 may be used in multi-level signaling operation modes.

[0176] In some instances, circuit 1100 can operate at the same symbol rate as circuit 900 while providing twice the per-pin output data rate of circuit 900. Thus, circuit 1100 can advantageously achieve an increased per-pin data rate for outputting data stored in a memory array without increasing the symbol rate (e.g., without increasing the clock rate that determines the symbol rate).

[0177] In some instances, circuit 900 can be obtained from circuit 1100 by disabling or bypassing any of the eight-to-one multiplexers within multiplexer 1115 (e.g., disabling or bypassing the first multiplexer 1115-a, the second multiplexer 1115-b, and the third multiplexer 1115-c, or the fourth multiplexer 1115-d, the fifth multiplexer 1115-e, and the sixth multiplexer 1115-f). Driver 1120 comprises both a multi-symbol signal driver and a binary symbol signal driver, and can be configured to generate multi-symbol signal symbols for each group of bits received from multiplexer 915 and binary symbol signal symbols for each bit received from multiplexer 915.

[0178] In some instances, circuit 1000 can be obtained from circuit 1100 by disabling or bypassing any of the eight-to-one multiplexers within multiplexer 1115 (e.g., disabling or bypassing the first multiplexer 1115-a, the second multiplexer 1115-b, and the third multiplexer 1115-c or the fourth multiplexer 1115-d, the fifth multiplexer 1115-e, and the sixth multiplexer 1115-f) and disabling the remaining two-to-one multiplexers (e.g., disabling or bypassing the third multiplexer 1115-c or the sixth multiplexer 1115-f).

[0179] Figure 12 An example circuit 1200 according to various embodiments of the present disclosure is shown. Circuit 1200 may include a memory array 1205, an output circuit 1235, and an output pin 1225. Output circuit 1235 may include a buffer 1210, a multiplexer 1215, a first driver 1220-a, and a second driver 1220-b. Output circuit 1235 may be incorporated into references. Figure 9 , 10 The output circuits 935, 1035, or 1135 described in section 11.

[0180] Memory array 1205 can store data and may include multiple memory cells, which may be volatile memory cells, non-volatile memory cells, or a combination thereof. In some instances, memory array 1205 may be coupled to output circuitry 1235 and may be directly or indirectly coupled to buffer 1210 within output circuitry 1235. For example, memory array 1205 may be coupled to a data bus, and buffer 1210 may also be coupled to the data bus. The data bus may be a serial or parallel data bus. Other components not shown in circuitry 1200 may also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0181] Data stored in memory array 1205 can be sensed or read by one or more memory sensing components, and buffer 1210 can store bits reflecting the data stored in memory array 1205 for a certain time length before supplying the bits to multiplexer 1215. Buffer 1210 can be incorporated into a reference. Figure 9 , 10 The aspects of buffers 910, 1010, or 1110 described in 11.

[0182] Multiplexer 1215 may be an instance of a multiplexer configurable to process bits output from buffer 1210. In some cases, multiplexer 1215 may be incorporated into a reference. Figure 9 , 10Aspects of multiplexers 915, 1015, or 1115 described in section 11. The memory controller can configure multiplexer 1215 to output multiple sets of bits (e.g., bit pairs) or a single bit. In some cases, bit pairs may represent data stored within memory array 1205. Multiplexer 1215 may be coupled to a first driver 1220-a and a second driver 1220-b. In some cases, the second driver 1220-b may be parallel to the first driver 1220-a. The first driver 1220-a and the second driver 1220-b may also be coupled to output pin 1225.

[0183] In some instances, the first driver 1220-a may be configured to receive bit pairs from the multiplexer 1215, generate symbols representing the bit pairs received from the multiplexer 1215, and supply such symbols to the output pin 1225. For example, the first driver 1220-a may be a multilevel signal driver and may generate multilevel signal symbols for each bit pair output by the multiplexer 1215, and supply those multilevel signal symbols to the output pin 1225.

[0184] In some cases, the second driver 1220-b may be configured to receive bits from the multiplexer 1215, generate a symbol representing each bit received from the multiplexer 1215, and supply such symbols to the output pin 1225. For example, the second driver 1220-b may be a binary symbol signal driver and may generate binary symbol signals for each bit output by the multiplexer 1215 and supply those binary symbol signal signals to the output pin 1225.

[0185] In some cases, the memory array 1205 may be coupled to multiple circuits 1200, and the memory controller may configure one or more of the multiple circuits 1200 to implement binary symbol signaling or multi-symbol signaling (e.g., PAM4) operation modes.

[0186] Figure 13 Example circuit 1300 according to various embodiments of the present disclosure is shown. Circuit 1300 may include memory array 1305, memory controller 1310, data bus 1315, output circuitry 1335, and output pins 1325. Memory array 1305 may be as described in reference... Figures 9 to 12 Examples of memory arrays 905, 1005, 1105, and 1205 are described. Output pin 1325 may be as referenced. Figures 9 to 12 Examples of output pins 925, 1025, 1125, and 1215 are described. Output circuit 1335 can be as shown in the reference. Figures 9 to 12Examples of the output circuits 935, 1035, 1135, and 1235 are described. Circuit 1300 may include one or more aspects of circuits 900, 1000, 1100, and 1200.

[0187] Memory array 1305 can store data and may include multiple memory cells, which may be volatile memory cells, non-volatile memory cells, or a combination thereof. In some instances, memory array 1305 may be coupled to output circuitry 1335. For example, memory array 1305 may be coupled to data bus 1315, and output circuitry 1335 may also be coupled to data bus 1315. Data bus 1315 may be a serial data bus or a parallel data bus. Memory controller 1310 may also be coupled to data bus 1315. Other components not shown in circuitry 1300 may also be coupled to data bus 1315, such as one or more memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0188] In some instances, the data bus 1315 may be coupled to four, eight, sixteen, or thirty-two output circuits 1335, and those output circuits 1335 may be collectively configured by the memory controller 1310 to each output binary symbol signals (collectively representing four, eight, sixteen, or thirty-two bits of information stored in the memory array 1305). These operating modes may be referred to as x4, x8 (or byte mode), x16, or x32 binary symbol signal operating modes, respectively.

[0189] In some cases, the data bus 1315 may be coupled to four, eight, sixteen, or thirty-two output circuits 1335, and those circuits may be collectively configured by the memory controller 1310 to each output multi-symbol signal symbols (collectively representing eight, sixteen, thirty-two, or sixty-four bits of information stored in the memory array 1305). These operating modes may be referred to as x4, x8, x16, or x32 multi-symbol signal operating modes, respectively.

[0190] In some instances, the memory controller 1310 may detect periods of inactivity (which may be referred to as idle time) or periods of output data rate below a threshold data rate for a duration greater than or equal to a threshold duration, and then transmit a signal to switch operating modes. For example, the memory controller 1310 may monitor the symbol rate associated with one or more output pins (which may include identifying the associated clock rate), determine the data rate of one or more output pins based on the symbol rate (e.g., based on the number of bits represented by each symbol, which may be based on the current signaling mode already known by the memory controller 1310), compare the data rate with one or more threshold data rates, determine the duration for which the data rate is higher or lower than the threshold data rate, and adjust the signaling mode at one or more output pins between binary symbol signals or multi-symbol signal orders, or alternatively or additionally, adjust the number of active output pins to optimize the output data rate, the number of active output pins, or power consumption based on observed conditions.

[0191] For example, circuit 1300 can switch from operating eight output circuits 1335 to operating sixteen output circuits 1335. That is, a signaling mode that outputs multi-level signal symbols on a certain number of output pins 1325 can be disabled, and a signaling mode that outputs dual-level signal symbols on the same, different, or additional output pins 1325 can be enabled. In some instances, circuit 1300 can operate eight or sixteen output circuits 1335 on the same die (i.e., the same silicon device). In some cases, circuit 1300 can act as an external master component to the controlled device, and memory controller 1310 can adjust the signaling mode between the orders of binary or multi-symbol signals at one or more output pins in response to commands from the master component, or alternatively or additionally, adjust the number of active output pins.

[0192] In some instances, the memory controller 1310 may be configured to determine a first signaling mode of the circuit 1300 and to configure one or more output circuits 1335 to generate non-binary symbols, each representing two or more bits of data output from the memory array 1305. For example, the first signaling mode may be an instance of an x8 multi-symbol signaling operation mode or an x16 multi-symbol signaling operation mode. In some cases, the memory controller 1310 may be configured to determine a second signaling mode of the circuit 1300 and to configure one or more output circuits 1335 to generate binary symbols, each representing less than two bits of data output from the memory array 1305.

[0193] For example, the second signaling mode may be an instance of an x8 binary symbol signaling operation mode or an x16 binary symbol signaling operation mode. In some cases, the first and second signaling modes may use the same symbol rate. In other instances, the first and second signaling modes may use different symbol rates. For example, a multi-symbol signaling (e.g., PAM4) operation mode may utilize a symbol rate less than (half) that is used for binary symbol signaling operation mode, but provides the same data rate per pin while improving robustness, reliability, or power consumption characteristics; or it may utilize the same symbol rate but provide a larger (e.g., twice) data rate per pin.

[0194] In some cases, a second signaling mode can be configured to support the full bandwidth of the memory device using half of the available I / O pins. By applying PAM4 signaling to half of the memory device's I / O pins, the same bandwidth as using all I / O pins and NRZ signaling can be achieved. This configuration increases the number of memory dies that can be connected to the channel by reducing the per-die I / O pin count. In some instances, eight I / O pins may be connected, while another eight may be unconnected, thus mode switching may be unavailable. The memory device can operate the eight connected I / O pins in either PAM4 or NRZ mode.

[0195] In some cases, each output circuit 1335 may include a multiplexer. For example, the memory controller 1310 may configure multiplexers of at least eight output circuits 1335 to output a first output type during a first signaling mode. For example, the first output type may be a set of bits (e.g., bit pairs) and may correspond to a multi-symbol signal (e.g., PAM4) operation mode. In other instances, the memory controller 1310 may configure multiplexers of at least sixteen output circuits 1335 to output a second output type during a second signaling mode.

[0196] For example, the second output type may be a single bit and may correspond to a binary symbol signal operation mode. The memory controller 1310 may also detect the data rate associated with the memory array 1305 for a certain period of time and determine the operation mode based on the detected data rate (e.g., determining whether to output binary symbol signal symbols, multi-symbol signal symbols, or other types of symbols, determining the number of output pins 1325 through which it outputs symbols, or determining the symbol rate).

[0197] For example, if the data rate is higher than a threshold data rate, a first signaling mode can be determined to use higher-order symbols (e.g., multi-symbol signals instead of binary symbol signals), a greater number of output pins 1325 (e.g., x16 instead of x8), a higher symbol rate, or a combination thereof, to support the higher data rate. As another example, if the data rate is lower than a threshold data rate, a second signaling mode can be determined to use lower-order symbols (e.g., binary symbol signals instead of multi-symbol signals), a smaller number of output pins 1325 (e.g., x8 instead of x16), a lower symbol rate, or a combination thereof, to support the lower data rate while saving power or improving the reliability or robustness of the output signal.

[0198] Figures 14 to 19 This diagram illustrates a memory device, waveforms, and a process for dynamically selecting a modulation scheme based on one or more parameters associated with the memory device. For example, the memory device can dynamically switch between a modulation scheme and, in some cases, a frequency, to adapt to or meet operating parameters such as bandwidth or power. Because transmission under different modulation schemes and frequencies causes variations in the amount of bandwidth and power consumption, the memory device can select a combination of modulation schemes and frequencies that provides sufficient bandwidth without consuming excessive power. (Reference) Figures 14 to 19 The described features and / or functions may be compared with those in reference. Figures 1 to 13 and Figures 20 to 22 Other features and / or combinations of functions of the described memory device.

[0199] Although described with reference to a memory device, the techniques described herein can be implemented by any type of device (e.g., the techniques described herein can be implemented by a CPU or GPU communicating with a modem or other peripheral device). The techniques described herein can be used for wireless communication (e.g., communication involving signals transmitted through air), wired communication (e.g., communication involving signals transmitted through a solid medium), or both. In some cases, the techniques described herein can be used for wired systems on a substrate.

[0200] Figure 14 Examples of circuit 1400 according to various embodiments of the present disclosure are shown. In some cases, circuit 1400 may be a reference. Figure 3 An example of circuit 300 is described. Therefore, many features of circuit 1400 are similar to those of circuit 300, and certain descriptions of some features are not repeated in the figures.

[0201] Circuit 1400 may include one or more internal signal paths 1415-a to 1415-N coupling at least one memory die 1403 to a memory controller 1401. Internal signal paths 1415 may be configured to transmit multi-symbol signals 1420 or binary symbol signals 1425, or both. Memory die 1403 may be referenced. Figure 1 and 3 Examples of memory dies 105 and 305 are described. Memory controller 1401 may be used as a reference. Figure 1 and 3 Examples of memory controllers 110 and 310 are described. Signal path 1415 may be referenced. Figure 1 and 3 Examples of signal paths 115 and 315 are described. In some cases, internal signal path 1415 may be an example of a data bus or channel.

[0202] Memory controller 1401 may be coupled to host 1430 (e.g., in electronic communication with host 1430), host 1430 may or may not be part of circuitry 1400. Host 1430 may be a system-on-a-chip (SoC) or a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU)). Although shown as separate components, in some cases, host 1430 and memory controller 1401 may be the same component or may be part of a common SoC. Although described with reference to memory interfaces, the techniques described herein can be implemented for non-memory interfaces (e.g., between non-memory components within a device, or between two devices).

[0203] Memory controller 1401 may include one or more driver circuits (“drivers”) 1405. Drivers 1405 may be electrically connected to signal paths 1415 (e.g., data buses) and may be configured to transmit (e.g., send or transmit) multi-level signals and / or binary level signals through one or more signal paths 1415 (e.g., data buses). For example, driver 1405 may include circuitry that converts one or more bit streams into multi-level and / or binary level signals. The bit stream may be a number of consecutive (e.g., serialized) bits representing a dataset. In some cases, driver 1405 may include one or more drivers 1405 that have been segmented (e.g., assigning a corresponding number of legs of driver 1405 to each signal to be driven) to drive multiple (e.g., more than one) voltage levels on internal signal paths 1415.

[0204] Driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) drive circuitry 1435. Encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. Drive circuitry 1435 may be configured to receive control signals 1425 and drive a voltage on internal signal path 1415 based on control signals 1425. The voltage amplitude may represent one or more bits. Thus, a binary-level signal or a multi-level signal may be output by drive circuitry 1435 by changing the voltage amplitude driven on internal signal path 1415. Whether a signal is transmitted as a binary-level signal or a multi-level signal can be determined by the type of modulation scheme used to modulate the signal.

[0205] The type of modulation scheme used for transmission (e.g., the type of signal output by driver 1405) can be controlled by memory controller 1401 and can be based on operating parameters associated with or on devices or applications that are part of memory controller 1401, host 1430, circuitry 1400, etc. Because different modulation schemes consume different amounts of power and provide different bandwidths, memory controller 1401 can dynamically switch between modulation schemes to adjust the power consumed and the bandwidth provided for changing power constraints and bandwidth requirements (e.g., demands).

[0206] In addition to driver 1405, memory controller 1401 may also be electronically connected to one or more clock circuits 1410. Clock circuit 1410 may be configured to generate clock pulses that can be used as a timing reference for other components. For example, clock circuit 1410 may be configured to generate a first clock signal at a first frequency and a second clock signal at a second frequency. The term frequency may refer to the reciprocal of the pulse duration used to represent a symbol in binary-level signaling or multi-level signaling. The first clock signal may represent a first clock rate, and the second clock signal may represent a second clock rate. In some cases, memory controller 1401 may control the output of clock circuit 1410 (e.g., memory controller 1401 may control the frequency of the clock signal or the clock rate generated by the clock circuit).

[0207] Clock circuit 1410 may be electronically connected to driver 1405. For example, driver 1405 or a sampling component electronically connected to driver 1405 may sample clock pulses generated by clock circuit 1410. The sampled clock pulses may be used as a reference for transmitting multilevel and binary level signals at frequencies determined by memory controller 1401. For example, driver 1405 or associated components may refer to the clock pulses output by clock circuit 1410 to determine the frequency for transmitting binary or multilevel signals. Because the amount of power consumed and the bandwidth provided by transmission differ at different frequencies, memory controller 1401 may dynamically select the frequency for transmission to adapt to changing power constraints and bandwidth requirements. In some cases, memory controller 1401 may dynamically select a combination of modulation scheme and frequency to adapt to changing power constraints and bandwidth requirements, or to adapt to other operating parameters.

[0208] In one example, memory controller 1401 may receive a first data set in a first number of bit streams. For example, memory controller 1401 may receive the first number of bit streams (e.g., at encoder 1440) from a data array or user input interface electronically connected to memory controller 1401. According to the techniques described herein, memory controller 1401 may generate a first signal having a first number of levels. The first signal may be a binary level signal (e.g., an NRZ signal, such as signal 1425) or a multilevel signal (e.g., a PAM4 signal, such as signal 1420). In some cases, the first signal may be based on the first number of bit streams. For example, the first signal may represent a first data set delivered via the first number of bit streams. In some cases, the number of levels may be based on the first number of bit streams. For example, the first number of levels may be twice the number of bit streams. In some cases, the first number of bit streams may be different from the first number of levels.

[0209] After receiving the first data set, the memory controller 1401 may receive the second data set from a second bit stream that is different from the first bit stream. For example, the memory controller 1401 may receive the first bit stream from a data array or user input interface that is electronically connected to the memory controller 1401. The first bit stream may be the same as or different from the second bit stream. In some cases, the first data set may be associated with a first application, and the second data set may be associated with a second application.

[0210] According to the techniques described herein, memory controller 1401 can determine operating parameters associated with means to which memory controller 1401 is a part. For example, memory controller 1401 can determine operating parameters associated with host 1430. Operating parameters can be requirements, requests, conditions, metrics, demands, or values. The determination of operating parameters can be based on receiving a second data set, or it can be independent of receiving a second data set (e.g., the determination of operating parameters can occur before receiving the second data set). Operating parameters can be temperature parameters, bandwidth parameters, power parameters, data rate parameters, or similar parameters, or combinations thereof.

[0211] After determining the operating parameters, the memory controller may generate a second signal having a second number of levels that differ from the first number of levels. The generation of the second signal may be based on the determined operating parameters and the second number of bit streams. For example, the second signal may represent a second set of data delivered in the second bit stream, and / or the second number of levels may vary with the second number of bit streams (e.g., it may be twice the number of bit streams). In some cases, the second number of bit streams differs from the second number of levels.

[0212] In some cases, the first signal is transmitted on the channel (e.g., on internal signal path 1415) at a first frequency (e.g., a first clock frequency, a first pulse frequency, or a first data rate frequency), and the second signal is transmitted on the same channel (or a different channel) at a second frequency (e.g., a second clock frequency, a second pulse frequency, or a second data rate frequency). Therefore, the modulation scheme and frequency can be different for the two individual signals. The frequency can be based on a clock pulse output by clock circuit 1410. In other cases, the first signal is transmitted on the channel (e.g., on internal signal path 1415) at a first frequency, and the second signal is transmitted on the same channel (or a different channel) at a first frequency (e.g., at the same frequency). Therefore, the modulation scheme can be different for the two individual signals, but the frequency can be the same.

[0213] According to the techniques described herein, memory controller 1401 can be configured to transmit a first signal to memory die 1403. The first signal can be modulated using a first modulation scheme having a first number of levels. Memory controller 1401 can also be configured to determine operating parameters associated with the device to which memory controller 1401 and memory die 1403 are part. Based on the determined operating parameters, memory controller 1401 can select a second modulation scheme different from the first modulation scheme. After selecting the second modulation scheme, memory controller 1401 can transmit a second signal to memory die 1403. The second signal can be modulated using the second modulation scheme, which may have a second number of levels different from the first number of levels.

[0214] In some cases, the memory controller 1401 may be configured to transmit the first signal at a first frequency based on a first clock signal generated by the clock circuit 1410. In these cases, the memory controller 1401 may also be configured to transmit the second signal at a second frequency based on a second clock signal and based on determined operating parameters. The second frequency may be higher or lower than the first frequency.

[0215] In some cases, the operating parameters are bandwidth parameters (e.g., current bandwidth requirements) or power parameters (e.g., parameters indicating current power consumption or saving requirements). When the operating parameter is a power parameter, the memory controller 1401 can determine the power parameter by detecting whether an external power supply is connected to a means that is part of the memory controller 1401. If the first modulation scheme is NRZ and the second modulation scheme is PAM4, then the second modulation scheme can be selected when an external power supply connection is detected. Using PAM4 instead of NRZ provides more bandwidth for communication. If the first modulation scheme is PAM4 and the second modulation scheme is NRZ, then the second modulation scheme can be selected when no external power supply connection is detected. Using NRZ instead of PAM4 reduces power consumption (e.g., increases power savings).

[0216] In some cases, determining the power parameters involves estimating the duration until the internal power source reaches a threshold. The selection of a second modulation scheme can be based on this estimation. For example, if the estimation indicates that the internal power supply will be depleted within a threshold (e.g., a short) time period, then the memory controller 1401 can switch from PAM4 to NRZ to save power. If the estimation indicates that the internal power supply will not be depleted within the threshold time period, then the memory controller 1401 can switch from NRZ to PAM4 to provide more bandwidth for data communication.

[0217] In some instances, the operating parameters are the startup of an application on the device including the memory controller 1401. Some applications may define a relatively low data rate for the transfer of their application data to the memory array, while others may define a relatively high data rate. For example, a camera application may require a high data rate, especially when it is in burst mode (e.g., a mode that captures multiple photos within a short time period). A camera application may also require a relatively high data rate when, for example, it is in video mode, playback mode, 4K burst mode, etc. Other applications with high data rates may include media consumption applications, virtual reality applications, augmented reality applications, artificial intelligence applications, machine learning applications, and the like.

[0218] Operating parameters can be associated with application startup. For example, a newly launched application may require a data rate greater than a threshold data rate. In this example, the operating parameters may instruct the application to enter a mode that requires a data rate higher than the threshold data rate. When the data rate requested or required by the application is greater than the threshold rate, the memory controller 1401 may select a multi-symbol modulation scheme (e.g., PAM4, PAM8, PAM16, etc.) as the second modulation scheme. When the data rate requested or required by the application is less than the threshold rate, the memory controller 1401 may select a dual-level modulation scheme (e.g., NRZ) as the second modulation scheme.

[0219] In some cases, the memory controller 1401 may be configured to select a first number of memory cells in the memory die 1403 to receive a first signal modulated using a first modulation scheme to represent a first data set. In other words, the memory controller may be configured to modify the page size in the memory die 1403 based on the modulation scheme being used to encode the data.

[0220] In these cases, the memory controller 1401 may also be configured to select a second number of memory cells in the memory die 1403 for receiving a second signal modulated using a second modulation scheme to represent a second data set. The second number of memory cells accessed using the second signal may differ from the first number of memory cells accessed using the first signal. For example, if the first signal is modulated using NRZ (e.g., the first signal is a binary level signal) and the second signal is modulated using PAM4 (e.g., the second signal is a multi-level signal), then the memory controller 1401 may select a small number of cells (e.g., a small page size) for receiving the first signal and a large number of cells (e.g., a larger page size) for receiving the second signal. In some cases, the first set of memory cells may be selected to overwrite with new data modulated using the second modulation scheme (e.g., a third data set). In these cases, the new data may be modulated at a data rate different from the first data rate (e.g., the second and / or third data rates may differ from the first and / or second data rates).

[0221] In some instances, the operating parameters are temperature parameters (e.g., temperature values ​​of components in the same device as memory controller 1401). Because high temperatures can damage components or impair performance, memory controller 1401 may select modulation schemes for communication that prevent or mitigate these temperatures.

[0222] For example, memory controller 1401 can determine temperature parameters by detecting the temperature associated with memory controller 1401 or a component of the same device containing memory controller 1401. If memory controller 1401 detects that the temperature associated with the component (e.g., memory controller 1401) meets a temperature threshold (e.g., a high temperature threshold), then memory controller 1401 may select NRZ as a second modulation scheme to reduce the temperature. If memory controller 1401 detects that the temperature associated with the component (e.g., memory controller 1401) does not meet a temperature threshold (e.g., the temperature is below the high temperature threshold), then memory controller 1401 may select PAM4 as a second modulation scheme to provide more bandwidth without the risk of negative effects caused by high heat.

[0223] In some cases, operating parameters are indicators or values ​​representing the ability of an external device to receive data. For example, operating parameters may indicate that the peripheral device is limited to a certain bandwidth, data rate, modulation scheme, or frequency. In these cases, the memory controller 1401 may select a second modulation scheme based on the limitations of the peripheral device. In some instances, operating parameters are communication metrics or requirements requested by the external device. For example, operating parameters may be requested data rates, bandwidth, frequencies, modulation schemes, voltage levels, etc.

[0224] Therefore, the device (e.g., a memory controller associated with the memory device) can select a second modulation scheme and / or frequency based on a request from an external device for one or more communication metrics or requirements (e.g., a second modulation scheme and / or frequency can be selected to comply with or satisfy the requested communication metrics or requirements). Alternatively or additionally, operating parameters can be based on the characteristics of the data represented by the second signal. Although described with reference to a single operating parameter, the memory controller 1401 can select a combination of modulation schemes and frequencies based on multiple operating factors. The operating parameters used as the basis for selection can be selected based on the detection of changes in the device's operation or conditions or based on a request from another device.

[0225] According to the techniques described herein, memory controller 1401 may be configured to transmit a first signal on signal path 1415 (e.g., a data bus) using a first driver 1405. The first signal may have a signal strength corresponding to one of a first number of levels representing a first data set. After determining operating parameters as described herein, memory controller 1401 may transmit a second signal on signal path 1415-a based on the determined operating parameters. The second signal may have a signal strength corresponding to one of a second number of levels representing a second data set, and the second number of levels may differ from the first number of levels. In some cases, the second signal is transmitted on signal path 1415-a using a second driver 1405 electrically connected to memory controller 1401.

[0226] In some cases, the first signal is transmitted on the first data bus and the second signal is transmitted on the second data bus. The first signal can be transmitted at a first clock rate generated by the clock circuit 1410 and the second signal can be transmitted at a second clock rate generated by the clock circuit 1410. Alternatively, the signals can be transmitted at different clock rates derived from the clock rate generated by the clock circuit 1410.

[0227] Figure 15 Exemplary diagrams illustrating waveform 1500 used in various embodiments according to the present invention are provided. The amplitude of waveform 1500, depicted as voltage, is shown as varying over time. Waveform 1500 can be transmitted between two different devices or between two components within a device. In examples of communication within a device (e.g., communication within a single device), waveform 1500 can be generated as shown in [reference missing]. Figure 14 The described memory controller 1401 generates and transmits (e.g., transmits or sends). For example, waveform 1500 may be transmitted from memory controller 1401 to memory die 1403 within the device.

[0228] According to the techniques described herein, waveform 1500 may include a first signal 1505 and a second signal 1510. Although shown as a continuous waveform, waveform 1500 may be a discontinuous waveform (e.g., an interruption may exist between the first signal 1505 and the second signal 1510, during which no data is transmitted). The first signal 1505 may be modulated using a first modulation scheme having a first number of levels, and the second signal 1510 may be modulated using a first modulation scheme having a second number of signals. For example, the first signal 1505 may be modulated using NRZ and the second signal may be modulated using PAM4. Therefore, the device may switch from transmission using the NRZ modulation scheme to transmission using the PAM4 modulation scheme (e.g., the device may switch modulation schemes). The switching may be based on operating parameters determined for the device or for components of the device (e.g., host, memory controller, SoC, processor, etc.).

[0229] The first signal 1505 can be transmitted at a first frequency, which may be based on a clock frequency generated and sampled by the device. The first frequency may be related to the pulse duration 1515 (sometimes referred to as the symbol duration) of the pulse of the first signal 1505. A single symbol may be transmitted during a single pulse duration 1515. One or more data bits may be represented in each pulse duration 1515. For example, when the first signal 1505 is modulated using NRZ, the amplitude of the signal 1505 during the pulse duration 1515 may represent fewer than two data bits (e.g., logic '0' or logic '1'). Therefore, starting from the tail pulse (i.e., read from left to right), the first signal 1505 may represent the data sequence: 1010010.

[0230] The second signal 1510 can also be transmitted at the first frequency. Therefore, the modulation scheme can be switched without switching the frequency. However, the second signal 1510 can represent a different number of bits per pulse duration 1515 compared to the first signal 1505. For example, when using PAM4 to modulate the second signal 1510, the amplitude of the signal 1510 during the pulse duration 1515 can represent two data bits. Therefore, starting from the tail pulse (i.e., read from left to right), the second signal 1510 can represent the data sequence: 00101101000110110101.

[0231] In some cases, changes in operating parameters can be detected. Based on these changes, the device can select a first modulation scheme for transmitting a third signal (e.g., a signal following the second signal 1510). Therefore, the device can transmit a third signal modulated using the first modulation scheme (e.g., NRZ) based on the selection of the first modulation scheme. In some cases, the first signal 1505 can be transmitted at a frequency different from the first frequency before transmitting the second signal 1510 (e.g., the first signal 1505 can be transmitted at the first frequency in one time period and then at another frequency in subsequent time periods).

[0232] Because different modulation schemes offer varying bandwidths and consume different amounts of power, a device can switch modulation schemes to optimize performance, efficiency, and power savings. For example, if using NRZ at a first frequency consumes less power than using PAM4 at the same frequency, the device can generally use NRZ to save power and can switch to PAM4 to accommodate bandwidth requirements above a certain threshold. Once the bandwidth requirement drops below the threshold, the device can switch back to NRZ. Although described with reference to NRZ and PAM4, the techniques described herein are applicable to any combination of pulse amplitude modulations, including PAM2 (e.g., NRZ), PAM4, PAM8, PAM16, etc. The techniques described herein are also applicable to switching from PAM4 to NRZ. Furthermore, although described with reference to two modulation schemes, switching between any number of modulation schemes is possible.

[0233] In some cases, the device can switch frequencies based on operating parameters. In other cases, the device can select modulation and frequency based on operating parameters. In these cases, two variables (modulation scheme and clock frequency) related to the encoded signal can be changed based on operating parameters. For example, the device might determine that switching from NRZ to PAM4 would provide excessive bandwidth and / or consume more power than the device can provide using the same frequency. In these cases, the device can switch the clock frequency of the encoded signal.

[0234] In some cases, the device can switch both the modulation scheme and clock frequency of the encoded signal. For example, the device can switch from using NRZ at a first frequency to using PAM4 at a second frequency lower than the first frequency. In another instance, the device may determine that switching from NRZ to PAM4 but using the same frequency does not provide sufficient bandwidth to support the bandwidth requirements. In this case, the device can switch from using NRZ at the first frequency to using PAM4 at a second frequency higher than the first frequency. Therefore, the device can adapt to changing operational constraints by customizing the modulation scheme and frequency used by the device for transmission.

[0235] Figure 16 Exemplary diagrams illustrating waveform 1600 used in various embodiments according to the present invention are provided. Waveform 1600 can be transmitted between two different devices or between components within a device. In examples of intra-device communication (e.g., communication within a single device), waveform 1600 can be generated as shown in [reference 1]. Figure 14 The described memory controller 1401 generates and transmits (e.g., transmits or sends). For example, waveform 1600 may be transmitted from memory controller 1401 to memory die 1403 within the device.

[0236] Waveform 1600 may include a first signal 1605 and a second signal 1610. The first signal 1605 may be modulated using PAM4 (e.g., using a first modulation scheme with a first number of levels), and the second signal 1610 may be modulated using NRZ (e.g., a second modulation scheme with a second number of levels). Therefore, data represented by the first signal 1605 may be transmitted using the first number of signal levels (e.g., four), and data represented by the second signal 1610 may be transmitted using the second number of signal levels (e.g., two). The device may switch between the two modulation schemes based on determining, detecting, or identifying operating parameters associated with the device (e.g., the launch of an application that requires or demands a data rate greater than a threshold data rate, or the launch of an application that consumes or provides data at a rate greater than a threshold rate). The first signal 1605 may follow a previous signal modulated using a different modulation scheme (e.g., NRZ) than the first signal 1605.

[0237] The first signal 1605 can be transmitted at a first frequency (e.g., the pulse duration 1615 may be inversely proportional to the first frequency) as the basis of the pulse duration 1615, and the second signal 1610 can be transmitted at a second frequency (e.g., the pulse duration 1620 may be inversely proportional to the second frequency) as the basis of the pulse duration 1620. Therefore, the device can switch between modulation schemes and frequencies simultaneously. While the first frequency is shown to be greater than the second frequency, the reverse is also permissible (e.g., the second frequency may be greater than the first frequency). The device can determine or select the second frequency based on operating parameters associated with the device (e.g., based on the detection of the device's battery power or power level being below or above a predetermined threshold), or components of the device (e.g., based on the temperature of the components), or applications of the device (e.g., based on the data rate requirements of the application).

[0238] Figure 17 Exemplary diagrams illustrating waveform 1700 used in various embodiments according to the present invention are provided. Waveform 1700 can be transmitted between two different devices or between components within a device. In examples of intra-device communication (e.g., communication within a single device), waveform 1700 can be generated as shown in [reference missing]. Figure 14 The described memory controller 1401 generates and transmits (e.g., transmits or sends). For example, waveform 1700 may be transmitted from memory controller 1401 to memory die 1403 within the device. Waveform 1700 may be an example of a waveform transmitted when the device switches between multiple (e.g., different) modulation schemes and multiple frequencies (e.g., in response to changes in one or more operating parameters).

[0239] Waveform 1700 may contain several signals modulated at different frequencies according to different modulation schemes. For example, waveform 1700 may contain signal 1710 modulated according to a two-level modulation scheme (e.g., NRZ), and signals 1705, 1715, and 1720 modulated according to a multi-level modulation scheme (e.g., PAM4). Signal 1705 may be transmitted based on a first frequency f1 of pulse duration 1720. At time t1, the modulation scheme and frequency of waveform 1700 may be modified. For example, the modulation scheme may be changed from PAM4 to NRZ and the frequency may be changed from f1 to f2. The modification may be based on one or more operating parameters associated with the device or a component of the device. Thus, after t1, signal 1710 may be transmitted at frequency f2 using the NRZ modulation scheme. Frequency f2 may be based on pulse duration 1725 (e.g., frequency f2 may be inversely proportional to pulse duration 1725). Although shown as f2 > f1, the second frequency f2 may be less than f1.

[0240] At time t2, the modulation scheme and frequency of waveform 1700 can be modified again. For example, the modulation scheme can be switched from NRZ to PAM4, and the frequency can be switched from f2 to f3. These modifications can be based on one or more operating parameters associated with the device or a component of the device. Thus, signal 1715 can be transmitted using the PAM4 modulation scheme at frequency f3. Frequency f3 can be based on a pulse duration 1730 that can be longer than the pulse duration 1725.

[0241] At time t3, the frequency of the transmitted waveform 1700 can be modified while maintaining the modulation scheme. For example, the modulation scheme can remain PAM4, and the frequency can be changed from f3 to f4. Before time t3, the device can determine that a change in operating parameters has occurred. The device can select frequency f4 based on the change in operating parameters. Therefore, signal 1740 can be transmitted using PAM4 at frequency f4. Frequency f4 can be based on pulse duration 1735. At time t4, the frequency can be changed again from f4 to fn. In some cases, the modulation scheme also changes. Frequency fn can be the same as or different from frequencies f1, f2, f3, and f4.

[0242] Therefore, different modulation schemes and frequencies can be used to generate and transmit different signals. The number of frequencies available or used can be a discrete number (e.g., n frequencies) and can be predetermined or dynamically determined. The frequency can be based on, for example, relative to... Figure 14 The clock rate or clock frequency generated by the described clock circuit 1410. For example, the pulse duration can be determined by sampling the clock pulse generated by the clock circuit 1410.

[0243] Selecting a specific combination of modulation scheme and frequency allows the device to achieve a desired bandwidth (e.g., data rate) and / or power consumption level. For example, the device can determine the bandwidth and power consumption provided by a specific combination of modulation scheme and frequency, and compare those values ​​with desired bandwidth and power consumption values ​​(e.g., bandwidth thresholds and power consumption thresholds). The desired bandwidth may be based on an application with data to be transmitted, and the power consumption may be based on the device's power state (e.g., the device's remaining battery power or whether the device is connected to an external power source). If the comparison yields a difference within the thresholds, the device can select the modulation scheme and frequency for communication. If the comparison yields a difference outside the thresholds, the device can select different combinations of modulation scheme and frequency for comparison.

[0244] In some cases, the process by which a device selects a modulation scheme and frequency for communication may involve the use of a lookup structure. For example, the lookup structure may contain several entries (e.g., pre-configured modulation data) indicating the bandwidth provided and power consumed associated with different combinations of modulation schemes and frequencies. Thus, the device can compare the desired bandwidth and / or power with the pre-configured modulation data to determine which combination of modulation scheme and frequency to use for communication. Although described with reference to bandwidth and power, the techniques described herein for selecting modulation schemes and frequencies may be based on bandwidth or power or on one or more other parameters.

[0245] Figure 18 Exemplary diagrams illustrating process flow 1800 supporting variable modulation schemes according to various embodiments of the present invention are provided. Features of process flow 1800 may be implemented or performed by a device (e.g., a memory controller associated with a memory device) or components of the device such as memory controller 110, SoC, processor, GPU, etc. Although described with reference to NRZ and PAM4, aspects and features of process flow 1800 may be implemented using other combinations of modulation schemes, including binary level modulation schemes and multilevel modulation schemes (e.g., QAM, PSK, etc.).

[0246] At 1805, the device can transmit a first signal modulated using a first modulation scheme (e.g., NRZ) at a first frequency. The first signal may represent a first data set, and the first modulation scheme may have a first number of levels (e.g., when the first modulation scheme is NRZ, the first modulation scheme may consist of two levels). The first signal may be transmitted between components of the device (e.g., between a memory controller and a memory array) or between the device and another device. In some instances, the first and second signals may be transmitted on the same channel at different times (e.g., via time multiplexing), or on the same channel at overlapping times, or on different channels simultaneously (e.g., concurrently), or on different channels at different times (e.g., not simultaneously), or at overlapping times. At 1810, the device can determine operating parameters associated with the device or components of the device (e.g., host, SoC, processor, memory die, memory controller, etc.).

[0247] For example, the device can determine power parameters associated with the device. The device can determine the power parameters by determining whether the device is connected to an external power supply (e.g., by determining whether the device can draw power from an external power source such as a socket, battery, battery charger, and the like). If the device is detected as connected to an external power source, then at 1815 the device can select a second modulation scheme (e.g., PAM4) that differs from the first modulation scheme, at least in part, based on the detection. The second modulation scheme can be used to modulate a second signal (which represents a second data set) and can have a second number of levels (e.g., four levels) different from the first number of levels.

[0248] If the device is not connected to an external power source, it can determine at 1820 whether its battery life (e.g., battery charge) is greater than a threshold battery life (e.g., threshold charge). For example, the device can estimate the duration until the internal power source (e.g., battery) reaches the threshold. If the device determines that the estimated duration is less than the threshold duration, it can maintain transmission at the first frequency using NRZ at 1825. If the device determines that the duration is greater than the threshold duration (e.g., the device has more than x hours until the internal power source has y% remaining battery), it can select PAM4 for communication of the second signal at 1815. Therefore, the device can select a second modulation scheme based on the estimate of the duration until the internal power source reaches the threshold.

[0249] In some cases, the device may select a second frequency at 1830 for transmitting a second signal modulated using PAM4. The second frequency may be based on a determination made at 1810 and / or 1815. At 1835, the device may transmit the second signal modulated using PAM4 at the selected second frequency. Alternatively, the device may transmit the second signal modulated using PAM4 at a first frequency. The second signal may be transmitted between components of the device or between the device and another device. In some cases, the first and second signals are transmitted by a memory controller. In other cases, the first and second signals may be transmitted to the memory controller (e.g., sent from or passed to the memory controller from another component).

[0250] Figure 19 Exemplary diagrams illustrating process flow 1900 supporting variable modulation schemes according to various embodiments of the present invention are provided. Features of process flow 1900 may be implemented or performed by a device (e.g., a memory controller associated with a memory device) or components of the device such as memory controller 110, SoC, processor, GPU, etc. Communication in process flow 1900 may occur between components of the device or between two different devices. Although described with reference to NRZ and PAM4, aspects and features of process flow 1900 may be implemented using any combination of modulation schemes (e.g., QAM, PSK, etc.).

[0251] In 1905, the device can transmit a first signal modulated according to a first modulation scheme (e.g., NRZ) at a first frequency. In 1910, the device can determine operating parameters associated with the device or its components. For example, the device can determine bandwidth parameters. Bandwidth parameters may be associated with a specific application (e.g., an application associated with a second signal, such as an application sending or receiving the second signal) and may indicate the bandwidth required, requested, or demanded by said application. Therefore, in 1910, the device can determine whether the bandwidth of the application is greater than a threshold bandwidth.

[0252] In some cases, the device may additionally or alternatively determine whether the bandwidth parameter associated with the first application is greater than the bandwidth parameter associated with the second application (e.g., a different application). The first application may be an application that has been started or is ready to send data, and the second application may be an application that has been closed or is not ready to send data. In some cases, the second application is associated with a first data set represented by a first signal, and the first application is associated with a second data set represented by a second signal.

[0253] If the bandwidth parameter associated with the application is greater than a threshold bandwidth, or greater than the bandwidth parameter associated with the second application, then the device may select a second modulation scheme (e.g., PAM4) different from the first modulation scheme at 1915. Therefore, the selection is at least partially based on the determined bandwidth parameter. The second modulation scheme may have a second number of levels (e.g., four) different from the first number of levels. If the bandwidth parameter associated with the first application is less than the bandwidth parameter associated with the second application, or less than the bandwidth parameter associated with the second application, then the device may determine at 1920 whether the initiated application has a data rate greater than a threshold data rate (e.g., a target data rate or a desired data rate). The term bandwidth may refer to the total amount of data that a device or component can transmit, while the term data rate may refer to the speed at which data is transmitted between two devices or components.

[0254] If the data rate is not greater than a threshold rate, the device may determine at 1925 to continue using the first modulation scheme (e.g., NRZ) at the first frequency. If the data rate is greater than the threshold rate, the device may select PAM4 for modulating the second signal at 1915. Optionally, the device may select a second frequency for transmitting the second signal at 1930. The second frequency may be different from the first frequency and may be selected based on determined operating parameters (e.g., bandwidth parameters or data rate parameters). At 1935, the device may transmit the second signal modulated using the second modulation scheme (e.g., PAM4) at the second frequency. In some cases, the second signal may be transmitted at the first frequency (e.g., if 1930 is not performed).

[0255] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, instances from two or more of the methods may be combined.

[0256] Figures 20 to 22 This describes a memory device configured to multiplex data. In some multilevel modulation schemes, symbols can represent data from different sources or different types of data. For example, control data, stored data, metadata, or combinations thereof can be transmitted in a single symbol containing multiple symbols. To multiplex signals, first data and second data can be multiplexed together into a data structure. Multi-symbol signals can be encoded with specific symbols based on the multiplexed data structure, and the modulation scheme has at least three levels. In some cases, multiple memory dies can receive the multi-symbol signal and can use only a portion of one or more of the symbols. For example, a first memory die can use the most significant bit of a symbol of the multi-symbol signal, and a second memory die can use the least significant bit of the same symbol of the multi-symbol signal. (See reference...) Figures 20 to 22 The described features and / or functions may be compared with those in reference. Figures 1 to 19 Other features and / or combinations of functions of the described memory device.

[0257] Figure 20 This describes an example memory device 2000 according to various embodiments of the present invention. The memory device 2000 may be as described in the reference... Figure 1 An example of the described system 100. The memory device 2000 may include a memory controller 2005, a memory die 2010, a memory die 2015, a multiplexer 2020, a bus 2025, and a host 2030. In some instances, the memory die 2010 may be referred to as a first memory die 2010 and the memory die 2015 may be referred to as a second memory die 2015. In some instances, the first memory die 2010 and the second memory die 2015 may be coupled to the bus 2025.

[0258] In some instances, multiplexer 2020 may be coupled to bus 2025 and configured to multiplex first data and second data. Multiplexer 2020 may be configured to multiplex the first data and second data into a signal modulated using a binary symbol modulation scheme or a multi-symbol modulation scheme. In some instances, memory controller 2005 may multiplex the first data and second data. In other instances, the modulation scheme of the signal may include at least one of three levels. Each of the first memory die 2010 and the second memory die 2015 may be configured to use at least a portion of the signal.

[0259] For example, a first memory die 2010 may be configured to use at least first data of the signal, and a second memory die 2015 may be configured to use at least second data of the signal. Each of the first or second data may include, for example, metadata, control data, or storage data. In some instances, metadata may contain information about various aspects of the memory device 2000—for example, information about the power usage of the memory device 2000. Alternatively or additionally, for example, metadata may contain information about storage data, control data, or both. In other instances, control data may contain information about one or more operations of the memory device 2000—for example, information about a read or write operation on one of the first memory die 2010 or the second memory die 2015. In other instances, storage data may contain information about the logical state of one or more memory cells of the first memory die 2010 or the second memory die 2015—for example, logic "0" or logic "1".

[0260] In some instances, the memory controller 2005 may receive signals associated with each of the first memory die 2010 and the second memory die 2015. In some instances, the signals may be received from a host 2030. The host 2030 may communicate with the memory controller 2005 via communication channel 2035. In response to receiving a signal, for example, the memory controller 2005 may determine whether the signal is associated with the first memory die 2010 or the second memory die 2015.

[0261] In some instances, this determination may be based at least in part on the corresponding signal level of the received signal. In some cases, this determination may be based on the type of modulation scheme used to encode data in the signal (e.g., binary level or multilevel). In other instances, the memory controller 2005 is operable to receive a first request associated with an operation to be performed on the first memory die 2010. This request may be, for example, a request to read data from or write data to the first memory die 2010. In either case, the memory controller 2005 may be configured to transmit signals to the first memory die 2010 and the second memory die 2015 based at least in part on the first request.

[0262] In other instances, memory controller 2005 may transmit, for example, first data and second data to first memory die 2010 and second memory die 2015 based on corresponding data requests. For example, first memory die 2010 and second memory die 2015 may transmit the first data request and the second data request to memory controller 2005, respectively. In some instances, the first data request and the second data request may be transmitted by host 2030. The first data request may instruct memory controller 2005 to transmit data to first memory die 2010—for example, the first data of the transmitted signal.

[0263] Alternatively or concurrently, a second data request may instruct the memory controller 2005 to transmit data to the second memory die 2015—for example, transmitting second data of a signal. In some instances, the first and second data requests may be associated with a read operation or a write operation. For example, the first data request may be associated with a read command for the first memory die 2010. Thus, a read operation on one or more memory cells in the first memory die 2010 may occur in response to the first data request. In other instances, the second data request may be associated with a write command for the second memory die 2015. For example, a write operation on one or more memory cells in the second memory die 2015 may occur in response to the second data request. In any instance, the memory controller 2005 may transmit first data of a signal, second data of a signal, or each of the two in response to the first and second data requests.

[0264] In some instances, the multiplexer 2020 can be configured to multiplex the first and second data into symbols of a multi-level signal. In other words, the multiplexer 2020 can be configured to produce a single modulation symbol containing data from two different sources. For example, a PAM4 modulation symbol can represent two data bits. The most significant bit of the modulation symbol can be based on the first data, and the least significant bit of the modulation symbol can be based on the second data.

[0265] Alternatively or alternatively, for example, the most significant bit of a modulation symbol may be based on second data, and the least significant bit of a modulation symbol may be based on first data. The number of data sources that can be multiplexed into a single symbol may be based on the number of bits represented by the symbol. For example, a multilevel modulation scheme containing eight levels may be configured to multiplex data from three sources, since the symbol can represent three data bits.

[0266] Alternatively or alternatively, for example, each of the first memory die 2010 and the second memory die 2015 may include multiple package and / or cell configurations. For example, each of the first memory die 2010 and the second memory die 2015 may be different memory dies in a single package (e.g., different stacked memory dies, stacked packages). In some instances, the second memory die 2015 may include a memory or storage device of a different type than the first memory die 2010. In other instances, the first memory die 2010 may include at least one of FeRAM, DRAM, NAND device, NOR device, or phase-change memory device. In other instances, the second memory die 2015 may include at least one of FeRAM, DRAM, NAND device, NOR device, or phase-change memory device. Therefore, in some instances, each of the first memory die 2010 and the second memory die 2015 may contain the same cell or device type, and in other instances, each of the first memory die 2010 and the second memory die 2015 may contain different cell or device types. In other words, although depicted as stacked dies, memory dies 2010 and 2015 can be physically distinct memory devices. For example, memory die 2010 can be an internal memory array for a device (e.g., a storage device), and memory die 2015 can be removable (e.g., a removable memory card). In these cases, either or both of memory dies 2010 and 2015 can be flash memory devices.

[0267] In other instances, memory device 2000 may include a third memory die (not shown). The third memory die may be coupled to bus 2025 and may be configured to receive multiplexed data. In some instances, the third memory die may be configured to decode signals and discard either first or second data. In other instances, the third memory die may be a different memory die from the first memory die 2010 and the second memory die 2015. Additionally or alternatively, for example, the third memory die may be configured to use at least a portion of the signals of the first and / or second data.

[0268] In some instances, memory controller 2005 may transmit first and second data, for example, to a first memory die 2010 and a third memory die, based on corresponding data requests. For example, the first memory die 2010 and the third memory die may transmit the first and second data requests to memory controller 2005, respectively. In some instances, the first and second data requests may be transmitted by host 2030 as described above. The first data request may instruct memory controller 2005 to transmit data to the first memory die 2010—for example, the first data of the transmitted signal.

[0269] Alternatively or, for example, a second data request may instruct the memory controller 2005 to transmit data to a third memory die—for example, transmit second data of a signal. Thus, the memory controller 2005 may, in response to the first and second data requests, transmit first data of a signal, second data of a signal, or each of the two.

[0270] Alternatively or alternatively, for example, the third memory die may comprise multiple package and / or cell configurations. For example, each of the first memory die 2010, the second memory die 2015, and the third memory die may be a different memory die within the same stacked package. In other instances, the third memory die may comprise at least one of FeRAM, DRAM, NAND, NOR, or phase-change memory devices. The third memory die may contain the same cell or device type as the first memory die 2010 and the second memory die 2015, or different cell or device types. Therefore, each of the first memory die 2010, the second memory die 2015, and the third memory die may contain the same cell or device type, each may contain different cell or device types, or combinations thereof.

[0271] In other instances, each of the first memory die 2010, the second memory die 2015, and the third memory die may be coupled to the bus 2025. In some instances, the memory controller 2005 may also be coupled to the bus 2025. The memory controller 2005 is operable to identify first data, second data, and third data, which may contain metadata, control data, or storage data.

[0272] The memory controller 2005 is operable to multiplex first data, second data, and third data in a signal using a first modulation scheme (e.g., PAM8) having at least five levels. In other instances, the memory controller 2005 is operable to transmit signals to a first memory die 2010, a second memory die 2015, and a third memory die. In some instances, the first memory die 2010, the second memory die 2015, and the third memory die may each include at least one of a FeRAM, DRAM, NAND device, NOR device, or phase-change memory device.

[0273] Figure 21 The process flowchart 2100 illustrates various embodiments of the present invention. The process flowchart 2100 can be described as follows (refer to...). Figure 20 The described memory device 2000 performs one or more operations. Process flowchart 2100 may include operations performed by memory controller 2105, multiplexer 2110, host 2115, memory die 2120, and memory die 2125. In some instances, memory controller 2105, multiplexer 2110, memory die 2120, and memory die 2125 may be respectively as referenced... Figure 20 Examples of the memory controller 2005, multiplexer 2020, memory die 2010, and memory die 2015 described herein.

[0274] At box 2130, memory controller 2105 can identify first data and second data. In some instances, the first data or the second data may contain, as referenced above. Figure 20The described metadata, control data, or stored data. In some instances, each of the first and second data may be configured to include metadata, control data, or stored data. This may exclude other types of data in some cases. After identifying the first and second data, the memory controller 2105 may immediately transmit indications of the first and second data to the multiplexer 2110 via transmission 2135. In other instances, the memory controller 2105 may transmit the first and second data to the multiplexer 2110. In either case, at block 2140, the multiplexer 2110 may multiplex the first and second data. For example, the multiplexer 2110 may multiplex the first and second data such that it is represented by a single symbol of a multi-level modulation scheme containing at least three unique symbols to represent the data. In other words, the multiplexer 2110 may multiplex the first and second data in a signal containing a signal strength corresponding to one of at least three levels.

[0275] After multiplexing the first and second data, multiplexer 2110 can immediately transmit an instruction of the multiplexed data to memory controller 2105 via transmitter 2145. In other instances, multiplexer 2110 can transmit the multiplexed data to memory controller 2105. In other instances, multiplexer 2110 can transmit data to an encoder that modulates a signal based on the multiplexed data. In yet another instance, memory controller 2105 can transmit an instruction to multiplexer 2110 to transmit the multiplexed data to at least one of a first memory die 2120 or a second memory die 2125 (not shown).

[0276] Alternatively or alternatively, for example, the memory controller 2105 may receive signals indicating one or more characteristics of the respective die from memory die 2120, memory die 2125, or both. For example, based on one or more characteristics of the signal (e.g., signal strength), the memory controller 2105 may first determine whether the signal is transmitted from the first memory die 2120 or the second memory die 2125. This is because the first memory die 2120 may include FeRAM cells, DRAM cells, NAND devices, NOR devices, or phase-change memory devices, as referenced above. Figure 1 Therefore, the memory controller 2105 can determine the type of unit or device in part based on the signals emitted from the first memory die 2120.

[0277] In addition, since the second memory die 2125 may contain memory cells or memory devices different from the first memory die 2120, the memory controller 2105 may determine the cell type or device type in part based on signals emitted from the second memory die 2125.

[0278] In any of the foregoing examples, the host may determine at block 2150 a first data request corresponding to either the first memory die 2120 or the second memory die 2125. The data request may instruct the memory controller 2105, for example, to transmit a multi-symbol signal representing multiplexed data to at least one of the first memory die 2120 and / or the second memory die 2125.

[0279] After determining the first data request at block 2150, for example, host 2115 may transmit the data request or an indication of a data request to memory controller 2105. This can occur via transmission 2155. Alternatively, for example, at block 2160, host 2115 may determine a second data request corresponding to either the first memory die 2120 or the second memory die 2125. As stated above, in relation to the first data request, the second data request may instruct memory controller 2105 to transmit multiplexed data to at least one of the first memory die 2120 or the second memory die 2125. After determining the second data request at block 2160, host 2115 may immediately transmit the data request or an indication of a data request to memory controller 2105. This can occur via transmission 2165.

[0280] At transmit 2170, memory controller 2105 can transmit first data and second data to first memory die 2120 and second memory die 2125. In some instances, memory controller 2105 can transmit the first data and second data to first memory die 2120 and second memory die 2125 via a bus coupled to each of the first and second memory dies. In some instances, second memory die 2125 may be or may include an external or removable memory device.

[0281] For example, upon insertion or activation, the memory controller 2105 may receive an indication of the presence of a second memory die 2125, which includes a removable storage device (not described). In some instances, the removable storage device may be a universal flash memory (UFS) device. In this example, the transmission of signals to the first memory die 2120 and the second memory die 2125 may be based in part on an indication transmitted to the memory controller 2105.

[0282] In some instances, memory dies 2120 and 2125 may receive signals modulated using a first modulation scheme and may identify one or more bits represented by symbols (e.g., one of three unique symbols). For example, one bit may be assigned to memory die 2120 and another bit may be assigned to memory die 2125. Therefore, memory die 2120 may discard the bit assigned to memory die 2125, and memory die 2125 may discard the bit assigned to memory die 2120. In other instances, each of memory dies 2120 and 2125 may partition data based on the type of data (e.g., control data). For example, memory die 2125 may decode the received signal and may discard the bit based on the type of data. Alternatively or additionally, for example, memory die 2120 may decode the received signal and may facilitate the transfer of specific data to memory die 2125.

[0283] In some instances, the memory die (e.g., memory die 2120 or memory die 2125) can decode symbols modulated using a multi-symbol modulation scheme and can determine the type of each bit represented by the decoded symbol. The memory die can perform one or more operations based on the type of data contained in the symbol.

[0284] In other instances, the first and second data may be transmitted as multiplexed signals having a signal strength corresponding to one of at least three levels. (See above reference.) Figure 1 As discussed, a pulse amplitude modulation (PAM) scheme can be used, for example, to modulate the signal. After signal transmission, at block 2175, the memory controller 2105 is immediately operable to adjust the timing of the transmission of the start signal to the first memory die 2120 and the second memory die 2125. During signal transmission, the memory controller 2105 can transmit the signal based on the timing of the system clock. In some instances, the system clock may be associated with the memory controller 2105 (e.g., integrated). In other instances, the system clock may be external to the memory controller 2105. For example, the memory controller 2105 may transmit the signal during the rising edge of the system clock, the falling edge of the system clock, or both. The memory controller 2105 can then transmit the adjusted signal to each of the first memory die 2120 and the second memory die 2125 via transmit 2180.

[0285] For example, at block 2130, memory controller 2105 can identify first and second data, each containing control data. Subsequently, for example, memory controller 2105 can transmit indications of the first and second control data to multiplexer 2110 via transmit 2135. At block 2140, multiplexer 2110 can multiplex the first and second data into a symbol containing a multi-level signal of at least three levels, and subsequently transmit an indication of the multiplexed data to memory controller 2105. At block 2150, host 2115 can determine a first data request, which may correspond to a data request from first memory die 2120.

[0286] Additionally, at block 2160, host 2115 may determine a second data request, which may correspond to a data request from second memory die 2125. Each of the data requests may be transmitted from host 2115 to memory controller 2105 via transmit 2155 and 2165, respectively. Upon receiving a data request, memory controller 2105 may immediately transmit a multiplexed signal simultaneously to each of first memory die 2120 and second memory die 2125 via transmit 2170. Based on the transmission, at block 2175, memory controller 2105 adjusts the communication of the multiplexed signal based on its clock cycle, and may simultaneously transmit the adjusted signal to each of first memory die 2120 and second memory die 2125 via transmit 2180.

[0287] Figure 22 A process flowchart 2200 illustrating various embodiments of the present invention is provided. Process flowchart 2200 can be described by referring to... Figure 20 The described memory device 2000 performs one or more operations. Process flowchart 2200 may include operations performed by memory controller 2205, multiplexer 2210, host 2215, memory die 2220, and memory die 2225. In some instances, memory controller 2205, multiplexer 2210, host 2215, memory die 2220, and memory die 2225 may be respectively as referenced... Figure 21 Examples of the memory controller 2105, multiplexer 2110, host 2115, memory die 2120, and memory die 2125 described herein.

[0288] At block 2230, host 2215 may determine a first data request corresponding to either first memory die 2220 or second memory die 2225. The first data request may instruct memory controller 2205, for example, to transfer data to one of the first or second memory dies. After determining the first data request at block 2230, host 2215 may, for example, transmit the data request or an indication of a data request to memory controller 2205. This can occur via transmission 2235.

[0289] Alternatively or alternatively, for example, at block 2240, host 2215 may determine a second data request corresponding to either the first memory die 2220 or the second memory die 2225. As stated above, the determination of the second data request, relative to the determination of the first data request, may instruct memory controller 2205 to transfer data to one of the first or second memory dies. In some instances, the determination of the first data request at block 2230 may correspond to the first memory die 2220, and the determination of the second data request at block 2240 may correspond to the second memory die 2225. After determining the second data request at block 2240, for example, host 2215 may transmit the second data request or an indication of the second data request to memory controller 2205 via transmit 2245.

[0290] After each of the first data request and the second data request, or an indication thereof, is transmitted to the memory controller 2205, the memory controller 2205 may identify the first data at block 2250. The memory controller 2205 may identify the first data, for example, in response to a determined first or second data request at blocks 2230 and 2240, respectively. In some instances, the identification of the first data includes identifying control data. After the first data is identified at block 2250, the multiplexer 2210 may immediately receive an indication of the first data from the memory controller 2205. In other instances, the multiplexer 2210 may receive an indication of the first data from the memory controller 2205.

[0291] In either case, reception (or indication of) the identified data can occur via transmitter 2255. After receiving the identified first data via transmitter 2255, memory controller 2205 can identify the second data at block 2260. Memory controller 2205 can identify the first data, for example, in response to a determined first or second data request at blocks 2230 and 2240, or in response to the identification of the first data at block 2250. In some instances, after identifying the second data at block 2260, multiplexer 2210 can receive the identified second data or an indication of the identified second data from memory controller 2205 via transmitter 2265.

[0292] Upon receiving the identified first data and second data or their indication, multiplexer 2210 can immediately multiplex the identified first data and the identified second data at block 2270 such that they are represented by a single symbol of a multi-level modulation scheme containing at least three unique symbols to represent the data. For example, multiplexer 2210 can multiplex the identified first data. In other words, multiplexer 2210 can multiplex the identified first data and the identified second data in a signal containing signal strengths corresponding to one of at least three levels.

[0293] After multiplexing the identified first data and the identified second data, for example, multiplexer 2210 can transmit an indication of the multiplexed data to memory controller 2205 via transmitter 2275. In other instances, multiplexer 2210 can transmit the multiplexed data to memory controller 2205. In yet another instance, memory controller 2205 can transmit an indication to multiplexer 2210 to transmit the multiplexed data to at least one of a first memory die 2220 or a second memory die 2225 (not shown).

[0294] Alternatively or alternatively, for example, the first memory die 2220, the second memory die 2225, or both may transmit signals indicating one or more characteristics of the respective die to the memory controller 2205. For example, based on one or more characteristics of the signal (e.g., signal strength), the signal may indicate that it originates at one of the first memory die 2220 or the second memory die 2225. This is because the first memory die 2220 may include FeRAM cells, DRAM cells, NAND devices, NOR devices, or phase-change memory devices, as referenced above. Figure 1 As discussed, the signal can indicate the cell or device type of the first memory die 2220. Additionally, because the second memory die 2225 may contain memory cells or memory devices different from the first memory die 2220, the signal can indicate the cell or device type of the second memory die 2225. In some instances, the multiplexer 2210 can multiplex the first and second data at block 2270 based on the cell or device type of the first memory die 2220 and the second memory die 2225.

[0295] Through transmission 2280, the first memory die 2220 and the second memory die 2225 can receive multiplexed first and second data from the memory controller 2205. In some instances, the multiplexed first and second data can be received via a bus (not shown) coupled to each of the first and second memory dies. In some instances, the second memory die 2225 may be or may include an external or removable memory device. For example, upon insertion or activation, the second memory die 2225 may transmit an indication to the memory controller 2205 indicating the insertion or activation of the device. In this example, the transmission of signals to the first memory die 2220 and the second memory die 2225 may be based in part on an indication transmitted to the memory controller 2205.

[0296] In other instances, the first and second data may be received at the first memory die 2220 and the second memory die 2225 as multiplexed signals having a signal strength corresponding to one of at least three levels. (See above reference.) Figure 1 As discussed, a PAM modulation scheme, for example, can be used to modulate the signal. Upon receiving the signal, at block 2285, the memory controller 2205 can immediately adjust the timing of the signal transmission. The signals received at the first memory die 2220 and the second memory die 2225 can be based on the timing of the system clock. In some instances, the system clock can be associated with the memory controller 2205 (e.g., integrated). In other instances, the system clock can be external to the memory controller 2205. For example, the memory controller 2205 can transmit the signal during the rising edge of the system clock, the falling edge of the system clock, or both. The first memory die 2220 and the second memory die 2225 can subsequently receive the adjusted signal based on the system clock of the memory controller 2205 by transmission 2290.

[0297] In some instances, memory dies 2220 and 2225 may receive signals modulated using a first modulation scheme and may identify one or more bits represented by symbols (e.g., one of three unique symbols). For example, one bit may be assigned to memory die 2220 and another bit may be assigned to memory die 2225. Therefore, memory die 2220 may discard the bit assigned to memory die 2225 and memory die 2225 may discard the bit assigned to memory die 2220. In other instances, each of memory dies 2220 and 2225 may partition data based on the type of data (e.g., control data). For example, memory die 2225 may decode the received signal and may discard the bit based on the type of data. Alternatively or additionally, for example, memory die 2220 may decode the received signal and may facilitate the transfer of specific data to memory die 2225.

[0298] For example, at block 2230, host 2215 may determine a first data request, which may correspond to a data request from first memory die 2220. Additionally, at block 2240, host 2215 may determine a second data request, which may correspond to a data request from second memory die 2225. Each of the data requests may be transmitted by host 2215 to memory controller 2205 at transmit points 2235 and 2245, respectively. After a memory request is transmitted to memory controller 2205, memory controller 2205 can immediately identify the first and second data requests, each containing control data.

[0299] This indication can occur at blocks 2250 and 2260, respectively. After identifying each of the first and second data, the identified data can be received by multiplexer 2210 at transmit points 2255 and 2265, respectively. At block 2240, multiplexer 2210 can multiplex the first and second data into a symbol containing a multi-level signal of at least three levels, and then transmit the indication of the multiplexed data to memory controller 2205. Based on this transmission, each of the first memory die 2220 and the second memory die 2225 can receive the multiplexed signal from the memory controller via transmit point 2280. The multiplexed signal can be transmitted simultaneously to each of the first memory die 2220 and the second memory die 2225. Upon receiving the multiplexed signal, memory controller 2205 can immediately adjust the communication of the multiplexed signal based on the clock cycle of memory controller 2205. Subsequently, the adjusted signal can be received by each of the first memory die 2220 and the second memory die 2225.

[0300] Figure 23 A block diagram 2300 illustrates a memory controller 2315 supporting a variable modulation scheme according to an embodiment of the present invention. The memory controller 2315 may be a reference. Figures 1 to 22 Examples of aspects of the described memory controller are shown. The memory controller 2315 may include a communication component 2330, a determination component 2335, a modulation scheme component 2340, a receiving component 2345, a signaling component 2350, an operating parameter component 2355, a frequency component 2360, an application component 2365, a power component 2370, and a transmitting component 2375. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0301] Communication component 2330 can communicate using a first signal modulated with a first modulation scheme having a first number of levels at a first frequency. Communication component 2330 can also communicate using a second signal modulated with a second modulation scheme selected by modulation scheme component 2340. In some cases, transmitting the second signal includes transmitting the second signal at a second frequency different from the first frequency. In some cases, transmitting the second signal includes transmitting the second signal at the first frequency. In some cases, communication component 2330 can transmit a third signal modulated with the first modulation scheme. Modulating the third signal with the first modulation scheme can be based on the selection of the first modulation scheme by modulation scheme component 2340.

[0302] The determining component 2335 can determine operating parameters associated with the memory controller 2315, a device housed therein, or a host coupled to the memory controller 2315. In some cases, the determining component 2335 can also determine changes in the operating parameters. In some cases, the operating parameters are temperature parameters. In these cases, determining the temperature parameter may include determining that the temperature associated with the host (or with another device or component) meets a temperature threshold. The modulation scheme component 2340 can select a second modulation scheme based on the determination that the temperature meets the temperature threshold.

[0303] Modulation scheme component 2340 can select a second modulation scheme different from the first modulation scheme based on determined operating parameters, and the second modulation scheme can have a second number of levels different from the first number of levels. In some cases, modulation scheme component 2340 can select the second modulation scheme based on comparing operating parameters with pre-configured modulation table data. In these cases, the first or second modulation scheme includes a PAM scheme with two levels, and the other of the first or second modulation scheme includes a PAM scheme with at least three levels. When determination component 2335 determines a change in operating parameters, modulation scheme component 2340 can select the first modulation scheme based on the determination.

[0304] Frequency component 2360 can select the frequency at which the signal is transmitted. For example, when communication component 2330 transmits a second signal at a second frequency, frequency component 2360 can select the second frequency based on determined operating parameters. Therefore, transmitting the second signal at the second frequency can be based on the selection of the second frequency. In some cases, frequency component 2360 can select a third frequency for transmitting a second signal modulated using a second modulation scheme, or select a third frequency for transmitting a first signal modulated using a first modulation scheme, based on determined changes.

[0305] Application component 2365 can determine one or more parameters, characteristics, or metrics associated with the application. For example, when the operating parameter is a bandwidth parameter, application component 2365 can determine the bandwidth parameter by determining the bandwidth requirements of the application associated with the second signal. In these cases, modulation scheme component 2340 can select a second modulation scheme based on the determined bandwidth requirements. In some cases, the operating parameter is the startup of an application with a data rate greater than a threshold data rate. Therefore, application component 2365 can detect when this application has started.

[0306] Power component 2370 can determine power parameters. For example, when the operating parameter is a power parameter, power component 2370 can determine the power parameter by determining whether an external power supply is connected. In these cases, the selection of the second modulation scheme can be based on the determination of whether an external power supply is connected. In other cases, when the operating parameter is a power parameter, power component 2370 can determine the power parameter by estimating the duration until the internal power source reaches a threshold. In these cases, the selection of the second modulation scheme can be based on the estimation. In some cases, the selection of the second modulation scheme can be based on both bandwidth parameters and power parameters.

[0307] The receiving component 2345 can receive a first data set in a first number of bit streams and a second data set in a second number of bit streams. In some cases, the first number of bit streams is equal to the second number of bit streams.

[0308] Signal component 2350 can generate a first signal having a first number of levels based on a first number of bit streams containing a first data set. Signal component 2350 can also generate a second signal having a second number of levels based on a second number of bit streams containing a second data set and based on determined operating parameters. The second number of levels may differ from the first number of levels. In some cases, the first number of bit streams differs from the first number of levels, and the second number of bit streams differs from the second number of levels.

[0309] The operation parameter component 2355 can determine operation parameters associated with a host (or other component) coupled to the memory controller 2315 or associated with the memory controller itself 2315. This determination may be based on receiving a second data set.

[0310] The transmitting component 2375 can transmit a first signal on the channel at a first frequency and transmit a second signal on the channel at a second frequency different from the first frequency. Alternatively, the transmitting component 2375 can transmit a first signal on the channel at a first frequency and transmit a second signal on the channel at the first frequency.

[0311] Figure 24A diagram illustrates a system 2400 including a device 2405 supporting a variable modulation scheme according to an embodiment of the present invention. Device 2405 may be, for example, as described above with reference to... Figures 1 to 23 Examples of the described apparatus may include its components. Apparatus 2405 may include components for bidirectional voice and data communication, components for transmitting and receiving communication, and includes a memory controller 2415, a memory unit 2420, a basic input / output system (BIOS) component 2425, a processor 2430, an I / O controller 2435, and peripheral components 2440. These components may communicate electronically via one or more buses (e.g., bus 2410).

[0312] Memory controller 2415 can operate on one or more memory cells as described herein. Specifically, memory controller 2415 can be configured to support variable modulation schemes. In some cases, memory controller 2415 may include a row decoder, a column decoder, or both, as described herein (not illustrated). Memory cell 2420 can store information (i.e., in the form of logical states) as described herein.

[0313] BIOS component 2425 is a software component that includes a BIOS operating as firmware, which can initialize and run various hardware components. BIOS component 2425 can also manage data flow between the processor and various other components, such as peripheral components, input / output control components, etc. BIOS component 2425 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0314] Processor 2430 may include intelligent hardware devices (such as general-purpose processors, DSPs, central processing units (CPUs), microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, processor 2430 may be configured to use a memory controller to operate a memory array. In other cases, the memory controller may be integrated into processor 2430. Processor 2430 may be configured to execute computer-readable instructions stored in memory to perform various functions (e.g., functions or tasks supporting variable modulation schemes).

[0315] I / O controller 2435 manages input and output signals for device 2405. I / O controller 2435 can also manage peripheral devices not integrated into device 2405. In some cases, I / O controller 2435 may represent a physical connection or port to an external peripheral device. In some cases, I / O controller 2435 may utilize an operating system, such as... Or another known operating system. In other cases, the I / O controller 2435 may represent or interact with a modem, keyboard, mouse, touchscreen, or similar device. In some cases, the I / O controller 2435 may be implemented as part of a processor. In some cases, a user may interact with the device 2405 via the I / O controller 2435 or via hardware components controlled by the I / O controller 2435.

[0316] Peripheral component 2440 may include any input or output device, or an interface for such devices. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, Universal Serial Bus (USB) controller, serial or parallel port, or peripheral device card slot (such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) card slot).

[0317] Input 2445 may represent a device or signal external to device 2405 that provides input to device 2405 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 2445 may be managed by I / O controller 2435 and may interact with device 2405 via peripheral component 2440.

[0318] Output 2450 may also represent a device or signal external to device 2405, configured to receive output from device 2405 or any of its components. Examples of output 2450 may include a display, audio speaker, printing device, another processor, or printed circuit board, etc. In some cases, output 2450 may be a peripheral element that interfaces with device 2405 via peripheral component 2440. In some cases, output 2450 may be managed by I / O controller 2435.

[0319] The components of device 2405 may include circuitry designed to perform its functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive components. Device 2405 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, or the like. Alternatively, device 2405 may be a part or aspect of such a device.

[0320] Figure 25 A flowchart illustrating a method 2500 for a variable modulation scheme according to an embodiment of the present invention is shown. Operation of method 2500 may be implemented by means of an apparatus or its components as described herein. For example, operation of method 2500 may be performed by means of means as described in reference... Figures 14 to 19The memory controller described herein performs the functions. In some instances, the device may execute a set of code to control the functional elements of the device to perform the functions described below. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the functions described below.

[0321] In 2505, the method may include communicating (e.g., with a memory controller) at a first frequency using a first signal modulated with a first modulation scheme having a first number of levels. Operation of 2505 may be performed according to the method described herein. In some instances, aspects of operation of 2505 may be as referenced... Figure 23 The described communication component is executed.

[0322] In 2510, the method may include determining and associating with operating parameters of a host coupled to a memory controller. The operation of 2510 may be performed according to the methods described herein. In some instances, aspects of the operation of 2510 may be derived from, as referenced... Figure 23 The described component is executed.

[0323] In 2515, the method may include selecting, at least in part, a second modulation scheme different from the first modulation scheme based on determined operating parameters, the second modulation scheme having a second number of levels different from the first number of levels. The operation of 2515 may be performed according to the method described herein. In some instances, aspects of the operation of 2515 may be as referenced... Figure 23 The described modulation scheme components are executed.

[0324] In 2520, the method may include communicating (e.g., with a memory controller) using a second signal modulated with a second modulation scheme. In some cases, transmitting the second signal includes transmitting the second signal at a first frequency. In some cases, transmitting the second signal includes transmitting the second signal at a second frequency different from the first frequency. In some cases, the method may also include selecting the second frequency at least in part based on determined operating parameters, wherein transmitting the second signal at the second frequency is at least in part based on selecting the second frequency. Operation of 2520 may be performed according to the method described herein. In some instances, aspects of operation of 2520 may be provided by reference to [reference needed]. Figure 23 The described communication component is executed.

[0325] In some cases, the method may further include selecting a second modulation scheme based at least in part on comparing operating parameters with pre-configured modulation table data. In these cases, one of the first or second modulation schemes is a two-level PAM scheme (NRZ), and the other of the first or second modulation schemes is a three-level PAM scheme.

[0326] In some cases, the method may further include determining a change in operating parameters. In some cases, the method may further include selecting a third frequency for transmitting a second signal modulated using a second modulation scheme, at least in part based on the determined change. In some cases, the method may further include selecting a third frequency for transmitting a first signal modulated using a first modulation scheme. In some cases, the method may further include transmitting a third signal modulated using a first modulation scheme, at least in part based on the selection of the first modulation scheme.

[0327] In some cases, the operating parameter is a bandwidth parameter, and determining the bandwidth parameter involves determining the bandwidth requirements of the application associated with the second signal, wherein the selection of the second modulation scheme is at least in part based on determining the bandwidth requirements. In some cases, the operating parameter is the startup of an application with a data rate greater than a threshold data rate.

[0328] In some cases, the operating parameters are temperature parameters, and determining the temperature parameters includes determining that the temperature associated with the host meets a temperature threshold, wherein the selection of the second modulation scheme is at least in part based on determining that the temperature meets the temperature threshold.

[0329] In some cases, the operating parameter is a power parameter. Determining the power parameter may include determining whether an external power supply is connected, wherein the selection of a second modulation scheme is at least in part based on the determination of whether an external power supply is connected. Alternatively, determining the power parameter may include estimating the duration until the internal power source reaches a threshold, wherein the selection of a second modulation scheme is at least in part based on said estimation.

[0330] In some cases, the device may include: means for transmitting a first signal to a memory die, wherein the first signal is modulated using a first modulation scheme having a first number of levels; means for determining operating parameters associated with the device; means for selecting a second modulation scheme different from the first modulation scheme based at least in part on the determined operating parameters; and means for transmitting a second signal to the memory die based at least in part on the selected second modulation scheme, wherein the second signal is modulated using a second modulation scheme having a second number of levels different from the first number of levels.

[0331] In some cases, the device may include: means for generating a first clock signal at a first frequency and a second clock signal at a second frequency; means for transmitting the first signal at least partially based on the first frequency; and means for transmitting the second signal at least partially based on the second frequency and determined operating parameters, wherein the second frequency is higher than the first frequency.

[0332] In some cases, the device may include: means for selecting a first number of memory cells in a memory die to receive a first data set modulated using a first modulation scheme; and means for selecting a second number of memory cells in a memory die to receive a second data set modulated using a second modulation scheme, wherein the second number of memory cells is different from the first number of memory cells.

[0333] In some cases (e.g., when the operating parameter is a bandwidth parameter), the device may include components for determining power parameters for the device, wherein the selection of a second modulation scheme is based at least in part on the bandwidth parameter and the power parameter.

[0334] In some cases (e.g., when the operating parameter is a temperature parameter), the component for determining the operating parameter may include a component for determining whether the temperature associated with the memory controller meets a temperature threshold, wherein the selection of the second modulation scheme is at least in part based on determining whether the temperature meets the temperature threshold.

[0335] In some cases (e.g., when the operating parameter is a power parameter), the component for determining the operating parameter may include a component for determining whether an external power supply is connected, wherein the selection of the second modulation scheme is at least in part based on the determination of whether an external power supply is connected.

[0336] In some cases (e.g., when the operating parameters include power parameters), the components for determining the operating parameters may include components for estimating the duration until the internal power source reaches a threshold, wherein the selection of the second modulation scheme is at least partially based on said estimation. In some cases, the operating parameters are the startup of an application with a target data rate greater than a threshold data rate.

[0337] In some cases, the device may include: means for transmitting a first signal on a data bus using a first driver, the first signal having a signal strength corresponding to one of a first number of levels representing a first data set; means for determining operating parameters associated with the device; and means for transmitting a second signal on the data bus based at least in part on the determined operating parameters, the second signal having a signal strength corresponding to one of a second number of levels representing a second data set, the second number of levels being different from the first number of levels.

[0338] In some cases, the device includes: means for generating a first clock rate and a second clock rate; means for transmitting a first signal at the first clock rate; and means for transmitting a second signal at the second clock rate, at least in part based on determined operating parameters.

[0339] Figure 26A flowchart illustrating a method 2600 for a variable modulation scheme according to an embodiment of the present invention is shown. Operation of method 2600 may be implemented by means of an apparatus or its components as described herein. For example, operation of method 2600 may be performed by means of means as described in reference to... Figures 14 to 19 The memory controller described herein performs the functions. In some instances, the device may execute a set of code to control the functional elements of the device to perform the functions described below. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the functions described below.

[0340] In 2605, the method may include communicating at a first frequency using a first signal modulated with a first modulation scheme having a first number of levels (e.g., using a memory controller or other component). Operation of 2605 may be performed according to the methods described herein. In some instances, aspects of operation of 2605 may be as referenced... Figure 23 The described communication component is executed.

[0341] In 2610, the method may include determining power parameters and bandwidth parameters. The operation of 2610 may be performed according to the methods described herein. In some instances, aspects of the operation of 2610 may be derived from, as referenced... Figure 23 The described component is executed.

[0342] In 2615, the method may include selecting a second modulation scheme, different from the first modulation scheme, based at least in part on determined power and bandwidth parameters, the second modulation scheme having a second number of levels different from the first number of levels. Operation of 2615 may be performed according to the method described herein. In some instances, aspects of operation of 2615 may be as referenced... Figure 23 The described modulation scheme components are executed.

[0343] In 2620, the method may include communication (e.g., with a memory controller or other components) using a second signal modulated with a second modulation scheme. Operation of 2620 may be performed according to the methods described herein. In some instances, aspects of operation of 2620 may be as referenced... Figure 23 The described communication component is executed.

[0344] In some cases, refer to Figure 25 and 26The operation of the described method can be performed by a device. For example, the device may include means for communicating (e.g., with a memory controller) at a first frequency using a first signal modulated with a first modulation scheme having a first number of levels. The device may also include means for determining operating parameters associated with a host coupled to the memory controller. The device may further include means for selecting a second modulation scheme, different from the first modulation scheme, having a second number of levels different from the first number of levels, based at least in part on the determined operating parameters. The device may also include means for communicating with the memory controller using a second signal modulated with the second modulation scheme.

[0345] In some instances, the device may include means for transmitting a second signal at a second frequency different from the first frequency. In some instances, the device may include means for selecting the second frequency at least in part based on determined operating parameters, wherein transmitting the second signal at the second frequency may be at least in part based on the selection of the second frequency.

[0346] In some instances, the device may include components for determining changes in operating parameters. In some instances, the device may include components for selecting a third frequency for transmitting a second signal modulated using a second modulation scheme, at least in part based on the determined changes.

[0347] In some instances, the device may include components for transmitting a second signal at a first frequency. In some instances, the device may include components for selecting a third frequency for transmitting a first signal modulated using a first modulation scheme.

[0348] In some instances, the device may include means for determining changes in operating parameters. In some instances, the device may include means for selecting a first modulation scheme at least in part based on the determined changes in operating parameters. In some instances, the device may include means for transmitting a third signal modulated using the first modulation scheme at least in part based on the selected first modulation scheme. In some instances, the device includes means for determining the bandwidth requirements of an application associated with a second signal. In these cases, the selection of the second modulation scheme may be at least in part based on the determined bandwidth requirements.

[0349] In some instances, the device may include components for determining temperature parameters. For example, the device may include components for determining whether the temperature associated with the host meets a temperature threshold. In these cases, the selection of a second modulation scheme may be based at least in part on determining that the temperature meets the temperature threshold.

[0350] In some instances, the device may include components for determining power parameters. For example, the device may include components for determining whether an external power source can be connected. In these cases, the selection of a second modulation scheme may be based at least in part on the determination of whether an external power source can be connected. In some instances, the device includes components for estimating the duration until an internal power source reaches a threshold. In these cases, the selection of a second modulation scheme may be based at least in part on the estimation.

[0351] In some instances of the methods and apparatus described above, the operating parameters are the startup of an application with a data rate greater than a threshold data rate. In some instances, the apparatus includes components for determining power parameters and components for determining bandwidth parameters. In these cases, the selection of a second modulation scheme may be based at least in part on the bandwidth parameters and power parameters.

[0352] In some instances, the device may include components for selecting a second modulation scheme at least in part based on a comparison of operating parameters with pre-configured modulation table data. One of the first or second modulation schemes may be a PAM scheme with two levels, and the other of the first or second modulation schemes may be a PAM scheme with at least three levels.

[0353] Figure 27 A flowchart illustrating a method 2700 for a variable modulation scheme according to an embodiment of the present invention is shown. Operation of method 2700 may be implemented by means of an apparatus or its components as described herein. For example, operation of method 2700 may be performed by means of means as described in reference... Figures 14 to 19 The memory controller described herein performs the functions. In some instances, the device may execute a set of code to control the functional elements of the device to perform the functions described below. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the functions described below.

[0354] In 2705, the method may include receiving a first data set in a first number of bit streams. The operation of 2705 may be performed according to the method described herein. In some instances, aspects of the operation of 2705 may be as referenced... Figure 23 The described receiving component is executed.

[0355] In 2710, the method may include generating a first signal having a first number of levels by a memory controller, at least in part, based on a first number of bit streams comprising a first data set. Operation of 2710 may be performed according to the method described herein. In some instances, aspects of operation of 2710 may be as referenced... Figure 23 The described signal components are executed.

[0356] In 2715, the method may include receiving a second data set in a second number of bit streams. The operation of 2715 may be performed according to the method described herein. In some instances, aspects of the operation of 2715 may be as referenced... Figure 23 The described receiving component is executed.

[0357] In 2720, the method may include determining, at least in part, operational parameters associated with a host (or other component) coupled to a memory controller based on the receipt of a second data set. Operation of 2720 may be performed according to the methods described herein. In some instances, aspects of operation of 2720 may be derived from, as referenced... Figure 23 The described operation parameters are executed by the component.

[0358] In 2725, the method may include generating a second signal having a second number of levels based at least in part on a second number of bit streams including a second data set and determined operating parameters, wherein the second number of levels differs from the first number of levels. In some cases, the first number of bit streams differs from the first number of levels and the second number of bit streams differs from the second number of levels. The operation of 2725 may be performed according to the method described herein. In some instances, aspects of the operation of 2725 may be as referenced Figure 23 The described signal components are executed.

[0359] In some cases, the method may further include transmitting a second signal on the channel at a second frequency different from the first frequency. In some cases, the method may further include transmitting a first signal on the channel at the first frequency. In some cases, the method may further include transmitting a second signal on the channel at the first frequency. In some cases, the first number of bit streams is equal to the second number of bit streams. In some cases, the method may further include transmitting the first signal on the channel at the first frequency.

[0360] Figure 28 A flowchart illustrating a method 2800 for a variable modulation scheme according to an embodiment of the present invention is shown. Operation of method 2800 may be implemented by means of an apparatus or its components as described herein. For example, operation of method 2800 may be performed by means of means as described in reference... Figures 14 to 19 The memory controller described herein performs the functions. In some instances, the device may execute a set of code to control the functional elements of the device to perform the functions described below. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the functions described below.

[0361] In 2805, the method may include receiving a first data set in a first number of bit streams. The operation of 2805 may be performed according to the method described herein. In some instances, aspects of the operation of 2805 may be as referenced... Figure 23The described receiving component is executed.

[0362] In 2810, the method may include generating (e.g., by a memory controller) a first signal having a first number of levels, at least in part, based on a first number of bit streams comprising a first data set. Operation of 2810 may be performed according to the method described herein. In some instances, aspects of operation of 2810 may be as referenced... Figure 23 The described signal components are executed.

[0363] In 2815, the method may include transmitting a first signal on a channel at a first frequency. The operation of 2815 may be performed according to the method described herein. In some instances, aspects of the operation of 2815 may be as referenced... Figure 23 The described launch component is executed.

[0364] In 2820, the method may include receiving a second data set in a second number of bit streams. The operation of 2820 may be performed according to the method described herein. In some instances, aspects of the operation of 2820 may be as referenced... Figure 23 The described receiving component is executed.

[0365] In 2825, the method may include operational parameters determined at least in part based on the received second data set and associated with the host coupled to the memory controller. The operation of 2825 may be performed according to the method described herein. In some instances, aspects of the operation of 2825 may be provided by reference to... Figure 23 The described operation parameters are executed by the component.

[0366] In 2830, the method may include generating a second signal having a second number of levels based at least in part on a second number of bit streams including a second data set and determined operating parameters, wherein the second number of levels differs from the first number of levels. Operation of 2830 may be performed according to the method described herein. In some instances, aspects of operation of 2830 may be as referenced... Figure 23 The described signal components are executed.

[0367] In 2835, the method may include transmitting a second signal on the channel at a second frequency different from the first frequency. Operation of 2835 may be performed according to the method described herein. In some instances, aspects of operation of 2835 may be as referenced... Figure 23 The described launch component is executed.

[0368] In some cases, refer to Figure 27 and 28The operation of the described method can be performed by a device. For example, the device may include means for receiving a first set of data in a first number of bit streams. The device may also include means for generating (e.g., by a memory controller) a first signal having a first number of levels, at least in part based on the first number of bit streams including the first data set. The device may also include means for receiving a second set of data in a second number of bit streams. The device may also include means for determining, at least in part based on the received second data set, operating parameters associated with a host coupled to the memory controller. The device may also include means for generating a second signal having a second number of levels, at least in part based on the second number of bit streams including the second data set and the determined operating parameters, wherein the second number of levels differs from the first number of levels.

[0369] In some instances, the device may include components for transmitting a first signal on a channel at a first frequency. In some instances, the device may include components for transmitting a second signal on the channel at a second frequency different from the first frequency. In some instances, the device may include components for transmitting the first signal on the channel at a first frequency. In some instances, the device may include components for transmitting the second signal on the channel at a first frequency. In some instances, the first number of bit streams may be equal to the second number of bit streams. In some instances, the first number of bit streams may be different from the first number of levels, and the second number of bit streams may be different from the second number of levels.

[0370] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0371] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a signal bus, wherein the bus may have multiple bit widths.

[0372] As used herein, the term "virtual ground" refers to a circuit node being maintained at approximately zero volts (0V) but not directly connected to ground. Therefore, the voltage of a virtual ground can fluctuate over time and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0V.

[0373] The terms "electronic communication" and "coupling" refer to the relationship between components that support the flow of electrons between them. This can include direct connections between components or may include intermediate components. Components that are electronically communicating or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit) or passively exchange electrons or signals (e.g., in an unenergized circuit), but can be configured and operable to exchange electrons or signals immediately after the circuit is energized. For example, two components physically connected via a switch (e.g., a transistor) can be electronically communicating or coupled regardless of the state of the switch (i.e., open or closed).

[0374] The term "isolation" refers to the relationship between components in which electrons are currently unable to flow between them; if there is an open circuit between the components, then the components are isolated from each other. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0375] The devices containing memory devices discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0376] This document describes exemplary configurations with reference to the accompanying drawings, and does not represent all instances that can be implemented or are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and does not imply "preferred" or "superior to other instances." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0377] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by reference numerals following dashed lines and second numerals, which differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of similar components having the same first reference numeral but independent of the second reference numeral.

[0378] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0379] The various illustrative blocks and modules described in this invention can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0380] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase “based on” should not be construed as referring to a set of closing conditions. For example, without departing from the scope of the invention, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0381] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave) is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0382] The description herein is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will readily be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: A memory device transmits a first signal via a data bus according to a first clock frequency and a double data rate (DDR) signaling scheme. The first signal represents first sense data and is modulated according to a first modulation scheme having a first number of levels. The memory device determines that a second signal representing second sensing data will be transmitted using a second clock frequency and a second modulation scheme, the second modulation scheme having a second number of levels; as well as The memory device transmits the second signal via the data bus according to the second clock frequency and the DDR signaling scheme. The second signal represents the second sensed data and is modulated according to the second modulation scheme.

2. The method of claim 1, wherein the first sensing data and the second sensing data are sensed from the dynamic random access memory (DRAM) array of the memory device.

3. The method according to claim 1, further comprising: Determine the signaling mode of the memory device, wherein the first signal, the second signal, or both are transmitted based at least in part on the signaling mode.

4. The method of claim 1, further comprising: The change in the operating parameters is detected, wherein the second clock frequency, the second modulation scheme, or both are at least partially based on the change in the operating parameters.

5. The method of claim 1, wherein the first clock frequency and the first modulation scheme are associated with the first data rate.

6. The method of claim 5, wherein the second clock frequency and the second modulation scheme are associated with the first data rate.

7. The method of claim 1, wherein the first number of levels is two levels and the second number of levels is more than two levels.

8. The method according to claim 1, wherein the second number of levels is two levels and the first number of levels is more than two levels.

9. A memory device operating according to a Double Data Rate (DDR) signaling scheme, comprising: Volatile memory array; as well as The data bus, wherein the memory device is configured to: A first signal representing first sensing data is transmitted via the data bus according to a first clock frequency and according to the DDR signaling scheme, the first signal representing the first sensing data being modulated according to a first modulation scheme having a first number of levels; A second clock frequency and a second modulation scheme are determined to be used to transmit a second signal representing second sensing data, the second modulation scheme having a second number of levels; as well as The second signal is transmitted via the data bus according to the second clock frequency and the DDR signaling scheme, the second signal representing the second sensed data and modulated according to the second modulation scheme.

10. The memory device of claim 9, wherein the first sensing data and the second sensing data are sensed from the dynamic random access memory (DRAM) array of the memory device.

11. The memory device of claim 9, wherein the memory device is configured to: Determine the signaling mode of the memory device, wherein the first sensing data, the second sensing data, or both are transmitted based at least in part on the signaling mode.

12. The memory device of claim 9, wherein the memory device is configured to: The change in the operating parameters is detected, wherein the second clock frequency, the second modulation scheme, or both are at least partially based on the change in the operating parameters.

13. The memory device of claim 9, wherein the first clock frequency and the first modulation scheme are associated with the first data rate.

14. The memory device of claim 13, wherein the second clock frequency and the second modulation scheme are associated with the first data rate.

15. The memory device of claim 9, wherein the first number of levels is two levels and the second number of levels is more than two levels.

16. The memory device of claim 9, wherein the second number of levels is two levels and the first number of levels is more than two levels.

17. A method comprising: A memory device according to the double data rate (DDR) signaling scheme transmits a first signal via a data bus, the first signal representing first sensed data and modulated according to a first modulation scheme having a first number of levels; A second modulation scheme is determined for transmitting a second signal representing second sensing data via the data bus, the second modulation scheme having a second number of levels; as well as The memory device transmits the second signal via the data bus according to the DDR signaling scheme. The second signal represents the second sensed data and is modulated according to the second modulation scheme.

18. The method of claim 17, wherein the first signal is transmitted according to a first clock frequency, and wherein the second signal is transmitted according to a second clock frequency.

19. The method of claim 18, wherein the first clock frequency is higher than the second clock frequency.

20. The method of claim 17, further comprising: The memory device transmits a third signal via the data bus according to the DDR signaling scheme. The third signal represents third sensed data and is modulated according to the first modulation scheme.

21. The method of claim 20, further comprising: The memory device transmits a fourth signal via the data bus according to the DDR signaling scheme. The fourth signal represents fourth sense data and is modulated according to the second modulation scheme.

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