A self-selecting resistive random access memory and a preparation method thereof
By using a peak-shaped barrier structure of niobium oxide layer and Nb-doped titanium oxide layer in a self-selected resistive switching memory, the nonlinearity and on-state current density of the memory are improved, solving the problem of poor compatibility in the prior art.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-07-03
- Publication Date
- 2026-07-03
AI Technical Summary
Existing self-gated memory cells suffer from a problem where nonlinearity and on-state current density are mutually constrained and cannot be balanced.
A niobium oxide layer is used as the storage layer, and Nb is doped into the titanium oxide layer to form a peak-shaped barrier structure. By combining the stacked structure of the titanium oxide layer and the niobium oxide layer, a self-selected pass-resistance switching memory is fabricated.
This invention achieves a self-selected gate resistive random access memory that simultaneously possesses high nonlinearity and high on-state current density, solving the problem in existing technologies that cannot simultaneously achieve both nonlinearity and on-state current density.
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Figure CN117082873B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics technology, specifically to a self-selected pass-resistive random access memory and its fabrication method. Background Technology
[0002] With the development of memory technology, higher demands are being placed on memory density, making the three-dimensional integration of resistive random access memory (RRAM) a research hotspot. Three-dimensional integration of RRAM falls into two structural categories: three-dimensional stacked cross-array structure and three-dimensional vertical cross-array structure. Compared to the three-dimensional stacked cross-array structure, the three-dimensional vertical cross-array structure requires fewer photolithography steps and has lower costs. In the three-dimensional vertical cross-array structure, the presence of the intermediate electrode in the 1S1R structure causes memory cells on the same bit line (BL) to be short-circuited due to their connection to the same gate transistor. Self-gated memory cells with built-in nonlinear or self-rectifying characteristics become the only option for realizing three-dimensional vertical RRAM (3D VRRAM). Compared to RRAM based on self-rectifying characteristics, RRAM devices based on self-gated memory cells may have greater advantages in achieving high-density storage. Therefore, there is an urgent need to fabricate self-gated memory cells with excellent performance.
[0003] Currently proposed self-gated memory cells suffer from a trade-off between nonlinearity and on-state current density, making it impossible to achieve both simultaneously. Filament-type RRAM devices exhibit high on-state current density but low nonlinearity; while non-filament-type RRAM devices improve nonlinearity but generally suffer from low on-state current density.
[0004] Therefore, the fabrication of a self-selected resistive random access memory (RRAM) with both high nonlinearity and high on-state current density has become an urgent problem to be solved. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a self-selecting resistive random access memory that can simultaneously possess high nonlinearity and high on-state current density.
[0006] Another object of the present invention is to provide a method for fabricating the self-selected resistive random access memory.
[0007] To achieve the above objectives, the present invention provides the following technical solution.
[0008] A self-selecting on-resistance variable memory, comprising:
[0009] A stacked structure is provided with vertical trenches. The stacked structure includes n TiN layers and n insulating dielectric layers that are alternately stacked, where n is an integer from 1 to 16. The TiN layer is the lower electrode, and part of the upper surface of each TiN layer is exposed.
[0010] A titanium oxide layer is disposed in the vertical trench and formed on the TiN layer;
[0011] A niobium oxide layer is disposed in the vertical trench and covers the titanium oxide layer; wherein the titanium oxide layer contains TiO₂ on the side near the TiN layer. x N y Nb element is doped on the side near the niobium oxide layer;
[0012] An upper electrode is disposed in the vertical trench and covers the niobium oxide layer.
[0013] The method for fabricating the self-selected pass-resistance variable memory includes the following steps:
[0014] n TiN layers and n insulating dielectric layers are sequentially and alternately formed on a silicon oxide layer. The n TiN layers and n insulating dielectric layers form a stacked structure, where n is an integer from 1 to 16. The TiN layers are the lower electrode.
[0015] The stacked structure is etched to form vertical trenches;
[0016] Photolithography and etching are used to expose a portion of the upper surface of each TiN layer;
[0017] In the vertical trench, the TiN layer is treated with oxygen plasma to obtain a titanium oxide layer;
[0018] In the vertical trench, a niobium oxide layer is formed by magnetron sputtering to cover the titanium oxide layer;
[0019] An upper electrode is formed in the vertical trench, covering the niobium oxide layer.
[0020] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0021] This invention improves the on-state current density by using niobium oxide, which is less prone to oxygen vacancy accumulation, as the storage layer; at the same time, it enhances the nonlinearity of the device by setting a titanium oxide layer with a peak-shaped band structure as the gate layer. Thus, the self-gated resistive switching memory has both high nonlinearity and high on-state current density, solving the problem that high nonlinearity and high on-state current density cannot be achieved simultaneously in the prior art. Attached Figure Description
[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0023] Figure 1 This is a schematic diagram of the structure of a self-selected pass-resistance variable memory according to an embodiment of the present invention.
[0024] Figure 2 This is the current-voltage characteristic curve of a self-selected on-resistance variable memory according to an embodiment of the present invention.
[0025] Figure 3 This is a schematic diagram of the band structure of a self-selected gate-resistive variable memory according to an embodiment of the present invention, used to explain high nonlinearity.
[0026] Figure 4 a- Figure 4 b is a schematic diagram illustrating the calculation of oxygen vacancy accumulation in the niobium oxide layer using first-principles calculations, used to explain the high on-state current density, wherein... Figure 4 (a) shows the calculation model for oxygen vacancy polymerization energy. Figure 4 (b) shows the oxygen vacancy polymerization energy of niobium oxide.
[0027] Figures 5-9 This is a schematic diagram of the structure obtained in each step of the preparation method according to an embodiment of the present invention.
[0028] Explanation of reference numerals in the attached figures:
[0029] 100 is the silicon oxide layer, 200 is the TiN layer, 300 is the insulating dielectric layer, 400 is the vertical trench, 500 is the titanium oxide layer, 600 is the niobium oxide layer, and 700 is the top electrode. Detailed Implementation
[0030] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0031] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0032] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0033] Existing self-gated memory cells suffer from a trade-off between nonlinearity and on-state current density, making it impossible to achieve both simultaneously. Therefore, fabricating self-gated resistive random access memory (RRAM) with both high nonlinearity and high on-state current density has become an urgent problem to be solved.
[0034] To address the aforementioned problems, this invention provides an improved self-selective pass-resistance variable memory that simultaneously possesses high nonlinearity and high on-state current density.
[0035] Specifically, such as Figure 1 As shown, the self-selecting resistive switching memory of the present invention includes: a stacked structure, wherein a vertical trench 400 is provided in the stacked structure, the stacked structure includes n alternating layers of TiN layers 200 and n layers of insulating dielectric layers 300, where n is an integer from 1 to 16, the TiN layers 200 are the lower electrode, and a portion of the upper surface of each TiN layer 200 is exposed; a titanium oxide layer 500, which is disposed in the vertical trench 400 and formed on the TiN layers 200; and a niobium oxide layer 600, which is disposed in the vertical trench 400 and covers the titanium oxide layer 500; wherein the titanium oxide layer 500 contains TiO2 on the side near the TiN layers 200. x N y Nb element is doped on the side near the niobium oxide layer 600; upper electrode 700 is disposed in the vertical trench 400 and covers the niobium oxide layer 600.
[0036] from Figure 2 As can be seen, the self-selected resistive random access memory of the present invention simultaneously exhibits high nonlinearity (>5000) and high on-state current (>1uA). The present invention uses a niobium oxide layer 600 as the storage layer. Since the polymerization energy of niobium oxide is positive, the niobium oxide layer 600 is less prone to oxygen vacancy accumulation, effectively preventing device breakdown and thus achieving a high on-state current density, such as... Figure 4 As shown in a-4b. Furthermore, a titanium oxide layer 500 is obtained by treating the lower electrode TiN with oxygen plasma. The titanium oxide layer 500 is located between the TiN layer 200 and the niobium oxide layer 600. The titanium oxide layer 500 contains TiO₂ on the side closest to the TiN layer 200. x N yMeanwhile, Nb donor doping is formed on the side of the titanium oxide layer 500 near the niobium oxide layer 600, resulting in a peak-shaped potential barrier inside the titanium oxide layer 500, thereby enabling the device to achieve high nonlinearity, such as... Figure 3 As shown.
[0037] In some embodiments, the titanium oxide layer 500 comprises one or more of TiO, Ti2O3, and TiO2. In some specific embodiments, the titanium oxide layer 500 is TiO2.
[0038] In some embodiments, the niobium oxide layer 600 comprises one or more of NbO, NbO2, Nb2O3, and Nb2O5. In some specific embodiments, the niobium oxide layer 600 is Nb2O5.
[0039] In some specific implementations, the titanium oxide layer 500 is TiO2, and the niobium oxide layer 600 is Nb2O5.
[0040] In some implementations, the insulating dielectric layer 300 is SiO2.
[0041] In some implementations, the upper electrode 700 is Ru.
[0042] This invention also provides a method for fabricating the self-selected resistive random access memory, see reference. Figure 5-9 This includes the following steps:
[0043] n TiN layers 200 and n insulating dielectric layers 300 are sequentially and alternately formed on the silicon oxide layer 100. The n TiN layers 200 and n insulating dielectric layers 300 form a stacked structure, where n is an integer from 1 to 16, and the TiN layer 200 is the lower electrode.
[0044] The etched stacked structure forms vertical trenches 400;
[0045] Photolithography and etching are used to expose part of the upper surface of each TiN layer 200;
[0046] In the vertical trench 400, the TiN layer 200 is treated with oxygen plasma to obtain the titanium oxide layer 500.
[0047] In the vertical trench 400, a niobium oxide layer 600 is formed by magnetron sputtering, which covers the titanium oxide layer 500.
[0048] An upper electrode 700 is formed in the vertical trench 400, which is covered with a niobium oxide layer 600.
[0049] This invention forms a titanium oxide layer 500 by treating the TiN layer 200 with oxygen plasma, thus forming TiO2 on the side of the titanium oxide layer 500 close to the TiN layer 200. x N yIn addition, when forming the niobium oxide layer 600 by magnetron sputtering, Nb element is doped into the titanium oxide layer 500, which forms a peak-shaped potential barrier inside the titanium oxide layer 500, thereby enabling the device to achieve high nonlinearity.
[0050] In some embodiments, after forming the upper electrode 700, the resulting structure is sequentially immersed in acetone solution and ethanol solution, washed with deionized water, and dried with nitrogen gas.
[0051] In some embodiments, physical vapor deposition is used to form the TiN layer 200 and the insulating dielectric layer 300.
[0052] In some embodiments, forming a vertical trench 400 includes: coating a photoresist on the upper surface of a stacked structure and performing photolithography; using the photoresist as a mask, first performing plasma etching on the insulating dielectric layer 300 with CF4, then performing plasma etching on the TiN layer 200 with BCl3, repeating this process n times; and removing the photoresist.
[0053] In some embodiments, exposing a portion of the upper surface of each TiN layer 200 includes etching the insulating dielectric layer 300 with CF4 and etching the TiN layer 200 with BCl3.
[0054] The present invention will be further described below with reference to specific embodiments.
[0055] Example 1
[0056] (1) Fabrication of the bottom electrode: TiN (20 nm thick) / SiO2 (30 nm thick) was grown sequentially using physical vapor deposition. This step was repeated twice to obtain the following: Figure 5 The stacked structure shown uses TiN as the lower electrode and SiO2 as the insulating dielectric layer 300.
[0057] (2) Photolithography: The resulting stacked structure is photolithographically etched and developed;
[0058] (3) Etching: Using photoresist as a mask, SiO2 is plasma etched with CF4, followed by TiN plasma etched with BCl3. This step is repeated twice to obtain a vertical trench of 400°. Figure 6 As shown;
[0059] (4) Removal of photoresist: The structure obtained in step (3) is soaked in acetone solution and then soaked in ethanol to remove the photoresist.
[0060] (5) Photolithography: The structure obtained in step (4) is photolithographically etched and developed;
[0061] (6) Etching: SiO2 is etched with CF4 to expose the top TiN layer 200 (for ease of description, the top TiN layer 200 is simply referred to as the first TiN layer 200, and from top to bottom are the second TiN layer 200, the third TiN layer 200, ... the sixteenth TiN layer 200).
[0062] (7) Cleaning: The structure obtained in step (6) is soaked in acetone solution and then soaked in ethanol solution to clean away the photoresist;
[0063] (8) Photolithography: Repeat step (5);
[0064] (9) Etching: Using photoresist as a mask, BCl3 is used to etch the exposed TiN layer 200, followed by CF4 etching of SiO2 to expose the second TiN layer 200, as shown. Figure 7 As shown;
[0065] (10) Photolithography: Repeat step (5);
[0066] (11) Preparation of functional layer: First, the TiN electrode is treated with oxygen plasma to obtain a titanium oxide layer of 500, such as... Figure 8 As shown; then, a niobium oxide layer of 600 was grown using magnetron sputtering with Ar gas as the working gas, and the resulting structure is shown. Figure 9 As shown;
[0067] (12) Fabrication of the top electrode: A 40 nm thick Ru top electrode was grown using ion beam sputtering, and the resulting structure is shown in the figure. Figure 1 As shown;
[0068] (13) Peeling: First, soak the structure obtained in step (14) in acetone solution, then soak it in ethanol solution, and finally rinse it with deionized water and blow it dry with nitrogen.
[0069] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A self-selecting, resistive random access memory, comprising: include: A stacked structure is provided with vertical trenches. The stacked structure includes n TiN layers and n insulating dielectric layers that are alternately stacked, where n is an integer from 1 to 16. The TiN layer is the lower electrode, and part of the upper surface of each TiN layer is exposed. A titanium oxide layer is disposed in the vertical trench and formed on the TiN layer; a niobium oxide layer disposed in the vertical trench and covering the titanium oxide layer; wherein the titanium oxide layer contains TiO x N y doped with Nb element on a side close to the niobium oxide layer; An upper electrode is disposed in the vertical trench and covers the niobium oxide layer.
2. The self-switching resistive memory of claim 1, wherein, The titanium oxide layer includes one or more of TiO, Ti2O3, and TiO2.
3. The self-switching resistive random access memory of claim 1 or 2, wherein, The niobium oxide layer includes one or more of NbO, NbO2, Nb2O3, and Nb2O5.
4. The self-selecting pass-resistance variable memory according to claim 1 or 2, characterized in that, The insulating dielectric layer is SiO2; the upper electrode is Ru.
5. A method for fabricating a self-selected on-resistive variable memory, characterized in that, Includes the following steps: n TiN layers and n insulating dielectric layers are sequentially and alternately formed on a silicon oxide layer. The n TiN layers and n insulating dielectric layers form a stacked structure, where n is an integer from 1 to 16. The TiN layers are the lower electrode. The stacked structure is etched to form vertical trenches; Photolithography and etching are used to expose a portion of the upper surface of each TiN layer; In the vertical trench, the TiN layer is treated with oxygen plasma to obtain a titanium oxide layer; In the vertical trench, a niobium oxide layer is formed by magnetron sputtering to cover the titanium oxide layer; An upper electrode is formed in the vertical trench, covering the niobium oxide layer.
6. The preparation method according to claim 5, characterized in that, Also includes: After forming the upper electrode, the resulting structure was sequentially immersed in acetone solution and ethanol solution, washed with deionized water, and dried with nitrogen gas.
7. The preparation method according to claim 5 or 6, characterized in that, The TiN layer and the insulating dielectric layer are formed by physical vapor deposition.
8. The preparation method according to claim 5 or 6, characterized in that, Forming the vertical trench includes: Photoresist is coated onto the upper surface of the stacked structure and photolithography is performed. Using photoresist as a mask, the insulating dielectric layer is first plasma etched with CF4, then the TiN layer is plasma etched with BCl3, and this process is repeated n times; and Remove the photoresist.
9. The preparation method according to claim 5 or 6, characterized in that, Exposing a portion of the upper surface of each TiN layer includes: The insulating dielectric layer was etched using CF4, and the TiN layer was etched using BCl3.
10. The preparation method according to claim 5 or 6, characterized in that, The insulating dielectric layer is SiO2; the upper electrode is Ru.