System and data receiving method for receiving multiple ssi interface encoders with single spi

Abstract

The application discloses a system and a data receiving method for receiving multiple SSI interface encoders by using a single SPI, and the system comprises a microcontroller, an SSI interface encoder, an RS-422 serial data transceiver and a multiplexer; the microcontroller is used for providing an SPI communication interface, generating a synchronization pulse signal CLK+ and a synchronization pulse signal CLK-, and receiving data of the SSI interface encoder; the SSI interface encoder comprises a Clock+ signal, a Clock- signal, a DATA+ signal and a DATA- signal; the RS-422 serial data transceiver is used for converting a TTL level of the synchronization pulse signal into a differential level, and converting a differential level of the data of the SSI interface encoder into a TTL level; the multiplexer judges whether signals of output pins and input one or input two are the same through high and low levels of a gate pin; the application utilizes an SPI interface of a microcontroller MCU to realize the reception of data of the SSI interface encoder, does not need to increase a logic chip such as an FPGA or a CPLD, simplifies hardware circuit design, and reduces cost.

Description

Technical Field

[0001] This invention relates to the field of signal communication technology, and in particular to a system and data receiving method that uses a single-channel SPI to receive data from multiple SSI interface encoders. Background Technology

[0002] Absolute encoders are frequently used in precision automation equipment to measure attitude information at different positions. The Synchronous Serial Interface (SSI) is a commonly used interface for high-precision absolute encoders, enabling high-precision, real-time angle output while exhibiting strong anti-interference capabilities, and is widely applied. Generally, the SPI interface of a microcontroller (MCU) is used to receive SSI encoder data. However, because the SSI interface protocol lacks a chip select signal, it is impossible to read data from multiple SSI encoders using a single SPI interface. An existing patent, titled "System and Transmission Method for Receiving SSI Interface Encoder Data Based on SPI Bus" (application number CN202210845992.2), mentions two methods for reading SSI encoder data without using an SPI interface, but both have irreparable drawbacks.

[0003] To overcome these shortcomings, this chapter proposes a system and data reception method that uses a single-channel SPI to receive data from multiple SSI interface encoders. Summary of the Invention

[0004] The purpose of this application is to provide a system and data receiving method for receiving multiple SSI interface encoders using a single SPI interface, aiming to solve the problem that existing microcontrollers (MCUs) cannot acquire data from multiple SSI interface encoders due to insufficient SPI interfaces.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] This application provides a system that uses a single SPI to receive multiple SSI interface encoders. The system includes a microcontroller, an SSI interface encoder, an RS-422 serial data transceiver, and a multiplexer.

[0007] The microcontroller is used to provide an SPI communication interface, generate synchronization pulse signals CLK+ and CLK-, and receive data from the SSI interface encoder.

[0008] The SSI interface encoder includes a Clock+ signal, a Clock- signal, a DATA+ signal, and a DATA- signal; the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- are respectively connected to the Clock+ signal and the Clock- signal, and the DATA+ signal and the DATA- signal are respectively connected to the RS-422 serial data transceiver.

[0009] The RS-422 serial data transceiver is used to convert the TTL level of the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- into a differential level, and to convert the DATA+ signal and the DATA- signal into a TTL level.

[0010] The multiplexer determines whether the signal of the output pin is the same as that of input one or input two by using the high or low level of the selection pin.

[0011] Furthermore, the connection relationships between the microcontroller, SSI interface encoder, RS-422 serial data transceiver, and multiplexer are as follows:

[0012] The CLK signal of the SPI in the microcontroller is connected to the transmitting end of the RS-422 serial data transceiver; the MISO signal of the SPI in the microcontroller is connected to the output pin of the multiplexer.

[0013] Each of the SSI interface encoders corresponds to one RS-422 serial data transceiver;

[0014] After passing through the RS-422 serial data transceiver, the SSI interface encoder generates four TTL signals, DataA, DataB, DataC, and DataD, which are connected to the input of the multiplexer.

[0015] The control terminal of the multiplexer is connected to the three I / O interfaces of the microcontroller.

[0016] This application also provides a method for receiving data from multiple SSI interface encoders using a single SPI interface, including the following steps:

[0017] The I / O interface of the multiplexer is controlled to send the chip select signal CSA;

[0018] Determine whether the DMA receive mode of the SPI interface in the microcontroller has received the complete flag.

[0019] According to the interface protocol delay t of the SSI interface encoder w The I / O controls the sending of chip select signals CSB, CSC, and CSD.

[0020] Furthermore, before the step of controlling the I / O interface of the multiplexer to send the chip select signal CSA, the following steps are included:

[0021] Configure the SPI interface and DMA mode initialization in the microcontroller. The SPI interface is configured as mode 2, with clock polarity CPOL=1 and phase CPHA=0.

[0022] Furthermore, the step of controlling the I / O interface of the multiplexer to send the chip select signal CSA includes the following steps:

[0023] The data input strobe of the multiplexer is set to SSI interface encoder A, which activates the DMA transmit mode of the SPI interface and transmits a synchronization clock pulse; wherein the clock frequency of the synchronization pulse ranges from 0.5 to 2 MHz.

[0024] Furthermore, the step of determining whether the DMA receive mode of the SPI interface in the microcontroller has received the complete flag includes the following steps:

[0025] When it is determined that the DMA receive mode of the SPI interface in the microcontroller has completed the reception, a DMA interrupt is generated. In the interrupt, the data of the SSI interface encoder A is stored in array 1 and parsed. When it is determined that the DMA receive mode of the microcontroller's SPI has not completed the reception, the DMA send mode is retransmitted.

[0026] Furthermore, the time for switching the control I / O level needs to wait until the data reception is complete, and the interface protocol delay is greater than the clock idle time specified in the interface protocol.

[0027] This application provides a system and data reception method for receiving data from multiple SSI interface encoders using a single-channel SPI, which has the following advantages:

[0028] (1) This application initializes the microcontroller and multiplexer by configuring the microcontroller and multiplexer, interrupting the timer, controlling the I / O to send the chip select signal, and determining whether the microcontroller's SPI DMA receive mode has received the complete flag. It then delays by t according to the SSI interface protocol. w The control IO sends a chip select signal to receive data from the SSI interface encoder without the need for additional logic chips such as FPGA or CPLD, simplifying hardware circuit design and reducing costs.

[0029] (2) The single-channel SPI interface proposed in this application realizes the data acquisition of the SSI interface encoder, expands the interface of the microcontroller MCU, and realizes the acquisition of multiple channels of data in the simplest way; and controls the IO to send the chip select signal according to the SSI interface protocol delay. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the system of Embodiment 1 of this application, which uses a single SPI to receive multiple SSI interface encoders;

[0031] Figure 2 This is a hardware connection diagram of Embodiment 1 of this application;

[0032] Figure 3 This is a control timing diagram for Embodiment 1 of this application;

[0033] Figure 4 This is a flowchart illustrating the data reception method of receiving data from multiple SSI interface encoders using a single-channel SPI receiver according to Embodiment 2 of this application.

[0034] Figure 5 This is a control flowchart for Embodiment 2 of this application. Detailed Implementation

[0035] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0037] Please see Figure 1 This is a schematic diagram of a system that uses a single-channel SPI to receive multiple SSI interface encoders, as proposed in this application; the system includes a microcontroller, an SSI interface encoder, an RS-422 serial data transceiver, and a multiplexer.

[0038] The microcontroller is used to provide an SPI communication interface, generate synchronization pulse signals CLK+ and CLK-, and receive data from the SSI interface encoder.

[0039] The SSI interface encoder includes a Clock+ signal, a Clock- signal, a DATA+ signal, and a DATA- signal; the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- are respectively connected to the Clock+ signal and the Clock- signal, and the DATA+ signal and the DATA- signal are respectively connected to the RS-422 serial data transceiver.

[0040] The RS-422 serial data transceiver is used to convert the TTL level of the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- into a differential level, and to convert the DATA+ signal and the DATA- signal into a TTL level.

[0041] The multiplexer determines whether the signal of the output pin is the same as that of input one or input two by using the high or low level of the selection pin.

[0042] In this embodiment, the connection relationship between the microcontroller, SSI interface encoder, RS-422 serial data transceiver, and multiplexer is described in detail.

[0043] The CLK signal of the SPI in the microcontroller is connected to the transmitting end of the RS-422 serial data transceiver; the MISO signal of the SPI in the microcontroller is connected to the output pin of the multiplexer.

[0044] Each of the SSI interface encoders corresponds to one RS-422 serial data transceiver;

[0045] After passing through the RS-422 serial data transceiver, the SSI interface encoder generates four TTL signals, DataA, DataB, DataC, and DataD, which are connected to the input of the multiplexer.

[0046] The control terminal of the multiplexer is connected to the three I / O interfaces of the microcontroller.

[0047] Please see Figure 2 This is a hardware connection diagram of Embodiment 1 of this application; Figure 2 The middle (11) is an ARM microcontroller of model GD32F450VKT6, which is used to provide an SPI communication interface, generate synchronization pulses, and receive data from the SSI interface encoder. Its SCK pin is connected to the transmit T pin of four MAX3490 RS-422 serial data transceivers (11) to share the clock signal.

[0048] The generated differential clock signals are connected to Clock+ and Clock- of encoder (12) respectively, and the differential data signals of the four encoders (13) are connected to R+ and R- of the corresponding transceiver (11) respectively. The generated four TTL signals DataA, DataB, DataC and DataD are connected to the input terminals of multiplexer (14) and multiplexer (15).

[0049] The outputs of multiplexers (14) and (15) are connected to the input of (16). The MISO pin of MCU (11) is connected to the output of multiplexer (16). The IO1, IO2 and IO3 of MCU (11) are connected to the signal gating pins of multiplexers (14), (16) and (15).

[0050] Please see Figure 3 Here is a control timing diagram for Embodiment 1 of this application; the working principle is explained as follows:

[0051] Set a 1ms timer interrupt in MCU(11) and read the angle values ​​of the four encoders in the interrupt.

[0052] In MCU(11) IO1, IO2 and IO3, "0" is defined as high level, "1" as low level and "X" as any level. Figure 5 The level states of IO1, IO2 and IO3 corresponding to CSA(21), CSB(22), CSC(23) and CSD(24) are “X00”, “X01”, “01X” and “11X”, respectively.

[0053] After entering the timer interrupt, the chip select signal CSA-"X00" is sent to enable the SPI DMA transmit mode. Three 8-bit data signals, totaling 24 synchronization pulses, are sent. After the angle data of encoder A is received, the SPI DMA receive interrupt is entered, and the angle parsing and processing are performed in the interrupt.

[0054] Interrupt reception complete, SPI DMA transmit mode disabled, delay tw, parameters Figure 3 (25), in this embodiment tw = 26us. The chip select signals CSB-“X01”, CSC-“01X” and CSD-“11X” are sent sequentially. The above steps are repeated to complete the reception of the angle data of encoders B, C and D.

[0055] In summary, this application solves the problem of no chip select signal for encoders in the SSI interface protocol by using a small-package multiplexer in Embodiment 1; it realizes the reception of four SSI interface encoders with a single SPI by using a microcontroller, an SSI interface encoder, an RS-422 serial data transceiver and a multiplexer; the system has simple hardware circuitry, is easy to implement, and can effectively expand the ability of the microcontroller MCU to receive SSI encoders.

[0056] Example 2

[0057] Please see Figure 4 This is a flowchart illustrating the data reception method using a single-channel SPI to receive data from multiple SSI interface encoders proposed in Embodiment 2 of this application; the specific steps include:

[0058] S1: Control the I / O interface of the multiplexer to send the chip select signal CSA.

[0059] In this embodiment, before controlling the I / O interface of the multiplexer to send the chip select signal CSA, the SPI interface and DMA mode initialization in the microcontroller are configured. The SPI interface is configured as mode 2, with clock polarity CPOL=1 and phase CPHA=0.

[0060] The interrupt time of the timer depends on the clock frequency of the SSI interface encoder and the number of bits of data to be transmitted. During the timer interrupt, the control IO sends the chip select signal CSA, the data input strobe of the multiplexer is selected as the SSI interface encoder A, the DMA transmit mode of SPI is started, and the synchronous clock pulse is sent. The clock frequency of the synchronous pulse is in the range of 0.5 to 2 MHz.

[0061] S2: Determine whether the DMA receive mode of the SPI interface in the microcontroller has received the complete flag.

[0062] In this embodiment, when it is determined that the DMA receive mode of the microcontroller SPI interface has completed receiving, a DMA interrupt is generated. In the interrupt, the data of the SSI interface encoder A is stored in array 1 and parsed. When it is determined that the DMA receive mode of the microcontroller SPI has not completed receiving, the DMA send mode is retransmitted.

[0063] S3: Delay t according to the interface protocol of the SSI interface encoder w The I / O controls the sending of chip select signals CSB, CSC, and CSD.

[0064] In this embodiment, the time for switching the control IO level needs to wait until the data reception is complete, and the SSI interface protocol delay is greater than the clock idle time specified in the SSI interface protocol.

[0065] Please see Figure 5 The following is a control flowchart of Embodiment 2 of this application; it will be described in detail below.

[0066] First, interrupt the timer, control the I / O to send the chip select signal CSA, enable SPI-VDA transmit, and determine whether the DMA receive mode of the SPI in the microcontroller has completed receiving. If the receiving is not complete, return to enable SPI-VDA transmit; if the receiving is complete, disable SPI-VDA transmit, and then delay t according to the SSI interface protocol. w The control I / O sends chip select signals CSB, CSC, and CSD until the timer stops interrupting, at which point the control is complete.

[0067] In summary, this application configures the microcontroller and multiplexer initialization through Embodiment 2, interrupts the timer, controls the IO to send the chip select signal, and determines whether the microcontroller's SPI DMA receive mode has received the complete flag. According to the SSI interface protocol delay tw, the IO is controlled to send the chip select signal, thereby realizing the reception of SSI interface encoder data. Moreover, it does not require the addition of logic chips such as FPGA or CPLD, simplifying hardware circuit design and reducing costs.

[0068] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0069] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0070] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

[0071] Of course, the present invention may have many other embodiments. Based on this embodiment, other embodiments obtained by those skilled in the art without any creative effort are all within the scope of protection of the present invention.

Claims

1. A system that uses a single-channel SPI receiver to receive multiple SSI interface encoders, characterized in that, The system includes a microcontroller, an SSI interface encoder, an RS-422 serial data transceiver, and a multiplexer. The microcontroller is used to provide an SPI communication interface, generate synchronization pulse signals CLK+ and CLK-, and receive data from the SSI interface encoder. The SSI interface encoder includes a Clock+ signal, a Clock- signal, a DATA+ signal, and a DATA- signal; the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- are respectively connected to the Clock+ signal and the Clock- signal, and the DATA+ signal and the DATA- signal are respectively connected to the RS-422 serial data transceiver. The RS-422 serial data transceiver is used to convert the TTL level of the synchronization pulse signal CLK+ and the synchronization pulse signal CLK- into a differential level, and to convert the DATA+ signal and the DATA- signal into a TTL level. The multiplexer determines whether the signal of the output pin is the same as input one or input two by using the high and low levels of the gating pin; The connection relationships between the microcontroller, SSI interface encoder, RS-422 serial data transceiver, and multiplexer are as follows: The CLK signal of the SPI in the microcontroller is connected to the transmitting end of the RS-422 serial data transceiver; the MISO signal of the SPI in the microcontroller is connected to the output pin of the multiplexer. Each of the SSI interface encoders corresponds to one RS-422 serial data transceiver; After passing through the RS-422 serial data transceiver, the SSI interface encoder generates four TTL signals, DataA, DataB, DataC, and DataD, which are connected to the input of the multiplexer. The control terminal of the multiplexer is connected to the three I / O interfaces of the microcontroller.

2. A data receiving method for a system employing a single-channel SPI receiver to receive data from multiple SSI interface encoders according to claim 1, characterized in that, Includes the following steps: The I / O interface of the multiplexer is controlled to send the chip select signal CSA; Determine whether the DMA receive mode of the SPI interface in the microcontroller has received the complete flag. According to the interface protocol delay t of the SSI interface encoder w The I / O interface is controlled to send chip select signals CSB, CSC and CSD.

3. The data receiving method for a system employing a single-channel SPI receiver to receive data from multiple SSI interface encoders according to claim 2, characterized in that, Before the step of controlling the I / O interface of the multiplexer to send the chip select signal CSA, the following steps are included: Configure the SPI interface and DMA mode initialization in the microcontroller. The SPI interface is configured as mode 2, with clock polarity CPOL=1 and phase CPHA=0.

4. The data receiving method for a system employing a single-channel SPI receiver to receive data from multiple SSI interface encoders according to claim 3, characterized in that, The step of controlling the I / O interface of the multiplexer to send the chip select signal CSA includes the following steps: The data input strobe of the multiplexer is set to SSI interface encoder A, which activates the DMA transmit mode of the SPI interface and sends a synchronization clock pulse; wherein the clock frequency of the synchronization pulse is in the range of 0.5~2MHz.

5. The data receiving method for a system employing a single-channel SPI receiver to receive data from multiple SSI interface encoders according to claim 3, characterized in that, The step of determining whether the DMA receive mode of the SPI interface in the microcontroller has received the complete flag includes the following steps: When it is determined that the DMA receive mode of the SPI interface in the microcontroller has completed receiving, a DMA interrupt is generated. In the interrupt, the data of the SSI interface encoder A is stored in array 1 and parsed. When it is determined that the DMA receive mode of the SPI interface in the microcontroller has not completed receiving, the DMA send mode is retransmitted.

6. The data receiving method of a system employing a single-channel SPI to receive data from multiple SSI interface encoders according to claim 3, characterized in that, The time required for the level switching of the chip select signal sent by the I / O interface to be completed is longer than the clock idle time specified in the interface protocol.

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