An analytical mapping method based on a resource model of a commercial Xilinx Virtex-7 FPGA chip

Abstract

The application relates to a parsing and drawing method based on a commercial Xilinx Virtex-7 FPGA chip resource model, which comprises the following steps: Virtex-7 FPGA architecture system files in.xml format are parsed, Virtex-7 FPGA chip attribute information is obtained, and the attribute information is stored in a first structure; a netlist circuit file in.net format is parsed, resource information of the netlist circuit file is obtained, and the resource information is stored in a cluster netlist class; a circuit layout file in.place format is parsed, resource information of the circuit layout file is obtained, and the resource information is stored in a second structure; a Virtex-7 FPGA chip architecture, a layout block distribution and network connection of a circuit are drawn according to the first structure, the cluster netlist class and the second structure; a circuit routing file in.route format is parsed, resource information of the circuit routing file is obtained, and a track vector is stored; and according to the cluster netlist class, the resource information of the circuit routing file and a preset routing resource graph, wiring connection and key wiring path delay of the circuit are drawn. The application has high overall operation efficiency and low resource consumption.

Description

Technical Field

[0001] This invention belongs to the field of auxiliary design software technology for FPGA chip resource models, and relates to a method for parsing and drawing resource models based on commercial Xilinx Virtex-7 FPGA chips. Background Technology

[0002] As a programmable semiconductor device, FPGA offers higher performance and flexibility than other programmable platforms such as CPUs and GPUs, giving it greater market potential in areas such as 5G communication systems, large-scale autonomous driving, edge computing, and machine learning. In recent years, with the development of FPGA underlying process technology, the capacity, integration level, device density, and number of programmable logic units in FPGA devices have increased rapidly. Xilinx's Virtex-7 FPGAs, offering up to 2 million logic units and high throughput, provide and customize high-performance computing solutions for aerospace, defense, and communications industries. However, Virtex-7 FPGAs are primarily obtained from Xilinx as packaged chips, and the Vivado EDA design software for Virtex-7 FPGAs is expensive and closed-source as a trade secret.

[0003] In summary, researchers face significant challenges in studying Virtex-7 FPGAs and developing corresponding EDA software. Therefore, developing design-aided design software based on Virtex-7 FPGA chip resource models would be beneficial for researchers in exploring and designing Virtex-7 FPGA architectures and conducting research on corresponding EDA algorithms.

[0004] Currently, research and techniques for Virtex-7 FPGA chip resource modeling primarily utilize structured abstract modeling methods, which are employed in the academic open-source EDA software VTR. This structured abstract modeling approach is based on XML (Extensible Markup Language), using hierarchical closed tag pairs and custom attributes to describe FPGA chip resource information. However, this modeling method requires researchers to possess extremely high levels of expertise and involves a massive workload. Furthermore, in the research of Virtex-7 FPGA architecture and EDA algorithms, researchers need to verify whether the architecture design meets expected results. Therefore, designing auxiliary visualization software for Virtex-7 FPGA chip resource models is of practical significance, as it can improve researchers' work efficiency and assist in solving the problems they face.

[0005] Currently, the academic open-source EDA software VTR mainly adopts a structured abstract modeling approach. However, the Virtex-7 FPGA chip resource models constructed using this modeling approach are quite large in scale and complex in structure, which cannot conveniently meet the actual needs of researchers. Summary of the Invention

[0006] To address the aforementioned problems in the existing technology, this invention provides a method for parsing and drawing resource models based on commercial Xilinx Virtex-7 FPGA chips. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] This invention provides a method for parsing and drawing resource models based on commercial Xilinx Virtex-7 FPGA chips, including the following steps:

[0008] S1. Obtain Virtex-7 FPGA chip attribute information by parsing the .xml format Virtex-7 FPGA architecture file, and store the Virtex-7 FPGA chip attribute information in the first structure;

[0009] S2. By parsing the .NET format netlist circuit file, the resource information of the netlist circuit file is obtained, and the resource information of the netlist circuit file is stored in the cluster netlist class;

[0010] S3. By parsing the .place format circuit layout file, the resource information of the circuit layout file is obtained, and the resource information of the circuit layout file is stored in the second structure;

[0011] S4. Draw the Virtex-7 FPGA chip architecture, the layoutable block distribution of the circuit, and the network connections based on the first structure, the cluster netlist class, and the second structure;

[0012] S5. By parsing the .route format circuit routing file, obtain the resource information of the circuit routing file and store it in the trajectory vector of the linked storage structure with the routing backtracking structure as an element.

[0013] S6. Based on the cluster netlist class, the resource information of the circuit routing file, and the preset routing resource diagram, draw the circuit routing connections and critical routing path delays.

[0014] In one embodiment of the present invention, the Virtex-7 FPGA chip attribute information includes: size, mesh position, netlist model primitives, devices, switches, general interconnect resources, dedicated interconnect resources, physical tile blocks, and complex logic blocks; storing the Virtex-7 FPGA chip attribute information into a first structure includes:

[0015] The dimensions and grid positions are stored in the chip grid distribution structure;

[0016] The netlist model primitives, the device, the switch, the general interconnect resources, and the dedicated interconnect resources are stored in the chip architecture information structure;

[0017] Store the physical tile block in a physical tile block type structure;

[0018] The complex logic block is stored in a logic block type structure.

[0019] In one embodiment of the present invention, the resource information of the circuit layout file includes: row and column coordinates of logic unit blocks, name of logic unit blocks, sub-blocks of logic unit blocks, and occupancy information of logic unit blocks; storing the resource information of the circuit layout file into a second structure includes:

[0020] Store the row and column coordinates of the logical unit block in a layout position coordinate structure;

[0021] The logical unit block name, the logical unit block sub-block, and the logical unit block occupancy information are stored in a matrix structure with cluster block structures at specific grid positions as elements.

[0022] In one embodiment of the present invention,

[0023] The resource information of the netlist circuit file includes: the internal composition of the physical logic block, the number of physical logic blocks, the inputs / outputs of the physical logic block, and the clock of the physical logic block;

[0024] The resource information in the circuit routing file includes: network name and network routing start and end points, horizontal or vertical channels, input or output pins, and coordinates.

[0025] In one embodiment of the present invention, step S4 includes:

[0026] Step S4.1: Obtain drawing configuration attributes, including: drawing font style, drawing text size, line style, and text alignment.

[0027] Step S4.2: Traverse the chip grid distribution data structure, ignoring non-starting Tile blocks at the current grid position.

[0028] Step S4.3: Based on the physical tile block type structure, the cluster netlist class, and the matrix structure, obtain each physical tile block type, calculate the capacity of each physical tile block, and determine whether the current physical tile block has child tiles.

[0029] Step S4.4: If the current physical tile block has child tiles, then traverse all child tiles of the current physical tile block and obtain the drawing algorithm for the child tile block corresponding to the child tile block;

[0030] Step S4.5: If the current physical tile block has no child tiles, then ignore it and do not draw it.

[0031] In one embodiment of the present invention, step S4.4 includes:

[0032] Step S4.4.1: If the layable block associated with the current grid position in the sub-Tile block is an invalid block, then exit the current traversal and re-execute the traversal process for the next physical Tile block.

[0033] Step S4.4.2: If the layable block associated with the current grid position in the sub-Tile block is a non-empty block, then fill it with the first color and draw the block boundary outline as a solid line.

[0034] If the layable block associated with the current grid position in the sub-Tile block is an empty block, then fill it with the second color and draw the block boundary outline as a dashed line, wherein the first color is darker than the second color;

[0035] Step S4.4.3: If the width and height offset of the chip grid distribution in the sub-Tile block are not 0, then draw the block name text at the center of the layable block;

[0036] If the width and height offset of the chip grid distribution in the sub-Tile block is 0, then the block name text is drawn at a preset position from the bottom of the layable block.

[0037] In one embodiment of the present invention, the method further includes:

[0038] Step S4.6: After receiving the network connection view display instruction, the network in the cluster netlist class is traversed, and the network connection view is drawn according to the drawing layout network connection algorithm.

[0039] In one embodiment of the present invention, step S4.5 includes:

[0040] Step S4.6.1: Ignore networks that have not been wired or connected;

[0041] Step S4.6.2: Obtain the source block of the current network and calculate the center of the block bounding box;

[0042] Step S4.6.3: Traverse all receiver blocks in the current network, obtain receiver blocks that have pin connections with the current network, and calculate the center of the block bounding box;

[0043] Step S4.6.4: Draw a solid black line from the center of the source block bounding box to the center of all receiver block bounding boxes.

[0044] In one embodiment of the present invention, step S6 includes:

[0045] Step S6.1: Traverse the cluster netlist class, ignoring networks that have not been wired;

[0046] Step S6.2: Based on the trajectory vector and the head node of the network to be wired in the trajectory vector, obtain the source node of the current network and assign it as the recursion starting point;

[0047] Step S6.3: Traverse the routing resource nodes driven by the current source node, and find the routing resource type of the routing resource node according to the preset routing resource graph;

[0048] Step S6.4: Traverse different routing resource types to complete the drawing of routing resources.

[0049] In one embodiment of the present invention, step S6.4 includes:

[0050] If the node type is a source / receiver type, then draw the source and receiver of the wiring connection;

[0051] If the node type is an output pin type, then call draw_rr_pin to draw the specific connection of the output pin;

[0052] If the node type is an input pin type, then call draw_rr_pin to draw the specific connection of the input pin; and determine whether the predecessor node of the node of the input pin type is an output pin type; if it is an output pin, then call draw_pin_to_pin to draw the connection from the output pin to the input pin; if it is not an output pin, then call draw_pin_to_chan_edge to draw the connection from the input pin to the horizontal / vertical routing resource channel;

[0053] If the node type is a vertical routing resource channel type, then draw_rr_chan is called to draw the connection of the vertical routing resource channel; and according to the predecessor type of the node of the vertical routing resource channel type, draw_chanx_to_chany_edge, draw_chany_to_chany_edge and draw_pin_to_chan_edge are called respectively to draw the connection between the horizontal and vertical routing resource channels, between the vertical and vertical routing resource channels, and between the input pin and the vertical routing resource channel;

[0054] If the node type is a horizontal routing resource channel type, then draw_rr_chan is called to draw the connection of the horizontal routing resource channel; and according to the predecessor type of the node of the horizontal routing resource channel type, draw_chanx_to_chanx_edge, draw_chanx_to_chany_edge and draw_pin_to_chan_edge are called respectively to draw the connection between horizontal and horizontal routing resource channels, between horizontal and vertical routing resource channels, and between the input pin and the horizontal routing resource channel.

[0055] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0056] The analytical drawing method based on the resource model of commercial Xilinx Virtex-7 FPGA chip provided by this invention completes the data analysis work by analyzing the resources of EDA software at different design stages. It uses two effective drawing algorithms to complete the visualization of circuit layout view and circuit routing view, which meets the actual needs of researchers for Virtex-7 FPGA architecture design and related EDA algorithm research. Moreover, the overall running efficiency is relatively high and the resource consumption is low.

[0057] Other aspects and features of the invention will become apparent from the following detailed description with reference to the accompanying drawings. However, it should be understood that the drawings are for illustrative purposes only and not as a limitation of the scope of the invention, as reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale; they are merely intended to conceptually illustrate the structures and processes described herein. Attached Figure Description

[0058] Figure 1 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0059] Figure 2A schematic diagram of the apparatus corresponding to a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided in an embodiment of the present invention;

[0060] Figure 3 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0061] Figure 4 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0062] Figure 5 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0063] Figure 6 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0064] Figure 7 This is an overall view of a circuit layout network connection result obtained through step S4, as provided in an embodiment of the present invention.

[0065] Figure 8 Provided for embodiments of the present invention Figure 7 The corresponding magnified view;

[0066] Figure 9 A flowchart illustrating a method for parsing and drawing a resource model based on a commercial Xilinx Virtex-7 FPGA chip, provided for an embodiment of the present invention;

[0067] Figure 10 An overall view of a circuit wiring connection result obtained through step S6, provided in an embodiment of the present invention;

[0068] Figure 11 Provided for embodiments of the present invention Figure 10 The corresponding magnified view. Detailed Implementation

[0069] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0070] This invention pertains to auxiliary design software for FPGA chip resource models, specifically relating to the technical field of Virtex-7 FPGA architecture construction and electronic design automation (EDA) software. More particularly, it relates to a method for analytically drawing resource models based on commercial Xilinx Virtex-7 FPGA chips. This invention, by designing an analytical drawing method based on Virtex-7 FPGA chip resource models, can assist researchers in quickly verifying whether Virtex-7 FPGA architecture design and EDA algorithms meet expected results. This is of significant importance for the industrial and academic applications of commercial Virtex-7 FPGA chips. Furthermore, the method of this invention can efficiently and conveniently complete the visualization of digital circuit placement and routing views in Xilinx Virtex-7 FPGA chips, making EDA algorithm research for commercial Xilinx Virtex-7 FPGA architectures more complete and potentially applicable to industrial fields.

[0071] The technical solution of the present invention will be described in detail below through specific embodiments.

[0072] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for parsing and drawing resource models based on a commercial Xilinx Virtex-7 FPGA chip, provided as an embodiment of the present invention. The present invention provides a method for parsing and drawing resource models based on a commercial Xilinx Virtex-7 FPGA chip, which includes the following steps:

[0073] S1. Obtain Virtex-7 FPGA chip attribute information by parsing the .xml format Virtex-7 FPGA architecture file, and store the Virtex-7 FPGA chip attribute information in the first structure;

[0074] like Figure 2 As shown, this step can be completed using the Virtex-7 FPGA chip architecture analysis module. Specifically:

[0075] The Virtex-7 FPGA chip architecture parsing module embeds a Virtex-7 FPGA chip architecture parsing algorithm. First, it parses the Virtex-7 FPGA architecture file in .xml format to obtain attribute information such as the size, mesh location, netlist model primitives, devices, switches, general interconnect resources, special interconnect resources, physical tile blocks, and complex logic blocks of the Virtex-7 FPGA chip.

[0076] Then, the size and grid position are stored in the chip grid distribution grid structure;

[0077] The netlist model primitives, devices, switches, general-purpose wiring resources, and special-purpose wiring resources are stored in the chip architecture information t_arch structure;

[0078] Store physical tiles in a t_physical_tile_type structure of physical tile type;

[0079] Complex logic blocks are stored in a logic block type t_logic_block_type structure.

[0080] The structure contains global information, logic unit block information, and routing resource information of the Virtex-7 FPGA chip.

[0081] S2. By parsing the .NET format netlist circuit file, obtain the resource information of the netlist circuit file, and store the resource information of the netlist circuit file in the cluster netlist class;

[0082] This step can be accomplished by packaging and parsing the module, specifically:

[0083] This packaging and parsing module embeds a netlist circuit parsing algorithm after the packaging stage. By parsing the .NET format netlist circuit file, it obtains resource information such as the internal composition of physical logic blocks, the number of physical logic blocks, the input / output of physical logic blocks, and the clock of physical logic blocks in the netlist circuit file; and stores it in the cluster netlist clb_nlist class.

[0084] The clb_nlist class contains information such as the composition, size, and configuration of physical logical blocks.

[0085] S3. By parsing the .place format circuit layout file, obtain the resource information of the circuit layout file, and store the resource information of the circuit layout file in the second structure;

[0086] This step can be accomplished using the layout parsing module, specifically:

[0087] This layout parsing module embeds a circuit layout parsing algorithm after the layout stage. By parsing the .place format circuit layout file, it obtains the resource information of the circuit layout file. The resource information of the circuit layout file includes: the row and column coordinates of the logic unit block, the name of the logic unit block, the sub-blocks of the logic unit block, and the occupancy information of the logic unit block. The row and column coordinates of the logic unit block are stored in the layout position coordinate t_pl_loc structure, and the name of the logic unit block, the sub-blocks of the logic unit block, and the occupancy information of the logic unit block are stored in the matrix structure grid_blocks with the cluster block structure t_grid_blocks of the specific grid position as elements.

[0088] The t_pl_loc structure and grid_blocks contain information such as the composition, location, and configuration of logical unit blocks.

[0089] S4. Draw the Virtex-7 FPGA chip architecture, the layout of the circuit blocks, and the network connections based on the first structure, the cluster netlist class, and the second structure.

[0090] This step can be completed using the layout drawing visualization module, specifically:

[0091] This layout visualization module embeds Virtex-7 FPGA chip architecture drawing and circuit layout view drawing algorithms. It uses the first structure (including: grid structure, t_arch structure, t_physical_tile_type structure, t_logic_block_type structure), cluster netlist class, and second structure (including: layout position coordinate t_pl_loc structure, matrix structure grid_blocks) obtained in steps S1, S2 and S3 to complete the visualization of the layoutable block distribution and network connections of Virtex-7 FPGA chip architecture and circuit.

[0092] In one possible implementation, such as Figure 3 As shown, step S4 includes:

[0093] Step S4.1: Obtain drawing configuration properties, including: drawing font style, drawing text size, line style, and text alignment.

[0094] Step S4.2: Traverse the chip grid distribution data structure, ignoring non-starting Tile blocks at the current grid position.

[0095] Traverse the grid structure obtained in step S1, ignoring non-starting tile blocks at the current grid position.

[0096] Step S4.3: Based on the physical tile block type structure, cluster netlist class and matrix structure, obtain the type of each physical tile block, calculate the capacity of each physical tile block and determine whether the current physical tile block has child tiles.

[0097] Based on the t_physical_tile_type structure obtained in step S1, the clb_nlist class obtained in step S2, and the grid_blocks matrix structure obtained in step S3, the capacity of different physical tile block types, such as IOB, CLB, RAM, BUFG, etc., is calculated and it is determined whether they have sub-tile blocks.

[0098] Step S4.4: If the current physical tile block has child tiles, then traverse all child tiles of the current physical tile block and obtain the drawing algorithm for the child tile block corresponding to the child tile block;

[0099] If the current tile has child tiles, then traverse all child tiles of the tile and call the corresponding child tile drawing algorithm.

[0100] In one possible implementation, such as Figure 4 As shown, step S4.4 includes:

[0101] Step S4.4.1: If the layable block associated with the current grid position in the sub-tile is an invalid block, then exit the current traversal and re-execute the traversal process for the next physical tile.

[0102] Step S4.4.2: If the layable block associated with the current grid position in the sub-Tile block is a non-empty block, fill it with the first color and draw the block boundary outline as a solid line; if the layable block associated with the current grid position in the sub-Tile block is an empty block, fill it with the second color and draw the block boundary outline as a dashed line, wherein the first color is darker than the second color.

[0103] For example, if the layable block associated with the current grid position in the child tile is a non-empty block, indicating that the block is occupied, then fill it with a darker color and draw the block boundary outline as a solid line; otherwise, indicating that the block is not occupied, fill it with a lighter color and draw the block boundary outline as a dashed line with a ratio of 5:3.

[0104] Step S4.4.3: If the width and height offset of the chip grid distribution in the sub-Tile block are not 0, draw the block name text at the center of the layable block; if the width and height offset of the chip grid distribution in the sub-Tile block are 0, draw the block name text at a preset position at the bottom of the layable block.

[0105] If, within a sub-tile, the layable block associated with the current grid position is neither an empty block nor an invalid block (i.e., the width and height offsets of the chip grid distribution grid are not 0), then the block name text is drawn at the center of the layable block; if the width and height offsets of the chip grid distribution grid are 0, then the block name text is drawn at 1 / 4 of the distance from the bottom of the block.

[0106] Step S4.5: If the current physical tile block has no child tiles, ignore it and do not draw it.

[0107] If the current tile block has no child tiles, i.e., it is an empty space, a chip grid corner, or a tile block with empty capacity, it is ignored and not drawn.

[0108] In one embodiment, such as Figure 5 As shown, the above method also includes the following sub-steps:

[0109] Step S4.6: After receiving the network connection view display instruction, traverse the networks in the cluster netlist class and draw the network connection view according to the drawing layout network connection algorithm.

[0110] If the user clicks the network connection option, which means the network connection view of the circuit layout needs to be displayed, then the network in the clb_nlist class obtained in step S2 is traversed, and the network connection drawing algorithm is used.

[0111] In one embodiment, such as Figure 6 As shown, step S4.6 includes:

[0112] Step S4.6.1: Ignore networks that have not been wired or connected;

[0113] Step S4.6.2: Obtain the source block of the current network and calculate the center of the block bounding box;

[0114] Step S4.6.3: Traverse all receiver SINK blocks in the current network, obtain the SINK blocks that have pin connections with the current network, and calculate the center of the block bounding box;

[0115] Step S4.6.4: Draw a solid black line from the center of the bounding box of the SOURCE block to the center of the bounding boxes of all SINK blocks.

[0116] Step S4 is as follows:

[0117] A layout drawing visualization module is used to visualize the circuit layout view. This module utilizes a specially designed circuit layout view drawing algorithm to iterate through the chip grid, ignoring undrawable tiles, and drawing sub-tiles for different tile types. During sub-tile drawing, different processing methods are applied based on whether the layable block associated with the current grid position is non-empty. Specifically, methods such as `set_color`, `set_line_dash`, `fill_rectangle`, `draw_rectangle`, and `draw_text` are used to set the color, line dash style, draw the filled rectangle, draw the rectangle outline, and draw the text, respectively, to draw blocks laid out on the correct logic blocks. Occupied blocks are filled with a darker color and have a solid black outline, while unoccupied blocks are filled with a lighter color and have a dashed black outline. Finally, the block name text is drawn. Furthermore, the `draw_line` method is used to draw the interconnection relationship between the center coordinates of the source SOURE logic block and the receiver SINK logic block, represented by a solid black line.

[0118] like Figure 7 As shown, this is an overall view of a circuit layout network connection result obtained in step S4 of the method of this embodiment. Figure 8 As shown Figure 7 The corresponding magnified view.

[0119] S5. By parsing the .route format circuit routing file, obtain the resource information of the circuit routing file and store it in the trajectory vector of the linked storage structure with the routing backtracking structure as an element.

[0120] The resource information in the circuit routing file includes: network name and network routing start and end points, horizontal or vertical channels, input or output pins, and coordinates.

[0121] This step can be completed using the wiring analysis module, specifically:

[0122] This routing parsing module embeds a circuit routing parsing algorithm after the routing stage. By parsing the .route format circuit routing file, it obtains the network name and network routing start and end points, horizontal or vertical channels, input or output pins, coordinates, and other attributes from the circuit routing file, and stores them in the trace vector of the linked storage structure with the routing backtracking t_traceback structure as an element.

[0123] The trace vector contains information such as the location, structure, and resource configuration of network cabling.

[0124] S6. Based on the cluster netlist class, the resource information of the circuit routing file, and the preset routing resource diagram, draw the circuit routing connections and critical routing path delays.

[0125] The preset wiring resource diagram can be imported from external sources.

[0126] This step can be completed using the wiring diagram visualization module, specifically:

[0127] The wiring drawing visualization module embeds a circuit wiring view drawing algorithm. It uses the clb_nlist class obtained in step S2, the trace vector obtained in step S5, and the externally imported wiring resource graph to complete the visualization of the wiring connection, critical wiring path delay, and other views of the circuit.

[0128] In one embodiment, such as Figure 9 As shown, step S6 includes:

[0129] Step S6.1: Traverse the cluster netlist class, ignoring networks that have not been wired;

[0130] Iterate through the clb_nlist class obtained in step S2, ignoring networks that have not been wired.

[0131] Step S6.2: Based on the trajectory vector and the head node of the network to be routed in the trajectory vector, obtain the source node of the current network and assign it as the recursion starting point;

[0132] Based on the trace vector obtained in step S5, and according to the head node of the network to be routed in the trace vector, obtain the source node of the current network and assign it as the starting point of recursion.

[0133] Step S6.3: Traverse the routing resource nodes driven by the current source node and find the routing resource type of the routing resource node according to the preset routing resource graph;

[0134] Traverse the routing resource nodes rr_node driven by the current SOURCE node, and find the specific routing resource type rr_type of the node according to the routing resource graph rr_graph.

[0135] Step S6.4: Traverse different routing resource types to complete the drawing of routing resources.

[0136] Iterate through different routing resource types (rr_type) to complete the drawing of the routing resources.

[0137] Furthermore, the routing resource logic in step S6.4 is divided into output pin OPIN, input pin IPIN, horizontal routing resource channel CHANX, vertical routing resource channel CHANNY, source end SOURCE, and receiver end SINK according to type.

[0138] In one embodiment, step S6.4 includes:

[0139] If the node type is SOURCE / SINK, then draw the source and receiver ends of the wiring connection.

[0140] If the node type is output pin OPIN type, then call draw_rr_pin to draw the specific connection of the output pin;

[0141] If the node type is an input pin (IPIN), then call draw_rr_pin to draw the specific connection of the input pin; and determine whether the predecessor node of the node of the input pin type is an output pin type; if it is an output pin, then call draw_pin_to_pin to draw the connection from the output pin to the input pin; if it is not an output pin, then call draw_pin_to_chan_edge to draw the connection from the input pin to the horizontal / vertical routing resource channel.

[0142] If the node type is a vertical routing resource channel CHANY, then draw_rr_chan is called to draw the connection of the vertical routing resource channel; and according to the predecessor type of the node of the vertical routing resource channel type, draw_chanx_to_chany_edge, draw_chany_to_chany_edge, and draw_pin_to_chan_edge are called respectively to draw the connection between the horizontal and vertical routing resource channels, between the vertical and vertical routing resource channels, and between the input pin and the vertical routing resource channel;

[0143] If the node type is a horizontal routing resource channel (CHANX), then draw_rr_chan is called to draw the connections of the horizontal routing resource channel; and according to the predecessor type of the node of the horizontal routing resource channel type, draw_chanx_to_chanx_edge, draw_chanx_to_chany_edge, and draw_pin_to_chan_edge are called respectively to draw the connections between horizontal and horizontal routing resource channels, between horizontal and vertical routing resource channels, and between the input pin and the horizontal routing resource channel.

[0144] like Figure 10 The image shown is an overall view of a circuit wiring connection result obtained in step S6 of this embodiment. Figure 11 To and Figure 10 The corresponding magnified view.

[0145] Specifically, step S6 uses a routing visualization module to visualize the circuit routing view. This module utilizes a specialized circuit routing view drawing algorithm to iterate through the trace vectors and obtain the SOURCE nodes in each network. It then iterates through the nodes driven by the SOURCE nodes, uses the routing resource graph to obtain the specific node type of each node, and applies different processing methods to different nodes until the chain routing connection drawing starting from the SOURCE node is completed, represented by a solid black line.

[0146] The Virtex-7 FPGA chip architecture parsing module, packing parsing module, routing parsing module, and placement parsing module in the above embodiments can be referred to as resource parsing modules. Resource parsing modules are mainly used to read intermediate files such as netlists, packing, placement, and routing generated by EDA software at different design stages, parse the resource information of different files, and store them in the corresponding data structures.

[0147] The layout drawing visualization module and the routing drawing visualization module in the above embodiments can be referred to as drawing visualization modules. The drawing visualization modules are mainly based on the resource data dependencies provided by the resource parsing module, and use the drawing API library to complete the visualization of the final results of the layout and routing stages.

[0148] This invention provides a method for parsing and drawing resource models based on commercial Xilinx Virtex-7 FPGA chips. It involves the visualization of layout and routing stages in the FPGA EDA design flow. Specifically, during the FPGA EDA software operation, the Virtex-7 FPGA chip structure, packaged netlist circuit, circuit layout, and circuit routing information are reverse-analyzed through Virtex-7 FPGA chip architecture parsing module, packaging parsing module, layout parsing module, and routing parsing module. The layout drawing visualization module and routing drawing visualization module are then used to complete the visualization of the circuit layout and routing results, including details such as logic block distribution and interconnection.

[0149] This disclosure provides a method for parsing and drawing resource models based on commercial Xilinx Virtex-7 FPGA chips, including the following steps: S1, obtaining Virtex-7 FPGA chip attribute information by parsing a .xml format Virtex-7 FPGA architecture file, and storing the Virtex-7 FPGA chip attribute information in a first structure; S2, obtaining resource information of a .net format netlist circuit file by parsing a netlist circuit file, and storing the resource information of the netlist circuit file in a cluster netlist class; S3, obtaining resource information of a .place format circuit layout file by parsing a circuit layout file, and storing the resource information of the circuit layout file in a second structure; S4, drawing the Virtex-7 based on the first structure, the cluster netlist class, and the second structure. The system analyzes the FPGA chip architecture, the layout of circuit blocks, and network connections. Step 5 involves parsing the .route format circuit routing file to obtain its resource information and storing it in a linked storage structure trajectory vector with routing backtracking structures as elements. Step 6 involves drawing the circuit routing connections and critical routing path delays based on the cluster netlist class, the resource information of the circuit routing file, and the preset routing resource diagram. By parsing resources from different design stages of the EDA software, the system completes data parsing and utilizes two effective drawing algorithms to visualize the circuit layout and routing views. This meets the practical needs of researchers in Virtex-7 FPGA architecture design and related EDA algorithm research, and boasts high overall efficiency and low resource consumption.

[0150] Furthermore, the method in this invention is quickly invoked via Bash instructions, utilizing embedded resource parsing modules and visualization modules for different design stages to visualize the resource model of the Xilinx Virtex-7 FPGA chip. It can also display the placement and routing results of digital circuits within the Virtex-7 FPGA chip during the placement and routing design stages. The method of this invention achieves high overall operating efficiency and low resource consumption.

[0151] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0152] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0153] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for analytical drawing of resource models based on commercial Xilinx Virtex-7 FPGA chips, characterized in that, Includes the following steps: S1. By parsing the Virtex-7 FPGA architecture file in .xml format, the Virtex-7 FPGA chip attribute information is obtained, and the Virtex-7 FPGA chip attribute information is stored in a first structure; wherein, the Virtex-7 FPGA chip attribute information includes: size, mesh position, netlist model primitives, devices, switches, general interconnect resources, dedicated interconnect resources, physical tiles, and complex logic blocks; storing the Virtex-7 FPGA chip attribute information in the first structure includes: storing the size and mesh position in a chip mesh distribution data structure; storing the netlist model primitives, devices, switches, general interconnect resources, and dedicated interconnect resources in a chip architecture information structure; storing the physical tiles in a physical tile type structure; and storing the complex logic blocks in a logic block type structure; S2. By parsing the .NET format netlist circuit file, the resource information of the netlist circuit file is obtained, and the resource information of the netlist circuit file is stored in the cluster netlist class; S3. By parsing the .place format circuit layout file, the resource information of the circuit layout file is obtained, and the resource information of the circuit layout file is stored in the second structure; wherein, the resource information of the circuit layout file includes: the row and column coordinates of the logic unit block, the name of the logic unit block, the sub-blocks of the logic unit block, and the occupancy information of the logic unit block; storing the resource information of the circuit layout file in the second structure includes: storing the row and column coordinates of the logic unit block in the layout position coordinate structure; storing the name of the logic unit block, the sub-blocks of the logic unit block, and the occupancy information of the logic unit block in a matrix structure with cluster block structures at specific grid positions as elements; S4. Draw the Virtex-7 FPGA chip architecture, the layoutable block distribution of the circuit, and the network connections according to the first structure, the cluster netlist class, and the second structure; S4 includes: Step S4.1, obtaining drawing configuration attributes, including: drawing font style, drawing text size, line style, and text alignment; Step S4.2, traversing the chip grid distribution data structure, ignoring non-starting Tile blocks at the current grid position; Step S4.3, obtaining each physical Tile block type according to the physical Tile block type structure, the cluster netlist class, and the matrix structure, calculating the capacity of each physical Tile block, and determining whether the current physical Tile block has child Tile blocks; Step S4.4, if the current physical Tile block has child Tile blocks, traversing all child Tile blocks of the current physical Tile block, and obtaining the drawing algorithm for the child Tile block corresponding to the child Tile block; Step S4.5, if the current physical Tile block does not have child Tile blocks, ignoring them and not drawing them; S5. By parsing the .route format circuit routing file, obtain the resource information of the circuit routing file and store it in the trajectory vector of the linked storage structure with the routing backtracking structure as an element. S6. Based on the cluster netlist class, the resource information of the circuit routing file, and the preset routing resource diagram, draw the circuit routing connections and critical routing path delays; Step S6 includes: Step S6.1: Traverse the cluster netlist class, ignoring networks that have not been routed; Step S6.2: Based on the trajectory vector and the head node of the network to be routed in the trajectory vector, obtain the source node of the current network and assign it as the recursion starting point; Step S6.3: Traverse the routing resource nodes driven by the current source node, and find the routing resource type of the routing resource node according to the preset routing resource diagram; Step S6.4: Traverse different routing resource types to complete the drawing of the routing resources.

2. The analytical drawing method based on the resource model of a commercial Xilinx Virtex-7 FPGA chip according to claim 1, characterized in that, The resource information of the netlist circuit file includes: the internal composition of the physical logic block, the number of physical logic blocks, the inputs / outputs of the physical logic block, and the clock of the physical logic block. The resource information in the circuit routing file includes: network name and network routing start and end points, horizontal or vertical channels, input or output pins, and coordinates.

3. The analytical drawing method based on the resource model of a commercial Xilinx Virtex-7 FPGA chip according to claim 1, characterized in that, Step S4.4 includes: Step S4.4.1: If the layable block associated with the current grid position in the sub-Tile block is an invalid block, then exit the current traversal and re-execute the traversal process for the next physical Tile block. Step S4.4.2: If the layable block associated with the current grid position in the sub-Tile block is a non-empty block, then fill it with the first color and draw the block boundary outline as a solid line. If the layable block associated with the current grid position in the sub-Tile block is an empty block, then fill it with the second color and draw the block boundary outline as a dashed line, wherein the first color is darker than the second color; Step S4.4.3: If the width and height offset of the chip grid distribution in the sub-Tile block are not 0, then draw the block name text at the center of the layable block; If the width and height offset of the chip grid distribution in the sub-Tile block is 0, then the block name text is drawn at a preset position from the bottom of the layable block.

4. The analytical drawing method based on the resource model of a commercial Xilinx Virtex-7 FPGA chip according to claim 1, characterized in that, The method further includes: Step S4.6: After receiving the network connection view display instruction, the network in the cluster netlist class is traversed, and the network connection view is drawn according to the drawing layout network connection algorithm.

5. The analytical drawing method based on the resource model of a commercial Xilinx Virtex-7 FPGA chip according to claim 4, characterized in that, Step S4.6 includes: Step S4.6.1: Ignore networks that have not been wired or connected; Step S4.6.2: Obtain the source block of the current network and calculate the center of the block bounding box; Step S4.6.3: Traverse all receiver blocks in the current network, obtain receiver blocks that have pin connections with the current network, and calculate the center of the block bounding box; Step S4.6.4: Draw a solid black line from the center of the source block bounding box to the center of all receiver block bounding boxes.

6. The analytical drawing method based on the resource model of a commercial Xilinx Virtex-7 FPGA chip according to claim 1, characterized in that, Step S6.4 includes: If the node type is a source / receiver type, then draw the source and receiver of the wiring connection; If the node type is an output pin type, then call draw_rr_pin to draw the specific connection of the output pin; If the node type is an input pin type, then call draw_rr_pin to draw the specific connection of the input pin; and determine whether the predecessor node of the node of the input pin type is an output pin type; if it is an output pin, then call draw_pin_to_pin to draw the connection from the output pin to the input pin; if it is not an output pin, then call draw_pin_to_chan_edge to draw the connection from the input pin to the horizontal / vertical routing resource channel; If the node type is a vertical routing resource channel type, then draw_rr_chan is called to draw the connection of the vertical routing resource channel; and according to the predecessor type of the node of the vertical routing resource channel type, draw_chanx_to_chany_edge, draw_chany_to_chany_edge and draw_pin_to_chan_edge are called respectively to draw the connection between the horizontal and vertical routing resource channels, between the vertical and vertical routing resource channels, and between the input pin and the vertical routing resource channel; If the node type is a horizontal routing resource channel type, then draw_rr_chan is called to draw the connection of the horizontal routing resource channel; and according to the predecessor type of the node of the horizontal routing resource channel type, draw_chanx_to_chanx_edge, draw_chanx_to_chany_edge and draw_pin_to_chan_edge are called respectively to draw the connection between horizontal and horizontal routing resource channels, between horizontal and vertical routing resource channels, and between the input pin and the horizontal routing resource channel.

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