Pixel circuit and driving method thereof

Abstract

The present application provides a pixel circuit and a driving method thereof. The pixel circuit includes a driving circuit, a data writing circuit and a voltage adjuster. The driving circuit generates a driving current according to a light emitting control signal. The data writing circuit provides a data voltage to an input terminal according to a source driving signal. The voltage adjuster adjusts the voltage passing through a first control terminal and a second control terminal according to the light emitting control signal, the source driving signal and a previous stage source driving signal.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a pixel circuit and its driving method. Background Technology

[0002] In display devices, when the manufacturing process varies, the threshold voltage of the driving transistor in the pixel circuit is prone to drift, causing unexpected changes in the current flowing through the light-emitting element. This results in unstable brightness of the display panel, affecting the quality of the displayed image.

[0003] On the other hand, the driving circuit in the pixel circuit is also susceptible to the line resistance of the transmission path, which causes the terminal voltage of each pixel to be different, and thus causes the current flowing through the light-emitting element in each pixel to be inaccurate.

[0004] Therefore, how to mitigate the impact of process variations in pixel circuits and effectively reduce their power consumption to improve display quality will be an important topic for those skilled in the art. Summary of the Invention

[0005] The present invention provides a pixel circuit that can compensate for the critical voltage of the driving transistor through timing control and effectively reduce the power consumption of the pixel circuit, thereby improving the quality of the display image.

[0006] The pixel circuit of the present invention includes a driving circuit, a data writing circuit, and a voltage regulator. The driving circuit generates a driving current based on a light emission control signal. The data writing circuit has an input terminal, is coupled to the driving circuit, and provides a data voltage to the input terminal based on a source drive signal. The voltage regulator has a first control terminal and a second control terminal, is coupled to the driving circuit and the data writing circuit, and adjusts the voltage passing through the first control terminal and the second control terminal based on the light emission control signal, the source drive signal, and the previous stage source drive signal.

[0007] The pixel circuit driving method of the present invention includes: providing a driving circuit to generate a driving current according to a light emission control signal; providing a data writing circuit having an input terminal, and causing the data writing circuit to provide a data voltage to the input terminal according to a source drive signal; and providing a voltage regulator having a first control terminal and a second control terminal, and causing the voltage regulator to adjust the voltage passing through the first control terminal and the second control terminal according to the light emission control signal, the source drive signal and the previous stage source drive signal.

[0008] Based on the above, the pixel circuit described in the embodiments of the present invention can compensate for the critical voltage of the driving transistor through timing control, and make the magnitude of the driving current independent of the critical voltage of the driving transistor, the system high voltage, and the system low voltage. In this way, the pixel circuit of the present invention can effectively eliminate the offset of the critical voltage of the driving transistor caused by process variations, and the driving current is less susceptible to errors caused by the line resistance in the paths of system high voltage and system low voltage. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0010] Figure 2 According to the present invention Figure 1 Timing diagram of the pixel circuit in the embodiment.

[0011] Figures 3A to 3C According to the present invention Figure 1 Equivalent circuit diagrams of the pixel circuit in the embodiment at various stages of operation.

[0012] Figure 4 This is a flowchart of a pixel circuit driving method according to an embodiment of the present invention.

[0013] In the attached figures, the following labels are used:

[0014] 100: Pixel Circuit

[0015] 110: Drive circuit

[0016] 120: Data writing circuit

[0017] 130: Voltage Regulator

[0018] AT: Test signal

[0019] C1: Capacitor

[0020] CT1, CT2: Control Terminal

[0021] CDP: Compensation and Data Writing Phase

[0022] EM: Light emission control signal

[0023] EP: Luminescent Stage

[0024] ID: Drive Current

[0025] LED: Light-emitting element

[0026] PIN: Input terminal

[0027] RP: Reset Phase

[0028] SN: Source drive signal

[0029] SN-1: Pre-amplifier source drive signal

[0030] S410~S430: Steps

[0031] T1~T9: Transistors

[0032] TFR: Pixel Period

[0033] VDATA: Data Voltage

[0034] VDD: System high voltage

[0035] VSS: System Low Voltage

[0036] VREF1, VREF2: Reference voltages Detailed Implementation

[0037] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0038] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or some means of connection. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terminology in different embodiments may be referred to mutually in the relevant descriptions.

[0039] Figure 1 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the pixel circuit 100 includes a driving circuit 110, a data writing circuit 120, and a voltage regulator 130. The driving circuit 110 includes a light-emitting element (LED) and transistors T1 and T2. The anode of the LED is coupled to the system high voltage VDD. The first terminal of transistor T1 is coupled to the cathode of the LED, and the second terminal of transistor T1 is coupled to the control terminal CT2 of the voltage regulator 130. The control terminal of transistor T1 receives a light-emitting control signal EM. The first terminal of transistor T2 is coupled to the data voltage VDATA, and the second terminal of transistor T2 is coupled to the cathode of the LED. The control terminal of transistor T2 receives a test signal AT.

[0040] Specifically, in this embodiment, when the pixel circuit 100 is operating in the testing phase (i.e., when the pixel circuit 100 is not equipped with the light-emitting element LED), the transistor T2 of the driving circuit 110 can receive the enabled test signal AT (e.g., low voltage passing) and be turned on according to the test signal AT. In this case, during the testing phase, the pixel circuit 100 can provide a data voltage VDATA to the pixel circuit 100 by controlling the timing state of the light-emitting control signal EM, the source drive signal SN, and the previous stage source drive signal SN-1 to detect the current state of each path and thereby test whether the operation of the pixel circuit 100 is normal.

[0041] Next, when the pixel circuit 100 operates in the operation phase after the test phase (i.e., when the pixel circuit 100 is equipped with a light-emitting element LED), the transistor T2 of the driving circuit 110 can receive a disabled test signal AT (e.g., high voltage passing through) and be turned off according to the test signal AT. During the operation phase, the transistor T1 of the driving circuit 110 can provide a drive current ID according to the light-emitting control signal, and correspondingly illuminate the light-emitting element LED. In this embodiment, the light-emitting element LED can be, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), or other miniature light-emitting elements; the present invention is not particularly limited in this regard.

[0042] Data writing circuit 120 is coupled to drive circuit 110. Data writing circuit 120 has an input terminal PIN. Data writing circuit 120 can provide data voltage VDATA to input terminal PIN according to source drive signal SN. In this embodiment, data writing circuit 120 includes capacitor C1 and transistors T3 and T4. Capacitor C1 is coupled between input terminal PIN and drive circuit 110. A first terminal of transistor T3 is coupled to system low voltage VSS, a second terminal of transistor T3 is coupled to input terminal PIN, and the control terminal of transistor T3 receives source drive signal SN-1 from the previous stage. A first terminal of transistor T4 is coupled to data voltage VDATA, a second terminal of transistor T4 is coupled to input terminal PIN, and the control terminal of transistor T4 receives source drive signal SN.

[0043] On the other hand, voltage regulator 130 is coupled to drive circuit 110 and data writing circuit 120. Voltage regulator 130 has control terminals CT1 and CT2. Voltage regulator 130 can adjust the voltage passing through control terminals CT1 and CT2 according to the light emission control signal EM, source drive signal SN, and the previous stage source drive signal SN-1.

[0044] The voltage regulator 130 includes transistors T5 to T9. The first terminal of transistor T5 is coupled to the input terminal PIN, and the second terminal of transistor T5 is coupled to the control terminal CT1. The control terminal of transistor T5 receives the light emission control signal EM. The first terminal of transistor T6 is coupled to the reference voltage VREF2, and the second terminal of transistor T6 is coupled to the control terminal CT1. The control terminal of transistor T6 receives the source drive signal SN-1 from the preceding stage. The first terminal of transistor T7 is coupled to the reference voltage VREF1, and the second terminal of transistor T7 is coupled to the control terminal CT1. The control terminal of transistor T7 receives the source drive signal SN.

[0045] The first terminal of transistor T8 (e.g., a driver transistor) is coupled to the system low voltage VSS, the second terminal of transistor T8 is coupled to the control terminal CT2, and the control terminal of transistor T8 is coupled to the control terminal CT1. The first terminal of transistor T9 is coupled to the reference voltage VREF2, the second terminal of transistor T9 is coupled to the control terminal CT2, and the control terminal of transistor T9 receives the source drive signal SN-1 from the preceding stage.

[0046] It is worth mentioning that in the design of transistors T1 to T9, transistors T1 to T9 in this embodiment can be P-type transistors, but this embodiment of the invention is not limited to this. Furthermore, in the design of the system high voltage VDD, system low voltage VSS, reference voltage VREF1, and reference voltage VREF2, the voltage values ​​of each voltage, from largest to smallest, can be in the following order: reference voltage VREF2, system high voltage VDD, reference voltage VREF1, and system low voltage VSS.

[0047] Figure 2 According to the present invention Figure 1 Timing diagram of the pixel circuit in the embodiment. Please refer to... Figure 2 In this embodiment, a pixel period TFR of the pixel circuit 100 can be divided into a reset phase RP, a compensation and data writing phase CDP, and an emission phase EP. The pixel circuit 100 can operate sequentially in the reset phase RP, the compensation and data writing phase CDP, and the emission phase EP. The reset phase RP, the compensation and data writing phase CDP, and the emission phase EP do not overlap with each other.

[0048] For implementation details of pixel circuit 100, please also refer to... Figure 2 as well as Figures 3A to 3C , Figures 3A to 3C According to the present invention Figure 1 The equivalent circuit diagram of the pixel circuit 100 in the embodiment during various stages of operation is shown. It should be noted that, for ease of illustration, [the diagram is omitted here]. Figures 3A to 3C A transistor that is off is indicated by an "X", while a transistor that is on is indicated by no "X".

[0049] Please refer to the following at the same time Figure 2 as well as Figure 3A In this embodiment, Figure 3A This is an equivalent circuit diagram of the pixel circuit 100 during the reset phase RP. Specifically, during the reset phase RP, the source drive signal SN and the light emission control signal EM can be set to pass at high voltage, while the preceding source drive signal SN-1 can be set to pass at low voltage.

[0050] In detail, during the reset phase RP, the data writing circuit 120 can provide the system low voltage VSS to the input terminal PIN through the conduction path of transistor T3 according to the pulled-down pre-stage source drive signal SN-1, so that the voltage of the input terminal PIN is correspondingly pulled down to the voltage value equal to the system low voltage VSS.

[0051] Next, voltage regulator 130 can provide a reference voltage VREF2 to control terminal CT1 through the conduction path of transistor T6 based on the pulled-down source drive signal SN-1 of the preceding stage. Furthermore, voltage regulator 130 can provide a reference voltage VREF2 to control terminal CT2 through the conduction path of transistor T9 based on the pulled-down source drive signal SN-1 of the preceding stage. In this case, voltage regulator 130 can adjust the voltages of control terminals CT1 and CT2 accordingly to be equal to the reference voltage VREF2.

[0052] After completing the reset of each node, please refer to the following: Figure 2 as well as Figure 3B In this embodiment, Figure 3B This is an equivalent circuit diagram of the pixel circuit 100 during the compensation and data writing phase (CDP). Specifically, during the compensation and data writing phase (CDP), the front-end source drive signal SN-1 and the light emission control signal EM can be set to pass at high voltage, while the source drive signal SN can be set to pass at low voltage.

[0053] In detail, during the compensation and data writing stage CDP, the data writing circuit 120 can provide the data voltage VDATA to the input terminal PIN through the conduction path of the transistor T4 according to the pulled-down source drive signal SN, so that the voltage of the input terminal PIN is pulled up to the voltage value of the data voltage VDATA.

[0054] Next, the voltage regulator 130 can provide a reference voltage VREF1 to the control terminal CT1 through the conduction path of the transistor T7 according to the pulled-down source drive signal SN, so that the voltage of the control terminal CT1 is pulled down to the reference voltage VREF1.

[0055] It is worth mentioning that, since the reference voltage VREF1 in this embodiment is designed to be lower than the reference voltage VREF2, at least one threshold voltage VTH8 of transistor T8, transistor T8 of voltage regulator 130 can be turned on according to the voltage of control terminal CT1, and the voltage of control terminal CT2 is pulled down to the voltage difference between the reference voltage VREF1 and the threshold voltage VTH8 of transistor T8 (i.e., VREF1-|VTH8|).

[0056] Please refer to the following at the same time Figure 2 as well as Figure 3C In this embodiment, Figure 3C This is an equivalent circuit diagram of the pixel circuit 100 during the light-emitting stage EP. Specifically, during the light-emitting stage EP, the source drive signal SN and the preceding source drive signal SN-1 can be set to pass at high voltage, while the light-emitting control signal EM can be set to pass at low voltage.

[0057] In detail, during the light-emitting stage EP, the transistor T8 (e.g., a driving transistor) of the voltage regulator 130 generates a driving current ID based on the voltage state of the control terminal CT1, and the driving circuit 110 illuminates the light-emitting element LED through the conduction path of the transistor T1 based on the pulled-down light-emitting control signal EM and the driving current ID. In this case, the voltage regulator 130 can make the voltage of the control terminal CT2 equal to the voltage difference between the voltage value pulled down to the system high voltage VDD and the voltage value of the LED's on-state voltage VLED (i.e., VDD-VLED).

[0058] On the other hand, voltage regulator 130 can interconnect the input terminal PIN and the control terminal CT1 through the conduction path of transistor T5 based on the pulled-down light emission control signal EM. Then, based on the coupling effect of capacitor C1 and the voltage state of input terminal PIN and control terminal CT1 during the compensation and data writing phase CDP, voltage regulator 130 can further pull down the voltage of input terminal PIN and control terminal CT1 to the voltage value of VDATA+(VDD-VLED)-(VREF1-VTH8).

[0059] Therefore, when the pixel circuit 100 operates in the light-emitting stage TP and the transistor T8 operates in the saturation region, the transistor T8 can generate a drive current ID. At this time, the drive current ID flowing through the light-emitting element LED can be expressed as follows:

[0060] ID = K(VDATA-VREF1)^2

[0061] Wherein, ID is the current value of the drive current ID; K is the process parameter of transistor T8; VDATA is the voltage value of the data voltage VDATA; and VREF1 is the voltage value of the reference voltage VREF1.

[0062] As can be seen from the above description, in the light-emitting stage EP, since the driving current ID generated by the pixel circuit 100 is independent of the threshold voltage VTH8 of transistor T8, the system high voltage VDD, and the system low voltage VSS, the pixel circuit 100 can effectively eliminate the offset of the threshold voltage of transistor T8 caused by process variations, and the driving current ID is less likely to be affected by the line resistance in the path of system high voltage VDD and system low voltage VSS and thus cause errors.

[0063] In addition, since a transistor T1 controlled by the light-emitting control signal EM is disposed between the light-emitting element LED and the transistor T8 of the pixel circuit 100, the pixel circuit 100 of this embodiment can effectively perform multi-pulse operation to improve the uniformity of the displayed image.

[0064] Therefore, the pixel circuit 100 of this embodiment can compensate for the critical voltage of the driving transistor through timing control, and effectively reduce the power consumption of the pixel circuit 100, thereby improving the quality of the display screen.

[0065] Figure 4 This is a flowchart of a pixel circuit driving method according to an embodiment of the present invention. Please also refer to... Figure 1 as well as Figure 4 In step S410, the pixel circuit provides a driving circuit to generate a driving current according to the light emission control signal. In step S420, the pixel circuit provides a data writing circuit with an input terminal, and the data writing circuit provides a data voltage to the input terminal according to the source drive signal. In step S430, the pixel circuit provides a voltage regulator with a first control terminal and a second control terminal, and the voltage regulator adjusts the voltage passing through the first control terminal and the second control terminal according to the light emission control signal, the source drive signal, and the previous stage source drive signal.

[0066] The implementation details of each step are explained in detail in the foregoing embodiments and implementation methods, and will not be repeated here.

[0067] In summary, the pixel circuit described in the embodiments of the present invention can compensate for the critical voltage of the driving transistor through timing control, and make the magnitude of the driving current independent of the critical voltage of the driving transistor, the system high voltage, and the system low voltage. In this way, the pixel circuit of the present invention can effectively eliminate the offset of the critical voltage of the driving transistor caused by process variations, and the driving current is less susceptible to errors caused by the line resistance in the paths of system high voltage and system low voltage.

[0068] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: A driving circuit generates a driving current based on a light emission control signal; A data writing circuit has an input terminal, the data writing circuit being coupled to the driving circuit, and providing a data voltage to the input terminal according to a source drive signal; and A voltage regulator has a first control terminal and a second control terminal. The voltage regulator is coupled to the driving circuit and the data writing circuit, and adjusts the voltage of the first control terminal and the second control terminal according to the light emission control signal, the source drive signal and a pre-stage source drive signal. The voltage regulator includes: A first transistor, the first terminal of which is coupled to the input terminal, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the light emission control signal; A second transistor, the first terminal of which is coupled to a second reference voltage, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the source drive signal of the preceding stage; A third transistor, the first terminal of which is coupled to a first reference voltage, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the source drive signal; A fourth transistor, wherein a first terminal is coupled to a system low voltage, a second terminal is coupled to the second control terminal, and the control terminal is coupled to the first control terminal; and A fifth transistor, the first terminal of which is coupled to the second reference voltage, and the second terminal of which is coupled to the second control terminal, the control terminal receiving the source drive signal of the preceding stage.

2. The pixel circuit as described in claim 1, characterized in that, During a reset phase, the data writing circuit provides a system low voltage to the input terminal based on the pulled-down source drive signal of the preamplifier, and the voltage regulator provides a second reference voltage to the first control terminal and the second control terminal based on the pulled-down source drive signal of the preamplifier.

3. The pixel circuit as described in claim 1, characterized in that, During a compensation and data writing phase, the data writing circuit provides the data voltage to the input terminal based on the pulled-down source drive signal, and the voltage regulator provides a first reference voltage to the first control terminal and the second control terminal based on the pulled-down source drive signal, so as to pull down the voltage of the first control terminal and the second control terminal.

4. The pixel circuit as described in claim 1, characterized in that, During a light-emitting phase, the voltage regulator pulls down the voltage of the input terminal, the first control terminal, and the second control terminal according to the pulled-down light-emitting control signal, and the driving circuit generates the driving current according to the pulled-down light-emitting control signal.

5. The pixel circuit as described in claim 1, characterized in that, The driving circuit includes: A light-emitting element, the anode of which is coupled to a system high voltage; and A first transistor has a first terminal coupled to the cathode of the light-emitting element and a second terminal coupled to the second control terminal, which receives the light-emitting control signal.

6. The pixel circuit as described in claim 1, characterized in that, The data writing circuit includes: A first transistor, the first terminal of which is coupled to a system low voltage, the second terminal of which is coupled to the input terminal, and the control terminal of which receives the source drive signal of the preceding stage; A second transistor, the first terminal of which is coupled to the data voltage, the second terminal of which is coupled to the input terminal, and the control terminal of which receives the source drive signal; and A capacitor is coupled between the input terminal and the second control terminal.

7. A driving method for a pixel circuit, characterized in that, include: A driving circuit is provided to generate a driving current based on a light emission control signal; Provide a data writing circuit having an input terminal, and provide a data voltage to the input terminal according to a source drive signal; and A voltage regulator is provided having a first control terminal and a second control terminal, and the voltage regulator is configured to adjust the voltage passing through the first control terminal and the second control terminal according to the light emission control signal, the source drive signal and a pre-stage source drive signal; The voltage regulator includes: A first transistor, the first terminal of which is coupled to the input terminal, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the light emission control signal; A second transistor, the first terminal of which is coupled to a second reference voltage, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the source drive signal of the preceding stage; A third transistor, the first terminal of which is coupled to a first reference voltage, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the source drive signal; A fourth transistor, wherein a first terminal is coupled to a system low voltage, a second terminal is coupled to the second control terminal, and the control terminal is coupled to the first control terminal; and A fifth transistor, the first terminal of which is coupled to the second reference voltage, and the second terminal of which is coupled to the second control terminal, the control terminal receiving the source drive signal of the preceding stage.

8. The driving method as described in claim 7, characterized in that, Including: During a reset phase, the data writing circuit provides a system low voltage to the input terminal based on the pulled-down source drive signal of the preamplifier, and the voltage regulator provides a second reference voltage to the first control terminal and the second control terminal based on the pulled-down source drive signal of the preamplifier.

9. The driving method as described in claim 7, characterized in that, Including: During a compensation and data writing phase, the data writing circuit provides the data voltage to the input terminal based on the pulled-down source drive signal, and the voltage regulator provides a first reference voltage to the first control terminal and the second control terminal based on the pulled-down source drive signal, so as to pull down the voltage of the first control terminal and the second control terminal.

10. The driving method as described in claim 7, characterized in that, Including: During a light-emitting stage, the voltage regulator pulls down the voltage of the input terminal, the first control terminal, and the second control terminal according to the pulled-down light-emitting control signal, and the driving circuit generates the driving current according to the pulled-down light-emitting control signal.

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