DRAM command tailing efficiency management

Abstract

The present invention provides a memory controller including a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter processes tailing of consecutive read commands and tailing of consecutive write commands. The arbiter processes tailing of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbiter. After the minimum burst length, the arbiter decides to start a new command tailing of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

Description

Background Art

[0001] Computer systems typically use inexpensive and high-density dynamic random access memory (DRAM) chips as main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards issued by the Joint Electron Device Engineering Council (JEDEC). DDR DRAM uses a conventional DRAM memory cell array with high-speed access circuits to achieve high transfer rates and improve the utilization of the memory bus.

[0002] A typical DDR memory controller maintains a queue to store pending read and write requests to allow the memory controller to pick up these pending requests out of order and thereby improve efficiency. For example, the memory controller can retrieve multiple memory access requests for the same row in a given storage column out of order from the queue (called a "page hit"), and issue the multiple memory access requests to the memory system continuously to avoid the overhead of repeatedly precharging the current row and activating another row. However, while utilizing the bus bandwidth provided by modern memory technologies (such as DDR5), scanning and picking up accesses from deep queues becomes difficult to implement using known memory controllers. The memory controller can use techniques such as generating tails of read commands or write commands to improve bus efficiency. However, such techniques are accompanied by performance tradeoffs, such as latency issues caused by delaying commands that are not part of the current tail, and additional performance overhead associated with "turning over" the command bus from the read tail to the write tail (and vice versa). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An accelerated processing unit (APU) and a memory system known in the prior art are shown in block diagram form;

[0004] Figure 2 A block diagram is shown in accordance with some embodiments suitable for use in a similar Figure 1 A memory controller used in an APU of an APU;

[0005] Figure 3 According to some embodiments, Figure 2 A block diagram of a portion of a memory controller;

[0006] Figure 4 is a flow chart of a process for managing tailing efficiency according to some embodiments; and

[0007] Figure 5 is a flow chart of another process for managing tailing efficiency according to some additional embodiments.

[0008] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0009] A memory controller includes a command queue having a first input for receiving a memory access request, and a memory interface queue having an output for coupling to a memory channel suitable for connecting to at least one dynamic random access memory (DRAM). An arbitrator is connected to the command queue for selecting entries from the command queue and placing the entries in the memory interface queue so that the entries are transmitted through the memory channel. The arbitrator is operable to process the tailing of continuous read commands and the tailing of continuous write commands through the memory channel. The arbitrator is operable to process the tailing of at least a minimum burst length based on a plurality of commands of a specified type that can be selected by the arbitrator. After the minimum burst length, the arbitrator is operable to decide to start a new command tailing of a different type based on a first set of one or more conditions indicating efficiency within the burst.

[0010] The method includes causing tailing of consecutive read commands and tailing of consecutive write commands to be processed by a memory channel. The method includes the arbitrator processing tailing of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbitrator. After the minimum burst length, the method includes deciding to start a new command tailing of a different type based on a first set of one or more conditions indicative of intra-burst efficiency.

[0011] A data processing system includes a central processing unit, a data fabric connected to the central processing unit, and a memory controller connected to the data fabric for fulfilling memory requests from the central processing unit. The memory controller includes: a command queue having a first input for receiving a memory access request; and a memory interface queue having an output for coupling to a memory channel, the memory channel being adapted to be connected to at least one DRAM. An arbiter is connected to the command queue for selecting entries from the command queue and placing the entries in the memory interface queue so that the entries are transmitted through the memory channel. The arbiter is operable to process tailing of consecutive read commands and tailing of consecutive write commands through the memory channel. The arbiter is operable to process tailing of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbiter. After the minimum burst length, the arbiter is operable to decide to start a new command tailing of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

[0012] Figure 1 An accelerated processing unit (APU) 100 and a memory system 130, known in the art, are shown in block diagram form. The APU 100 is an integrated circuit suitable for use as a processor in a host data processing system and generally includes a central processing unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a memory management hub 140, a data fabric 125, a set of peripheral controllers 160, a set of peripheral bus controllers 170, and a system management unit (SMU) 180.

[0013] The CPU core complex 110 includes a CPU core 112 and a CPU core 114. In this example, the CPU core complex 110 includes two CPU cores, but in other embodiments, the CPU core complex 110 may include any number of CPU cores. Each of the CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN) (which forms a control fabric) and a data fabric 125, and can provide memory access requests to the data fabric 125. Each of the CPU cores 112 and 114 can be a unitary core, or can also be a core complex with two or more unitary cores that share certain resources such as a cache.

[0014] The graphics core 120 is a high-performance graphics processing unit (GPU) that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. The graphics core 120 is bidirectionally connected to the SMN and the data texture 125, and can provide memory access requests to the data texture 125. In this regard, the APU 100 may support a unified memory architecture in which the CPU core complex 110 and the graphics core 120 share the same memory space, or a memory architecture in which the CPU core complex 110 and the graphics core 120 share a portion of the memory space while the graphics core 120 also uses a private graphics memory that the CPU core complex 110 cannot access.

[0015] The display engine 122 renders and rasterizes objects generated by the graphics core 120 for display on the monitor. The graphics core 120 and the display engine 122 are bidirectionally connected to a common memory management hub 140 for unified translation to the appropriate addresses in the memory system 130, and the memory management hub 140 is bidirectionally connected to the data fabric 125 for generating such memory accesses and receiving read data returned from the memory system.

[0016] The data fabric 125 includes a crossbar switch for routing memory access requests and memory responses between any memory access agents and the memory management hub 140. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) for determining the destination of memory accesses based on the system configuration, and a buffer for each virtual connection.

[0017] Peripheral controllers 160 include a Universal Serial Bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to a system hub 166 and the SMN bus. These two controllers are merely examples of peripheral controllers that may be used with APU 100.

[0018] The peripheral bus controller 170 includes a system controller or "South Bridge" (SB) 172 and a peripheral component interconnect express (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. The I / O hub 176 is also bidirectionally connected to the system hub 166 and the data texture 125. Thus, for example, the CPU core can program registers in the USB controller 162, the SATA interface controller 164, the SB 172, or the PCIe controller 174 through accesses routed through the I / O hub 176 through the data texture 125. The software and firmware of the APU 100 are stored in a system data drive or system BIOS memory (not shown), which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), etc. Typically, the BIOS memory is accessed through the PCIe bus, and the system data drive is through the SATA interface.

[0019] The SMU 180 is a local controller that controls the operation of resources on the APU 100 and synchronizes communications between these resources. The SMU 180 manages the power-up sequencing of the various processors on the APU 100 and controls a number of off-chip devices via reset, enable, and other signals. The SMU 180 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals to each component of the APU 100. The SMU 180 also manages the power of the various processors and other functional blocks, and may receive measured power consumption values ​​from the CPU cores 112 and 114 and the graphics core 120 to determine the appropriate power state.

[0020] In this embodiment, the memory management hub 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with the APU 100. The memory management hub 140 includes memory channels 141 and 142 and a power engine 149. The memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147. The host interface 145 connects the memory channel controller 143 bidirectionally to the data texture 125 via a serial presence detection link (SDP). The physical interface 147 connects the memory channel controller 143 bidirectionally to the PHY 151 and conforms to the DDR PHY interface (DFI) specification in an exemplary embodiment. The memory channel 142 includes a host interface 146, a memory channel controller 144, and a physical interface 148. The host interface 146 connects the memory channel controller 144 bidirectionally to the data texture 125 via another SDP. The physical interface 148 connects the memory channel controller 144 bidirectionally to the PHY 152 and conforms to the DFI specification. Power engine 149 is bidirectionally connected to SMU 180 via the SMN bus, to PHY 151 and PHY 152 via APB, and also bidirectionally connected to memory channel controllers 143 and 144. PHY 151 has a bidirectional connection to memory channel 131. PHY 152 has a bidirectional connection to memory channel 133.

[0021] The memory management hub 140 is an instantiation of a memory controller having two memory channel controllers, and uses a shared power engine 149 to control the operation of both memory channel controller 143 and memory channel controller 144 in a manner that will be further described below. Each of the memory channels 141 and 142 can be connected to prior art DDR memories, such as fifth generation DDR (DDR5), fourth generation DDR (DDR4), low power DDR4 (LPDDR4), fifth generation graphics DDR (GDDR5), and high bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptops, and also provide built-in thermal monitoring.

[0022] Memory system 130 includes memory channel 131 and memory channel 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs) connected to DDRx bus 132, including representative DIMMs 134, 136, and 138, which correspond to separate memory ranks in this example. Similarly, memory channel 133 includes a set of DIMMs connected to DDRx bus 129, including representative DIMMs 135, 137, and 139.

[0023] The APU 100 operates as the central processing unit (CPU) of the host data processing system and provides various buses and interfaces available in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connecting to a PCIe link, a USB controller for connecting to a USB network, and an interface to a SATA mass storage device.

[0024] APU 100 also implements various system monitoring and power saving functions. Specifically, one system monitoring function is thermal monitoring. For example, if APU 100 becomes hot, SMU 180 may reduce the frequency and voltage of CPU cores 112 and 114 and / or graphics core 120. If APU 100 becomes overheated, it may be shut down completely. SMU 180 may also receive thermal events from external sensors via the SMN bus, and in response, SMU 180 may reduce the clock frequency and / or the power supply voltage.

[0025] Figure 2 The block diagram shows a suitable Figure 1 The memory controller 200 used in the APU of the APU of the present invention. The memory controller 200 generally includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 generally includes an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, a replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and a refresh logic 247.

[0026] The interface 212 has a first bidirectional connection to the data fabric 125 through an external bus and has an output. In the memory controller 200, the external bus is compatible with the Advanced eXtensible Interface version four (referred to as AXI4) specified by ARM Holdings, PLC of Cambridge, England, but may be other types of interfaces in other embodiments. The interface 212 converts memory access requests from a first clock domain referred to as the FCLK (or MEMCLK) domain to a second clock domain internal to the memory controller 200 referred to as the UCLK domain. Similarly, the memory interface queue 214 provides memory access from the UCLK domain to the DFICLK domain associated with the DFI interface.

[0027] The address generator 222 decodes the address of the memory access request received from the data texture 125 via the AXI4 bus. The memory access request includes an access address represented in a normalized format in the physical address space. The address generator 222 converts the normalized address into a format that can be used to address the actual memory device in the memory system 130 and efficiently schedule the related access. The format includes a region identifier that associates the memory access request with a specific storage column, row address, column address, storage body address, and storage body group. At startup, the system BIOS queries the memory devices in the memory system 130 to determine their size and configuration, and programs a set of configuration registers associated with the address generator 222. The address generator 222 uses the configuration stored in the configuration register to convert the normalized address into the appropriate format. The command queue 220 is a queue of memory access requests received from memory access agents in the APU 100, such as the CPU cores 112 and 114 and the graphics core 120. Command queue 220 stores address fields decoded by address generator 222 and other address information, including access type and quality of service (QoS) identification, that allows arbiter 238 to efficiently select memory accesses. CAM 224 includes information to implement ordering rules such as write-after-write (WAW) and read-after-write (RAW) ordering rules.

[0028] Error correction code (ECC) generation block 244 determines the ECC of the write data to be sent to the memory. ECC check circuit 242 checks the received ECC against the incoming ECC.

[0029] The replay queue 230 is a temporary queue for storing selected memory accesses selected by the arbiter 238, which are awaiting responses, such as address and command parity responses. The replay control logic 231 accesses the ECC check circuit 242 to determine whether the returned ECC is correct or indicates an error. The replay control logic 231 initiates and controls a replay sequence in which the access is replayed if a parity error or ECC error occurs in one of these cycles. The replayed commands are placed in the memory interface queue 214.

[0030] The refresh control logic 232 includes a state machine for various power-down, refresh and terminal resistance (ZQ) calibration cycles, which are generated separately from the normal read and write memory access requests received from the memory access agent. For example, if the memory storage column is in pre-charge power-down, the memory storage column must be periodically awakened to run the refresh cycle. The refresh control logic 232 generates refresh commands periodically and in response to specified conditions to prevent data errors caused by charge leakage from the storage capacitor of the memory cell in the DRAM chip. The refresh control logic 232 includes an activation counter 248, which has a counter for each memory area in this embodiment, and the counter counts the rolling number of activation commands sent to the memory area through the memory channel. The storage area is a memory storage body in some embodiments, and a memory sub-storage body in other embodiments, as discussed further below. In addition, the refresh control logic 232 periodically calibrates the ZQ to prevent mismatches of on-chip terminal resistances caused by thermal changes in the system.

[0031] The arbiter 238 is bidirectionally connected to the command queue 220 and is the heart of the memory channel controller 210 and improves the use of the memory bus by intelligently scheduling accesses to increase efficiency. The arbiter 238 uses the timing block 234 to enforce correct timing relationships by determining whether certain accesses in the command queue 220 are eligible to be issued based on DRAM timing parameters. For example, each DRAM has a minimum specified time between activation commands, called "t RC ". The timing block 234 maintains a set of counters that determine eligibility based on the timing parameters and other timing parameters specified in the JEDEC specification, and the timing block is bidirectionally connected to the replay queue 230. The page table 236 maintains status information about the active pages in each memory bank and memory column of the memory channel of the arbiter 238, and is bidirectionally connected to the replay queue 230.

[0032] In response to receiving a write memory access request from the interface 212, the ECC generation block 244 calculates the ECC based on the write data. The data buffer 246 stores the write data and ECC for the received memory access request. When the arbiter 238 selects the corresponding write access for dispatching to the memory channel, the data buffer outputs the combined write data / ECC to the memory interface queue 214.

[0033] The power controller 250 generally includes an interface 252 to the Advanced eXtensible Interface version 1 (AXI), an Advanced Peripheral Bus (APB) interface 254, and a power engine 260. The interface 252 has a first bidirectional connection to the SMN, which includes a first bidirectional connection for receiving Figure 2The APB interface 254 has an input connected to the output of the interface 252, and an output for connecting to the PHY via the APB. The power engine 260 has an input connected to the output of the interface 252, and an output connected to the input of the memory interface queue 214. The power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self-refresh controller (SLFREF / PE) 266, and a reliable read / write timing engine (RRW / TE) 268. The configuration registers 262 are programmed via the AXI bus and store configuration information to control the operation of various blocks in the memory controller 200. Therefore, the configuration registers 262 have outputs connected to these blocks, which are in Figure 2 SLFREF / PE 266 is an engine that allows refreshes to be manually generated in addition to the refreshes automatically generated by refresh control logic 232. Reliable read / write timing engine 268 provides a continuous memory access stream to the memory or I / O device for purposes such as DDR interface maximum read latency (MRL) training and loopback testing.

[0034] The memory channel controller 210 includes circuitry that allows it to select memory accesses for scheduling to associated memory channels. In order to make the desired arbitration decision, the address generator 222 decodes the address information into pre-decoding information, which includes storage columns, row addresses, column addresses, memory bank addresses, and memory bank groups in the memory system, and the command queue 220 stores the pre-decoding information. The configuration register 262 stores configuration information to determine the manner in which the address generator 222 decodes the received address information. The arbitrator 238 uses the decoded address information, the timing qualification information indicated by the timing block 234, and the active page information indicated by the page table 236 to efficiently schedule memory accesses while complying with other criteria such as quality of service (QoS) requirements. For example, the arbitrator 238 implements priority for accessing open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides the overhead access to one memory bank by interleaving the overhead access to one memory bank with the read and write access to another memory bank. Particularly during normal operation, arbiter 238 typically keeps pages open in different memory banks until the pages need to be precharged and then selects a different page. In some embodiments, arbiter 238 determines eligibility for command selection based at least on the corresponding value of activation counter 248 for the target memory region of the corresponding command.

[0035] Figure 3 According to some embodiments Figure 22 is a block diagram of a portion 300 of a memory controller 200 of the embodiment of the present invention. The portion 300 includes an arbiter 238 and a set of control circuits 360 associated with the operation of the arbiter 238. The arbiter 238 includes a set of sub-arbiters 305 and a final arbiter 350. The sub-arbiter 305 includes a sub-arbiter 310, a sub-arbiter 320, and a sub-arbiter 330. The sub-arbiter 310 includes a page hit arbiter 312 labeled "PH ARB" and an output register 314. The page hit arbiter 312 has a first input, a second input, and an output connected to the command queue 220. The register 314 has a data input connected to the output of the page hit arbiter 312, a clock input for receiving a UCLK signal, and an output. The sub-arbiter 320 includes a page conflict arbiter 322 labeled "PC ARB" and an output register 324. The page conflict arbiter 322 has a first input, a second input, and an output connected to the command queue 220. Register 324 has a data input connected to the output of page conflict arbiter 322, a clock input for receiving the UCLK signal, and an output. Sub-arbiter 330 includes a page miss arbiter 332 labeled "PM ARB" and an output register 334. Page miss arbiter 332 has a first input, a second input, and an output connected to command queue 220. Register 334 has a data input connected to the output of page miss arbiter 332, a clock input for receiving the UCLK signal, and an output. Final arbiter 350 has a first input connected to the output of refresh control logic 232, a second input from page close predictor 362, a third input connected to the output of output register 314, a fourth input connected to the output of output register 324, a fifth input connected to the output of output register 334, a first output for providing a first arbitration winner labeled "CMD1" to queue 214, and a second output for providing a second arbitration winner labeled "CMD2" to queue 214.

[0036] The control circuit 360 includes the Figure 2The timing block 234 and page table 236, page close predictor 362, current mode register 302 and cross mode enable logic 304 are depicted. The timing block 234 has an output connected to the cross mode enable logic 304, inputs and outputs connected to the page hit arbiter 312, the page conflict arbiter 322 and the page miss arbiter 332. The page table 234 has an input connected to the output of the replay queue 230, an output connected to the input of the replay queue 230, an output connected to the input of the command queue 220, an output connected to the input of the timing block 234 and an output connected to the input of the page close predictor 362. The page close predictor 362 has an input connected to one output of the page table 236, an input connected to the output of the output register 314 and an output connected to a second input of the final arbiter 350. Cross mode enable logic 304 has an input connected to current mode register 302 and to command queue 220 , as well as input and output connected to final arbiter 350 , and input and output connected to page hit arbiter 310 , page conflict arbiter 320 , and page miss arbiter 330 .

[0037] In operation, the arbiter 238 selects memory access commands from the command queue 220 and the refresh control logic 232 by considering the current mode (indicating whether read tailing or write tailing is in progress), the page status of each entry, the priority of each memory access request, and the correlation between these requests. The priority is related to the quality of service or QoS of the request received from the AXI4 bus and stored in the command queue 220, but can be changed based on the type of memory access and the dynamic operation of the arbiter 238. The arbiter 238 includes three sub-arbiters that operate in parallel to address the mismatch between the processing and transmission limitations of existing integrated circuit technologies. The winners of the corresponding sub-arbitrations are presented to the final arbiter 350. The final arbiter 350 selects between the three sub-arbitration winners and selects the refresh operation from the refresh control logic 232, and can further modify the read or write command to a read or write with an automatic precharge command as determined by the page close predictor 362.

[0038] The cross mode enable logic 304 operates to cause tailing of read commands and tailing of write commands on the memory channel. During the current tailing of either type of command, the cross mode enable logic 304 monitors an indication of the data bus efficiency of the memory channel, as described below with respect to Figure 4 and Figure 5 As further described, in response to the indication of the data bus efficiency indicating that the data bus efficiency is below a specified threshold, the crossover mode enable logic 304 stops the current tailing, starts another type of tailing, and changes the current mode in the current mode register 302 .

[0039] Each of the page hit arbiter 312, the page conflict arbiter 322, and the page miss arbiter 332 has an input connected to the output of the timing block 234 to determine the timing qualifications of the commands in the command queue 220 that fall into these corresponding categories. The timing block 234 includes an array of binary counters that count the duration associated with the specific operation of each memory bank in each storage column. The number of timers required to determine the state depends on the timing parameters, the number of memory banks of a given memory type, and the number of memory banks supported by the system on a given memory channel. The number of timing parameters implemented depends on the type of memory implemented in the system. For example, compared with other DDRx memory types, GDDR5 memory requires more timers to comply with more timing parameters. By including an array of general timers implemented as binary counters, the timing block 234 can be scaled and reused for different memory types. The input from the cross mode enable logic 304 signals to the sub-arbiter which type of command (read or write) is provided as a candidate for the final arbiter 350.

[0040] A page hit is a read or write cycle to an open page. The page hit arbiter 312 arbitrates between accesses in the command queue 220 to open a page. Timing eligibility parameters tracked by the timer in the timing block 234 and checked by the page hit arbiter 312 include, for example, the row address strobe (RAS) to column address strobe (CAS) delay time (t RCD ) and CAS waiting time (t CL ). For example, t RCD The minimum amount of time that must pass before read or write access to a page after it has been opened in a RAS cycle is specified. The page hit arbitrator 312 selects the sub-arbitration winner based on the assigned access priority. In one embodiment, the priority is a 4-bit, unique hot value, thus indicating the priority among four values, however, it should be apparent that this four-level priority scheme is only an example. If the page hit arbitrator 312 detects two or more requests of the same priority level, the oldest entry wins.

[0041] A page conflict is an access to a row in a bank when another row in the bank is currently active. The page conflict arbitrator 322 arbitrates between accesses to pages in the command queue 220 that conflict with pages currently open in the corresponding bank and rank. The page conflict arbitrator 322 selects the sub-arbitration winner that results in the issuance of a precharge command. The timing eligibility parameters tracked by the timer in the timing block 234 and checked by the page conflict arbitrator 322 include, for example, the number of active precharge command cycles (t RAS). The page conflict arbitrator 322 selects a sub-arbitration winner based on the assigned access priority. If the page conflict arbitrator 322 detects two or more requests of the same priority level, the oldest entry wins.

[0042] A page miss is an access to a memory bank that is in a precharged state. The page miss arbiter 332 arbitrates between accesses to precharged memory banks in the command queue 220. Timing eligibility parameters tracked by the timer in the timing block 234 and checked by the page miss arbiter 332 include, for example, the precharge command period (t RP ). If there are two or more requests that are page misses at the same priority level, the oldest entry wins.

[0043] Each sub-arbitrator outputs a priority value for their respective sub-arbitration winner. The final arbitrator 350 compares the priority values ​​of the sub-arbitration winners from each of the page hit arbitrator 312, the page conflict arbitrator 322, and the page miss arbitrator 332. The final arbitrator 350 determines the relative priority between the sub-arbitration winners by performing a set of relative priority comparisons that consider two sub-arbitration winners at a time. The sub-arbitrators may include a set of logic for arbitrating commands for read and write for each mode so that when the current mode changes, a set of available candidate commands are quickly available as sub-arbitration winners.

[0044] After determining the relative priorities between the three sub-arbitration winners, the final arbitrator 350 then determines whether these sub-arbitration winners conflict (i.e., whether they point to the same memory bank and memory column). When there is no such conflict, the final arbitrator 350 selects at most two sub-arbitration winners with the highest priority. When there is a conflict, the final arbitrator 350 follows the following rules. When the priority value of the sub-arbitration winner of the page hit arbitrator 312 is higher than the priority value of the sub-arbitration winner of the page conflict arbitrator 322 and both point to the same memory bank and memory column, the final arbitrator 350 selects the access indicated by the page hit arbitrator 312. When the priority value of the sub-arbitration winner of the page conflict arbitrator 322 is higher than the priority value of the sub-arbitration winner of the page hit arbitrator 312 and both point to the same memory bank and memory column, the final arbitrator 350 selects the winner based on several additional factors. In some cases, the page close predictor 362 causes the page to be closed at the end of the access indicated by the page hit arbitrator 312 by setting the automatic precharge attribute.

[0045] Within the page hit arbiter 312, the priority is initially set by the request priority from the memory access agent, but is dynamically adjusted based on the access type (read or write) and the access sequence. In general, the page hit arbiter 312 assigns a higher implicit priority to reads, but implements a priority boosting mechanism to ensure that writes make progress toward completion.

[0046] Whenever the page hit arbiter 312 selects a read or write command, the page close predictor 362 determines whether to send a command with an automatic precharge (AP) attribute. During the read or write cycle, the automatic precharge attribute is set with a predefined address bit, and the automatic precharge attribute causes the DDR device to close the page after the read or write cycle is completed, which avoids the need for the memory controller to send a separate precharge command for the memory bank later. The page close predictor 362 considers other requests that already exist in the command queue 220 to access the same memory bank as the selected command accesses. If the page close predictor 362 converts the memory access into an AP command, the next access to the page will be a page miss.

[0047] By using different sub-arbiters for different memory access types, each arbitrator can be implemented with simpler logic than if arbitration between all access types (page hits, page misses, and page conflicts) were required. Thus, the arbitration logic can be simplified and the size of arbitrator 238 can be kept relatively small.

[0048] In other embodiments, arbitrator 238 may include a different number of sub-arbiters. In yet another embodiment, arbitrator 238 may include two or more sub-arbiters of a specific type. For example, arbitrator 238 may include two or more page hit arbiters, two or more page conflict arbiters, and / or two or more page miss arbiters.

[0049] Figure 4 400 is a flow chart of a process for managing tailing efficiency according to some embodiments. In some versions, the process is embodied in an arbiter of a memory controller (such as Figure 2 In other versions, the process may be performed by a digital logic or controller having similar functionality, while using a different arbitration method than that used by the sub-arbiter 305 and the final arbiter 350 described above. The process is typically used to determine when to perform a turnaround of command tailing, thereby changing the current mode from write to read or from read to write to improve data bus utilization efficiency. The process may be used in combination with other techniques for determining the length of the tail of a read or write command.

[0050] At the start of each command tail, the process starts at block 402 and determines a snapshot or count of commands currently in the command queue for the mode (read or write) of commands that will burst in the tail. In some embodiments, this snapshot count is tracked by the tail turnaround process and is available when a new tail starts. In some embodiments, the process updates the snapshot count to account for any new commands that enter the command queue after the decision to end the previous tail is made.

[0051] At block 404, the process determines a minimum burst length, i.e., the minimum number of commands to be sent in the tail, based on the number snapshot of the commands from block 402. Thus, the minimum burst length can adapt to the current conditions at the memory controller. In this embodiment, the minimum burst length is calculated by scaling up or multiplying the snapshot by predetermined coefficients provided to the arbitrator. The first coefficient "READ eCoefficiency" is used for the read data tail, and the second coefficient "WRITE eCoefficiency" is used for the write data stream, as shown at block 404. In some embodiments, the snapshot is adjusted to take into account commands that can be used for the new current mode selected by the arbitrator, which will not be "blocked", i.e., will not generate page conflicts due to cross-mode activation. The adjustment is made by setting a minimum burst length that is equal to the smaller value of the scaled number of snapshots and the total number of new current mode requests that are not blocked by cross-mode activation. The adjustment is made due to the scenario where a cross-mode request becomes a page hit and a current mode request of the same memory bank becomes a page conflict during the tail turnaround. The process does not include these current mode page conflicts that conflict with cross mode hits into the count of commands that can be scheduled for the new tail, otherwise the minimum tail length would offset the benefit of the cross mode ACT due to the cross mode activation.

[0052] In block 406 , the process begins sending commands for the tail and monitors the size of the tail (the number of commands sent in the tail) until the minimum burst length set at block 404 is reached.

[0053] After the minimum burst length is reached, blocks 408 and 410 are executed for each command sent. At block 408, after the minimum burst length, the process monitors a first set of one or more conditions indicating intra-burst efficiency, as further described below. In this embodiment, a second set of conditions indicating inter-burst efficiency is also monitored at block 408. In some other embodiments, after the minimum burst length, efficiency conditions are monitored only for intra-burst efficiency. In some embodiments, monitoring one or more sets of conditions includes calculating one or more indications, such as bus usage efficiency or CAS latency. Monitoring efficiency conditions may also include monitoring conditions at the memory controller, such as available current mode or cross mode commands. This will be described below in conjunction with Figure 5 An exemplary implementation using multiple CAS latency conditions is described.

[0054] At box 410, the process determines whether to end the tail based on whether the monitored conditions indicate that it will be more effective to end the tail and start a new tail of another mode. In some embodiments, at least the first set of conditions (efficiency within the burst) are used to make a decision at box 410. In other embodiments, a combination of the first set of conditions and the second set of conditions is used. In different embodiments, the first set of conditions and the second set of conditions may each include one or more conditions. If the process does not decide to end the tail at box 410, then return to box 408 to continue monitoring the tail when sending a new command. If the process decides to end the tail at box 410, then proceed to box 412, change the current mode at the box and start a new command tail of the command type that is a cross-mode command in the previous tail. In order to determine whether one or more groups of conditions indicate that the tail is over, one or more conditions are compared with a threshold value, or these one or more conditions can be compared with each other. In some embodiments, the second set of conditions related to the efficiency between bursts is compared with a threshold value, which is at least partially based on the time required to turn around the process to start a new tail.

[0055] In general, the depicted process has several advantages over other known tail management processes that make it suitable for managing a variety of memory access workloads. It also solves several problems that various tail management techniques tend to exhibit. For example, using intra-burst efficiency management alone tends to result in excessively high tail turnover rates because intra-burst management will often decide to end tailing when there is no valid set of burst commands for cross-mode tailing. Especially for workloads with poor bank-level parallelism, this excessive turnover rate can hurt overall efficiency. While using a minimum threshold may appear to alleviate this problem, the minimum threshold also has associated problems. If the minimum threshold is too large, the burst may become inefficient even before the minimum threshold is reached. If the minimum burst length is too low, there will be more turnovers. The minimum burst threshold also depends on the workload, meaning that a threshold selected for one type of workload may not be appropriate for another type of workload.

[0056] While using only adaptive minimum burst length tends to improve inter-burst efficiency, it does not adequately manage the many different situations and workloads where intra-burst efficiency may be affected. For example, a burst may not last long enough to achieve high efficiency for a particular workload. The depicted process addresses this problem by combining intra-burst efficiency management with adaptive minimum burst length.

[0057] Figure 5is a flowchart 500 of a process for managing tailing efficiency according to some additional embodiments. The process is typically performed by monitoring an arbiter (such as Figure 2 The process described is performed by the logic inside the arbiter 238 in the system memory to handle the continuous read command tailing and continuous write command tailing sent to the system memory. Figure 4 An exemplary implementation of the process of and generally adopts the interval between two or more adjacent CAS commands as the intra-burst efficiency indication, and also adopts other CAS intervals as the inter-burst efficiency indication.

[0058] When a new tail begins, block 502 begins the turnaround monitoring process. Figure 4 At block 504, an initial tail command is sent via the command bus until the minimum burst length is met.

[0059] After the minimum burst length is met, the process performs several checks for each command sent in the tail to determine whether the tail should end or continue. At box 506, the current command is sent. At box 508, the process determines whether only the current mode command is available to be sent at the arbitrator. For example, if the current tail is a write tail, box 508 determines whether only write commands are pending. If so, the process continues the tail, returning to box 506 to send the next command. If not, the process proceeds to box 510, where it is determined whether only cross mode commands are available at the arbitrator. If so, the process ends the current tail and starts a new tail.

[0060] At box 510, if there are still current mode commands available, the process continues to box 512, where the process monitors the efficiency of each command within the burst based on the interval between CAS commands (referred to as the "CAS to CAS" interval). In some embodiments, the interval is determined for multiple candidate commands at the arbitrator. The interval is a measurement or prediction of one or more time intervals between column address strobe (CAS) commands. The interval includes the time interval between the most recently transmitted CAS command and the time when the selected subsequent CAS command can be transmitted. The calculation results produce a prediction of the efficiency of the data bus within the burst of the corresponding candidate command. In this embodiment, the interval in clock cycles is compared with a predetermined threshold to determine whether the interval is considered a high-efficiency command.

[0061] At block 514, the process determines whether any cross-mode command that can be used as a candidate has high efficiency. If there is no high-efficiency cross-mode command available, the process continues the current tailing. Block 514 uses one or more efficiency conditions indicating inter-burst efficiency, which in this example are efficiency indications based on potential CAS to CAS thresholds of cross-mode commands. In general, at block 514, an efficiency indication is calculated for a cross-mode command that can be selected at the arbitrator, and the efficiency indication is compared with one of the thresholds 526 or 528 to determine whether the cross-mode command is efficient. If the indication is a CAS to CAS interval calculated directly in clock cycles, the indication can be regarded as a cost function in which low cost signals high efficiency. The advantage of this check is to prevent this sequence: a turnaround is made, and then there is no high-efficiency command available in another mode, and the process turns around again repeatedly. The thresholds for cross-mode commands are a "cross-mode write CAS gap threshold" 526 for comparison when the read command is the current mode and a "cross-mode read CAS gap threshold" 528 for comparison when the write command is the current mode. In this embodiment, thresholds 526 and 528 are set based on adjustable configuration register values ​​that are selected to take into account the minimum CAS to CAS timing for the corresponding command type for the command, the time required to perform a tail turnaround, the burst length employed (the number of data beats sent or pulled for each CAS command), and other considerations such as the possibility of storage column switching and storage body group switching.

[0062] If there is a high efficiency interleaved mode command available at block 514, the process proceeds to block 516 where the process uses another type of intra-burst efficiency indication to prevent a sequence of consecutive commands that are only slightly within the high efficiency threshold but provide an overall low efficiency tail. Block 516 calculates the "last 3" current mode CAS to CAS interval, which provides the interval between the most recently transmitted CAS command and the previous CAS command that occurred three CAS commands ago. If this "last 3" interval is greater than a specified threshold, the process ends the current tail and performs a turnaround.

[0063] If the "last 3" interval is within the specified threshold, the process at block 516 proceeds to block 518. At block 518, the process checks if there is an available high efficiency current mode command for the current mode by comparing the candidate command's CAS to CAS interval to one of thresholds 522 or 524. If there is an available high efficiency current mode command, the process continues the current tail. If not, the process proceeds to block 520 where the current tail is ended. Ending the tail in each of the depicted cases results in a turnaround process where a tail for another mode is started.

[0064] As depicted by the thresholds input to box 518, two different thresholds 522 and 524 are used at box 518 to monitor the efficiency of the command, depending on whether the current mode is read or write. The thresholds for current mode commands are "current mode write CAS gap threshold" 522 for comparison when write commands are the current mode and "current mode read CAS gap threshold" 524 for comparison when read commands are the current mode. In this embodiment, the thresholds 522 and 524 are set based on adjustable configuration register values, which are selected to take into account the minimum CAS to CAS timing for the corresponding command type of the command, the burst length adopted (the number of data beats sent or pulled for each CAS command), and other considerations, such as, for example, the possibility of storage column switching and storage bank group switching. Since the desired minimum burst length has been achieved, the depicted process allows for greater flexibility in managing intra-burst efficiency compared to solutions that also need to consider excessive tailing turnover related to intra-burst efficiency management. In this embodiment, the intra-burst efficiency conditions monitored at box 512 are used at boxes 516 and 518 to determine whether to end tailing. In other embodiments, block 516 is not used. In various embodiments, other process decision flows are also employed to achieve similar results.

[0065] Although the process in this embodiment uses several different determinations when deciding whether to end the current tail, other embodiments may include less than all of the conditional determinations depicted. In addition, although the various determinations in flow chart 500 are depicted in a particular order, this is not restrictive, and various embodiments may use circuits that perform selected boxes in different orders or simultaneously to achieve similar functions.

[0066] Figure 2 The memory controller 200 or any part thereof (such as the arbiter 238 and the refresh control logic 232) can be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure can be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool, which can synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represents the functionality of the hardware comprising the integrated circuit. The netlist can then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask can then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer accessible storage medium can be a netlist (with or without a synthesis library) or a data set (as required) or a graphic data system (GDS) II data.

[0067] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the internal architecture of the memory channel controller 210 and / or the power engine 250 may vary in different embodiments. The memory controller 200 may be interfaced to other types of memory such as high bandwidth memory (HBM) etc. in addition to DDRx. Although the illustrated embodiment shows each memory storage rank corresponding to a separate DIMM or SIMM, in other embodiments, each module may support multiple storage ranks. Still other embodiments may include other types of DRAM modules or DRAM not included in a particular module, such as DRAM mounted to a host motherboard. Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A memory controller, comprising: a command queue having a first input for receiving a memory access request; as well as an arbiter coupled to the command queue for selecting an entry from the command queue and causing the entry to be transmitted through a memory channel, the arbiter being operable to: transmitting a tail of consecutive read commands and a tail of consecutive write commands through the memory channel; transmitting a current tail of one of a continuous read command or a continuous write command of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbitrator; as well as After the minimum burst length, if no new tailing command is available to send a CAS command within a first defined column address strobe (CAS) to CAS interval, the current tailing is continued. 2 . The memory controller of claim 1 , wherein the minimum burst length is calculated as the number of available commands for the current tail multiplied by a selected ratio.

3. The memory controller of claim 1 , wherein the arbiter is further operable to: after the minimum burst length, if there is no command available to send the current tail of a CAS command within a second defined CAS to CAS interval, end the current tail. 4 . The memory controller of claim 3 , wherein the arbiter is further operable to: end the current tailing if a total CAS to CAS interval of a plurality of the current tailing commands exceeds a third defined interval.

5. The memory controller of claim 3 , wherein when the current tail is a read command, a first interval is used for the first defined CAS to CAS interval, and when the current tail is a write command, a second interval different from the first interval is used for the first defined CAS to CAS interval.

6. The memory controller of claim 5 , wherein when the current tail is a read command, a third interval is used for the second defined CAS to CAS interval, and when the current tail is a write command, a fourth interval different from the third interval is used for the second defined CAS to CAS interval.

7. The memory controller of claim 1, wherein the first defined CAS-to-CAS interval is an interval between a most recently transmitted CAS command and a time at which a selected subsequent CAS command can be transmitted.

8. A method comprising: causing tailing of consecutive read commands and tailing of consecutive write commands to be transmitted through a memory channel; transmitting a current tail of one of a continuous read command or a continuous write command of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbitrator; as well as After the minimum burst length, if no new tailing command is available to send a CAS command within a first defined column address strobe (CAS) to CAS interval, the current tailing is continued.

9. The method of claim 8, wherein the minimum burst length is calculated as the number of available commands for the current tail multiplied by a selected ratio.

10. The method according to claim 8, further comprising: After the minimum burst length, if there is no command available to send a CAS command for the current tail within a second defined CAS to CAS interval, the current tail is ended.

11. The method of claim 10, wherein when the current tail is a read command, a first interval is used for the first defined CAS to CAS interval, and when the current tail is a write command, a second interval different from the first interval is used for the first defined CAS to CAS interval.

12. The method of claim 11 , wherein when the current tail is a read command, a third interval is used for the second defined CAS to CAS interval, and when the current tail is a write command, a fourth interval different from the third interval is used for the second defined CAS to CAS interval.

13. The method according to claim 10, further comprising: If the total CAS-to-CAS interval of multiple current tailing commands exceeds a third defined interval, the current tailing is ended.

14. The method of claim 8, wherein the first defined CAS-to-CAS interval is an interval between a most recently transmitted CAS command and a time at which a selected subsequent CAS command can be transmitted.

15. A data processing system comprising: Processing unit; a data texture coupled to the processing unit; as well as a memory controller coupled to the data fabric for fulfilling a memory request from the processing unit, the memory controller comprising: a command queue having a first input for receiving a memory access request; an arbiter coupled to the command queue for selecting an entry from the command queue and causing the entry to be transferred to at least one dynamic random access memory through a memory channel, the arbiter being operable to: transmitting a tail of consecutive read commands and a tail of consecutive write commands through the memory channel; transmitting a current tail of one of consecutive read commands or consecutive write commands of at least a minimum burst length based on a plurality of commands of a specified type available for selection by the arbitrator; and After the minimum burst length, if no new tailing command is available to send a column address strobe (CAS) command within a first defined CAS to CAS interval, the current tailing is continued.

16. The data processing system of claim 15, wherein the minimum burst length is calculated as the number of available commands for the current tail multiplied by the selected ratio.

17. The data processing system of claim 15, wherein the arbiter is further operable to: after the minimum burst length, if there is no command available to send a CAS command for the current tail within a second defined CAS to CAS interval, end the current tail.

18. The data processing system of claim 17 , wherein when the current tail is a read command, a first interval is used for the first defined CAS to CAS interval, and when the current tail is a write command, a second interval different from the first interval is used for the first defined CAS to CAS interval.

19. The data processing system of claim 18, wherein when the current tail is a read command, a third interval is used for the second defined CAS to CAS interval, and when the current tail is a write command, a fourth interval different from the third interval is used for the second defined CAS to CAS interval.

20. The data processing system of claim 17, wherein the arbiter is further operable to: end the current tail if a total CAS to CAS interval of a plurality of the current tail commands exceeds a third defined interval.

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