An NPN type adjustable low temperature drift current reference circuit

Abstract

This invention discloses an NPN-type adjustable low-temperature drift current reference circuit, comprising a startup circuit module and a current reference generation circuit module. The startup circuit module includes NMOS transistors M3, M4, M5, PMOS transistors M6 and M7, and resistor R3. The current reference generation circuit module includes PMOS transistors M1 and M2, NPN transistors Q1 and Q2, resistors R1 and R2. The NPN-type adjustable low-temperature drift current reference circuit provided by this invention reduces the temperature drift of the reference current, significantly improves the temperature coefficient, and enhances the accuracy of the current reference circuit. Furthermore, this invention only adds resistors to the circuit, making the circuit simple and easy to implement without requiring additional manufacturing processes, thus facilitating practical applications.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to an NPN type adjustable low temperature drift current reference circuit. Background Technology

[0002] In analog integrated circuits, reference circuits are widely used due to their invariance to temperature changes. In bandgap circuits, the base-emitter voltage difference ΔV between two bipolar junction transistors (BJTs) is... BE Bipolar transistors (BJTs) possess a positive temperature coefficient under unequal current bias. Utilizing this principle, the bias current generated by a BJT circuit is proportional to its absolute temperature; this current is generally called the PTAT (proportional to absolute temperature) current. Some traditional current reference circuits achieve low current temperature drift by superimposing the PTAT current with another current having a negative temperature coefficient to obtain a parabolic reference current. However, in practical applications, due to manufacturing limitations or stringent requirements for the temperature drift of the reference current, the accuracy of traditional current reference circuits cannot reach ideal levels, thus reducing chip performance. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides an NPN type adjustable low-temperature drift current reference circuit.

[0004] The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides an NPN type adjustable low temperature drift current reference circuit, comprising: a startup circuit module and a current reference generation circuit module;

[0006] The startup circuit module includes NMOS transistors M3, M4, M5, M6, and M7, and resistor R3.

[0007] The gate of the PMOS transistor M7 is connected to an enable signal, the source is connected to the power supply voltage, and the drain is connected to the drain of the NMOS transistor M5 and the gate of the NMOS transistor M3 through the resistor R3.

[0008] The gate of the PMOS transistor M6 is connected to the current reference generation circuit module as the input terminal of the startup circuit module, the source is connected to the power supply voltage, and the drain is connected to the gate of the transistor M5 and the gate and drain of the transistor M4, respectively.

[0009] The gate of NMOS transistor M5 is connected to the gate and drain of NMOS transistor M4 and the drain of NMOS transistor M6, respectively. The source is grounded, and the drain is connected to the drain of NMOS transistor M7 through the resistor R3. The drain is also connected to the gate of NMOS transistor M3.

[0010] The drain and gate of the NMOS transistor M4 are connected, and the connection point is also connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5, respectively, while the source is grounded.

[0011] The gate of the NMOS transistor M3 is connected to the drain of the NMOS transistor M5. The gate is also connected to the drain of the NMOS transistor M7 through the resistor R3. The source is grounded, and the drain is connected to the current reference generation circuit module as the output terminal of the startup circuit module.

[0012] The current reference generation circuit module includes PMOS transistor M1, PMOS transistor M2, NPN transistor Q1, NPN transistor Q2, resistor R1, and resistor R2; resistor R1 and resistor R2 have the same temperature coefficient.

[0013] The source of the PMOS transistor M1 is connected to the power supply voltage, and the drain and gate are connected together. The connection point is also connected to the gate of the PMOS transistor M2, the input terminal of the startup circuit module, the output terminal of the startup circuit module, and the collector of the NPN transistor Q1.

[0014] The gate of the PMOS transistor M2 is connected to the gate of the PMOS transistor M1, the source is connected to the power supply voltage, and the drain is connected to the base of the NPN transistor Q1 and the collector of the NPN transistor Q2, respectively. The drain is also connected to the base of the NPN transistor Q2 through the resistor R2.

[0015] The collector of the NPN transistor Q1 is connected to the drain of the PMOS transistor M1 and the output terminal of the startup circuit module, respectively. The emitter is grounded through the resistor R1. The base is connected to the drain of the PMOS transistor M2 and the collector of the NPN transistor Q2, respectively. The base is also connected to the base of the NPN transistor Q2 through the resistor R2.

[0016] The base of the NPN transistor Q2 is connected to the base of the NPN transistor Q1, the drain of the PMOS transistor M2, and its own collector via the resistor R2, while the emitter is grounded.

[0017] In one embodiment, the startup circuit module is used to eliminate the degenerate bias point of the current reference generation circuit module.

[0018] In one embodiment, the area ratio of the NPN transistor Q1 to the area of ​​the NPN transistor Q2 is n:1, where n is an integer greater than 1.

[0019] In one embodiment, both resistor R1 and resistor R2 are resistors with a positive temperature coefficient.

[0020] In one embodiment, both resistor R1 and resistor R2 are resistors with negative temperature coefficients.

[0021] In one embodiment, the resistance values ​​of resistor R1 and resistor R2 satisfy the following formula:

[0022]

[0023] Where I1 is the current flowing through the PMOS transistor M1, n is the area ratio of the NPN transistor Q1 to the NPN transistor Q2, k is the Boltzmann constant, T is the absolute temperature, q is the charge, and β is the current amplification factor of the NPN transistor Q2.

[0024] The NPN type adjustable low temperature drift current reference circuit provided by the present invention has the following beneficial effects:

[0025] The NPN-type adjustable low-temperature drift current reference circuit provided by this invention connects the input terminal of the startup circuit module to the current reference generation circuit module. When the current in the branch of the current reference generation circuit module is detected to be zero, the startup circuit module starts working, transitioning the current reference generation circuit module from a zero-current state to an operating state. After the current reference generation circuit module enters the operating state, the startup current module automatically switches to low-power standby, eliminating the degenerate bias point of the current reference generation circuit and enabling the current reference generation circuit module to operate normally. Specifically, this invention adds a resistor R2 with the same temperature coefficient as resistor R1 to the current reference generation circuit module. By adjusting the size and ratio of resistors R1 and R2, the influence of the temperature coefficient can be eliminated, thereby changing the direct relationship between the reference current and temperature to a parabolic linear relationship, reducing the temperature drift of the reference current, greatly improving the temperature coefficient, and enhancing the accuracy of the current reference circuit. Furthermore, this invention only adds a resistor to the circuit, making the circuit simple and easy to implement without requiring additional manufacturing processes, thus facilitating practical applications.

[0026] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an NPN type adjustable low temperature drift current reference circuit provided in an embodiment of the present invention;

[0028] Figure 2This is a schematic diagram of an existing current reference circuit;

[0029] Figure 3 This is the temperature characteristic curve of the reference current of an NPN type adjustable low-temperature drift current reference circuit provided in an embodiment of the present invention. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0031] Current reference circuits are widely used because they do not change with temperature. Existing current reference circuit structures include... Figure 2 As shown, the array includes PMOS transistors M8 and M9, NPN transistors Q3 and Q4, and resistor R4. The area ratio of NPN transistors Q3 and Q4 is n. The source of PMOS transistor M8 and the drain of PMOS transistor M9 are both connected to the power supply voltage VDD. The gates of PMOS transistors M8 and M9 are connected, and the connection node also connects the drain of PMOS transistor M8 and the collector of NPN transistor Q3. The source of PMOS transistor M9 is connected to the base of NPN transistor Q3, the base of NPN transistor Q4, and the collector of NPN transistor Q4. The emitter of NPN transistor Q3 is grounded through resistor R4, and the emitter of NPN transistor Q4 is also grounded. The two branches formed by NPN transistors Q3 and Q4 have positive temperature coefficients, so the currents I3 and I4 flowing through PMOS transistors M8 and M9 are PTAT currents.

[0032] The base-emitter voltage difference ΔV between NPN transistors Q3 and Q4 BE Satisfy the following formula:

[0033] ΔV BE =V T lnn;

[0034] Among them, V T Represents thermal voltage, V T It can also be expressed as;

[0035]

[0036] In the formula, k is the Boltzmann constant, T is the absolute temperature, and q is the charge. As can be seen from the above formula, the thermal voltage is directly proportional to the absolute temperature.

[0037] like Figure 2 As shown, PMOS transistors M8 and M9 in the current reference circuit form a current mirror structure, thus ensuring that currents I3 and I4 satisfy I3 = I4. Therefore:

[0038]

[0039] When R4 is a resistor independent of temperature coefficient, currents I3 and I4 are PTAT currents proportional to absolute temperature. However, in practical applications, due to manufacturing processes and other issues, the temperature coefficient of resistor R4 is generally not 0, which makes currents I3 and I4 not meet the requirement of being proportional to absolute temperature.

[0040] To address the aforementioned problems of existing current reference circuits, embodiments of the present invention provide an NPN type adjustable low-temperature drift current reference circuit. For example... Figure 1 As shown, the current reference circuit includes a startup circuit module and a current reference generation circuit module.

[0041] The startup circuit module includes NMOS transistors M3, M4, M5, M6, and M7, and resistor R3.

[0042] The gate of PMOS transistor M7 is connected to the enable signal ENN, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of NMOS transistor M5 and the gate of NMOS transistor M3 through resistor R3.

[0043] The gate of PMOS transistor M6 is connected to the current reference generation circuit module as the input terminal of the startup circuit module, the source is connected to the power supply voltage VDD, and the drain is connected to the gate of transistor M5 and the gate and drain of transistor M4, respectively.

[0044] The gate of NMOS transistor M5 is connected to the gate and drain of NMOS transistor M4 and the drain of NMOS transistor M6, respectively. The source is grounded, and the drain is connected to the drain of NMOS transistor M7 through resistor R3. This drain is also connected to the gate of NMOS transistor M3.

[0045] The drain and gate of NMOS transistor M4 are connected, and the connection point is also connected to the drain of NMOS transistor M6 and the gate of NMOS transistor M5, respectively. The source is grounded.

[0046] The gate of NMOS transistor M3 is connected to the drain of NMOS transistor M5. The gate is also connected to the drain of NMOS transistor M7 through resistor R3. The source is grounded. The drain is connected to the current reference generation circuit module as the output terminal of the startup circuit module.

[0047] The startup circuit module is used to avoid a "degenerate" bias point in the current reference generation circuit module, eliminating the zero-current state when the current reference generation circuit module is powered on. When the power supply voltage VDD powers on the current reference circuit, the drain voltage of NMOS transistor M5 increases, causing NMOS transistor M3 in the circuit module to turn on. The drain output current of NMOS transistor M3 is input to the current reference generation circuit module, making the current I1 of the current reference generation circuit module non-zero, thus transitioning the current generation circuit module from a zero-current state to a non-zero operating state. NMOS transistors M4 and M5 form a current mirror structure. When the current reference circuit is working normally, the current flowing through NMOS transistor M4 is non-zero, and the current flowing through NMOS transistor M5 is equal to the current flowing through NMOS transistor M4. NMOS transistor M5 turns on, reducing its gate voltage, causing the startup circuit module to switch to a low-power standby state. At this time, NMOS transistor M3 is turned off, and the startup circuit achieves the function of eliminating the degenerate bias point.

[0048] The current reference generation circuit module includes PMOS transistor M1, PMOS transistor M2, NPN transistor Q1, NPN transistor Q2, resistor R1, and resistor R2.

[0049] It should be noted that resistors R1 and R2 have the same temperature coefficient, that is, resistors R1 and R2 are both resistors with a positive temperature coefficient or both resistors with a negative temperature coefficient. In this embodiment of the invention, a resistor with a positive temperature coefficient is taken as an example.

[0050] The area ratio of NPN transistor Q1 to NPN transistor Q2 is n:1, where n is an integer greater than 1. For example, as shown... Figure 1 As shown in the figure, m represents the area of ​​the NPN transistor; for example, Figure 1 The area of ​​NPN transistor Q1 is m = 9, the area of ​​NPN transistor Q2 is m = 1, and the ratio of their areas is n = 9.

[0051] The source of PMOS transistor M1 is connected to the power supply voltage VDD, and the drain and gate are connected together. The connection point is also connected to the gate of PMOS transistor M2, the input terminal of the startup circuit module, the output terminal of the startup circuit module, and the collector of NPN transistor Q1.

[0052] The gate of PMOS transistor M2 is connected to the gate of PMOS transistor M1, the source is connected to the power supply voltage VDD, and the drain is connected to the base of NPN transistor Q1 and the collector of NPN transistor Q2. The drain is also connected to the base of NPN transistor Q2 through resistor R2.

[0053] The collector of NPN transistor Q1 is connected to the drain of PMOS transistor M1 and the output terminal of the startup circuit module, respectively. The emitter is grounded through resistor R1. The base is connected to the drain of PMOS transistor M2 and the collector of NPN transistor Q2, respectively. The base is also connected to the base of NPN transistor Q2 through resistor R2.

[0054] The base of NPN transistor Q2 is connected to the base of NPN transistor Q1, the drain of PMOS transistor M2, and its own collector via resistor R2, while the emitter is grounded.

[0055] like Figure 1 As shown, PMOS transistors M1, M2, and M6 form a current mirror structure. When the current flowing through PMOS transistor M1 is a current with zero temperature coefficient, the current flowing through PMOS transistors M2 and M6 is also a current with zero temperature coefficient.

[0056] This current reference generation circuit module generates a temperature-independent parabolic reference current. Under normal operating conditions, the base-emitter voltage difference between NPN transistors Q1 and Q2 is directly proportional to temperature.

[0057] The circuit formed by NPN transistor Q1, NPN transistor Q2, resistor R1, and resistor R2 in the current reference generation circuit module has the following voltage relationship:

[0058]

[0059] Wherein, voltage V BE1 V represents the base-emitter voltage of NPN transistor Q1, and I1 represents the current flowing through NPN transistor Q1. BE2 Let I2 represent the base-emitter voltage of NPN transistor Q2, I2 represent the current flowing through NPN transistor Q2, and β represent the current amplification factor of NPN transistor Q2. From the above formula, we can derive:

[0060]

[0061] In the formula ΔV BE Representing the base-emitter voltage difference between NPN transistors Q1 and Q2, let I1 = I2, and we can obtain:

[0062]

[0063]

[0064] As can be seen from the above formula, compared with the existing current reference circuit, adding a resistor R2 with the same temperature coefficient as resistor R1 to the current reference generation circuit module allows both resistors R1 and R2 to be considered as linear terms in one variable with respect to T. By adjusting the resistance values ​​of resistors R1 and R2, the desired temperature coefficient can be achieved. The zeroth term in the linear term of the two resistors can be eliminated, making... The reference current is proportional to the absolute temperature T, so the temperature T in the reference current I1 can be canceled out in the numerator and denominator, resulting in a reference current independent of temperature. This reduces the temperature drift of the reference current and greatly improves the temperature coefficient. This structure solves the problem that the reference current in the original circuit could not be corrected due to excessive temperature changes.

[0065] The existing PTAT reference current generating circuit only generates a current with a positive temperature coefficient. This invention changes the topology of the original PTAT reference current generating circuit by adding a resistor R2 with the same temperature coefficient as resistor R1. By adjusting the size and ratio of resistors R1 and R2, the circuit can generate a reference current that is independent of the temperature coefficient, and at the same time, the waveform of the generated reference current can be parabolic.

[0066] Traditional PTAT current reference circuits output current that is positively correlated with temperature. The current reference circuit of this invention outputs a reference current as follows: Figure 3 As shown, when the temperature is negative, the output reference current is positively correlated with the temperature; when the temperature is near 0℃, the output reference current reaches its maximum; when the temperature is positive, the output reference current is negatively correlated with the temperature, and the overall reference current temperature characteristic curve is parabolic.

[0067] The NPN-type adjustable low-temperature drift current reference circuit provided in this embodiment of the invention connects the input terminal of the startup circuit module to the current reference generation circuit module. When the current in the branch of the current reference generation circuit module is detected to be zero, the startup circuit module starts working, causing the current reference generation circuit module to transition from a zero-current state to a working state. After the current reference generation circuit module enters the working state, the startup current module automatically switches to low-power standby, eliminating the degenerate bias point of the current reference generation circuit and enabling the current reference generation circuit module to work normally. Specifically, this embodiment of the invention adds a resistor R2, which has the same positive temperature coefficient as resistor R1, to the current reference generation circuit module. By adjusting the size and ratio of resistors R1 and R2, the influence of the temperature coefficient can be eliminated, thereby changing the direct relationship between the reference current and temperature to a parabolic linear relationship, thus reducing the temperature drift of the reference current, greatly improving the temperature coefficient, and increasing the accuracy of the current reference circuit. Furthermore, this embodiment of the invention only adds a resistor to the circuit, making the circuit simple and easy to implement without requiring additional manufacturing processes, and thus easier to implement in practical applications.

[0068] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An NPN type adjustable low temperature drift current reference circuit, characterized by, include: Start-up circuit module and current reference generation circuit module; The startup circuit module includes NMOS transistors M3, M4, M5, M6, and M7, and resistor R3. The gate of the PMOS transistor M7 is connected to an enable signal, the source is connected to the power supply voltage, and the drain is connected to the drain of the NMOS transistor M5 and the gate of the NMOS transistor M3 through the resistor R3. The gate of the PMOS transistor M6 is connected to the current reference generation circuit module as the input terminal of the startup circuit module, the source is connected to the power supply voltage, and the drain is connected to the gate of the NMOS transistor M5 and the gate and drain of the NMOS transistor M4, respectively. The gate of NMOS transistor M5 is connected to the gate and drain of NMOS transistor M4 and the drain of NMOS transistor M6, respectively. The source is grounded, and the drain is connected to the drain of NMOS transistor M7 through the resistor R3. The drain is also connected to the gate of NMOS transistor M3. The drain and gate of the NMOS transistor M4 are connected, and the connection point is also connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5, respectively, while the source is grounded. The gate of the NMOS transistor M3 is connected to the drain of the NMOS transistor M5. The gate is also connected to the drain of the NMOS transistor M7 through the resistor R3. The source is grounded, and the drain is connected to the current reference generation circuit module as the output terminal of the startup circuit module. The current reference generation circuit module includes PMOS transistor M1, PMOS transistor M2, NPN transistor Q1, NPN transistor Q2, resistor R1, and resistor R2; resistor R1 and resistor R2 have the same temperature coefficient. The source of the PMOS transistor M1 is connected to the power supply voltage, and the drain and gate are connected together. The connection point is also connected to the gate of the PMOS transistor M2, the input terminal of the startup circuit module, the output terminal of the startup circuit module, and the collector of the NPN transistor Q1. The gate of the PMOS transistor M2 is connected to the gate of the PMOS transistor M1, the source is connected to the power supply voltage, and the drain is connected to the base of the NPN transistor Q1 and the collector of the NPN transistor Q2, respectively. The drain is also connected to the base of the NPN transistor Q2 through the resistor R2. The collector of the NPN transistor Q1 is connected to the drain of the PMOS transistor M1 and the output terminal of the startup circuit module, respectively. The emitter is grounded through the resistor R1. The base is connected to the drain of the PMOS transistor M2 and the collector of the NPN transistor Q2, respectively. The base is also connected to the base of the NPN transistor Q2 through the resistor R2. The base of the NPN transistor Q2 is connected to the base of the NPN transistor Q1, the drain of the PMOS transistor M2, and its own collector through the resistor R2, and the emitter is grounded. Both resistor R1 and resistor R2 are resistors with positive temperature coefficients, or both are resistors with negative temperature coefficients; The resistance values ​​of resistor R1 and resistor R2 satisfy the following formula: Where I1 is the current flowing through the PMOS transistor M1, n is the area ratio of the NPN transistor Q1 to the NPN transistor Q2, k is the Boltzmann constant, T is the absolute temperature, q is the charge, and β is the current amplification factor of the NPN transistor Q2.

2. The NPN type adjustable low-temperature drift current reference circuit according to claim 1, characterized in that, The startup circuit module is used to eliminate the degenerate bias point of the current reference generation circuit module.

3. The NPN type adjustable temperature drift current reference circuit of claim 1, wherein, The area ratio of the NPN transistor Q1 to the area of ​​the NPN transistor Q2 is n:1, where n is an integer greater than 1.

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