Circuit for improving the efficiency of a switched mode power supply under heavy load

Abstract

The application discloses a circuit for improving the heavy load efficiency of a switching power supply, comprising three comparators comp, the non-inverting terminals of the comparators are connected with an error amplifier output signal Vc, the inverting terminal Vx of the first comparator is connected with the Vc value when Io=700mA, the inverting terminal Vy of the second comparator is connected with the Vc value when Io=770mA, and the inverting terminal Vz of the third comparator is connected with the Vc value when Io=820mA. The output terminals a, b and c of the three comparators are connected with the input terminals of a logic control circuit, and the four output terminals of the logic control circuit are connected with four switches of different reference generation circuits. The different reference generation circuits are connected in series through four resistors, and the resistors are used for voltage division to obtain different gate voltages of power tubes. The application discloses a power tube adaptive conduction resistance circuit applied to improving the heavy load efficiency of a switching power supply, and the application effectively improves the conversion efficiency of the switching power supply under heavy load.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply conversion efficiency technology, and relates to a circuit for improving the heavy-load efficiency of switching power supplies. Background Technology

[0002] The stability, reliability, and high efficiency of power management chips have become primary concerns in the current research and development of electronic equipment. Boost DC-DC converters convert the magnetic energy stored in inductors into electrical energy by controlling the on and off states of power transistors, thus achieving energy transfer. Therefore, conversion efficiency is a crucial parameter for measuring system performance, and reducing power consumption is essential to improving system efficiency.

[0003] There are three modulation modes for converters: pulse width modulation (PWM), pulse frequency modulation (PFM), and cycle skipping modulation (PSM). Pulse width modulation (PWM) is widely used under heavy loads due to its stable output voltage and low ripple. Conduction loss is proportional to the square of the load current and increases with increasing load current, making it a key factor affecting heavy load efficiency. When the system is under a high current load, the on-resistance should be minimized to reduce conduction loss and improve conversion efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a circuit for improving the heavy-load efficiency of switching power supplies. This circuit can solve the problem of a large proportion of conduction loss under heavy load, reduce the conduction loss of the system, and improve the conversion efficiency of the system under heavy load.

[0005] The technical solution adopted in this invention is a circuit for improving the heavy-load efficiency of a switching power supply, including voltage comparators comp1, comp2, and comp3. The three voltage comparators comp1, comp2, and comp3 are connected in sequence to a logic control circuit and different reference generation circuits.

[0006] The invention is further characterized by:

[0007] The non-inverting inputs of voltage comparators comp1, comp2, and comp3 are all connected to the output signal Vc of the error amplifier. The inverting input of voltage comparator comp1 is connected to the Vx signal; the inverting input of voltage comparator comp2 is connected to the Vy signal; and the inverting input of voltage comparator comp3 is connected to the Vz signal. The output signals a, b, and c of voltage comparators comp1, comp2, and comp3 are connected to the logic control circuit.

[0008] Voltage comparators comp1, comp2, and comp3 have the same structure. Voltage comparator comp1 includes a current bias circuit composed of NMOS transistors M1, M2, and M3. NMOS transistor M2 is connected to the input differential pair transistors M4 and M5. Load NMOS transistors M6 and M7 are connected to the input differential pair transistors M4 and M5, respectively. NMOS transistors M2, M4 to M7 serve as the first-stage amplifier, and M3 and M8 serve as the second-stage amplifier. The final output signal a is shaped by three inverters.

[0009] The logic control circuit is a three-input, four-output decoder, including six inverters and four AND gates, which ultimately output four different signals Y0, Y1, Y2, and Y3. The four signals Y0, Y1, Y2, and Y3 are connected to different reference generation circuits to control the opening and closing of the switch.

[0010] The different reference generation circuits include four series resistors R1, R2, R3, and R4; the lower end of resistor R1 is grounded, the upper end of resistor R1 is connected to one side of switch S1, and the other side of switch S1 is connected to the gate voltage PVIN of the power transistor; the lower end of resistor R2 is connected to resistor R1, the upper end of resistor R2 is connected to one side of switch S2, and the other side of switch S2 is connected to the gate voltage PVIN of the power transistor; the lower end of resistor R3 is connected to resistor R2, the upper end of resistor R3 is connected to one side of switch S3, and the other side of switch S3 is connected to the gate voltage PVIN of the power transistor; the lower end of resistor R4 is connected to resistor R3, the upper end of resistor R4 is connected to the output voltage and one side of switch S4, and the other side of switch S4 is connected to the gate voltage PVIN of the power transistor.

[0011] The logic control circuit converts the three input signals into four control signals to turn on different gate voltages of the power transistors.

[0012] When the load current is less than 700mA, the non-inverting input Vc of voltage comparators comp1, comp2, and comp3 is less than the inverting input voltage, and the output signals a=b=c of the three inverters are all low level. The logic control circuit makes Y0=1, Y1=Y2=Y3=0 to open switch S1, while the other switches remain closed. At this time, the output voltage PVIN is V1.

[0013] When the load current is in the range of 700mA-770mA, the voltage at the non-inverting input of voltage comparator comp1 is greater than the voltage at the inverting input Vx, and the output signal a is high. The voltages at the non-inverting inputs of voltage comparators comp2 and comp3 are both less than the voltages at the inverting inputs, and the output signals b and c are low. Through the logic control circuit, Y1=1, Y0=Y2=Y3=0, switch S2 is opened, and other switches are in the closed state. At this time, the output voltage PVIN is V2.

[0014] When the load current is within the range of 771 mA - 820 mA, the value of the non-inverting terminal Vc of voltage comparator comp1 and voltage comparator comp2 is greater than the values of the inverting terminals Vx and Vy, and the output signals a = b are at high level; the Vc of voltage comparator comp3 < Vz, the output signal c is at low level, and then through the logic control circuit, Y2 = 1, Y0 = Y1 = Y3 = 0 to turn on switch S3, and other switches are in the off state. At this time, the output voltage PVIN is V3;

[0015] When the load current is within the range of 821 mA - 900 mA, the non-inverting terminals of voltage comparators comp1, comp2, and comp3 are all greater than the inverting terminals, and the output signals a = b = c are all at high level. Through the logic control circuit, Y3 = 1, Y0 = Y1 = Y2 = 0 to turn on switch S4, and other switches are in the off state. At this time, the output voltage PVIN is V4.

[0016] The beneficial effects of the present invention are as follows. A circuit for improving the heavy-load efficiency of a switching power supply provided by the present invention. When the system enters a large-current load, due to the influence of conduction loss, the conversion efficiency of the system is limited. To improve the conversion efficiency, it is necessary to reduce the on-resistance, that is, increase the gate-source voltage of the power transistor. Increasing the gate-source voltage of the power transistor will increase the drive loss and switching loss. Therefore, different gate-source voltages need to be adopted according to different load currents to make the conversion efficiency of the system reach the highest. The circuit provided by the present invention has a simple structure, low power consumption, and high efficiency. By using voltage comparators, logic control circuits, and different reference generation circuits, when the system enters a large load current, different gate voltages of the power transistors are turned on, reducing the conduction loss and improving the conversion efficiency of the system under heavy load. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of the circuit for improving the heavy-load efficiency of the switching power supply of the present invention;

[0018] Figure 2 [[ID=十六]]It is a schematic structural diagram of the specific circuit of voltage comparator comp1 in the circuit for improving the heavy-load efficiency of the switching power supply of the present invention;

[0019] Figure 3 Schematic structural diagram of the logic control circuit in the circuit for improving the heavy-load efficiency of the switching power supply of the present invention;

[0020] Figure 4 It is a schematic structural diagram of the different reference generation circuits in the circuit for improving the heavy-load efficiency of the switching power supply of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0022] IDThe circuit of the present invention for improving the heavy-load efficiency of a switching power supply is as follows Figure 1 shown, including voltage comparators comp1, comp2, and comp3. Among the three comparators, the non-inverting input terminal of the first comparator comp1 is connected to the output V C of an error amplifier, the inverting input terminal is connected to a fixed voltage Vx, and the output signal a is connected to the input terminal of a logic control circuit; the non-inverting input terminal of the second comparator comp2 is connected to the output V C of the error amplifier, the inverting input terminal is connected to a fixed voltage Vy, and the output signal b is connected to the input terminal of the logic control circuit; the non-inverting input terminal of the third comparator comp3 is connected to the output V C of the error amplifier, the inverting input terminal is connected to a fixed voltage Vz, and the output signal c is connected to the input terminal of the logic control circuit.

[0023] The output terminals a, b, and c of the three voltage comparators are connected to the input terminals of a logic control circuit, and the output terminals Y0, Y1, Y2, and Y3 of the logic control circuit are connected to the switches S1, S2, S3, and S4 of different reference generation circuits.

[0024] Figure 2 Fig. is the specific circuit diagram of comparator comp1. Among them, NMOS transistors M1 - M3 are current bias circuits, providing bias current for the circuit.

[0025] M4 and M5 are input differential pair transistors, improving the transconductance gm of the circuit. M4 is the non-inverting input terminal, inputting the output signal V C of the error amplifier, M5 is the inverting input terminal, inputting a fixed voltage V X , and NMOS transistors M6 and M7 are used as loads. To obtain high gain, M2, M4 - M7 are used as the first-stage amplifier, and M3 and M8 are used as the second-stage amplifier. The output signal a is finally output after being shaped by three inverters. It mainly compares the magnitudes of the output signal V C of the error amplifier and the fixed voltage Vx. When V C >Vx, the output signal a is at a high level; when V C <Vx, the output signal a is at a low level.

[0026] Figure 3 Fig. is the specific circuit diagram of the logic control circuit, which is a decoder with three inputs and four outputs. It consists of six inverters and four AND gates. Among them, the input terminals are connected to three logic signals a, b, and c, and the output terminals output four logic signals Y0, Y1, Y2, and Y3. When the input signals a = b = c are at a low level, the output signal Y0 is at a high level, and the output signals Y1 = Y2 = Y3 are at a low level. When the input signal a is at a high level and b = c are at a low level, the output signal Y1 is at a high level, and the output signals Y0 = Y2 = Y3 are at a low level.

[0027] When the input signals a = b are at high level and c is at low level, the output signal Y2 is at high level, and the output signals Y0 = Y1 = Y3 are at low level. When the input signals a = b = c are at high level, the output signal Y3 is at high level, and the output signals Y0 = Y1 = Y2 are at low level.

[0028] Figure 4 It is the specific circuit diagram of different reference generation circuits. Among them, the lower end of R1 is grounded, the upper end of R1 is connected to the left side of the switching transistor S1, and the right side of the switching transistor S1 is connected to the gate voltage PVIN of the power transistor. The lower end of R2 is connected to R1, the upper end of R2 is connected to the left side of the switching transistor S2, and the right side of the switching transistor S2 is connected to the gate voltage PVIN of the power transistor. The lower end of R3 is connected to R2, the upper end of R3 is connected to the left side of the switching transistor S3, and the right side of the switching transistor S3 is connected to the gate voltage PVIN of the power transistor. The lower end of R4 is connected to R3, the upper end of R4 is connected to the output voltage and the left side of the switching transistor S4, and the right side of the switching transistor S4 is connected to the gate voltage PVIN of the power transistor. The system uses a BOOST boost converter, and the output voltage is the highest voltage. The output voltage is divided to obtain different reference voltages.

[0029] The working principle of the circuit for improving the heavy load efficiency of the switching power supply in the present invention is as follows Figure 3 As shown, through the logic control circuit, the three input signals are converted into four control signals to turn on different gate voltages of the power transistors. When the load current is less than 700 mA, the non-inverting terminals Vc of the three comparators are all less than the inverting terminal voltage, and the output signals a = b = c of the three inverters are all at low level. Through the logic control circuit, Y0 = 1, Y1 = Y2 = Y3 = 0 to turn on the switch S1, and the other switches remain off. At this time, the output voltage PVIN is V1. When the load current is in the range of 700 mA - 770 mA, the non-inverting terminal voltage of the first comparator comp1 is greater than the inverting terminal voltage Vx, and the output signal a is at high level. The non-inverting terminal voltages of the second and third comparators are both less than the inverting terminal voltage, and the output signals b and c are at low level. Through the logic control circuit, Y1 = 1, Y0 = Y2 = Y3 = 0 to turn on the switch S2, and the other switches are off. At this time, the output voltage PVIN is V2. When the load current is in the range of 771 mA - 820 mA, the non-inverting terminal Vc values of the first comparator comp1 and the second comparator comp2 are greater than the inverting terminals Vx, Vy values, and the output signals a = b are at high level. The third comparator Vc < Vz, and the output signal c is at low level. Then, through the logic control circuit, Y2 = 1, Y0 = Y1 = Y3 = 0 to turn on the switch S3, and the other switches are off. At this time, the output voltage PVIN is V3. When the load current is in the range of 821 mA - 900 mA, the non-inverting terminals of the three comparators are all greater than the inverting terminals, and the output signals a = b = c are all at high level. Through the logic control circuit, Y3 = 1, Y0 = Y1 = Y2 = 0 to turn on the switch S4, and the other switches are off. At this time, the output voltage PVIN is V4.

[0030] When a boost DC-DC converter is under heavy load, the voltage drop across the on-resistance of the power transistor increases, causing energy loss and a decrease in conversion efficiency. Reducing conduction losses can improve heavy-load efficiency; the on-resistance should be:

[0031]

[0032] In the formula, u n For electron mobility, C ox The gate oxide capacitance is W / L, which is the width-to-length ratio of the power transistor, and V is V. GS V is the gate-source voltage of the power transistor. TH This is the threshold voltage of the power transistor.

[0033] Q GATE =CU=It (2);

[0034]

[0035] P GATE =Q GATE ·V IN ·f (4);

[0036] In equation (2) above, C represents the gate capacitance of the power transistor, U is the driving voltage, I is the current flowing through the power transistor, and t is the time required to drive the gate signal of the power switch. In equation (3), I MAX and I MIN t represents the maximum and minimum currents flowing through the power switch. r and t f These represent the rise time and fall time of the gate drive signal for the power switch, respectively. V IN Q is the input voltage of the power transistor, and f is the switching frequency. In equation (4), Q GATE This represents the amount of charge consumed by the gate capacitance of the driving power transistor. From equation (1) above, it can be seen that increasing the gate-source voltage V of the power transistor... GS While this can reduce the on-resistance, it also shows from equation (2) that an increase in the gate-source voltage of the power transistor will cause an increase in the charge, meaning that a large transient current will flow through the power transistor at the moment of conduction, leading to an increase in the switching loss in equation (3) and the drive loss in equation (4). Therefore, in order to maximize efficiency, a compromise is made between the on-resistance, switching loss, and drive loss, and the adaptive on-resistance method of the power transistor is adopted.

[0037] In summary, the power transistor adaptive on-resistance circuit of this invention can open different switches within different load current ranges to obtain different gate voltages of the power transistor. This reduces conduction losses and improves the system's conversion efficiency under heavy loads.

Claims

1. A circuit for improving the heavy-load efficiency of a switching power supply, characterized in that: It includes voltage comparators comp1, comp2, and comp3. The three voltage comparators comp1, comp2, and comp3 are simultaneously and sequentially connected to a logic control circuit and different reference generation circuits; The different reference generation circuits include four series resistors R1, R2, R3, and R4; the lower end of resistor R1 is grounded, the upper end of resistor R1 is connected to one side of switch tube S1, and the other side of switch tube S1 is connected to the gate voltage PVIN of the power tube; the lower end of resistor R2 is connected to resistor R1, the upper end of resistor R2 is connected to one side of switch tube S2, and the other side of switch tube S2 is connected to the gate voltage PVIN of the power tube; the lower end of resistor R3 is connected to resistor R2, the upper end of resistor R3 is connected to one side of switch tube S3, and the other side of switch tube S3 is connected to the gate voltage PVIN of the power tube; the lower end of resistor R4 is connected to resistor R3, the upper end of resistor R4 is connected to the output voltage and one side of switch tube S4, and the other side of switch tube S4 is connected to the gate voltage PVIN of the power tube; The logic control circuit converts the three signals input by the voltage comparators into four control signals to turn on different gate voltages of the power tubes; When the load current is less than 700 mA, the non-inverting terminals Vc of voltage comparators comp1, comp2, and comp3 are all less than the inverting terminal voltage, and the output signals a = b = c of the three inverters are all low levels; through the logic control circuit, Y0 = 1, Y1 = Y2 = Y3 = 0 to turn on switch S1, and the other switches remain off. At this time, the output voltage PVIN is V1; When the load current is in the range of 700 mA - 770 mA, the non-inverting terminal voltage of voltage comparator comp1 is greater than the inverting terminal voltage Vx, and the output signal a is a high level; the non-inverting terminal voltages of voltage comparators comp2 and comp3 are both less than the inverting terminal voltage, and the output signals b and c are low levels. Through the logic control circuit, Y1 = 1, Y0 = Y2 = Y3 = 0 to turn on switch S2, and the other switches are off. At this time, the output voltage PVIN is V2; When the load current is in the range of 771 mA - 820 mA, the non-inverting terminal Vc values of voltage comparator comp1 and voltage comparator comp2 are greater than the inverting terminal Vx and Vy values, and the output signals a = b are high levels; the Vc of voltage comparator comp3 < Vz, and the output signal c is a low level. Then, through the logic control circuit, Y2 = 1, Y0 = Y1 = Y3 = 0 to turn on switch S3, and the other switches are off. At this time, the output voltage PVIN is V3; When the load current is in the range of 821 mA - 900 mA, the non-inverting terminals of voltage comparators comp1, comp2, and comp3 are all greater than the inverting terminals, and the output signals a = b = c are all high levels. Through the logic control circuit, Y3 = 1, Y0 = Y1 = Y2 = 0 to turn on switch S4, and the other switches are off. At this time, the output voltage PVIN is V4.

2. The circuit for improving the heavy-load efficiency of a switching power supply according to claim 1, characterized in that: The non-inverting inputs of voltage comparators comp1, comp2, and comp3 are all connected to the output signal Vc of the error amplifier. The inverting input of voltage comparator comp1 is connected to the Vx signal; the inverting input of voltage comparator comp2 is connected to the Vy signal; and the inverting input of voltage comparator comp3 is connected to the Vz signal. The output signals a, b, and c of voltage comparators comp1, comp2, and comp3 are connected to the logic control circuit.

3. The circuit for improving the heavy-load efficiency of a switching power supply according to claim 2, characterized in that: The voltage comparators comp1, comp2, and comp3 have the same structure. Voltage comparator comp1 includes a current bias circuit composed of NMOS transistors M1, M2, and M3. NMOS transistor M2 is connected to input differential pair transistors M4 and M5. Load NMOS transistors M6 and M7 are connected to input differential pair transistors M4 and M5, respectively. NMOS transistors M2, M4~M7 serve as the first-stage amplifier, and M3 and M8 serve as the second-stage amplifier. The final output signal a is shaped by three inverters.

4. The circuit for improving the heavy-load efficiency of a switching power supply according to claim 2, characterized in that: The logic control circuit is a three-input, four-output decoder, including six inverters and four AND gates, which ultimately output four different signals Y0, Y1, Y2, and Y3. The four signals Y0, Y1, Y2, and Y3 are connected to different reference generation circuits to control the opening and closing of the switch.

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