Enhanced gallium nitride high electron mobility transistor unit chip and circuit system

Abstract

The application relates to an enhanced gallium nitride high electron mobility transistor unit chip and a circuit system. The unit chip comprises an enhanced gallium nitride high electron mobility transistor device body, an adjustable resistance circuit for reducing voltage fluctuation by adjusting resistance, a device metal pad, a resistance metal pad and an on-chip interconnection metal; the adjustable resistance circuit is integrated in the enhanced gallium nitride high electron mobility transistor device body, one end of the adjustable resistance circuit is connected with a gate of the enhanced gallium nitride high electron mobility transistor device body, and the other end is connected with a source of the enhanced gallium nitride high electron mobility transistor device body through a switch or grounded. The circuit system comprises the above-mentioned enhanced gallium nitride high electron mobility transistor unit chip, a driving circuit and a switch, and can further comprise a signal reading and feedback circuit. The application can improve the working stability and safety reliability, and balance the power consumption and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, specifically to the design of an enhanced gallium nitride high electron mobility transistor (GaN HEMT) unit chip and a circuit system using it. Background Technology

[0002] Gallium nitride (GaN) material, due to its excellent physical properties such as wide bandgap, high electron drift velocity, radiation resistance, and high temperature resistance, has become a popular research subject in fields such as high frequency, high temperature, high voltage, and high power. Currently, most mature GaN-based devices are GaN HEMT devices, mainly used in consumer electronics, rail transportation, industrial equipment, and communication base stations.

[0003] For GaN HEMT devices, due to the two-dimensional electron gas (2DEG) generated by the combined piezoelectric and spontaneous polarization effects at the AlGaN / GaN heterojunction interface, conventionally manufactured GaN HEMT devices are depletion-mode devices (D-mode, threshold voltage < 0). This means that GaN HEMT devices still possess a natural conductive channel even without bias, keeping the device in a conducting state at zero bias. Therefore, in practical applications, additional circuitry is needed to apply a negative gate voltage to turn the device off, which complicates the circuitry and increases power consumption. Therefore, for safety, circuit simplification, and to reduce additional power losses, practical applications generally require devices to be enhancement-mode devices (E-mode, threshold voltage > 0V), meaning the device is off when the gate voltage is 0V.

[0004] Currently, common GaN HEMT enhancement technologies include p-GaN gate, grooved gate, and fluoride ion implantation. The main advantages of p-GaN gate technology are stable threshold voltage and high reliability, while its main disadvantages are relatively low threshold voltage and weak gate control capability. The main advantage of grooved gate technology is improved gate control capability, while its main disadvantage is decreased reliability. The main advantage of fluoride ion implantation technology is a relatively high threshold voltage, while its main disadvantage is decreased threshold voltage stability.

[0005] Therefore, on the one hand, due to the characteristics of the device principle and process technology, devices manufactured by different enhancement-mode GaN HEMT technologies still have obvious shortcomings: firstly, the threshold voltage is low, generally around 0.5V, and secondly, the reliability is poor. On the other hand, since the main application areas of GaN HEMT devices are not only power electronics but also radio frequency electronics, GaN HEMTs face inherent circuit problems, such as false triggering and increased power consumption caused by gate voltage fluctuations, reduced switching reliability due to decreased signal drive, and decreased circuit stability due to signal reflection and electromagnetic interference. Summary of the Invention

[0006] The purpose of this invention is to provide an enhanced gallium nitride high electron mobility transistor unit chip that indirectly improves the threshold voltage, enhances stability and safety reliability, and can achieve a balance between power consumption and reliability in different working scenarios.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An enhancement-mode gallium nitride (GaN) high electron mobility transistor (HEMT) chip includes an GNT device body, an adjustable resistor circuit for reducing voltage fluctuations received by the GNT device body by adjusting its resistance value, a device metal pad, a resistor metal pad, and on-chip interconnect metal; the adjustable resistor circuit is integrated into the GNT device body, and the device metal pad and the resistor metal pad are both formed on the surface of the GNT device body; The enhanced gallium nitride high electron mobility transistor device body has a gate electrode, a source electrode, and a drain electrode; the device metal terminal block includes a gate metal terminal block, a source metal terminal block, and a drain metal terminal block; the resistor metal terminal block includes a resistor terminal metal terminal block and a ground terminal metal terminal block, which are respectively connected to the two ends of the switch. The on-chip interconnect metal includes gate interconnect metal connecting the gate electrode and the gate metal terminal block, source interconnect metal connecting the source electrode and the source metal terminal block, drain interconnect metal connecting the drain electrode and the drain metal terminal block, interconnect metal connecting the first terminal of the adjustable resistor circuit to the gate electrode or the first terminal of the gate interconnect metal, interconnect metal connecting the second terminal of the adjustable resistor circuit to the second terminal of the resistor terminal block, and ground interconnect metal connecting the ground terminal block to the ground terminal of the enhancement-mode gallium nitride high electron mobility transistor device body or the source electrode or the source interconnect metal.

[0008] A preferred embodiment is as follows: the adjustable resistor circuit includes a plurality of pull-down resistors, the first end of each pull-down resistor is connected to the gate electrode or the gate interconnect metal through the first end interconnect metal; the resistor metal terminal block includes a plurality of pairs of resistive end metal terminal blocks and ground end metal terminal blocks, each pair of resistive end metal terminal blocks and ground end metal terminal blocks is connected to a corresponding switch, the second end of each pull-down resistor is connected to each resistive end metal terminal block one-to-one through the second end interconnect metal, and each ground end metal terminal block is connected to the ground terminal of the enhancement gallium nitride high electron mobility transistor device body or the source electrode or the source interconnect metal through the ground end interconnect metal.

[0009] In one embodiment, the pull-down resistor is made of TaN material and has a resistance of 1kΩ-10kΩ.

[0010] Furthermore, the pull-down resistor is fabricated using a thin-film resistor process.

[0011] Furthermore, the enhanced gallium nitride high electron mobility transistor device body is an enhanced gallium nitride high electron mobility transistor device fabricated using p-GaN gate, groove gate, or fluorine ion implantation technology.

[0012] Preferably, the enhanced gallium nitride high electron mobility transistor (GaNHPT) unit chip further includes a driving circuit integrated with the GaNHPT device body.

[0013] The present invention also provides a circuit system based on the above-mentioned enhanced gallium nitride high electron mobility transistor unit chip, the solution of which is: An enhanced gallium nitride high electron mobility transistor circuit system, comprising: An enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip, wherein the enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip is the aforementioned enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip; A driving circuit, which is connected to the enhanced gallium nitride high electron mobility transistor unit chip, is used to output a driving signal to the enhanced gallium nitride high electron mobility transistor unit chip; A switch, the two ends of which are respectively connected to the resistive metal terminal block and the ground metal terminal block.

[0014] Another approach to the circuit system based on the aforementioned enhanced gallium nitride high electron mobility transistor (GaN) unit chip is: An enhanced gallium nitride high electron mobility transistor circuit system, comprising: An enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip, wherein the enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip is the aforementioned enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip; A driving circuit, which is connected to the enhanced gallium nitride high electron mobility transistor unit chip, is used to output a driving signal to the enhanced gallium nitride high electron mobility transistor unit chip; A switch, the two ends of which are respectively connected to the resistive metal terminal block and the ground metal terminal block, and the switch has a control terminal for receiving control signals; A signal reading and feedback circuit is connected to the drive circuit and the control terminal of the switch, respectively, for detecting the drive signal and outputting the control signal based on the drive signal to control the opening and closing of the switch.

[0015] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art: The present invention directly improves the working stability and safety reliability of the device and circuit by adding an adjustable resistor circuit in the unit chip, and indirectly improves the threshold voltage of the enhanced gallium nitride high electron mobility transistor device, thus achieving a balance between power consumption and reliability. Attached Figure Description

[0016] Appendix Figure 1 This is a cross-sectional schematic diagram of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0017] Appendix Figure 2 This is an equivalent circuit diagram of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0018] Appendix Figure 3 This is a schematic diagram of step 0 in the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0019] Appendix Figure 4 This is a schematic diagram of step 1 of the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0020] Appendix Figure 5 This is a schematic diagram of step 2 in the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0021] Appendix Figure 6 This is a schematic diagram of step 3 in the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0022] Appendix Figure 7 This is a schematic diagram of step 4 in the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0023] Appendix Figure 8 This is a schematic diagram of step 5 in the fabrication process of the enhanced gallium nitride high electron mobility transistor unit chip of the present invention.

[0024] In the attached diagrams above: 1. Enhanced gallium nitride high electron mobility transistor device body; 2. Adjustable resistor circuit; 3. Metal terminal block for the device; 4. Metal terminal block for the resistor; 5. On-chip interconnect metal; 101. Gate electrode; 102. Source electrode; 103. Drain electrode; 104. Substrate; 105. Buffer layer; 106. Channel layer; 107. Barrier layer; 108. Cap layer; 109. Two-dimensional electron gas; 110. p-GaN gate; 111. Device isolation; 112. First passivation layer; 113. Second passivation layer; 114. Polyimide layer; 21. Pull-down resistor / film resistor; 31. Gate metal terminal block; 32. Source metal terminal block; 33. Drain metal terminal block; 41. Metal terminal block for resistance; 42. Metal terminal block for ground; 51. Gate interconnect metal; 52. Source interconnect metal; 53. Drain interconnect metal; 54. Second-terminal interconnect metal. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] Example 1: As shown in the attached document Figure 1 and attached Figure 2 As shown, an enhanced gallium nitride high electron mobility transistor (GaNHEMT) unit chip includes an enhanced gallium nitride high electron mobility transistor device body 1, an adjustable resistor circuit 2, a device metal terminal block 3, a resistor metal terminal block 4, and an on-chip interconnect metal 5.

[0028] The enhancement-mode gallium nitride high electron mobility transistor (EMT) device body 1 can be an EMT device fabricated using p-GaN gate, recessed gate, fluorine ion implantation technology, or other existing technologies, and it has a gate electrode 101, a source electrode 102, and a drain electrode 103. This embodiment takes a unit chip composed of an EMT device fabricated using p-GaN gate technology as an example.

[0029] The adjustable resistor circuit 2 is integrated within the body 1 of the enhanced gallium nitride high electron mobility transistor device 1, and is used to reduce voltage fluctuations received by the enhanced gallium nitride high electron mobility transistor device body 1 by adjusting the resistance value.

[0030] A metal terminal block 3 is formed on the surface of the enhancement-mode gallium nitride high electron mobility transistor (GMT-HMT) device body 1, providing terminals for connecting the GMT-HMT device body 1. The metal terminal block 3 includes a gate metal terminal block 31, a source metal terminal block 32, and a drain metal terminal block 33. A resistor metal terminal block 4 is also formed on the surface of the GMT-HMT device body 1, providing terminals for connecting the adjustable resistor circuit 2. The resistor metal terminal block 4 includes a resistive terminal metal terminal block 41 connected to both ends of the switch and a ground terminal metal terminal block 42.

[0031] The on-chip interconnect metal 5 is formed within the body 1 of the enhancement-mode gallium nitride high electron mobility transistor (GMT) device, and includes gate interconnect metal 51, source interconnect metal 52, drain interconnect metal 53, first-terminal interconnect metal, second-terminal interconnect metal 54, and ground interconnect metal. Gate interconnect metal 51 connects the gate electrode 101 to the gate metal terminal block 31, source interconnect metal 52 connects the source electrode 102 to the source metal terminal block 32, and drain interconnect metal 53 connects the drain electrode 103 to the drain metal terminal block 33. The first-terminal interconnect metal (not shown) connects the first terminal of the adjustable resistor circuit 2 to the gate electrode 101, or connects the first terminal of the adjustable resistor circuit 2 to the gate interconnect metal 51, thereby achieving the connection between the first terminal of the adjustable resistor circuit 2 and the gate of the GMT device body 1. The second-terminal interconnect metal 54 connects the second terminal of the adjustable resistor circuit 2 to the resistive terminal metal terminal block 41. The ground interconnect metal (not shown in the figure) connects the ground metal terminal block 42 to the ground terminal GND of the enhancement gallium nitride high electron mobility transistor device body 1, or connects the ground metal terminal block 42 to the source electrode 102, or connects the ground metal terminal block 42 to the source interconnect metal 52, thereby connecting the ground metal terminal block 42 to the ground terminal GND or the source electrode Source of the enhancement gallium nitride high electron mobility transistor device body 1.

[0032] The adjustable resistor circuit 2 includes multiple pull-down resistors 21, and the resistor metal terminal block 4 includes multiple pairs of resistive metal terminal blocks 41 and ground metal terminal blocks 42. That is, the number of pull-down resistors 21 is equal to the number of pairs of resistive metal terminal blocks 41 and ground metal terminal blocks 42, with one pull-down resistor 21 corresponding to one pair of resistive metal terminal blocks 41 and ground metal terminal blocks 42. A switch can be connected between each pair of resistive metal terminal blocks 41 and ground metal terminal blocks 42. One end of each pull-down resistor 21 is connected to the gate electrode 101 or gate interconnect metal 51 through its corresponding first-terminal interconnect metal segment. The second end of each pull-down resistor 21 is connected to each resistive metal terminal block 41 through its corresponding second-terminal interconnect metal segment 54. Each ground metal terminal block 42 is connected to the ground terminal GND or source electrode 102 or source interconnect metal 52 of the enhancement-mode gallium nitride high electron mobility transistor device body 1 through its corresponding ground interconnect metal segment. The resulting circuit is as follows: each pull-down resistor 21 is connected in series with a switch to form a series circuit. These series circuits are then connected in parallel and connected between the gate and ground of the GaN high electron mobility transistor (GaN HMT) device body 1, or between the gate and source of the GaN HMT device body 1. The pull-down resistor 21 can be controlled by opening and closing the switch. In this embodiment, as shown in the attached... Figure 2 As shown, two pull-down resistors R1 and R2 with different resistance values ​​are set, and two switches K1 and K2 are configured accordingly. Thus, by opening and closing switches K1 and K2, three different resistance values ​​can be achieved. The pull-down resistor 21 is made of TaN material, but other materials can also be used; its resistance value is 1kΩ-10kΩ. The switches can be led out from the resistors via a terminal block and implemented on the packaged unit chip.

[0033] The metal terminal block 3 for the device, the metal terminal block 4 for the resistor, and the on-chip interconnect metal 5 can be fabricated using conventional GaN HEMT processes.

[0034] The aforementioned enhanced gallium nitride high electron mobility transistor (GNTH) unit chip with adjustable resistor circuit 2 operates as follows: When a voltage fluctuation higher than the threshold voltage of the GNTH device body 1 occurs in the circuit or its driving circuit where the GNTH unit chip is located, the parallel pull-down resistor 21 can pull down the high voltage fluctuation, so that the high voltage fluctuation is not directly applied to the GNTH device body 1. The voltage applied to the GNTH device body 1 is reduced, which is equivalent to indirectly increasing the threshold voltage of the GNTH device, thereby ensuring the normal operation of the GNTH device body 1 and the circuit.

[0035] Depending on the operating environment, the switching on and off of each switch corresponding to the pull-down resistor 21 can be configured. By changing the switching on and off of different switches corresponding to the pull-down resistor 21 in the parallel structure, the total resistance value of the pull-down resistor 21 can be changed, forming circuits with different combinations of pull-down resistor 21. This allows the device and circuit to achieve a balance between power consumption and reliability in different operating scenarios. The adjustable resistor circuit 2 formed by the pull-down resistors 21 indirectly increases the threshold voltage of the enhancement-mode gallium nitride high electron mobility transistor device, directly improving the operating stability and reliability of the device and circuit.

[0036] The pull-down resistor 21 is fabricated using thin-film resistor technology and integrated into the body 1 of the enhancement-mode gallium nitride high electron mobility transistor device. Compared with active GaN HEMT devices, the cost of adding a thin-film resistor process is lower. Furthermore, this solution is compatible with various mainstream enhancement-mode GaN HEMT technologies and can retain the advantages of each technology.

[0037] The following section uses a p-GaN gate enhancement-mode gallium nitride high electron mobility transistor (GaN HEMT) device as an example to illustrate the fabrication process of an enhancement-mode gallium nitride high electron mobility transistor unit chip.

[0038] Step 0: Preparation of epitaxial wafers.

[0039] The epitaxial structure of a GaN HEMT device, from bottom to top, generally includes several layers such as a substrate, nucleation layer, superlattice layer, buffer layer, channel layer, spacer layer, charge supply layer, barrier layer, and cap layer. The specific structure and composition vary depending on factors such as the performance and cost requirements of the GaN HEMT device. (See attached...) Figure 3 As shown, in this embodiment, the epitaxial layer, from bottom to top, includes a substrate 104, a buffer layer 105, a channel layer 106, a barrier layer 107, and a cap layer 109. Further, it includes a silicon (Si) or sapphire or silicon carbide (SiC) substrate 104, a GaN buffer layer 105, a GaN channel layer 106, an AlGaN barrier layer 107, and a p-GaN cap layer 109.

[0040] Step 1 is attached. Figure 4 As shown: Device fabrication, specifically including the fabrication of p-GaN gate 110, device isolation 111, and source / drain ohmic contact electrodes.

[0041] ① For the p-GaN gate 110, a photolithography process is performed using a photolithography machine (stepper photolithography machine), and the p-GaN gate 110 is fabricated on the p-GaN cap layer 109 using dry etching (IPC dry etching); ② For device isolation 111, a photolithography process is performed using a photolithography machine (stepper photolithography machine), and ion implantation is used to complete the fabrication of device isolation 111 in the upper half of AlGaN barrier layer 107, GaN channel layer 106 and GaN buffer layer 105. ③ For the source / drain ohmic contact electrodes (i.e., source electrode 102 and drain electrode 103), a photolithography process is performed using a photolithography machine (stepper photolithography machine); ④ Etch (IPC etching) AlGaN barrier layer 107, and further etch into GaN channel layer 106, so that the etching depth reaches the depth of two-dimensional electron gas (2EDG) 109 (shown by red dashed line in the figure); ⑤ The source / drain ohmic contact electrodes (i.e., source electrode 102 and drain electrode 103) are fabricated using E-beam evaporation, stripping, and annealing processes (800~900℃, 30s).

[0042] Step 2 is attached. Figure 5 As shown: Device fabrication, specifically including the fabrication of the gate Schottky contact electrode.

[0043] ① For the gate Schottky contact electrode (gate electrode 101), a photolithography process is performed using a photolithography machine (stepper photolithography machine); ② The gate Schottky contact electrode (gate electrode 101) is completed on the p-GaN cap layer 109 by E-beam evaporation and stripping.

[0044] Step 3 is attached. Figure 6 As shown: Device fabrication, specifically including the fabrication of thin-film resistor 21, i.e., pull-down resistor 21.

[0045] ① A first passivation layer 112 is grown using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) techniques. The material of the first passivation layer 112 is SiO2 or Si3N4. ② For the thin film resistor 21, a photolithography process is performed using a photolithography machine (stepper photolithography machine); ③ A thin film resistor 21 is grown on the first passivation layer 112 using a sputtering process.

[0046] Step 4 is attached. Figure 7 As shown: Device fabrication, specifically including the fabrication of on-chip interconnect metal 5.

[0047] ① A second passivation layer 113 is grown on the first passivation layer 112 and the thin film resistor 21 using plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) technology. The material of the second passivation layer 113 is SiO2 or Si3N4. ② Photolithography is performed on the gate interconnect metal 51, source interconnect metal 52, drain interconnect metal 53, first terminal interconnect metal, second terminal interconnect metal 54, and ground terminal interconnect metal using a photolithography machine (stepper photolithography machine); ③ Etch (RIE etching) the second passivation layer 113 to create openings at the required locations of the on-chip interconnect metal 5 (such as the top of the gate electrode 101, the top of the source electrode 102, the top of the drain electrode 103, the top of the thin film resistor 21, etc.); ④ Use E-beam vapor deposition to grow interconnect metals within each wafer 5.

[0048] Step 5 is attached. Figure 8 As shown: Component fabrication, specifically including the fabrication of component terminal blocks and resistor terminal blocks.

[0049] ① Coating with polyimide to form a polyimide layer 114; ② For the terminal blocks for devices and the terminal blocks for resistors, a photolithography machine (stepper photolithography machine) is used for photolithography. ③ A metal seed layer is sputtered on the polyimide layer 114, and an E-beam metal layer is evaporated to form a terminal block for the device and a terminal block for the resistor.

[0050] Example 2: Based on the enhanced gallium nitride high electron mobility transistor unit chip of Example 1, the enhanced gallium nitride high electron mobility transistor unit chip may further include a driver circuit (Rc is the equivalent resistance of the driver circuit), which can be integrated with the enhanced gallium nitride high electron mobility transistor device body 1 through existing process technology.

[0051] Example 3: A circuit system comprising the enhancement-mode gallium nitride high electron mobility transistor (GMT-HMT) unit chip, a driver circuit, and corresponding switches as described in Example 1. The driver circuit is connected to the GMT-HMT unit chip and outputs a drive signal to the GMT-HMT unit chip. The two ends of the switch are connected to a resistive metal terminal block 41 and a ground metal terminal block 42, respectively.

[0052] Example 4: A circuit system comprising the enhancement-mode gallium nitride high electron mobility transistor (GMT-HMT) unit chip, a driver circuit, a switch, and a signal readout and feedback circuit as described in Example 1. The driver circuit is connected to the GMT-HMT unit chip and outputs a drive signal to it. The two ends of the switch are connected to a resistive metal terminal block 41 and a ground metal terminal block 42, respectively. The switch also has a control terminal for receiving control signals, enabling automatic opening and closing based on these signals. The signal readout and feedback circuit is connected to both the driver circuit and the control terminal of the switch, detecting the drive signal and outputting a control signal to control the opening and closing of the switch. Under the action of the signal readout and feedback circuit, voltage fluctuations based on the drive signal can be automatically adjusted by connecting a pull-down resistor of the corresponding value to reduce the voltage fluctuations.

[0053] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. An enhanced gallium nitride high electron mobility transistor unit chip, characterized in that: The enhanced gallium nitride high electron mobility transistor (GaNHMT) unit chip includes an enhanced gallium nitride HNHMT device body, an adjustable resistor circuit that reduces voltage fluctuations received by the enhanced gallium nitride HNHMT device body by adjusting the resistance value, a device metal pad, a resistor metal pad, and on-chip interconnect metal; the adjustable resistor circuit is integrated into the enhanced gallium nitride HNHMT device body, and the device metal pad and the resistor metal pad are both formed on the surface of the enhanced gallium nitride HNHMT device body; The enhanced gallium nitride high electron mobility transistor device body has a gate electrode, a source electrode, and a drain electrode; the device metal terminal block includes a gate metal terminal block, a source metal terminal block, and a drain metal terminal block; the resistor metal terminal block includes a resistor terminal metal terminal block and a ground terminal metal terminal block, which are respectively connected to the two ends of the switch. The on-chip interconnect metal includes gate interconnect metal connecting the gate electrode and the gate metal terminal block, source interconnect metal connecting the source electrode and the source metal terminal block, drain interconnect metal connecting the drain electrode and the drain metal terminal block, interconnect metal connecting the first terminal of the adjustable resistor circuit to the gate electrode or the first terminal of the gate interconnect metal, interconnect metal connecting the second terminal of the adjustable resistor circuit to the second terminal of the resistor terminal block, and ground interconnect metal connecting the ground terminal block to the ground terminal of the enhancement-mode gallium nitride high electron mobility transistor device body or the source electrode or the source interconnect metal.

2. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 1, characterized in that: The adjustable resistor circuit includes multiple pull-down resistors, and the first end of each pull-down resistor is connected to the gate electrode or the gate interconnect metal through the first end interconnect metal. The resistor metal terminal block includes multiple pairs of resistive end metal terminal blocks and ground end metal terminal blocks, and a switch is connected between each pair of resistive end metal terminal blocks and ground end metal terminal blocks. The second end of each pull-down resistor is connected to each resistive end metal terminal block one-to-one through the second end interconnect metal. Each ground end metal terminal block is connected to the ground terminal of the enhancement gallium nitride high electron mobility transistor device body or the source electrode or the source interconnect metal through the ground end interconnect metal.

3. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 2, characterized in that: The pull-down resistor is made of TaN material.

4. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 2, characterized in that: The pull-down resistor has a resistance value of 1kΩ-10kΩ.

5. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 2, characterized in that: The pull-down resistor is fabricated using thin-film resistor technology.

6. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 1, characterized in that: The enhanced gallium nitride high electron mobility transistor device body is an enhanced gallium nitride high electron mobility transistor device fabricated using p-GaN gate, groove gate, or fluorine ion implantation technology.

7. The enhanced gallium nitride high electron mobility transistor unit chip according to claim 1, characterized in that: The enhanced gallium nitride high electron mobility transistor (GaN high electron mobility transistor) unit chip also includes a driving circuit integrated with the GaN high electron mobility transistor device body.

8. An enhanced gallium nitride high electron mobility transistor circuit system, characterized in that: The enhanced gallium nitride high electron mobility transistor circuit system includes: An enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip, wherein the enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip is the enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip as described in any one of claims 1 to 6; A driving circuit, which is connected to the enhanced gallium nitride high electron mobility transistor unit chip, is used to output a driving signal to the enhanced gallium nitride high electron mobility transistor unit chip; A switch, the two ends of which are respectively connected to the resistive metal terminal block and the ground metal terminal block.

9. An enhanced gallium nitride high electron mobility transistor circuit system, characterized in that: The enhanced gallium nitride high electron mobility transistor circuit system includes: An enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip, wherein the enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip is the enhanced gallium nitride high electron mobility transistor (GaNHMT) cell chip as described in any one of claims 1 to 6; A driving circuit, which is connected to the enhanced gallium nitride high electron mobility transistor unit chip, is used to output a driving signal to the enhanced gallium nitride high electron mobility transistor unit chip; A switch, the two ends of which are respectively connected to the resistive metal terminal block and the ground metal terminal block, and the switch has a control terminal for receiving control signals; A signal reading and feedback circuit is connected to the drive circuit and the control terminal of the switch, respectively, for detecting the drive signal and outputting the control signal based on the drive signal to control the opening and closing of the switch.

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