A substrate positioning method and system based on wafer vision recognition

Abstract

The present invention discloses a substrate positioning method and system based on wafer vision recognition. By pre-collecting a complete wafer image and a single-substrate image of a single substrate contained in the wafer, obtaining a feature recognition anchor box according to the complete wafer image, real-time collecting a high-resolution wafer image, and obtaining a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box, fitting a grid map reflecting the etching lines according to the substrate contour map, matching the single-substrate image with the wafer grayscale image corresponding to the high-resolution wafer image according to the grid map, marking the substrate, and positioning the substrate according to the substrate marking result, the technical problem of low accuracy of the existing wafer vision positioning substrate is solved. It can not only fit different wafer etching lines in real time and plan coordinates, has strong adaptability, but also has high positioning accuracy.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of wafer vision recognition, and particularly refers to a substrate positioning method and system based on wafer vision recognition. Background Art

[0002] Wafer vision recognition technology is one of the key processes in the chip manufacturing industry. It is used to achieve precise positioning and recognition of each integrated circuit chip on the wafer. The basic principle of wafer positioning technology is: capture the wafer surface image through an image acquisition device such as a CCD or CMOS image sensor, and then use image processing technology to perform operations such as image segmentation and feature extraction on the image to identify the contour and center position of each chip area. Calculate the precise position and mapping coordinates of each chip based on this information, provide a position reference for subsequent processes such as scanning, exposure, or testing, and achieve automated precise positioning. Compared with traditional mechanical positioning, the vision-based wafer positioning technology has the following advantages:

[0003] 1) High precision. Using image processing technology can achieve sub-micron positioning accuracy, meeting the strict requirements of integrated circuit manufacturing.

[0004] 2) High automation. Wafer recognition is an automated image processing process that does not require manual intervention and can greatly improve production efficiency.

[0005] 3) Direct positioning. Obtain positioning information directly based on the real wafer image without pre-defining a coordinate system, avoiding the slight errors introduced thereby.

[0006] 4) High adaptability. The algorithm has a certain self-learning and adaptation ability, can better adapt to wafers of different batches or specifications, and meet production requirements.

[0007] 5) Non-contact. As an optical positioning method, vision positioning technology realizes non-contact positioning of the wafer, avoiding problems such as surface damage caused by mechanical contact.

[0008] Vision recognition technology provides an efficient and reliable wafer automatic positioning method for the semiconductor manufacturing industry, is an important means to achieve high automation and production volume, and has very important significance for ensuring product quality and improving productivity. It develops rapidly and is constantly innovating, and has also become one of the most active research directions in this technical field.

[0009] The invention patent with the publication number CN102472759B provides a method for identifying the center position of a picking object based on an image autocorrelation algorithm. It calculates the autocorrelation function of the image and locates the center by finding the peak points, thus achieving the positioning purpose. However, when there are complex patterns or noises on the picking object, multiple false peaks will be generated in the autocorrelation function, resulting in misidentification of the center of the picking object and inability to achieve accurate positioning.

[0010] The invention patent with the publication number US7796807B2 proposes a visual positioning method based on image sharpness and periodicity. It infers the chip area by analyzing the sharpness and repeating patterns of the image to achieve rough positioning. However, this method is overly dependent on image quality. Once the lighting conditions change, the sharpness will change, making it difficult to stably identify. At the same time, it is also unable to accurately position irregularly shaped chips.

[0011] The invention patent with the publication number US8222618B2 proposes a wafer visual positioning method based on template matching. It stores multiple chip templates and determines the approximate positions of each chip according to the matching scores. However, the template matching algorithm has a large template dependence. When the chip batches or designs are frequently changed, a large number of templates need to be re-entered, making it difficult to achieve dynamic recognition and automatic adaptation. Moreover, for the case where the chip structure is relatively complex, the effect of template matching is also poor, and the positioning accuracy is difficult to guarantee. Summary of the Invention

[0012] A substrate positioning method and system based on wafer vision recognition provided by the present invention solve the technical problem of low accuracy in positioning the substrate by existing wafer vision.

[0013] To solve the above technical problem, a substrate positioning method based on wafer vision recognition proposed by the present invention includes:

[0014] Pre-collect a complete wafer image and a single substrate image of a single substrate included in the wafer.

[0015] Obtain feature recognition anchor boxes according to the complete wafer image.

[0016] Real-time collect a high-resolution wafer image and obtain a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor boxes.

[0017] Fit a grid map reflecting the etching lines according to the substrate contour map.

[0018] Match the single substrate image and the wafer grayscale image corresponding to the high-resolution wafer image according to the grid map, and mark the substrate.

[0019] Locate the substrate according to the substrate marking result.

[0020] Further, obtaining the feature recognition anchor box according to the complete wafer image includes:

[0021] Performing grayscale processing on the complete wafer image to obtain a complete wafer grayscale image.

[0022] Using the Canny operator to detect the edges of the complete wafer grayscale image and performing binarization processing to obtain a complete wafer vein map, where the set of pixel point coordinates constituting the complete wafer vein map is represented as:

[0023] Net = {(u, v)|f(u, v) = 0, 0 ≤ u ≤ N - 1, 0 ≤ v ≤ M - 1, u, v ∈ Z},

[0024] where Net represents the set of pixel point coordinates of the complete wafer vein map, M and N are respectively the number of rows and columns of the complete wafer vein map pixels, f(u, v) is the grayscale value of the pixel point (u, v) in the complete wafer vein map, and Z represents integers.

[0025] Performing row scanning on the complete wafer vein map, retaining the first pixel point with a grayscale level of 0 and the last pixel point with a grayscale level of 0 scanned in each row to obtain the outer circular contour of the complete wafer.

[0026] Removing the outer circular contour of the complete wafer to obtain a wafer grid.

[0027] Performing row scanning on the wafer grid, recording the coordinates of the first point with a grayscale level of 0 and the last point with a grayscale level of 0 scanned in each row to obtain the left and right row boundaries of each row of the wafer grid.

[0028] According to the left and right row boundaries of each row of the wafer grid, draw an initial contour curve outside the wafer grid and construct a functional for extracting the pseudo-edge suppression criterion.

[0029] Extract the contour curve corresponding to the minimum value of the functional for extracting the pseudo-edge suppression criterion as the feature recognition anchor box.

[0030] Further, the specific formula for constructing the functional for extracting the pseudo-edge suppression criterion is:

[0031]

[0032] where F represents the functional for extracting the pseudo-edge suppression criterion, P(s) = [u(s), v(s)] represents the dynamic contour curve, s is the contour arc length normalized to the [0, 1] interval, α, β, and λ are respectively positive first, second, and third weight factors, f(u, v) is the grayscale value of the pixel point at the coordinate (u, v) in the complete wafer vein map, and u and v are both integers, is the indicator function; B is the open operation structuring element, is an opening operation operator; x1'(i) and x2'(i) are the abscissas of the first and last pixels marked as edges in the i-th row during the row scanning of the scanned wafer grid, respectively, and m' and n' are the ordinates of the upper and lower bounds of the wafer grid.

[0033] Further, the real-time acquisition of the high-resolution image of the wafer and obtaining the substrate contour map corresponding to the high-resolution image of the wafer based on the feature recognition anchor box includes:

[0034] Real-time acquisition of the high-resolution image of the wafer, performing grayscale processing on the high-resolution image of the wafer to obtain a high-resolution grayscale wafer image.

[0035] Using the Canny operator to detect the edges of the high-resolution grayscale wafer image and performing binarization processing to obtain a high-resolution wafer vein map.

[0036] Project the feature recognition anchor box onto the high-resolution wafer vein image and calculate the cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image.

[0037] Rotate the wafer at a preset angle every preset time, and obtain the high-resolution wafer vein map corresponding to the rotated wafer and calculate the cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image corresponding to the rotated wafer until the wafer rotates one circle, and obtain the high-resolution wafer vein map corresponding to the maximum cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image as the substrate contour map.

[0038] Further, according to the substrate contour map, fitting the grid map reflecting the etching lines includes:

[0039] Obtain a set of contour pixel points according to the contour pixel points in the substrate contour map.

[0040] Arbitrarily select two contour pixel points from the set of contour pixel points to construct a fitting line.

[0041] Calculate the fitting distance from the other contour pixel points in the set of contour pixel points except those used to construct the fitting line to the fitting line.

[0042] Select the contour pixel points with a fitting distance greater than the preset distance as the fitting points corresponding to the fitting line.

[0043] When it is determined that the number of times of constructing the fitting line satisfies the number of times of constructing the fitting line, take the fitting line corresponding to the most fitting points as the optimal fitting etching line.

[0044] Delete the contour pixel points corresponding to the optimal fitting etching line from the set of contour pixel points and update the set of contour pixel points;

[0045] Continue to iteratively fit the optimal etching line according to the updated set of contour pixel points until the set of contour pixel points is included in the pixel points of the outer circular contour of the complete wafer.

[0046] Obtain a grid map reflecting the etching line according to the optimal etching line.

[0047] Further, after fitting the grid map reflecting the etching line, before matching the wafer grayscale map corresponding to the single substrate image and the high-resolution wafer image according to the grid map, it includes:

[0048] Select the optimal etching line obtained from the first fitting as the X coordinate axis, and calculate the slope of the optimal etching line obtained from the first fitting as the first slope.

[0049] Select the optimal etching line when the product of the slope of the optimal etching line and the first slope is negative for the first time during the fitting process as the Y coordinate axis.

[0050] Construct a matching coordinate axis according to the X coordinate axis and the Y coordinate axis.

[0051] Further, when matching the wafer grayscale map corresponding to the single substrate image and the high-resolution wafer image according to the grid map, marking the substrate includes:

[0052] Directly project the grid map onto the wafer grayscale map corresponding to the high-resolution image to obtain a sub-region substrate map.

[0053] Calculate the similarity between the single substrate image and the sub-region substrate map, and mark the substrate corresponding to the sub-region substrate map with a similarity greater than the preset similarity threshold to the single substrate image as a non-defective substrate, otherwise do not mark it. The specific formula for calculating the similarity between the single substrate image and the sub-region substrate map is:

[0054]

[0055] Among them, H is the similarity, E represents the integral, I g and I s are the sub-region substrate map and the single substrate image respectively, δ(I g , i) and δ(I s , i) represent the gray distribution operators of the sub-region substrate map and the single substrate image at the i-th gray level respectively, and f g (p) is the gray value at the pixel point p in the sub-region substrate map, m and n are the number of rows and columns of the pixels in the single substrate image respectively, and i ∈ [0, 255].

[0056] Further, according to the substrate marking result, positioning the substrate includes:

[0057] Calculate the relative coordinates of spatial transformation based on the positions of the matching coordinate axes and the substrate marking results, and feedback the relative coordinates of spatial transformation to the pick-up head manipulator.

[0058] A substrate positioning system based on wafer vision recognition provided by the present invention includes:

[0059] A memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of a substrate positioning method based on wafer vision recognition provided by the present invention are implemented.

[0060] The substrate positioning method and system based on wafer vision recognition proposed by the present invention, by pre-collecting a complete wafer image and a single substrate image of a single substrate contained in the wafer, obtaining a feature recognition anchor box according to the complete wafer image, collecting a high-resolution wafer image in real time, and obtaining a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box, fitting a grid map reflecting the etching lines according to the substrate contour map, matching the single substrate image with the wafer gray-scale image corresponding to the high-resolution wafer image according to the grid map, marking the substrate, and positioning the substrate according to the substrate marking results, solves the technical problem of low accuracy of existing wafer vision-based substrate positioning. It can not only fit different wafer etching lines in real time and plan coordinates, but also has strong adaptability and high positioning accuracy.

[0061] The beneficial effects of the present invention specifically include:

[0062] ① The present invention designs a substrate positioning method based on wafer vision recognition, which can fit wafer etching lines in real time and plan coordinates, and has strong adaptability.

[0063] ② The present invention designs a substrate positioning method based on wafer vision recognition, which can cleverly use the etching lines to construct a world coordinate system and divide the available substrate blocks. Position the starting point of the pick-up head directly above the intersection of the etching lines, which simplifies the subsequent coordinate calculation of each single substrate.

[0064] ③ The present invention designs a substrate positioning method based on wafer vision recognition, which extracts a functional using the designed pseudo-edge suppression criterion, selects regions for relatively complex wafer veins, and at the same time avoids the interference of a large number of redundant lead-out lines, providing a feasible method for wafer pose correction and positioning. Description of the Drawings

[0065] Figure 1 It is a flowchart of the substrate positioning method based on wafer vision recognition according to the second embodiment of the present invention;

[0066] Figure 2 It is a schematic diagram of the edge detection result according to the second embodiment of the present invention;

[0067] Figure 3 Schematic diagram of coordinate marking of matching blocks according to the second embodiment of the present invention;

[0068] Figure 4 Schematic diagram of pick-up head positioning using the second embodiment of the present invention; (Do Vx, Vy, etc. in the figure need to be explained in the embodiment?)

[0069] Figure 5 Block diagram of the substrate positioning system based on wafer vision recognition according to the embodiment of the present invention.

[0070] Reference numerals:

[0071] 10. Memory; 20. Processor. Detailed implementation manners

[0072] To facilitate the understanding of the present invention, the following will describe the present invention more comprehensively and meticulously in conjunction with the accompanying drawings of the specification and preferred embodiments. However, the protection scope of the present invention is not limited to the following specific embodiments.

[0073] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings. However, the present invention can be implemented in many different ways defined and covered by the claims.

[0074] Embodiment 1

[0075] The substrate positioning method based on wafer vision recognition provided by the first embodiment of the present invention includes:

[0076] Step S101: Pre-collect a complete wafer image and a single substrate image of a single substrate included in the wafer.

[0077] Step S102: Obtain a feature recognition anchor box according to the complete wafer image.

[0078] Step S103: Real-time collect a high-resolution wafer image, and obtain a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box.

[0079] Step S104: Fit a grid map reflecting the etching lines according to the substrate contour map.

[0080] Step S105: Match the single substrate image and the wafer grayscale image corresponding to the high-resolution wafer image according to the grid map, and mark the substrate.

[0081] Step S106: Locate the substrate according to the substrate marking result.

[0082] The substrate positioning method based on wafer vision recognition provided by the embodiments of the present invention acquires a complete wafer image and a single substrate image of a single substrate included in the wafer in advance, obtains a feature recognition anchor box according to the complete wafer image, acquires a high-resolution wafer image in real time, and obtains a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box. According to the substrate contour map, a grid map reflecting the etching lines is fitted. According to the grid map, the single substrate image is matched with the wafer grayscale image corresponding to the high-resolution wafer image, the substrate is marked, and the substrate is positioned according to the substrate marking result, solving the technical problem of low accuracy of the existing wafer vision positioning substrate. It can not only fit different wafer etching lines in real time and plan coordinates, but also has strong adaptability and high positioning accuracy.

[0083] Specifically, for the substrate positioning method based on wafer vision recognition in the embodiments of the present invention, when the substrates in the industrial process do not belong to the same batch and the model changes temporarily, this method is still applicable. It can fit different wafer etching lines in real time and plan coordinates, and has strong adaptability.

[0084] Embodiment 2

[0085] There are various reasons for wafer loss in the process flow, including but not limited to severe collision damage to the wafer during improper transportation, uneven or excessive polishing resulting in local thinning of the wafer, offset of the slicing knife, improper chamfering operation, and improper adjustment of laser etching parameters. In modern process flows, every effort has been made to avoid wafer loss or wafer damage. To further reduce yield loss, the present invention designs a substrate positioning method based on wafer vision recognition, providing a reliable and efficient idea for the positioning operation before the wafer pick-up head sucks a qualified substrate.

[0086] In the general industrial process, the center of the wafer is first identified to obtain the center coordinates and radius of the wafer. Then, according to the center coordinates, the center coordinates of each substrate are converted into relative coordinates relative to the center of the wafer. This is a common way to construct a coordinate system for the movement of the robotic arm in the industrial process. Moreover, when actually acquiring the wafer image, the etching lines are not clear, which interferes with the method of visually identifying and positioning the substrate, resulting in inaccurate positioning. In this embodiment, to simplify the process, a substrate positioning method with a simple idea and easy to understand is designed. A straight line reflecting the trend of the etching lines is fitted using the edge of the substrate, and a coordinate axis is constructed based on this straight line to achieve accurate positioning.

[0087] As Figure 1 shown, the specific process of the embodiments of the present invention includes:

[0088] 1. At the start of detection, the robotic arm controls the pick-up head to move quickly. When it moves above the wafer, the pick-up head stops moving, and at this time, it enters the preprocessing operation process. The pick-up head positioning schematic diagram of the embodiments of the present invention is as Figure 4 shown.

[0089] 2. The equipment has not been put into operation yet, and preprocessing operations are carried out. The specific content is as follows:

[0090] ① Obtain a single-chip substrate image in advance to prepare for subsequent steps. The acquisition method is to extract the image of a single tiny substrate from the wafer, and the quality of this substrate is intact. Place it on a clean workbench and take a single-chip substrate image at a height of h. Use this substrate image as the traversal template I s .

[0091] ② Obtain a high-resolution image of a complete wafer in advance to prepare for subsequent steps. The acquisition method is to take a complete wafer with intact quality, place it on a clean workbench, and take a complete wafer image I at a height of h directly above the wafer h .

[0092] 3. Carry out feature recognition anchor box extraction. The specific content is as follows:

[0093] ① Wafer grid extraction. For the obtained complete wafer image I h perform grayscale processing, and filter the image to reduce the impact on subsequent edge detection. This grayscale image is named I h '. Use the Canny operator to detect the edges of image I h ' and perform binary processing on the image to obtain the edge detection result as a standard wafer vein map. Record the pixel point coordinates that make up the vein in the set Net, that is: (1)

[0094] Net = {(u, v)|f(u, v) = 0, 0 ≤ u ≤ N - 1, 0 ≤ v ≤ M - 1, u, v ∈ Z} (1)

[0095] M and N are the number of rows and columns of the wafer vein image pixels, and f(u, v) is the grayscale value of the corresponding pixel point.

[0096] Perform row scanning on the edge detection result, and retain the first pixel point with a grayscale level of 0 and the last pixel point with a grayscale level of 0 scanned in each row. After scanning, obtain the outer circular contour of the wafer:

[0097] 1) Assume the image is of size M×N, and scan the i-th row, i ∈ [1, M].

[0098] 2) Find the first pixel point marked as an edge in the i-th row, and record its abscissa as x1(i).

[0099] 3) Find the last pixel point marked as an edge in the i-th row, and record the abscissa as x2(i).

[0100] 4) Repeat the above operations for each row to obtain multiple sets of coordinate pairs (x1(i), x2(i)). Assume that the vertical coordinates of the upper and lower bounds of the wafer are m and n respectively. The set of pixel points on the outer contour of the wafer can be expressed as:

[0101] Cir = {(x1(i), i)|i = m, m + 1,..., n} ∪ {(x2(i), i)|i = m, m + 1,..., n} (2)

[0102] Remove the outer contour of the wafer grid to obtain the inner grid of the wafer:

[0103]

[0104] ② Feature recognition anchor box extraction.

[0105] Perform a row scan on the inner grid of the wafer, record the coordinates of the first point with a gray level of 0 and the last point with a gray level of 0 scanned in each row. After scanning, obtain the left and right row boundaries of each row of the wafer grid:

[0106] 1) Assume the image size is M×N, scan the i-th row, i ∈ [1, M].

[0107] 2) Find the first pixel point marked as an edge in the i-th row and record its abscissa as x1'(i).

[0108] 3) Find the last pixel point marked as an edge in the i-th row and record the abscissa as x2'(i).

[0109] 4) Repeat the above operations for each row to obtain multiple sets of coordinate pairs (x1'(i), x2'(i)). Assume that the vertical coordinates of the upper and lower bounds of the grid are m' and n' respectively. The set of left and right row boundaries of each row of the wafer grid can be expressed as:

[0110] Grd = {(x1'(i), i)|i = m', m' + 1,..., n'} ∪ {(x2'(i), i)|i = m', m' + 1,..., n'} (4)

[0111] The above formula represents the range occupied by the wafer grid in the overall image. The following operations are carried out within this range.

[0112] In this embodiment, a method is designed to effectively extract the feature recognition anchor box. The meaning of this anchor box is: the boxed area is the largest boxed area that can contain the largest number of complete wafer substrates. Therefore, each wafer has one and only one such area box, that is, it has uniqueness. Therefore, it can be used as a feature recognition criterion for wafer pose correction and substrate positioning.

[0113] Draw an initial contour curve outside the wafer grid and construct a functional for extracting the pseudo-edge suppression criterion:

[0114]

[0115] Among them, P(s) = [u(s), v(s)] represents the dynamic contour curve, s is the contour arc length normalized to the interval [0, 1], which can be regarded as the proportional parameter of the contour perimeter. Among them, the first derivative term controls the curve continuity, the second derivative term controls the curve smoothness, and α, β, and λ are positive weight factors respectively. f(u, v) is the gray value of the pixel at the coordinate (u, v), and both u and v are integers. is the indicator function, and B is the morphological opening structuring element. is the morphological opening operator. The original wafer grid is structurally complemented using the designed algorithm to obtain a filled image with consistent gray values for each internal pixel. Since the wafer grid map contains a large number of edge leads, morphological opening is performed to suppress these pseudo-edges, and finally the contour fitting term is constructed using the gradient operator ▽.

[0116] The dynamic contour curve moves and deforms in the image. Finally, when the functional F of the pseudo-edge suppression criterion reaches the minimum value, the contour curve fits the outermost boundary of the wafer grid, and the contour curve at this time is the feature recognition anchor box.

[0117] 4. The device starts operation and performs rotation correction based on the feature recognition anchor box. The specific content is as follows:

[0118] ① When a substrate wafer is placed in a specific area of the workbench, control the industrial RGB camera inside the pick-up head to take a picture to obtain a single-frame high-resolution image I of the wafer o , if the image is acquired based on the video stream, then super-resolution reconstruction is performed on the sequence diagram if necessary to obtain a single-frame high-resolution image of the wafer.

[0119] ② Perform grayscale processing on the obtained high-resolution image I of the wafer o , and perform filtering operation on the image to reduce the influence on subsequent edge detection. This grayscale image is named I g , and is saved in the memory.

[0120] ③ Use the Canny operator to detect the edges of the image I g and perform binary processing on the image to obtain the edge detection result as a wafer vein map. For the convenience of subsequent pick-up head positioning and grasping, it is necessary to perform rotation correction on the wafer based on the feature recognition anchor box.

[0121] ④ Rotation correction operation based on the recognition anchor box. Simply project the feature recognition anchor box onto the current wafer vein image for comparison. Assume that the coordinates of each pixel point on the anchor box form a set L, and record the coordinates of the pixel points that make up the current wafer vein in the set Dot, that is:

[0122] Dot = {(u, v)|f(u, v) = 0, 0 ≤ u ≤ N - 1, 0 ≤ v ≤ M - 1, u, v ∈ Z} (6)

[0123] Where M and N are the number of rows and columns of the pixels in the wafer vein image, and f(u, v) is the gray value of the corresponding pixel. Every t time, the wafer is rotated by a small angle to θ° and the above steps ①-③ are repeated, that is, the wafer vein images at each moment are obtained in real time based on the video stream and compared with the fixed feature recognition anchor box. θ ∈ (0, 360), and the set Dot is updated in real time. When and only when the wafer rotates one full circle:

[0124]

[0125] That is, there is exactly one angle θ° such that the cardinality of the intersection of the two sets reaches the maximum value. At this time, the rotation correction ends, and the anchor box is registered with the wafer vein to ensure that the wafer is placed correctly at this time and the veins are horizontal and vertical, facilitating subsequent pick-up head positioning and grasping. It should be noted that in this embodiment, the cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image specifically refers to the number of overlapping pixels between the feature recognition anchor box and the high-resolution wafer vein image.

[0126] At this time, the edge detection result schematic diagram I as shown in Figure 2 is obtained. e . Figure 2 In it, S1 and S2 represent different defective substrate contours shown in the edge detection result; S2 represents the missing substrate contour shown in the edge detection result; S3 represents the wafer edge substrate contour that cannot be used.

[0127] The image shows the contours of each complete substrate in the wafer. At the same time, irregular contours at the damaged parts of the substrate, contours at large missing areas of the wafer, and wafer corner material substrate contours can be clearly observed in the image. However, in actual operation, this ideal imaging cannot be achieved. Since the substrates are closely attached to each other, the etching lines are not clearly shown, and the image needs to be further processed to obtain accurate information about the etching lines.

[0128] 5. Optimize the etching path and register the reference system.

[0129] ① For the substrate contour diagram I e , record the coordinates of all contour pixels in Dot, that is:

[0130] Dot = {(u, v)|f(u, v) = 0, 0 ≤ u ≤ N - 1, 0 ≤ v ≤ M - 1, u, v ∈ Z} (8)

[0131] Where M and N are the number of rows and columns of the pixels in the wafer vein image, and f(u, v) is the gray value of the corresponding pixel.

[0132] ②Optimize the etching path. Randomly select two different points (u1, v1) and (u2, v2) in Dot, and construct a fitting line l1 through these two points. Calculate the distance d from the remaining pixel points in Dot to the fitting line l1 i (i = 1, 2, 3, …, n - 2) to judge the fitting degree, that is, d i <η (η is a pre-set small threshold. When the distance is less than this threshold, it can be considered that the pixel point is on the fitting line). The pixel points that meet the above conditions are recorded as "fitting points". Count the number of fitting points and record it as P1, and the corresponding set is represented as Del1.

[0133] ③Repeat the above steps m times to obtain multiple numbers of fitting points P i (i = 1, 2, 3, …, m). Find the maximum number of fitting points max{P1, P2,..., P m} by comparison, record its subscript as j. At this time, the corresponding fitting line is the optimal fitting etching line. After determining the current etching line, delete all the corresponding fitting points from Dot, so as to update Dot and find the next optimal fitting etching line, that is:

[0134]

[0135] ④According to the number of fitting lines k required for the actual wafer's etching lines, repeat the above steps ② and ③ k times, so as to perform linear fitting on each etching line of the current wafer to form a grid map. Take the etching line of the first fitting and the etching line of the second fitting. When the wafer damage is not very serious, the fitting points corresponding to these two fitting lines are the most, so they are closest to the center of the circle. If the product of their slopes is positive, then take the etching line of the third fitting, and so on until the product of the slopes with the first fitting line is negative, which approximately represents that the two lines are orthogonal and close to the center of the circle. Take the two lines to form the x and y axis directions of the world coordinate system, only for positioning without lowering the pick-up probe, so the z axis is not described, and the intersection point is marked on the image. So far, the coordinate axis registration is completed.

[0136] 6. Find the matching block and make marking points. The single-chip substrate image I has been obtained in the preprocessing s , take the wafer grayscale image I corresponding to the high-resolution image g , and project the grid directly and simply onto the wafer grayscale image I g . Then this grayscale image is divided into several sub-regions I g1 , I g2 , I g3 , …, I gn , and define the operator:

[0137]

[0138] δ(I, i) represents the gray - level distribution operator of image I at the i - th gray - level. f(p) is the gray - level value at pixel point p, i is each gray - level from 0 to 255, and m, n represent the number of rows and columns of pixels in the single - substrate image I. s Perform template matching between I s and each sub - region, that is:

[0139]

[0140] where H is the similarity, E represents the integral, I g and I s are the sub - region substrate map and the single - substrate image respectively. δ(I g , i) and δ(I s , i) represent the gray - level distribution operators of the sub - region substrate map and the single - substrate image at the i - th gray - level respectively, and f g (p) is the gray - level value at pixel point p in the sub - region substrate map, m and n are the number of rows and columns of pixels in the single - substrate image respectively, and i ∈ [0, 255].

[0141] Preset a threshold H s , when H ∈ [0, H s )), it can be considered that the sub - region I gi (i = 1, 2, …, n) has a high similarity with the traversed template I s , and mark its corresponding position (the center of the rectangle) on the gray - scale image; similarly, when , it is considered that the sub - region I gi (i = 1, 2, …, n) has a low similarity with the traversed template, and do not mark this sub - region block. The marking result is as shown in Figure 3 , Figure 3 where S4 in it is the preset ideal substrate pattern for matching good substrates in the coordinate marking step.

[0142] 7. The pick - up head starts to be calibrated and moves to directly above the origin of the world coordinate. Given the x, y axes and the origin of the world coordinate system, calculate the relative coordinates according to the position of the marked points, and feed the coordinate information back to the pick - up head manipulator for path planning.

[0143] 8. After the route planning is completed, the pick - up head starts to perform the pick - up action.

[0144] The substrate positioning method based on wafer vision recognition provided by the embodiment of the present invention pre-collects a complete wafer image and a single substrate image of a single substrate included in the wafer, obtains a feature recognition anchor box according to the complete wafer image, real-time collects a high-resolution image of the wafer, and obtains a substrate contour map corresponding to the high-resolution image of the wafer based on the feature recognition anchor box. According to the substrate contour map, a grid map reflecting the etching line is fitted. According to the grid map, the single substrate image is matched with the wafer grayscale image corresponding to the high-resolution image of the wafer, the substrate is marked, and according to the substrate marking result, the substrate is positioned, solving the technical problem of low accuracy of the existing wafer vision positioning substrate. It can not only fit different wafer etching lines in real time and plan coordinates, has strong adaptability, but also has high positioning accuracy.

[0145] Embodiment III

[0146] The cleanliness of the wafer surface will affect the qualification rate of subsequent semiconductor processes and products. Even among all yield losses, up to 50% is due to wafer surface contamination or defects. The integrity of the wafer surface characterizes the wafer yield rate and has an important impact on the subsequent semiconductor processes and product qualification rate. There are various reasons for wafer defects in the process flow, including but not limited to severe collision damage to the wafer during improper transportation, uneven or excessive polishing resulting in local thinning of the wafer, offset of the slicing knife, improper chamfering operation, and improper adjustment of laser etching parameters. In modern process flows, every effort has been made to avoid wafer defects or wafer damage. To further reduce yield losses, instead of discarding the above unqualified wafers, they are maximally utilized. The embodiment of the present invention realizes the purpose of only picking up the good substrates on the wafer by designing a substrate positioning method based on wafer vision recognition, thereby abandoning the defective substrates and the unusable corner substrates at the wafer edge, and avoiding picking up actions at the substrate defect locations (saving working hours). In summary, the purpose of maximizing the utilization of the wafer with a low yield rate substrate and further reducing yield losses is achieved.

[0147] The specific steps of Embodiment III of the present invention are as follows:

[0148] 1. At the start of detection, the robotic arm controls the pick-up head to move quickly. When it moves above the wafer, the pick-up head stops moving, and at this time, it enters the preprocessing operation process.

[0149] 2. Before the equipment is put into operation, preprocessing operations are carried out. The specific content is as follows:

[0150] ① Obtain a single substrate image in advance as a preparation for the subsequent steps, and use this substrate image as the traversal template I s .

[0151] ② Obtain a high-resolution image I of a complete wafer in advance h as a preparation for the subsequent steps.

[0152] 3. Extract feature recognition anchor frames. The specific contents are as follows:

[0153] ① Wafer grid extraction. Perform edge detection to obtain a standard wafer vein map, and record the coordinates of the pixel points that make up the vein in the set Net.

[0154] The result after edge detection is scanned in rows, and the first pixel with gray level 0 and the last pixel with gray level 0 scanned in each row are retained, and the circular outline of the wafer exterior is obtained after scanning. Then the outer outline of the wafer grid is eliminated to obtain the internal grid of the wafer.

[0155] ② Feature recognition anchor frame extraction.

[0156] Scan the internal grid of the wafer in rows, record the coordinates of the first point with a gray level of 0 and the last point with a gray level of 0 in each row, and obtain the left and right row boundaries of each row of the wafer grid after scanning. That is, the range occupied by the wafer grid in the overall image is obtained, and the following operations are performed within this range.

[0157] A method is designed to effectively extract the feature recognition anchor frame: the initial contour curve is drawn outside the wafer grid, and a pseudo-edge suppression criterion extraction functional is constructed. The dynamic contour curve moves and deforms in the image. Finally, when the pseudo-edge suppression criterion extraction functional F reaches the minimum value, the contour curve coincides with the outermost boundary of the wafer grid. The contour curve at this time is the feature recognition anchor frame.

[0158] 4. The equipment starts to be put into operation, and rotation correction is performed based on the feature recognition anchor frame. The specific contents are as follows:

[0159] ① Obtain a single-frame wafer high-resolution image I o . For the acquired wafer high-resolution image I o Grayscale processing is performed and the image is filtered to reduce the impact on subsequent edge detection. The grayscale image is named I g , stored in memory. Detection image I g The edges are binarized and the edge detection result is a wafer vein map.

[0160] ② Rotation correction operation based on the recognition anchor frame. Simply project the feature recognition anchor frame to the current wafer vein image for comparison. Assume that the coordinates of each pixel point on the anchor frame constitute a set L, and record the coordinates of the pixel points that make up the current wafer vein in the set Dot. Rotate the wafer at a small angle every time t and repeat the above steps ①-③. That is, obtain the wafer vein map at each moment in real time based on the video stream and compare it with the fixed feature recognition anchor frame. The set Dot is updated in real time. The rotation correction ends if and only if, during the rotation process, there is only one angle θ° that maximizes the cardinality of the intersection of the two sets. At this time, we get Figure 2Schematic Diagram I of Edge Detection Results Shown e 。

[0161] 5. Perform etching path optimization and reference system registration.

[0162] ① For the substrate contour diagram I e , record the coordinates of all contour pixel points in Dot.

[0163] ② Perform etching path optimization. Randomly select two different points (u1, v1), (u2, v2) in Dot, and construct a fitting line l1 through these two points. Calculate the distance from the remaining pixel points in Dot to the fitting line l1 to judge the fitting degree, that is, d i < θ (θ is a preset small threshold. When the distance is less than this threshold, it can be considered that the pixel point is on the fitting line). The pixel points that meet the above conditions are recorded as "fitting points", and the number of fitting points is counted and recorded as P1, and the corresponding set is represented as Del1.

[0164] ③ Repeat the above steps m times to obtain multiple numbers of fitting points P i (i = 1, 2, 3,..., m). Find the largest number of fitting points P among them through comparison max . At this time, the fitting line corresponding to it is the optimal fitting etching line. After determining the current etching line, delete all the corresponding fitting points from Dot, so as to update Dot and find the next optimal fitting etching line.

[0165] ④ Select the required number of fitting lines k according to the etching lines required by the actual wafer, and repeat the above steps ② and ③ k times to form a grid diagram. Take the etching line of the first fitting and the etching line of the second fitting. If the product of their slopes is positive, then take the etching line of the third fitting, and so on until the product of the slopes with the first fitting line is negative, which approximately represents that the two lines are orthogonal and close to the center of the circle. Take the two lines to form the x and y axis directions of the world coordinate system, and mark the intersection point on the image. So far, the coordinate axis registration is completed.

[0166] 6. Find the matching blocks and make marking points. In the preprocessing, the single-chip substrate image I has been obtained s . Take the wafer grayscale image I saved in the preprocessing g , and directly project the grid simply onto the wafer grayscale image I g . Then the grayscale image is divided into several sub-regions. I s Perform template matching with each sub-region. If the sub-region has a high similarity with the traversed template I s , make a mark at the center of the corresponding substrate rectangle on the grayscale image; do not make a mark on the sub-region block with low similarity to the template.

[0167] 7. The pick-up head starts calibration and moves to directly above the origin of the world coordinate system. Given the x and y axes and the origin of the world coordinate system, the relative coordinates are calculated based on the positions of the marking points, and the coordinate information is fed back to the pick-up head manipulator for path planning.

[0168] 8. After the route planning is completed, the pick-up head starts the picking action.

[0169] The substrate positioning method based on wafer vision recognition provided by the embodiment of the present invention, by collecting the wafer image and the single substrate image of the single substrate included in the wafer, grayscaling the wafer image to obtain the wafer grayscale image, performing edge detection on the wafer grayscale image to obtain the substrate contour image, fitting a grid image reflecting the etching lines according to the substrate contour image, matching the single substrate image and the wafer grayscale image according to the grid image, marking the substrate, and positioning the substrate according to the substrate marking result, solves the technical problem of low accuracy of the existing wafer vision positioning substrate. It can not only fit different wafer etching lines in real time and plan coordinates, has strong adaptability, but also has high positioning accuracy.

[0170] Specifically, for the substrate positioning method based on wafer vision recognition in the embodiment of the present invention, when the substrates in the industrial process do not belong to the same batch and the model changes temporarily, this method is still applicable. It can fit different wafer etching lines in real time and plan coordinates, and has strong adaptability.

[0171] In addition, the embodiment of the present invention can cleverly use the etching lines to construct the world coordinate system and divide the available substrate blocks. The starting point of the pick-up head operation is positioned directly above the intersection of the etching lines, which simplifies the subsequent coordinate calculation of each single substrate. And even if the wafer is deflected, this fitting method can still handle this situation well and construct an inclined coordinate system.

[0172] Refer to Figure 5 , the substrate positioning system based on wafer vision recognition proposed by the embodiment of the present invention includes a memory 10, a processor 20, and a computer program stored on the memory 10 and executable on the processor 20. Among them, when the processor 20 executes the computer program, it implements the steps of the substrate positioning method based on wafer vision recognition proposed in this embodiment.

[0173] The specific working process and working principle of the substrate positioning system based on wafer vision recognition in this embodiment can refer to the working process and working principle of the substrate positioning method based on wafer vision recognition in this embodiment.

[0174] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A substrate positioning method based on wafer vision recognition, characterized in that, The method includes: Pre-collecting a complete wafer image and a single substrate image of a single substrate included in the wafer; Obtaining a feature recognition anchor box according to the complete wafer image; Real-time collecting a high-resolution wafer image, and obtaining a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box; Fitting a grid map reflecting the etching line according to the substrate contour map; Matching the single substrate image and the wafer grayscale image corresponding to the high-resolution wafer image according to the grid map, and marking the substrate; Positioning the substrate according to the substrate marking result.

2. The substrate positioning method based on wafer vision recognition according to claim 1, characterized in that Obtaining a feature recognition anchor box according to the complete wafer image includes: Performing grayscale processing on the complete wafer image to obtain a complete wafer grayscale image; Using the Canny operator to detect the edges of the complete wafer grayscale image and performing binary processing to obtain a complete wafer vein map, where the set of pixel point coordinates constituting the complete wafer vein map is expressed as: Net = {(u, v)|f(u, v) = 0, 0 ≤ u ≤ N - 1, 0 ≤ v ≤ M - 1, u, v ∈ Z}, where Net represents the set of pixel point coordinates of the complete wafer vein map, M and N are respectively the number of rows and columns of the complete wafer vein map pixels, f(u, v) is the grayscale value of the pixel point (u, v) in the complete wafer vein map, and Z represents an integer; Performing a row scan on the complete wafer vein map, retaining the first pixel point with a grayscale level of 0 and the last pixel point with a grayscale level of 0 scanned in each row to obtain the outer circular contour of the complete wafer; Removing the outer circular contour of the complete wafer to obtain a wafer grid; Performing a row scan on the wafer grid, recording the coordinates of the first point with a grayscale level of 0 and the last point with a grayscale level of 0 scanned in each row to obtain the left and right row boundaries of each row of the wafer grid; According to the left and right row boundaries of each row of the wafer grid, drawing an initial contour curve outside the wafer grid and constructing a functional for extracting the pseudo-edge suppression criterion; Extracting the contour curve corresponding to the minimum value of the functional for extracting the pseudo-edge suppression criterion as the feature recognition anchor box.

3. The substrate positioning method based on wafer vision recognition according to claim 2, wherein The specific formula for constructing the functional for extracting the pseudo-edge suppression criterion is: Among them, F represents the functional extracted by the pseudo-edge suppression criterion, P(s) = [u(s), v(s)] represents the dynamic contour curve, s is the contour arc length normalized to the interval [0, 1], α, β, and λ are the positive first, second, and third weight factors respectively, f(u, v) is the gray value of the pixel at the coordinate (u, v) in the complete wafer vein map, and both u and v are integers. is the indicator function, and B is the morphological opening structuring element. is the morphological opening operator. x1'(i) and x2'(i) are the abscissas of the first and last pixels marked as edges found in the i-th row during the row scanning of the scanned wafer grid, respectively. m' and n' are the ordinates of the upper and lower bounds of the wafer grid.

4. The substrate positioning method based on wafer vision recognition according to claim 3, characterized in that, Real-time collecting a high-resolution wafer image, and obtaining a substrate contour map corresponding to the high-resolution wafer image based on the feature recognition anchor box includes: Real-time collecting a high-resolution wafer image, performing grayscale processing on the high-resolution wafer image to obtain a high-resolution wafer grayscale image; Using the Canny operator to detect the edges of the high-resolution wafer grayscale image and performing binary processing to obtain a high-resolution wafer vein map; Projecting the feature recognition anchor box onto the high-resolution wafer vein image and calculating the cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image; Rotating the wafer at a preset angle every preset time, obtaining the high-resolution wafer vein map corresponding to the rotated wafer and calculating the cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image corresponding to the rotated wafer until the wafer rotates one circle, and obtaining the high-resolution wafer vein map corresponding to the maximum cardinality of the intersection of the feature recognition anchor box and the high-resolution wafer vein image as the substrate contour map.

5. The substrate positioning method based on wafer vision recognition according to any one of claims 1-4, characterized in that, Fitting a grid map reflecting the etching line according to the substrate contour map includes: Obtain a set of contour pixel points according to the contour pixel points in the substrate contour map; Arbitrarily select two contour pixel points from the set of contour pixel points to construct a fitting line; Calculate the fitting distance from the other contour pixel points in the set of contour pixel points except those used to construct the fitting line to the fitting line; Select the contour pixel points with a fitting distance greater than the preset distance as the fitting points corresponding to the fitting line; When it is determined that the number of times of constructing the fitting line satisfies the number of times of constructing the fitting line, take the fitting line corresponding to the most fitting points as the optimal fitting etching line; Delete the contour pixel points corresponding to the optimal fitting etching line from the set of contour pixel points and update the set of contour pixel points; According to the updated set of contour pixel points, continue to iteratively fit the optimal fitting etching line until the set of contour pixel points is included in the pixel points of the outer circular contour of the complete wafer; Obtain a grid map reflecting the etching line according to the optimal fitting etching line; 6. The substrate positioning method based on wafer vision recognition according to claim 5, characterized in that, Before matching the wafer grayscale map corresponding to the single-chip substrate image and the wafer high-resolution image after fitting the grid map reflecting the etching line, it includes: Select the optimal fitting etching line obtained in the first fitting as the X coordinate axis, and calculate the slope of the optimal fitting etching line obtained in the first fitting as the first slope; Select the optimal fitting etching line when the product of the slope of the optimal fitting etching line and the first slope is negative for the first time during the fitting process as the Y coordinate axis; Construct a matching coordinate axis according to the X coordinate axis and the Y coordinate axis; 7. The substrate positioning method based on wafer vision recognition according to claim 6, wherein When matching the wafer grayscale map corresponding to the single-chip substrate image and the wafer high-resolution image according to the grid map and marking the substrate, it includes: Directly project the grid map onto the wafer grayscale map corresponding to the high-resolution image to obtain a sub-region substrate map; Calculate the similarity between the single-chip substrate image and the sub-region substrate map, and mark the substrate corresponding to the sub-region substrate map with a similarity greater than the preset similarity threshold to the single-chip substrate image as a non-defective substrate, otherwise do not mark it. The specific formula for calculating the similarity between the single-chip substrate image and the sub-region substrate map is: Among them, H is the similarity, E represents the integral, and I g and I s are the sub-region substrate map and the single-chip substrate image respectively. δ(I g , i) and δ(I s , i) represent the gray-level distribution operators of the sub-region substrate map and the single-chip substrate image at the i-th gray level respectively, and f g (p) is the gray value at the pixel point p in the sub-region substrate map, m and n are the number of rows and columns of the single-chip substrate image pixels respectively, and i ∈ [0, 255].

8. The substrate positioning method based on wafer vision recognition according to claim 7, characterized in that According to the substrate marking result, position the substrate, including: Calculate the spatial transformation relative coordinates according to the matching coordinate axis and the position of the substrate marking result, and feed the spatial transformation relative coordinates back to the pick-up head manipulator; 9. A substrate positioning system based on wafer vision recognition, the system includes: A memory (10), a processor (20), and a computer program stored on the memory (10) and executable on the processor (20), characterized in that when the processor (20) executes the computer program, it implements the steps of the method according to any one of claims 1 to 8 above.

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