Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The method first uses a second mask layer to form a first non-injection region in a first mask layer, and then uses a third mask layer to form a first trench in the first mask layer. This divides the first non-injection region in the first mask layer into the first trench. The divided first non-injection region is used to form a first structural trench. That is, the region in the first mask layer used to form the first trench and the first structural trench is defined and formed by the second and third mask layers. This method can overcome the limitations of existing photolithography processes, allowing the second interconnect and connecting interconnect formed in the first structural trench to form a bidirectional winding structure, improving design flexibility and freedom, and helping to simplify the process and save process costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] Photolithography is a commonly used patterning method and one of the most critical production technologies in semiconductor manufacturing. With the continuous miniaturization of semiconductor process nodes, self-aligned double patterning (SADP) has become a favored patterning method in recent years. This method can increase the density of patterns formed on the substrate and further reduce the pitch between adjacent patterns, thus enabling photolithography to overcome the limitations of photolithography resolution.

[0004] However, due to limitations in photolithography, existing methods for forming semiconductor structures suffer from operational complexity, resulting in relatively low efficiency in forming semiconductor structures. Summary of the Invention

[0005] The problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to overcome the limitations of existing photolithography processes, simplify process operations, and save process costs.

[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate comprising a layer to be etched;

[0008] A first mask layer and a second mask layer located on the first mask layer are formed on the layer to be etched;

[0009] Ion implantation is performed on the first mask layer using the second mask layer as a mask to form a first non-implanted region extending along the first direction;

[0010] After forming the first non-injection region, a third mask layer is formed on the first mask layer. The third mask layer has a plurality of first openings. The first openings extend along the first direction and are spaced apart along the first direction. On a projection plane parallel to the substrate, the first openings at least partially overlap with the first non-injection region, such that the first non-injection region is divided by the first openings to form a first structural pattern. The first structural pattern includes a first pattern and a second pattern. The first patterns extend along the first direction and are spaced apart along the second direction. The second patterns are located between adjacent first openings and extend along the second direction to the non-ends of adjacent first patterns, such that adjacent first patterns are connected by the second pattern. The first direction is perpendicular to the second direction.

[0011] The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer;

[0012] Based on the first trench, the area where the first structural pattern is located in the first non-injection region is etched away, and a first structural trench is formed in the first mask layer; the first structural trench includes a second trench corresponding to the first pattern and a first connection trench corresponding to the second pattern;

[0013] The first trench and the layer to be etched at the bottom of the first structural trench are graphically visualized to form a target pattern.

[0014] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising:

[0015] A substrate, the substrate comprising a layer to be etched;

[0016] A first interconnect trench located in the layer to be etched; the first interconnect trench extends along a first direction and is spaced apart along the first direction;

[0017] The second interconnect trench is located in the layer to be etched, the second interconnect trench extends along the first direction and is spaced apart along the second direction, and the first interconnect trench is located between adjacent second interconnect trenches and spaced apart from the second interconnect trenches along the second direction; the second direction is perpendicular to the first direction;

[0018] The interconnecting trench is located in the layer to be etched, the interconnecting trench is located between the adjacent second interconnecting trenches and extends along the second direction to the non-end of the adjacent second interconnecting trenches, such that the adjacent second interconnecting trenches are connected through the interconnecting trench, and the first interconnecting trench is located on both sides of the interconnecting trench along the second direction.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a layer to be etched; forming a first mask layer and a second mask layer located on the first mask layer on the layer to be etched; performing ion implantation on the first mask layer using the second mask layer as a mask to form a first non-implanted region extending along a first direction; after forming the first non-implanted region, forming a third mask layer on the first mask layer, the third mask layer having a plurality of first openings; the first openings extending along the first direction and spaced apart along the first direction, and on a projection plane parallel to the substrate, the first openings at least partially overlap with the first non-implanted region, such that the first non-implanted region is divided by the first openings to form a first structural pattern; the first structural pattern includes a first pattern and a second pattern, wherein... The first pattern extends along a first direction and is spaced apart along a second direction. The second pattern is located between adjacent first openings and extends along the second direction to the non-ends of adjacent first patterns, such that adjacent first patterns are connected by the second pattern. The first direction is perpendicular to the second direction. The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer. Based on the first trench, the area where the first structural pattern is located in the first non-injection area is etched away to form a first structural trench in the first mask layer. The first structural trench includes a second trench corresponding to the first pattern and a first connecting trench corresponding to the second pattern. The layer to be etched is etched using the first sidewall layer and the first mask layer as masks to form the target pattern.

[0021] As can be seen, by using a second mask layer to form a first non-injection region in the first mask layer, and then using a third mask layer to form a first trench in the first mask layer, the first non-injection region in the first mask layer is divided by the first trench. The divided first non-injection region is used to form the first structural trench. That is, the region in the first mask used to form the first trench and the first structural trench is defined and formed by the second mask layer and the third mask layer. This can overcome the limitations of existing photolithography processes, and enable the second interconnect and the connecting interconnect formed in the etchable layer below the first structural trench to form a bidirectional winding structure, which improves the flexibility and freedom of design, and helps to simplify the process and save process costs. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a semiconductor structure;

[0023] Figures 2 to 11 This is a schematic diagram of the intermediate structure formed by each step of a semiconductor structure formation method in an embodiment of the present invention. Detailed Implementation

[0024] As can be seen from the background technology, the existing self-aligned dual patterning method in the back-end process has low performance of the semiconductor structure formed due to the limitations of photolithography process.

[0025] Please see Figure 1 A semiconductor structure includes a substrate, the substrate including a layer to be etched (not shown), the layer to be etched having first interconnects 11 and second interconnects 12 extending along a first direction and spaced apart along a second direction. The second interconnects 12 are connected to each other via third interconnects 21 disposed on different layers and corresponding plugs (not shown) to form a bidirectional winding structure with the first interconnects 11.

[0026] Therefore, in order to realize the dual-wire winding structure in the above semiconductor structure, the second interconnect 12 needs to be electrically connected through the third interconnect 21 and the corresponding plugs in different layers. The operation process is relatively complicated and limits the freedom and flexibility of the design.

[0027] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a layer to be etched; forming a first mask layer and a second mask layer on the layer to be etched; performing ion implantation on the first mask layer using the second mask layer as a mask to form a first non-implanted region extending along a first direction; after forming the first non-implanted region, forming a third mask layer on the first mask layer, the third mask layer having a plurality of first openings; the first openings extending along the first direction and spaced apart along the first direction, and on a projection plane parallel to the substrate, the first openings at least partially overlap with the first non-implanted region, such that the first non-implanted region is divided by the first openings to form a first structural pattern; the first structural pattern includes a first pattern and a second pattern. The first pattern extends along a first direction and is spaced apart along a second direction. The second pattern is located between adjacent first openings and extends along the second direction to the non-ends of adjacent first patterns, such that adjacent first patterns are connected by the second pattern. The first direction is perpendicular to the second direction. The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer. Based on the first trench, the area where the first structural pattern is located in the first non-injection area is etched away to form a first structural trench in the first mask layer. The first structural trench includes a second trench corresponding to the first pattern and a first connecting trench corresponding to the second pattern. The layer to be etched is etched using the first sidewall layer and the first mask layer as masks to form a target pattern.

[0028] As can be seen, by using a second mask layer to form a first non-injection region in the first mask layer, and then using a third mask layer to form a first trench in the first mask layer, the first non-injection region in the first mask layer is divided by the first trench. The divided first non-injection region is used to form the first structural trench. That is, the region in the first mask used to form the first trench and the first structural trench is defined and formed by the second mask layer and the third mask layer. This can overcome the limitations of existing photolithography processes, and enable the second interconnect and the connecting interconnect formed in the etchable layer below the first structural trench to form a bidirectional winding structure, which improves the flexibility and freedom of design, and helps to simplify the process and save process costs.

[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] The following will combine Figures 2 to 11 A method for forming a semiconductor structure according to an embodiment of the present invention will be described in further detail.

[0031] See Figure 2 A substrate is provided, the substrate including a layer 100 to be etched.

[0032] The substrate provides a process platform for subsequent process manufacturing.

[0033] The substrate can be a silicon substrate or a germanium substrate, etc. Furthermore, other devices, such as PMOS transistors or NMOS transistors, can be formed in the substrate; the substrate can also form an isolation structure, which is a shallow trench isolation (STI) structure or a localized silicon oxide (LOCOS) isolation structure. Similarly, conductive components can also be formed in the substrate, which can be the gate, source, or drain of a transistor, or a metal interconnect structure electrically connected to the transistor, etc.

[0034] The layer to be etched 100 is a film layer in the substrate that is to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor, or a hard mask (HM), etc.

[0035] In this embodiment, the layer to be etched 100 has a multilayer structure. Specifically, the layer to be etched 100 includes a dielectric layer 110, a hard mask material layer 120 located on the dielectric layer 110, and an etch stop layer 130 located on the hard mask material layer 120.

[0036] The subsequent patterned dielectric layer 110 is formed, in which multiple interconnect trenches are formed and interconnect lines are formed in the interconnect trenches. The dielectric layer 110 is used to achieve isolation between the interconnect lines.

[0037] The dielectric layer 110 is made of low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc. Among them, low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9, and ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6.

[0038] In this embodiment, the dielectric layer 110 is made of an ultra-low k dielectric material, thereby reducing the parasitic capacitance between the metal interconnect structures and thus reducing the subsequent RC delay. Specifically, the ultra-low k dielectric material can be hydrogenated silicon oxide.

[0039] In this embodiment, the hard mask material layer 120 is first patterned to form a hard mask layer, and then the dielectric layer 110 is patterned using the hard mask layer as a mask. This helps to improve the process stability of the patterned dielectric layer 110 and correspondingly improve the accuracy of pattern transfer.

[0040] The hard mask material layer 120 is made of one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon carbonitride. As an example, the hard mask material layer 120 is made of titanium nitride.

[0041] The etching stop layer 130 is used to define the etching stop position in subsequent etching steps, thereby reducing the wear on the hard mask material layer 120 and improving the effect of subsequent patterning processes.

[0042] The material of the etch stop layer 130 includes at least one of silicon nitride or silicon oxynitride.

[0043] It should be noted that, depending on the actual process requirements, a stress buffer layer can also be placed between the hard mask material layer and the dielectric layer to improve the adhesion between the hard mask material layer and the dielectric layer and reduce the stress generated between the film layers. Details regarding stress buffer layers will not be elaborated here.

[0044] Figure 4 yes Figure 3 A top-down view. See also... Figure 3 and Figure 4 A first mask layer 210 and a second mask layer 220 located on the first mask layer 210 are sequentially formed on the layer to be etched 100.

[0045] The first mask layer 210 is used to subsequently form the first trench and the first structural trench therein by etching.

[0046] In this embodiment, the layer to be etched 100 includes a dielectric layer 110, a hard mask material layer 120 located on the dielectric layer 110, and an etch stop layer 130 located on the hard mask material layer 120. Correspondingly, a first mask layer 210 is formed on the etch stop layer 130.

[0047] In this embodiment, the material of the first mask layer 210 is amorphous silicon. In other embodiments, the first mask layer can also be formed of other suitable materials, which are not limited here.

[0048] The process for forming the first mask layer 210 is chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or high-temperature furnace tube process, etc.

[0049] The second mask layer 220 is used as a mask for subsequent ion implantation processes on the first mask layer 210.

[0050] In this embodiment, the second mask layer 220 is a photoresist layer. Specifically, the material of the second mask layer 220 is photoresist.

[0051] In this embodiment, the second mask layer 220 is rectangular. Accordingly, the second mask layer 220 is formed using a positive photodiode (PTD) process.

[0052] See Figure 5 Ion implantation is performed on the first mask layer 210 using the second mask layer 220 as a mask to form a first non-implanted region I extending along the first direction.

[0053] Ion implantation is performed on the first mask layer 210 using the second mask layer 220 as a mask, such that the first mask layer 210 covered by the second mask layer 220 forms a first non-implantation region I, and the first mask layer 210 not covered by the second mask layer 220 forms an implantation region II.

[0054] Ion implantation is performed on the first mask layer 210, which correspondingly changes the etching selectivity ratio between the implanted region II and the first non-implanted region I formed in the first mask layer 210. Specifically, ion implantation is performed on the first mask layer 210 to increase the etching selectivity ratio between the first non-implanted region I and the implanted region II, thereby allowing the implanted region II to be retained during the subsequent removal of the first non-implanted region I.

[0055] The first non-injection region I is used to define the pattern and position of the first trench and the first structural trench subsequently formed in the first mask layer 210. Specifically, the first non-injection region I is subsequently divided by the first trench formed in the first mask layer 210, and the divided first non-injection region I is used to form the first structural trench. The first structural trench is used to define the second trench for forming a bidirectional winding structure and the connecting trench for connecting adjacent second trenches.

[0056] The first non-injection region I defines the pattern and position of the first trench and the first structural trench, making the size of the first non-injection region I larger. This helps to reduce the difficulty of forming the first non-injection region I, increase the process window of the photolithography process for forming the first non-injection region I, eliminate the limitations of the existing photolithography process, and correspondingly improve the pattern quality and pattern accuracy of the second trench and the first connecting trench formed subsequently.

[0057] In this embodiment, during the formation of the first non-injection region I, the second mask layer 220 is also used as a mask to form a second non-injection region III in the first mask layer 210 that extends along the first direction (X direction) and is spaced apart from the first non-injection region I in the second direction (Y direction).

[0058] The second non-injection region III is used to define the pattern and location of the third trench subsequently formed in the first mask layer 210.

[0059] See Figure 6 After forming the first non-injection region I, a third mask layer 230 is formed on the first mask layer 210. The third mask layer 230 has a plurality of first openings 231. The first openings 231 extend along the first direction and are spaced apart along the first direction. On a projection plane parallel to the substrate, the first openings 231 at least partially overlap with the first non-injection region I, such that the first non-injection region I is divided by the first openings 231 to form a first structural pattern.

[0060] The third mask layer 230 is used as a mask for subsequent etching of the first mask layer 210.

[0061] In this embodiment, the material of the third mask layer 230 is photoresist.

[0062] In this embodiment, a negative developing process (NTD) is used to form a third mask layer 230 on the first mask layer 210.

[0063] The first opening 231 is used to define the pattern and location of the first trench subsequently formed in the first mask layer 210. Specifically, the first mask layer 210 at the bottom of the first opening 231 is used for subsequent etching removal, thereby forming the first trench in the first mask layer 210.

[0064] In this embodiment, the first opening 231 extends along the first direction and is spaced apart along the first direction. The first opening 231 is located above the first non-injection region I in the first mask layer 210 and extends to the part of the injection region II on both sides of the first non-injection region I, so that on the projection plane parallel to the etchable layer 100, the first non-injection region I is divided by the first opening 231 to form a first structural pattern.

[0065] Specifically, please see Figure 7 The first structural pattern includes a first pattern 215 and a second pattern 216. The first pattern 215 extends along a first direction and is spaced apart along a second direction. The second pattern 216 is located between adjacent first openings 231 and extends along the second direction to the non-end of the adjacent first pattern, such that adjacent first patterns 215 are connected by the second pattern 216.

[0066] After the first mask layer 210 is subsequently etched to form the first trench at the bottom of the first opening 231, the remaining first non-injection region I in the first mask layer 210 forms the first structural pattern. The region containing the first pattern in the first structural pattern is used for subsequent etching to form the second trench, and the region containing the second pattern is used for subsequent etching to remove the non-end first connecting trenches that form the connected second trenches.

[0067] The first non-injection region I is first defined by the second mask layer 220, and then the pattern and position of the first trench are defined by the third mask layer 230. This allows the subsequently formed first trench to divide the first non-injection region I into a first structural pattern. The first structural pattern is used to define the pattern and position of the subsequently formed second trench and the first connecting trench connecting adjacent second trenches. Compared with the existing method of defining the pattern and position of the first trench and the second trench using the second and third mask layers, this method can define not only the pattern and position of the first trench and the second trench, but also the pattern and position of the connecting trench in the first structural trench for connecting adjacent second trenches, without adding an additional photomask. This is beneficial for saving process costs.

[0068] In this embodiment, there are two first openings 231. In other embodiments, the number of first openings 231 may be more or less than two, and those skilled in the art can set it according to actual needs, without limitation.

[0069] In this embodiment, a second opening 232 extending along the first direction is also formed in the third mask layer 230. The second opening 232 is arranged at intervals with the first opening 231 along the second direction, and the second opening 232 is located above the first mask layer between the first non-injection region I and the second non-injection region III.

[0070] The second opening 232 is used to define the pattern and location of the third trench subsequently formed in the first mask layer.

[0071] In this embodiment, the second opening 232 is located above the injection region II between the first non-injection region I and the second non-injection region III, and the second opening 232 extends along the second direction to a portion above the second non-injection region III, thereby increasing the process window of the photolithography process and reducing the process difficulty of forming the second opening.

[0072] In this embodiment, there is one second opening 232. In other embodiments, there may be multiple second openings, which is not limited here.

[0073] Please continue reading Figure 7 The first mask layer 210 is etched using the third mask layer 230 as a mask to form a first trench 211 located at the bottom of the first opening 231.

[0074] The first mask layer 210 is etched using the third mask layer 230 as a mask, so that the first mask layer 210 covered by the third mask layer 230 is retained, and the first mask layer 210 exposed at the bottom of the first opening 231 is etched away, thereby forming a first trench 211 at the bottom of the first opening 231 in the first mask layer 210.

[0075] The first trench 211 is used to define the pattern and position of the first interconnect trench subsequently formed in the etchable layer 100, and to divide the first non-injection region I in the first mask layer 210 to form the first structural pattern.

[0076] The first trench 211 divides the first non-injection region I to form a first structural trench. The first structural trench defines the shape and position of second trenches extending along a first direction and spaced apart along a second direction, and first connecting trenches located between adjacent second trenches, extending along the second direction and connecting the adjacent second trenches. After forming the first trench 211, a first mask layer 210, spaced apart in the first direction, is subsequently removed to form the first connecting trenches connecting adjacent second trenches in the first structural trench. That is, the end-to-end distance of the first trench 211 is consistent with the dimension of the subsequently formed first connecting trench in the first direction. Therefore, by adjusting the end-to-end distance of the first trench 211, the dimension of the first connecting trench in the first structural trench in the first direction can be controlled.

[0077] In this embodiment, a dry etching process is used. In other embodiments, a wet etching process can also be used to form the first trench.

[0078] The number of the first grooves 211 can be set according to actual needs. In this embodiment, there are two first grooves 211. In other embodiments, the number of the first grooves can also be four, six, eight, etc., and there is no limitation here.

[0079] In this embodiment, during the process of forming the first trench 211, the first mask layer 210 is also etched using the third mask layer 230 as a mask to form the third trench 213 located at the bottom of the second opening 232.

[0080] The third trench 213 is used to define the pattern and location of the third interconnect trench subsequently formed in the etched layer 100.

[0081] In this embodiment, after the first trench 211 and the third trench 213 are formed, the remaining third mask layer 230 is removed.

[0082] In this embodiment, the third mask layer 230 is a photoresist layer, and the remaining third mask layer 230 is removed using an ashing process. In other embodiments, the remaining third mask layer can also be removed using a wet photoresist removal process.

[0083] After the first trench 211 is formed, the first non-injection region I in the first mask layer 210 is divided by the first trench 211, and the divided first non-injection region I is used to form the first structural trench subsequently. That is, the region in the first mask layer 210 used to form the first trench 211 and the first structural trench is jointly defined and formed by the second mask layer 220 and the third mask layer 230, thus overcoming the limitations of existing photolithography processes and forming a bidirectional winding structure in the first mask layer 210.

[0084] In other embodiments, a SOC layer and a Si-ARC layer can be formed sequentially on the first mask layer before forming the third mask layer on the first mask layer; a third mask layer can be formed on the Si-ARC layer; the Si-ARC layer, the SOC layer, and the first mask layer can be etched sequentially using the third mask layer as a mask until the top surface of the hard mask material layer is exposed, forming a first trench in the first mask layer; after forming the first trench, the first SOC layer, the first Si-ARC layer, and the third mask layer can be removed. The relevant descriptions of the formation of the SOC layer and the Si-ARC layer will not be repeated here.

[0085] See Figure 8 A first sidewall layer 241 is formed on the sidewall of the first trench 211.

[0086] The first sidewall layer 241 is used to define the spacing between the first trench 211 and the subsequently formed first structural trench.

[0087] Specifically, the first sidewall layer 241 is used to occupy part of the space in the first trench 211, so that the first trench 211 and the first structural trench subsequently formed in the first mask layer 210 have corresponding spacing distances in the first direction and the second direction.

[0088] In this embodiment, during the process of forming the first sidewall layer 241, a second sidewall layer 242 is also formed on the sidewall of the third trench 213.

[0089] Specifically, the second sidewall layer 242 is used to occupy part of the space within the third trench 213, so that the third trench 213 has a corresponding spacing distance with the first structural trench subsequently formed in the first mask layer 210 and the fourth trench subsequently formed.

[0090] In this embodiment, the first sidewall layer 241 and the second sidewall layer 242 are made of the same material and are formed in the same process step to simplify the process and save process costs.

[0091] Specifically, the steps of forming the first sidewall layer 241 and the second sidewall layer 242 include: forming a sidewall material layer that conformally covers the bottom and sidewall of the first trench 211, the bottom and sidewall of the third trench 213, and the top surface of the first mask layer 210; removing the sidewall material layers located at the bottom of the first trench 211, the bottom of the third trench 213, and the top surface of the first mask layer 210, retaining the sidewall material layer located at the sidewall of the first trench 211 as the first sidewall layer 241, and retaining the sidewall material layer located at the sidewall of the third trench 213 as the second sidewall layer 242.

[0092] The first sidewall layer 241 and the second sidewall layer 242 can be selected from materials that have a high etch selectivity rate relative to the layer 100 to be etched. In this embodiment, the materials of the first sidewall layer 241 and the second sidewall layer 242 are titanium oxide (TiO). In other embodiments, the materials of the first sidewall layer and the second sidewall layer can also be aluminum monoxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), or other materials such as nitrides, oxides, oxynitrides, carbides, borides, and combinations thereof.

[0093] In this embodiment, the process for forming the sidewall material layer is atomic layer deposition (ALD). ALD results in a sidewall material layer with good thickness uniformity and excellent step coverage. Furthermore, ALD is a self-limiting reaction process, allowing for precise deposition of one atomic layer per cycle. The resulting film can achieve a single-atom thickness, facilitating precise control over the deposition thickness of the sidewall material layer.

[0094] In other embodiments, the process for forming the sidewall material layer can also be a deposition process such as chemical vapor deposition or a high-temperature furnace tube process.

[0095] Accordingly, the sidewall material layer conformally covers the bottom and sidewalls of the first trench 211, the bottom and sidewalls of the third trench 213, and the top surface of the first mask layer 210. Therefore, in this embodiment, an anisotropic maskless etching process can be used to remove the sidewall material layer located at the bottom of the first trench 211, the bottom of the third trench 213, and the top surface of the first mask layer 210. The steps of forming the first sidewall layer 241 and the second sidewall layer 242 do not require a photomask, which helps to save costs.

[0096] Specifically, using an anisotropic dry etching process to perform an anisotropic maskless etching process is beneficial to ensure that while removing the sidewall material layer located at the bottom of the first trench 211, the bottom of the third trench 213, and the top surface of the first mask layer 210, the damage to other film structures is minimized, and the lateral etching of the sidewall material layer located on the sidewall of the first trench 211 and the sidewall of the third trench 213 is reduced.

[0097] The dimensions of the first sidewall layer 241 in the first and second directions can be determined according to the required spacing between the first trench 211 and the second trench and the first connecting trench in the first structural trench subsequently formed in the first mask layer 210 in the first and second directions.

[0098] The dimensions of the second sidewall layer 242 in the second direction can be determined according to the required spacing distance between the third trench and the subsequently formed second and fourth trenches in the second direction.

[0099] See Figure 9 After forming the first sidewall layer 241, the area where the first structural pattern is located in the first non-injection region I is etched away, and a first structural trench is formed in the first mask layer 210. The first structural trench includes a second trench 212 and a first connecting trench 217. The second trench 212 extends along the first direction and is spaced apart along the second direction. The first connecting trench 217 is located between adjacent second trenches 212 and extends along the second direction to the non-end of the adjacent second trenches 212, so that adjacent second trenches 212 are connected through the first connecting trench 217.

[0100] The first structural trench is used to define the pattern and location of the second interconnect trench and the connecting interconnect trench subsequently formed in the layer to be etched 100.

[0101] In this embodiment, the second trench 212 and the first connecting trench 217 penetrate the first mask layer 210, that is, the bottom of the second trench 212 and the first connecting trench 217 exposes the top surface of the layer 100 to be etched.

[0102] Specifically, the layer to be etched 100 includes a dielectric layer 110, a hard mask material layer 120 located on the dielectric layer 110, and an etch stop layer 130 located on the hard mask material layer 120. The bottom of the second trench 212 and the first connecting trench 217 respectively expose the top surface of the etch stop layer 130.

[0103] The number of second grooves 212 and first connecting grooves 217 included in the first structural groove can be determined according to actual process requirements. In this embodiment, the number of third grooves 213 and first connecting grooves 217 included in the first structural groove are 2 and 1, respectively.

[0104] In other embodiments, the number of second trenches and first connecting trenches included in the first structural trench can be even greater. For example, the number of second trenches and first connecting trenches included in the first structural trench may be 3 and 2, respectively.

[0105] In this embodiment, during the formation of the first structural trench, the second non-injection region III is also etched away, and a fourth trench 214 is formed in the first mask layer 210. The fourth trench 214 extends along the first direction and is spaced apart from the third trench 213 along the second direction.

[0106] The fourth trench 214 is used to define the pattern and location of the fourth interconnect trench subsequently formed in the etched layer 100.

[0107] The number of the fourth groove 214 can be set according to actual needs. In this embodiment, the number of the fourth groove 214 is one. In other embodiments, the number of the fourth groove can be multiple, and there is no limitation here.

[0108] In this embodiment, the process for forming the second trench 212, the first connecting trench 217 and the fourth trench 214 is a wet etching process.

[0109] In order to retain the first mask layer 210, the first sidewall layer 241, the second sidewall layer 242, and the etchable layer 100 of the injection region II during the steps of forming the second trench 212, the first connecting trench 217, and the fourth trench 214, the etching rate of the first mask layer 210 of the first non-injection region I and the second non-injection region III should be greater than the etching selective rates of the first mask layer 210 of the injection region II, the etchable layer 100, and the first sidewall layer 241 and the second sidewall layer 242, respectively. In this embodiment, during the etching process of forming the third trench 213, the first connecting trench 217, and the fourth trench 214, the etching selectivity ratio of the first mask layer 210 of the first non-injection region I and the first mask layer 210 of the second non-injection region III to the first mask layer 210 of the injection region II and the etching layer 100 is greater than or equal to 100, such as 150, 200, etc., and the etching selectivity ratio of the first mask layer 210 of the first non-injection region I and the second non-injection region III to the first sidewall layer 241 and the second sidewall layer 242 is greater than or equal to 20, such as 50, 100, etc.

[0110] See Figure 10 The first sidewall layer 241 and the first mask layer 210 are used as masks to pattern the layer 100 to be etched, forming a target pattern.

[0111] In this embodiment, the layer to be etched 100 includes a dielectric layer 110. Therefore, using the first sidewall layer 241 and the first mask layer 210 as masks, the dielectric layer 110 below the first trench 211, the second trench 212, and the first connecting trench 217 is patterned, and a first interconnect trench 111 and the structural interconnect trench are formed in the dielectric layer 110. The structural interconnect trench includes a second interconnect trench 112 and a bit-connected interconnect trench 115.

[0112] In this embodiment, the layer to be etched 100 further includes a hard mask material layer 120. Using the first sidewall layer 241 and the first mask layer 210 as masks, the hard mask material layer 120 below the first trench 211, the second trench 212 and the first connecting trench 217 is patterned to form a hard mask layer. Using the hard mask layer as a mask, the dielectric layer 110 is patterned. A first interconnect trench 111 and the structural interconnect trench are formed in the dielectric layer 111. The structural interconnect trench includes a second interconnect trench 112 and a connecting interconnect trench 115.

[0113] In this embodiment, during the process of forming the first interconnect trench 111 located at the bottom of the first trench 211 and the structural interconnect trench located at the bottom of the first structural trench, a third interconnect trench 113 located at the bottom of the third trench 213 and a fourth interconnect trench 114 located at the bottom of the fourth trench 214 are also formed in the etchable layer 100.

[0114] Specifically, using the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210 as masks, the hard mask material layer 120 below the first trench 211, the second trench 212, the third trench 213, the fourth trench 214, and the first connecting trench 217 is patterned to form a hard mask layer. Using the hard mask layer as a mask, the dielectric layer 110 is patterned, and the first interconnect trench 111, the second interconnect trench 112, the third interconnect trench 113, the fourth interconnect trench 114, and the connecting interconnect trench 115 are formed in the dielectric layer 110.

[0115] In this embodiment, the process of etching the hard mask material layer 120 using the first mask layer 210, the first sidewall layer 241, and the second sidewall layer 242 as masks is a plasma dry etching process. Specifically, the process of etching the hard mask material layer 120 is a plasma dry etching process, and the etching angle of the second plasma dry etching process is 90°.

[0116] In this embodiment, during the process of removing the first sidewall layer 241 and the first mask layer 210, the second sidewall layer 242 is also removed.

[0117] The process for removing the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210 includes dry etching and wet etching. In this embodiment, wet etching is used to remove the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210.

[0118] To preserve the dielectric layer 110 and the hard mask layer, during the removal of the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210, the etching selectivity rates for the layer to be etched 100 and the hard mask layer should be lower than the etching selectivity rates for removing the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210, respectively. The materials of the dielectric layer 110 and the hard mask layer should be selected based on etching selectivity rates lower than those of the first sidewall layer 241, the second sidewall layer 242, and the first mask layer 210, respectively.

[0119] See Figure 11 A first interconnect line 111' is formed in the first interconnect groove 111, a second interconnect line 112' is formed in the second interconnect groove 112, and a connecting interconnect line 115' is formed in the connecting interconnect groove 115.

[0120] After forming the first interconnect 111', the second interconnect 112' and the connecting interconnect 115', adjacent second interconnects 112' are connected by corresponding connecting interconnects 113' to form a bidirectional winding structure.

[0121] Furthermore, the dimension of the connecting interconnect 113' in the first direction is the end-to-end distance of the first interconnect 111'. Therefore, the dimension of the connecting interconnect 113' in the first direction can be controlled by adjusting the end-to-end distance of the first interconnect 111'.

[0122] In this embodiment, during the process of forming the first interconnect line 111', the second interconnect line 112' and the connecting interconnect line 113', the third interconnect line 114' and the fourth interconnect line 114' are also formed in the third interconnect groove 113 and the fourth interconnect groove 114.

[0123] The first interconnect 111', the second interconnect 112', the connecting interconnect 113', the third interconnect 114' and the fourth interconnect 114' are formed in the same process step to simplify the process, reduce costs and improve efficiency.

[0124] The first interconnect 111', the second interconnect 112', the connecting interconnect 113', the third interconnect 114', and the fourth interconnect 114' are used to realize the electrical connection between the semiconductor structure and external circuits or other interconnect structures.

[0125] In this embodiment, the first interconnect 111', the second interconnect 112', the connecting interconnect 113', the third interconnect 114', and the fourth interconnect 114' are made of copper. In other embodiments, the interconnects can also be made of conductive materials such as cobalt, tungsten, and aluminum.

[0126] Accordingly, embodiments of the present invention also provide a semiconductor structure.

[0127] Please continue reading Figure 10 and Figure 11 The semiconductor structure includes: a layer to be etched 100; a first interconnect trench 111 located in the layer to be etched 100, the first interconnect trench 111 extending along a first direction and spaced apart along the first direction; a second interconnect trench 112 located in the layer to be etched 100, the second interconnect trench 112 extending along the first direction and spaced apart along the second direction, and the first interconnect trench 111 located between adjacent second interconnect trenches 112 and spaced apart from the second interconnect trenches 112 along the second direction; a connecting interconnect trench 115 located in the layer to be etched 100, the connecting interconnect trench 115 located between adjacent second interconnect trenches 112 and extending along the second direction to the non-end of the adjacent second interconnect trenches 112, such that adjacent second interconnect trenches 112 are connected through the connecting interconnect trench, and the first trench 211 is located on both sides of the connecting interconnect trench 115 along the second direction.

[0128] In this embodiment, the semiconductor structure further includes: a first interconnect line 111' located in the first trench 211; a second interconnect line 112' located in the second interconnect trench; and a connecting interconnect line 113' located in the connecting interconnect trench.

[0129] In this embodiment, the semiconductor structure further includes: a third interconnect trench 113 located in the etchable layer 100, the third interconnect trench 113 extending along the first direction and spaced apart from the second interconnect trench along the second direction, and disposed opposite to the first interconnect trench 112 on both sides of the second interconnect trench 112 along the first direction; and a fourth interconnect trench 114 located in the etchable layer 100, the third interconnect trench 113 extending along the first direction and spaced apart from the third interconnect trench 113 along the second direction, and disposed opposite to the second interconnect trench on both sides of the third interconnect trench 113 along the first direction;

[0130] In this embodiment, the semiconductor structure further includes: a third interconnect line 114' located in the third interconnect trench 113; and a fourth interconnect line 114' located in the fourth interconnect trench 114.

[0131] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a layer to be etched; A first mask layer and a second mask layer located on the first mask layer are formed on the layer to be etched; Ion implantation is performed on the first mask layer using the second mask layer as a mask to form a first non-implanted region extending along the first direction; A third mask layer is formed on the first mask layer, the third mask layer having a plurality of first openings; the first openings extend along the first direction and are spaced apart along the first direction, and on a projection plane parallel to the substrate, the first openings at least partially overlap with the first non-injection region, such that the first non-injection region is divided by the first openings to form a first structural pattern; the first structural pattern includes a first pattern and a second pattern, the first patterns extend along the first direction and are spaced apart along the second direction, the second patterns are located between adjacent first openings and extend along the second direction to the non-ends of adjacent first patterns, such that adjacent first patterns are connected by the second pattern; The first direction is perpendicular to the second direction; The first mask layer is etched using the third mask layer as a mask to form a first trench located at the bottom of the first opening in the first mask layer; Based on the first trench, the area where the first structural pattern is located in the first non-injection region is etched away to form the first structural trench in the first mask layer. The first structural trench includes a second trench corresponding to the first pattern and a first connecting trench corresponding to the second pattern; The first trench and the layer to be etched at the bottom of the first structural trench are graphically visualized to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first opening is located above the first non-injection region and extends along the first direction above a portion of the non-injection region.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of etching away the region containing the first structural pattern in the first non-injection region based on the first trench includes: After the first trench is formed, the third mask layer is removed; After removing the third mask layer, a first sidewall layer is formed on the sidewall of the first trench; After the first sidewall layer is formed, the area containing the first structural pattern in the first non-injected region is etched away.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, During the formation of the first non-injection region extending along the first direction, a second non-injection region extending along the first direction is also formed in the first mask layer, and the second non-injection region and the first non-injection region are spaced apart along the second direction. The third mask layer also has a second opening extending along the first direction, the second opening and the first opening being spaced apart along the second direction, and the second opening being located above the first mask layer between the first non-injection region and the second non-injection region; During the formation of the first trench, a third trench located at the bottom of the second opening is also formed in the first mask layer; During the formation of the first sidewall layer, a second sidewall layer is also formed on the sidewall of the second trench; during the formation of the first structural trench, the second non-injection area is also etched away, and a fourth trench is formed in the first mask layer. During the process of graphically illustrating the etchable layer at the bottom of the first trench and the first structural trench, the etchable layer at the bottom of the third trench and the fourth trench is also graphically illustrated.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The steps of forming the first sidewall layer and the second sidewall layer include: A sidewall material layer is formed to conformally cover the bottom and sidewalls of the first trench and the bottom and sidewalls of the third trench, as well as the top surface of the first mask layer. Remove the sidewall material layers located at the bottom of the first trench and the bottom of the third trench, as well as the top surface of the first mask layer, and retain the sidewall material layers located on the sidewalls of the first trench and the third trench as the first sidewall layer and the second sidewall layer, respectively.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The formation process of the sidewall material layer includes atomic layer deposition.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the sidewall material layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.

8. The method for forming a semiconductor structure according to claim 5, characterized in that, The process for removing the sidewall material layer located at the bottom of the first trench and the bottom of the third trench, as well as the top surface of the first mask layer, is an anisotropic maskless etching process.

9. The method for forming a semiconductor structure according to claim 5, characterized in that, The layer to be etched includes a dielectric layer; Using the first sidewall layer, the second sidewall layer, and the first mask layer as masks, the first trench, the second trench, the third trench, the fourth trench, and the dielectric layer below the first connecting trench are patterned to form a first interconnect trench below the first trench, a second interconnect trench below the second trench, a third interconnect trench below the third trench, a fourth interconnect trench below the fourth trench, and a connecting interconnect trench below the first connecting trench.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The dielectric layer is made of at least one of the following: low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The layer to be etched further includes a hard mask material layer; after the first mask layer is formed, the first mask layer is located on the hard mask material layer; After the fourth trench is formed, the hard mask material layer is patterned using the first sidewall layer, the second sidewall layer, and the first mask layer as masks to form a hard mask layer. Remove the first mask layer, the first sidewall layer, and the second sidewall layer; After removing the first mask layer, the first sidewall layer, and the second sidewall layer, the dielectric layer is patterned using the hard mask layer as a mask to form the first interconnect trench, the second interconnect trench, the third interconnect trench, the fourth interconnect trench, and the connecting interconnect trench.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The material of the hard mask material layer includes at least one of titanium nitride, tungsten carbide, silicon oxide, silicon carbide, and silicon carbonitride.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of etching the first mask layer using the third mask layer as a mask is a plasma dry etching process.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first mask layer includes amorphous silicon.

15. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a layer to be etched; The first interconnect trench is located in the layer to be etched; The first interconnecting slots extend along a first direction and are spaced apart along the first direction; The second interconnect trench is located in the layer to be etched, the second interconnect trench extends along the first direction and is spaced apart along the second direction, and the first interconnect trench is located between adjacent second interconnect trenches and spaced apart from the second interconnect trenches along the second direction; the second direction is perpendicular to the first direction; The interconnecting trench is located in the layer to be etched, the interconnecting trench is located between the adjacent second interconnecting trenches and extends along the second direction to the non-end of the adjacent second interconnecting trenches, such that the adjacent second interconnecting trenches are connected through the interconnecting trench, and the first interconnecting trench is located on both sides of the interconnecting trench along the second direction.

16. The semiconductor structure according to claim 15, characterized in that, Also includes: The third interconnect trench is located in the layer to be etched. The third interconnect trench extends along the first direction and is spaced apart from the second interconnect trench along the second direction. The third interconnect trench is disposed opposite to the first interconnect trench on both sides of the second interconnect trench along the first direction. The fourth interconnect trench is located in the layer to be etched. The third interconnect trench extends along the first direction and is spaced apart from the third interconnect trench along the second direction. The third interconnect trench and the second interconnect trench are disposed opposite to each other on both sides of the third interconnect trench along the first direction.

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