Oxide all-optical controlled memristor array and method of manufacturing the same

Abstract

This invention provides an oxide-based optically controlled memristor array and its fabrication method. The fabrication method includes: fabricating a composite bottom electrode array on a substrate using lift-off photolithography and backfill processes; fabricating an intermediate dielectric layer array on the composite bottom electrode array using lift-off photolithography and backfill processes; annealing the substrate, composite bottom electrode array, and intermediate dielectric layer array; fabricating a composite top electrode array on top of the intermediate dielectric layer array using lift-off photolithography; and performing overall annealing on the substrate, composite bottom electrode array, intermediate dielectric layer array, and composite top electrode array. The solution provided by this invention, by combining backfill and lift-off processes, effectively avoids the "rabbit ear" effect in memristor cross-arrays from affecting device performance, thus improving the stability of the memristor array. Simultaneously, by setting the top electrode as a composite top electrode, the process window of the top electrode of the oxide-based optically controlled memristor array can be expanded, greatly improving the device yield.

Description

Technical Field

[0001] This invention relates to the field of microelectronic devices and optoelectronic integration technology, specifically to an oxide fully optically controlled memristor array and its fabrication method, which is particularly suitable for neuromorphic computing, artificial vision and in-memory computing systems. Background Technology

[0002] In 1971, Professor Cai Shaotang, based on the symmetry of circuit theory, first predicted that the memristor would be the fourth basic circuit element after resistors, capacitors, and inductors, with its resistance determined by the amount of charge flowing through it and possessing non-volatile characteristics. In 2008, the HP Labs team reported on a memristor based on TiO2 material in *Nature*, verifying this theoretical prediction. Today, memristors have gradually moved from theoretical concepts and unit implementations to the stage of large-scale integration and in-memory computing application verification, advancing towards the goals of high-density, low-power, and neuromorphic computing, becoming one of the key technologies for breaking through the "memory wall" in the post-Moore's Law era.

[0003] Traditional memristors rely heavily on electrical signals to control conductance, resulting in high power consumption, severe crosstalk, and limited speed. The Joule heating induced by the electrical signals not only increases energy consumption but can also cause ion migration within the dielectric layer, affecting device stability. Accumulated thermal stress can further exacerbate interface degradation between the electrodes and the dielectric layer, causing irreversible structural damage and ultimately limiting device durability.

[0004] In contrast, fully optically controlled memristors rely on optical signals to modulate the conductance state, and the state is non-volatile, enabling a high degree of integration of data storage, computation, and sensing functions, providing new possibilities for the development of future intelligent electronic devices.

[0005] For example, in their paper "In situcryptography in a neuromorphic vision sensor based on light-driven memristors" published in *Applied Physics Reviews*, Hu Lingxiang et al. constructed an in-situ encryption architecture integrating image sensing, encrypted computation, and post-processing functions based on InGaZnO fully optically controlled memristors, achieving effective information protection. Passive cross-arrays integrated with fully optically controlled memristors have become a research hotspot in the field of neuromorphic computing due to their simple structure and ease of fabrication.

[0006] For example, Chen Lu et al., in their paper "Self-Rectifying All-OpticalModulated Optoelectronic Multistates Memristor Crossbar Array for Neuromorphic Computing" published in *Nano Letters*, reported an 8×8 fully optically controlled memristor crossbar array based on a titanium oxide / nickel oxide heterojunction as the intermediate dielectric layer. An ANN network was constructed based on this array, achieving 93% accuracy in recognizing 28×28 pixel handwritten digit images. However, key process defects still exist in the fabrication of memristor crossbar arrays, limiting device performance and integration density. For instance, in the bottom electrode array patterning process, metal is deposited and remains on the photoresist sidewalls, forming protruding structures distributed along the electrode edges, known as the "rabbit ear" effect. This structure leads to distortion of the effective field shape of the electrode and concentration of local electric field intensity, resulting in performance degradation, low yield, and even hard breakdown, severely impairing the array's electrical consistency and limiting the development of memristors towards high-density integration. In the fabrication of the top electrode array of an all-optically controlled memristor array, there is a contradiction between electrode thickness matching and performance compatibility. The formation of a Schottky contact between the bottom layer material of the top electrode and the intermediate dielectric layer array is a necessary condition for achieving fully optically reversible controllability of the device. If the total thickness of the top electrode is too thin, it is prone to structural damage or desorption during subsequent resist removal and organic layer stripping processes, leading to device failure. If the noble metal layer in the top electrode is too thick, it will attenuate the incident light signal, reducing the device's photoresponse sensitivity and the amplitude of the photomodulated conductivity state.

[0007] Therefore, it is urgent to develop an optimized fabrication scheme for fully optically controlled memristor arrays, design a reasonable device structure, and screen suitable top electrode material systems to fabricate oxide fully optically controlled memristor arrays with stable performance, high yield, and good consistency. This is of great significance for promoting the practical application of fully optically controlled memristors. Summary of the Invention

[0008] In view of the above problems, the purpose of this invention is to provide an oxide all-optically controlled memristor array and its fabrication method, so as to solve the problem of poor stability in existing all-optically controlled memristors.

[0009] The present invention provides an oxide-based optically controlled memristor array, characterized in that it comprises: a substrate, a composite bottom electrode array, an intermediate dielectric layer array, and a composite top electrode array; wherein... A first deposition trench is formed on the upper surface of the substrate, and a second deposition trench is formed at the bottom of the first deposition trench. The composite top electrode array is disposed on the upper surface of the substrate, the intermediate dielectric layer array is disposed within the first deposition trench, and the composite bottom electrode array is disposed within the second deposition trench; and, The composite top electrode array, the intermediate dielectric layer array, and the composite bottom electrode array are sequentially bonded to each other in the vertical direction.

[0010] Alternatively, the composite top electrode array may include a lower metal layer and an upper transparent conductive oxide layer; wherein the lower metal layer is vertically stacked above the intermediate dielectric layer array, and the upper transparent conductive oxide layer is vertically stacked above the lower metal layer.

[0011] Alternatively, the composite bottom electrode array may include a lower active metal layer and an upper inert metal layer; wherein the lower active metal layer is vertically stacked at the bottom of the second deposition tank, and the upper inert metal layer is vertically stacked above the lower metal layer.

[0012] Alternatively, the substrate may comprise at least one of a thermally oxidized silicon substrate and a quartz substrate; and / or, The metallic material of the lower active metal layer includes titanium, nickel; and / or, The metallic material of the upper inert metal includes at least one of platinum, gold, and palladium; and / or, The material of the intermediate dielectric layer array includes at least one of zinc oxide, zirconium oxide, hafnium oxide, silicon oxide, tantalum oxide, titanium oxide, aluminum oxide, nickel oxide, tungsten oxide, tin oxide, indium oxide, indium tin oxide, indium gallium zinc oxide, and indium gallium cadmium oxide; and / or, The metal material of the lower metal layer includes at least one of platinum, gold, silver, and palladium; and / or, The material of the upper transparent conductive oxide layer includes at least one of indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide.

[0013] Alternatively, the thickness of the lower active metal layer can be 1~100 nm. And / or, the thickness of the upper inert metal layer is 10~200 nm; and / or, The thickness of the intermediate dielectric layer array is 10~500 nm; and / or, The thickness of the lower metal layer is 1~20 nm; and / or, The thickness of the upper transparent conductive oxide layer is 10~200 nm.

[0014] On the other hand, the fabrication method of the aforementioned oxide all-optically controlled memristor array provided by the present invention includes: The composite bottom electrode array was fabricated on the substrate using lift-off lithography and backfill processes. The intermediate dielectric layer array is fabricated on the composite bottom electrode array using lift-off lithography and backfill processes. The substrate, the composite bottom electrode array, and the intermediate dielectric layer array are annealed. The composite top electrode array is fabricated above the intermediate dielectric layer array using a lift-off photolithography process; The substrate, the composite bottom electrode array, the intermediate dielectric layer array, and the composite top electrode array are subjected to overall annealing.

[0015] Alternatively, the process of fabricating the composite bottom electrode array on the substrate using lift-off lithography and backfill processes includes: Photoresist is spin-coated onto the substrate, and a pattern of the composite bottom electrode array is formed using a lift-off photolithography process, followed by development of the pattern. The substrate is etched based on the pattern of the composite bottom electrode array to form a primary pattern trench on the substrate; wherein the depth of the primary pattern trench is equal to the sum of the thickness of the composite bottom electrode array and the thickness of the intermediate dielectric layer array; A composite bottom electrode array film is deposited in the primary pattern trench and then subjected to a resist removal process; and / or, during the annealing of the substrate, the composite bottom electrode array, and the intermediate dielectric layer array, the annealing temperature is 400~700 ℃. And / or, during the overall annealing of the substrate, the composite bottom electrode array, the intermediate dielectric layer array, and the composite top electrode array, the annealing temperature is 100~200 ℃.

[0016] Alternatively, the process of fabricating the intermediate dielectric layer array on the composite bottom electrode array using lift-off lithography and backfill processes includes: The array pattern of the intermediate dielectric layer is formed on the composite bottom electrode array film using a lift-off photolithography process, and the pattern is then developed. The composite bottom electrode array film is etched based on the array pattern of the intermediate dielectric layer to form secondary pattern trenches on the composite bottom electrode array film; wherein the depth of the secondary pattern trenches is equal to the thickness of the intermediate dielectric layer array. An intermediate dielectric layer array oxide film is deposited in the secondary patterned trench and then subjected to a resist removal process; wherein the intermediate dielectric layer array oxide film is prepared by magnetron sputtering, electron beam evaporation, or atomic layer deposition.

[0017] Alternatively, the process of fabricating the composite top electrode array using a lift-off photolithography process above the intermediate dielectric layer array includes: The pattern of the composite top electrode array is formed on top of the intermediate dielectric layer array oxide film using a lift-off photolithography process, and the pattern is then developed. A composite top electrode array film is deposited on top of the intermediate dielectric layer array oxide film based on the pattern of the composite top electrode array, and then the resist is removed.

[0018] Furthermore, the present invention also provides a method for optical signal modulation of the aforementioned oxide all-optically controlled memristor array; comprising: Ultraviolet light with a wavelength of 200~450 nm is used as the writing light to increase the conductivity of the all-optically controlled memristor array, or visible light or infrared light with a wavelength of 500~1000 nm is used as the erasing light to decrease the conductivity of the all-optically controlled memristor array. The all-optically controlled memristor array can be controlled by the write light or the erase light.

[0019] Compared with the prior art, the oxide fully optically controlled memristor array and its fabrication method provided by the present invention have the following beneficial effects: First, compared to the purely vertical stacked array structure of existing oxide-based optically controlled memristor arrays, the solution provided by this invention, through a combination of backfill and lift-off processes, fundamentally solves the surface morphology problem of the array, avoids the "rabbit ear" effect, improves the stability of the cross array, and thus increases the integration density of the optically controlled memristor. Furthermore, by setting the top electrode as a composite top electrode, damage to the electrode during resist removal can be avoided, while simultaneously expanding the process window of the top electrode of the oxide-based optically controlled memristor array, greatly improving the device yield and laying a solid foundation for its neuromorphic computing applications. In addition, the fabrication method of the oxide-based optically controlled memristor array provided by this invention is highly compatible with modern CMOS processes, facilitating integration and mass production. Therefore, the fabrication method of the oxide-based optically controlled memristor array provided by this invention has broad application prospects.

[0020] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0021] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings and the contents of the claims, and with a more complete understanding of the invention. In the drawings: Figure 1 A schematic diagram of the structure of the oxide fully optically controlled memristor array provided according to the present invention: Figure 2 This is a schematic flowchart of the method for fabricating an oxide all-optically controlled memristor array according to the present invention; Figure 3 A physical diagram of an oxide all-optically controlled memristor array provided according to Embodiment 1 of the present invention; Figure 4 A process flow diagram of the fabrication method of an oxide all-optically controlled memristor array according to Embodiment 1 of the present invention; Figure 5 This is a photomask required for the lift-off lithography process according to Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the photoelectric response of the oxide fully optically controlled memristor array device prepared according to Example 1 of the present invention when the conductivity is enhanced and the photoelectric response when the conductivity is reduced in the high conductivity state. Figure 7 This is a schematic diagram of the photoelectric response of the oxide fully optically controlled memristor array device prepared according to Example 2 of the present invention when the conductivity is enhanced and the photoelectric response when the conductivity is reduced in the high conductivity state; Figure reference numerals: 1-Upper transparent conductive oxide layer, 2-Lower noble metal layer, 3-Substrate, 4-Intermediate dielectric layer, 5-Upper inert noble metal layer, 6-Lower metal layer. Detailed Implementation

[0022] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The following details the structure and fabrication process of the oxide fully optically controlled memristor array provided by this invention.

[0025] Figure 1 The structure of an oxide-based fully optically controlled memristor array according to the present invention is shown, as follows: Figure 1 As shown, the oxide all-optically controlled memristor array provided by the present invention includes: a substrate, a composite bottom electrode array, an intermediate dielectric layer array, and a composite top electrode array; and, in actual use, the incident light signal is input through the composite top electrode array.

[0026] Specifically, a first deposition trench and a second deposition trench are sequentially etched from top to bottom in the middle of the upper surface of the substrate. The upper surface of the first deposition trench is coplanar with the upper surface of the substrate. The second deposition trench is formed at the bottom of the first deposition trench and is located below the first deposition trench. The upper surface of the second deposition trench is coplanar with the lower surface of the first deposition trench. The first deposition trench and the second deposition trench are connected. The composite top electrode array is deposited on the upper surface of the substrate. The intermediate dielectric layer array is deposited in the first deposition trench. The composite bottom electrode array is deposited in the second deposition trench. The lower surface of the composite top electrode array is connected to the upper surface of the intermediate dielectric layer array. The lower surface of the intermediate dielectric layer array is connected to the upper surface of the composite bottom electrode array, so that the composite top electrode array, the intermediate dielectric layer array, and the composite bottom electrode array are sequentially attached to each other in the vertical direction.

[0027] It should be noted that, based on the principles of etching and deposition (as described in the preparation method below), the cross-section of the second deposition tank is usually smaller than that of the first deposition tank. Of course, in practical applications, the cross-section of the second deposition tank can also be set to be greater than or equal to that of the first deposition tank based on different practical needs.

[0028] Furthermore, the composite top electrode array may include a lower noble metal layer and an upper transparent conductive oxide layer; wherein the lower noble metal layer is vertically stacked above the intermediate dielectric layer array, and the upper transparent conductive oxide layer is vertically stacked above the lower noble metal layer. Additionally, the composite bottom electrode array may include a lower metal layer and an upper inert noble metal layer; wherein the lower metal layer is vertically stacked at the bottom of the second deposition tank, and the upper inert noble metal layer is vertically stacked above the lower metal layer.

[0029] In the actual material selection process, the substrate can be at least one of thermally oxidized silicon substrate and quartz substrate; the metal material of the lower metal layer can be titanium; the metal material of the upper inert noble metal layer can be at least one of platinum, gold and palladium; the material of the intermediate dielectric layer array can be at least one of zinc oxide, zirconium oxide, hafnium oxide, silicon oxide, tantalum oxide, titanium oxide, aluminum oxide, nickel oxide, tungsten oxide, tin oxide, indium oxide, indium tin oxide, indium gallium zinc oxide, and indium gallium cadmium oxide; the metal material of the lower noble metal layer can be at least one of platinum, gold, silver and palladium; and the material of the upper transparent conductive oxide layer can be at least one of indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide.

[0030] Regarding the size design, the thickness of the lower metal layer can be set to 1~30 nm, the thickness of the upper inert metal layer can be set to 10~200 nm, the thickness of the intermediate dielectric layer array can be set to 10~500 nm, the thickness of the lower noble metal layer can be set to 10 nm, and the thickness of the upper transparent conductive oxide layer can be set to 20~200 nm.

[0031] on the other hand, Figure 2 The flowchart illustrates the fabrication method of an oxide all-optically controlled memristor array according to the present invention, which is composed of... Figure 2 As shown, to illustrate in detail the fabrication process of the oxide fully optically controlled memristor array provided by the present invention, the present invention also provides a method for fabricating the aforementioned oxide fully optically controlled memristor array, comprising: S110: The composite bottom electrode array is fabricated on the substrate using lift-off photolithography and backfilling processes; S120: The intermediate dielectric layer array is prepared on the composite bottom electrode array using lift-off photolithography and backfilling processes; S130: Anneal the substrate, the composite bottom electrode array, and the intermediate dielectric layer array; wherein, the annealing temperature in this step is preferably 400~700℃; S140: The composite top electrode array is fabricated above the intermediate dielectric layer array using a lift-off photolithography process; S150: The substrate, the composite bottom electrode array, the intermediate dielectric layer array, and the composite top electrode array are subjected to overall annealing; wherein, the annealing temperature of this step is preferably 100~200℃.

[0032] It should be noted that the backfill process is a method for achieving surface planarization of electrodes or dielectric layers; it includes the following steps: Step A: Form patterned trenches of the composite bottom electrode layer array or intermediate dielectric layer array on the substrate by etching process; Step B: Fill the patterned trenches with metal or oxide material by deposition process.

[0033] Furthermore, the process of fabricating the composite bottom electrode array on the substrate using lift-off photolithography and backfill processes includes: S111: Spin-coat photoresist onto the substrate, and use lift-off photolithography to form the pattern of the composite bottom electrode array and develop the pattern; S112: The substrate is etched based on the pattern of the composite bottom electrode array (based on inductively coupled plasma etching or wet etching) to form a primary pattern trench (i.e., a composite bottom electrode array pattern trench) on the substrate; wherein the depth of the primary pattern trench is equal to the sum of the thickness of the composite bottom electrode array and the thickness of the intermediate dielectric layer array. S113: Deposit a composite bottom electrode array film in the primary patterned trench and perform a resist removal process.

[0034] Furthermore, the process of fabricating the intermediate dielectric layer array on the composite bottom electrode array using lift-off lithography and backfill processes includes: S121: Form the array pattern of the intermediate dielectric layer on the composite bottom electrode array film using lift-off photolithography and develop the pattern; S122: The composite bottom electrode array film is etched based on the array pattern of the intermediate dielectric layer (based on inductively coupled plasma etching or wet etching) to form secondary pattern trenches (i.e., intermediate dielectric layer array pattern trenches) on the composite bottom electrode array film; wherein the depth of the secondary pattern trenches is equal to the thickness of the intermediate dielectric layer array. S123: Deposit an intermediate dielectric layer array oxide film in the secondary patterned trench and perform a resist removal process; wherein the intermediate dielectric layer array oxide film is prepared by magnetron sputtering, electron beam evaporation, or atomic layer deposition.

[0035] In addition, the process of fabricating the composite top electrode array above the intermediate dielectric layer array using a lift-off photolithography process includes: S141: The pattern of the composite top electrode array is formed on the oxide film of the intermediate dielectric layer array using a lift-off photolithography process, and the pattern is developed. S142: A composite top electrode array film is deposited on top of the intermediate dielectric layer array oxide film based on the pattern of the composite top electrode array, and then the resist is removed.

[0036] Furthermore, the present invention also provides a method for optical signal modulation of the aforementioned oxide all-optically controlled memristor array; comprising: Ultraviolet light with a wavelength of 200~450 nm is used as the writing light to increase the conductivity of the all-optically controlled memristor array, or visible light or infrared light with a wavelength of 500~1000 nm is used as the erasing light to decrease the conductivity of the all-optically controlled memristor array. The all-optically controlled memristor array can be controlled by the write light or the erase light.

[0037] The oxide fully optically controlled memristor array, its fabrication method, and its control method provided by the present invention will be further illustrated below by way of examples.

[0038] Example 1: Figure 3 A physical diagram of an oxide-based fully optically controlled memristor array according to Embodiment 1 of the present invention is shown. Figure 4 The process flow of the fabrication method of the oxide all-optically controlled memristor array according to Embodiment 1 of the present invention is shown. Figure 5 The mask (array size 16×16, linewidth 10 μm) required for the lift-off lithography process provided according to Embodiment 1 of the present invention is shown. Figure 6The photoelectric response of the oxide fully optically controlled memristor array device prepared according to Embodiment 1 of the present invention is shown in the photoelectric response with enhanced conductivity and the photoelectric response with decreased conductivity in the high conductivity state (wherein, the optical signal with enhanced conductivity of the device in the memristor array uses 350 nm ultraviolet light, and the optical signal with decreased conductivity of the device in the memristor array uses 550 nm green light, and the optical power density is 20 μW / cm² in both cases). 2 ).

[0039] Combination Figures 3 to 6 As shown, this embodiment provides an oxide-based fully optically controlled memristor array, comprising a bottom electrode layer array, an intermediate dielectric layer array, and a top electrode layer array sequentially formed on a substrate. The intermediate dielectric layer array is composed of oxides. In this embodiment, the substrate is a thermally oxidized silicon wafer. The bottom electrode layer material is platinum with a thickness of 25 nm; the oxide layer material is zinc oxide (ZnO) with a thickness of 50 nm; and the top electrode layer material is platinum and indium tin oxide with a thickness of 40 nm (10 nm Pt + 30 nm ITO).

[0040] The detailed fabrication method of the memristor array in this embodiment is as follows: (1) Prepare a clean thermally oxidized silicon wafer as a substrate, and ultrasonically clean it for 10 min in acetone, anhydrous ethanol and deionized water respectively, and then dry it in a nitrogen atmosphere.

[0041] (2) The substrate was pretreated on a heating platform at 95 °C for 3 min to remove surface water vapor and organic residue, and then spin-coated with photoresist AZ5214; pre-baking was performed at 110 °C for 90 s; after cooling, ultraviolet lithography was performed (wavelength 365 nm, power density 10 μw / cm²). 2 Exposure for 40 seconds; reverse baking at 110°C for 150 seconds; secondary exposure using a UV lithography machine for 8 seconds; development.

[0042] (3) 75 nm of CHF3 plasma was etched using inductively coupled plasma without removing the resist. A 15 nm thick titanium film was deposited on the array pattern obtained by photolithography using magnetron sputtering as a buffer layer to prevent the bottom electrode film from falling off. A 10 nm thick platinum film was prepared as the bottom electrode using magnetron sputtering to obtain the bottom electrode array; the resist was removed by ultrasonic cleaning for 3 min using acetone, anhydrous ethanol and deionized water.

[0043] The specific parameters for the magnetron sputtering during the fabrication of the bottom electrode array are as follows: Using Ti as the sputtering target, a transition Ti thin film was grown on the substrate in an argon atmosphere by radio frequency sputtering. The gas flow rate was 30 sccm, the sputtering power was 60 W, and the growth pressure was 0.5 Pa.

[0044] Using Pt as the sputtering target, a platinum bottom electrode film was grown on a Ti film in a pure argon atmosphere by DC sputtering at a gas flow rate of 30 sccm, a sputtering power of 60 W, and a growth pressure of 1 Pa.

[0045] All of the above processes were carried out at room temperature.

[0046] (1) Repeat step (2) to obtain the intermediate dielectric layer array pattern.

[0047] (2) 50 nm thick zinc oxide film was etched using inductively coupled plasma of SF6 plasma without removing the resist. A 50 nm thick zinc oxide film was deposited on the array pattern obtained by photolithography using magnetron sputtering as an intermediate dielectric layer array; the resist was removed by ultrasonic cleaning with acetone, anhydrous ethanol and deionized water for 3 min.

[0048] The specific parameters for magnetron sputtering during the fabrication of the intermediate dielectric layer array are as follows: Using ZnO as the sputtering target, a ZnO thin film was grown on the etched bottom electrode layer in an argon atmosphere by radio frequency sputtering. The gas flow rate was 30 sccm, the sputtering power was 60 W, and the growth pressure was 0.5 Pa. The above process was carried out at room temperature.

[0049] (3) Anneal the substrate, bottom electrode array and intermediate dielectric layer array at 600 °C.

[0050] (4) Repeat step (2) to obtain the top electrode array pattern.

[0051] (5) A 10 nm thick Pt layer was sputtered onto the obtained intermediate dielectric layer array using a magnetron sputtering method with DC sputtering. Subsequently, a 30 nm thick ITO conductive layer was sputtered onto the Pt film, and the resulting composite top electrode film served as the top electrode array. The adhesive was removed by ultrasonic cleaning with acetone, anhydrous ethanol, and deionized water for 3 min. Finally, an oxide-based fully optically controlled memristor array was obtained.

[0052] (6) Anneal the entire device at 150 °C.

[0053] The specific parameters for magnetron sputtering during the fabrication of the top electrode array are as follows: Using Pt as the sputtering target, a transition layer Pt thin film was grown on the substrate in an argon atmosphere by radio frequency sputtering. The gas flow rate was 30 sccm, the sputtering power was 60 W, and the growth pressure was 1 Pa.

[0054] Using ITO as the sputtering target, ITO films were grown on Pt films by DC sputtering in an atmosphere of argon and oxygen in a ratio of 20:0.1, with a gas flow rate of 20 sccm:0.1 sccm, a sputtering power of 65 W, and a growth pressure of 0.6 Pa.

[0055] All of the above processes were carried out at room temperature.

[0056] A schematic diagram of the memristor array prepared in this embodiment is shown below. Figure 1 As shown, the memristor, from bottom to top, comprises a substrate, a bottom electrode layer array, an intermediate dielectric layer array, and a top electrode layer array. Illumination is input through the top electrode. The substrate is a thermally oxidized silicon wafer. Between the substrate and the bottom electrode layer is a buffer layer composed of a 15 nm thick titanium film, which contacts both the bottom electrode layer and the thermally oxidized layer of the thermally oxidized silicon wafer. The bottom electrode layer is a 10 nm thick platinum film. The intermediate dielectric layer is composed of ZnO oxide with a total thickness of 50 nm. The top electrode layer is a composite film of Pt and ITO with a thickness of 40 nm.

[0057] Electrical tests were performed on the devices in the memristor array prepared in this embodiment. The bottom electrode array pins were grounded, voltage was applied to the top electrode array, and light was input through the top electrode array. Figure 6 The photoelectric response of the devices in the memristor array prepared in this embodiment shows the increase in conductivity under ultraviolet light irradiation and the decrease in conductivity under green light irradiation.

[0058] Example 2

[0059] Figure 7 The photoelectric response of the oxide fully optically controlled memristor array device prepared according to Embodiment 2 of the present invention is shown in the photoelectric response with enhanced conductivity and the photoelectric response with decreased conductivity in the high conductivity state (wherein, the optical signal with enhanced conductivity of the device in the memristor array uses 350 nm ultraviolet light, and the optical signal with decreased conductivity of the device in the memristor array uses 550 nm green light, and the optical power density is 20 μW / cm² in both cases). 2 ).

[0060] The difference between this embodiment and Embodiment 1 is that the intermediate dielectric layer array deposition method is atomic layer deposition, the etching method is wet etching, and the etching solution is BOE.

[0061] Combination Figures 1 to 7 As shown, the detailed fabrication method of the memristor array in this embodiment is as follows: (1) Prepare a clean thermally oxidized silicon wafer as a substrate, and ultrasonically clean it for 10 min in acetone, anhydrous ethanol and deionized water respectively, and then dry it in a nitrogen atmosphere.

[0062] (2) The substrate was pretreated on a heating platform at 95 °C for 3 min to remove surface water vapor and organic residue, and then spin-coated with photoresist AZ5214; pre-baking was performed at 110 °C for 90 s; after cooling, ultraviolet lithography was performed (wavelength 365 nm, power density 10 μw / cm²). 2 Exposure for 40 seconds; reverse baking at 110°C for 150 seconds; secondary exposure using a UV lithography machine for 8 seconds; development.

[0063] (3) Etch 75 nm using BOE etching solution without removing the resist. Deposit a 15 nm thick titanium film on the array pattern obtained by photolithography using magnetron sputtering as a buffer layer to prevent the bottom electrode film from falling off. Prepare a 10 nm thick platinum film as the bottom electrode using magnetron sputtering to obtain the bottom electrode array; remove the resist by ultrasonic cleaning for 3 min using acetone, anhydrous ethanol and deionized water.

[0064] The specific parameters for the magnetron sputtering during the fabrication of the bottom electrode array are as follows: Using Ti as the sputtering target, a transition Ti thin film was grown on the substrate in an argon atmosphere by radio frequency sputtering. The gas flow rate was 30 sccm, the sputtering power was 60 W, and the growth pressure was 0.5 Pa.

[0065] Using Pt as the sputtering target, a platinum bottom electrode film was grown on a Ti film in a pure argon atmosphere by DC sputtering at a gas flow rate of 30 sccm, a sputtering power of 60 W, and a growth pressure of 1 Pa.

[0066] All of the above processes were carried out at room temperature.

[0067] (4) Repeat step (2) to obtain the intermediate dielectric layer array pattern.

[0068] (5) Use BOE etching solution to etch 50 nm without removing the resist. Deposit a 50 nm thick zinc oxide film on the array pattern obtained by photolithography using atomic layer deposition as an intermediate dielectric layer array; remove the resist by ultrasonic cleaning for 3 min using acetone, anhydrous ethanol and deionized water.

[0069] The atomic layer deposition precursors used were diethylzinc and ozone. The purge gas was high-purity nitrogen.

[0070] One cycle consists of the following steps: 1. Introduce diethylzinc for 25 ms; 2. Purge with nitrogen for 15 s; 3. Introduce ozone for 15 ms; 4. Purge with nitrogen for 15 s; repeat 500 times in total. The growth rate is 1.0 Å / cycle.

[0071] The above process was carried out at 150 °C.

[0072] (6) Anneal the substrate, bottom electrode array and intermediate dielectric layer array at 600 °C.

[0073] (7) Repeat step (2) to obtain the top electrode array pattern.

[0074] (8) A 10 nm thick Pt layer was sputtered onto the obtained intermediate dielectric layer array using DC sputtering via magnetron sputtering. Subsequently, a 30 nm thick ITO conductive layer was sputtered onto the Pt film, resulting in a composite top electrode film used as the top electrode array. The adhesive was removed by ultrasonic cleaning for 3 min using acetone, anhydrous ethanol, and deionized water. The final result was an oxide-based fully optically controlled memristor array. The specific parameters of the magnetron sputtering are as follows: Using Pt as the sputtering target, a transition layer Pt thin film was grown on the substrate in an argon atmosphere by radio frequency sputtering. The gas flow rate was 30 sccm, the sputtering power was 60 W, and the growth pressure was 1 Pa.

[0075] Using ITO as the sputtering target, ITO films were grown on Pt films by DC sputtering in an atmosphere of argon and oxygen in a ratio of 20:0.1, with a gas flow rate of 20 sccm:0.1 sccm, a sputtering power of 65 W, and a growth pressure of 0.6 Pa.

[0076] All of the above processes were carried out at room temperature.

[0077] (9) Anneal the entire array at 150 °C.

[0078] Electrical tests were performed on the devices in the memristor array prepared in this embodiment. The bottom electrode array pins were grounded, voltage was applied to the top electrode array, and light was input through the top electrode array. Figure 7 The photoelectric response of the device in the memristor array prepared in this embodiment is shown, where the conductivity increases under ultraviolet light irradiation and decreases under green light irradiation.

[0079] As can be seen from the above two embodiments, the method for fabricating the oxide fully optically controlled memristor array provided by the present invention has a simple fabrication process. The array can be fabricated using only three photolithography steps, two etching steps, and three magnetron sputtering steps. It does not involve complex processes such as high-temperature fabrication or double-layer homogenization, and is compatible with CMOS processes.

[0080] As referred above Figures 1 to 7 The oxide-based optically controlled memristor array, its fabrication method, and its control method according to the present invention are described by way of example. However, those skilled in the art should understand that various modifications can be made to the oxide-based optically controlled memristor array, its fabrication method, and its control method proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the content of the appended claims.

Claims

1. An oxide-based fully optically controlled memristor array, characterized in that, include: Substrate, composite bottom electrode array, intermediate dielectric layer array, and composite top electrode array; among which, A first deposition trench is formed on the upper surface of the substrate, and a second deposition trench is formed at the bottom of the first deposition trench. The composite top electrode array is disposed on the upper surface of the substrate, the intermediate dielectric layer array is disposed within the first deposition trench, and the composite bottom electrode array is disposed within the second deposition trench; and, The composite top electrode array, the intermediate dielectric layer array, and the composite bottom electrode array are sequentially bonded to each other in the vertical direction.

2. The oxide-based fully optically controlled memristor array as described in claim 1, characterized in that, The composite top electrode array includes a lower metal layer and an upper transparent conductive oxide layer; wherein the lower metal layer is vertically stacked above the intermediate dielectric layer array, and the upper transparent conductive oxide layer is vertically stacked above the lower metal layer.

3. The oxide-based fully optically controlled memristor array as described in claim 2, characterized in that, The composite bottom electrode array includes a lower active metal layer and an upper inert metal layer; wherein the lower active metal layer is vertically stacked at the bottom of the second deposition tank, and the upper inert metal layer is vertically stacked above the lower metal layer.

4. The oxide-based fully optically controlled memristor array as described in claim 3, characterized in that, The substrate includes at least one of a thermally oxidized silicon substrate and a quartz substrate; and / or, The metallic material of the lower active metal layer includes titanium, nickel; and / or, The metallic material of the upper inert metal includes at least one of platinum, gold, and palladium; and / or, The material of the intermediate dielectric layer array includes at least one of zinc oxide, zirconium oxide, hafnium oxide, silicon oxide, tantalum oxide, titanium oxide, aluminum oxide, nickel oxide, tungsten oxide, tin oxide, indium oxide, indium tin oxide, indium gallium zinc oxide, and indium gallium cadmium oxide; and / or, The metal material of the lower metal layer includes at least one of platinum, gold, silver, and palladium; and / or, The material of the upper transparent conductive oxide layer includes at least one of indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide.

5. The oxide-based fully optically controlled memristor array as described in claim 4, characterized in that, The thickness of the lower active metal layer is 1~100 nm; and / or, The thickness of the upper inert metal layer is 10~200 nm; and / or, The thickness of the intermediate dielectric layer array is 10~500 nm; and / or, The thickness of the lower metal layer is 1~20 nm; and / or, The thickness of the upper transparent conductive oxide layer is 10~200 nm.

6. A method for fabricating an oxide-based fully optically controlled memristor array as described in any one of claims 1 to 5, characterized in that, include: The composite bottom electrode array was fabricated on the substrate using lift-off lithography and backfill processes. The intermediate dielectric layer array is fabricated on the composite bottom electrode array using lift-off lithography and backfill processes. The substrate, the composite bottom electrode array, and the intermediate dielectric layer array are annealed. The composite top electrode array is fabricated above the intermediate dielectric layer array using a lift-off photolithography process; The substrate, the composite bottom electrode array, the intermediate dielectric layer array, and the composite top electrode array are subjected to overall annealing.

7. The method for fabricating an oxide-based fully optically controlled memristor array as described in claim 6, characterized in that, The process of fabricating the composite bottom electrode array on the substrate using lift-off lithography and backfill processes includes: Photoresist is spin-coated onto the substrate, and a pattern of the composite bottom electrode array is formed using a lift-off photolithography process, followed by development of the pattern. The substrate is etched based on the pattern of the composite bottom electrode array to form a primary pattern trench on the substrate; wherein the depth of the primary pattern trench is equal to the sum of the thickness of the composite bottom electrode array and the thickness of the intermediate dielectric layer array; A composite bottom electrode array film is deposited in the primary patterned trench and then subjected to a resist removal process. And / or, during the annealing process of the substrate, the composite bottom electrode array and the intermediate dielectric layer array, the annealing temperature is 400~700 °C; And / or, during the overall annealing of the substrate, the composite bottom electrode array, the intermediate dielectric layer array, and the composite top electrode array, the annealing temperature is 100~200 ℃.

8. The method for fabricating an oxide-based fully optically controlled memristor array as described in claim 7, characterized in that, The process of fabricating the intermediate dielectric layer array on the composite bottom electrode array using lift-off lithography and backfill processes includes: The array pattern of the intermediate dielectric layer is formed on the composite bottom electrode array film using a lift-off photolithography process, and the pattern is then developed. The composite bottom electrode array film is etched based on the array pattern of the intermediate dielectric layer to form secondary pattern trenches on the composite bottom electrode array film; wherein the depth of the secondary pattern trenches is equal to the thickness of the intermediate dielectric layer array. An intermediate dielectric layer array oxide film is deposited in the secondary patterned trench and then subjected to a resist removal process; wherein the intermediate dielectric layer array oxide film is prepared by magnetron sputtering, electron beam evaporation, or atomic layer deposition.

9. The method for fabricating an oxide-based fully optically controlled memristor array as described in claim 8, characterized in that, The process of fabricating the composite top electrode array using lift-off photolithography on top of the intermediate dielectric layer array includes: The pattern of the composite top electrode array is formed on top of the intermediate dielectric layer array oxide film using a lift-off photolithography process, and the pattern is then developed. A composite top electrode array film is deposited on top of the intermediate dielectric layer array oxide film based on the pattern of the composite top electrode array, and then the resist is removed.

10. A method for optical signal modulation of an oxide-based fully optically controlled memristor array as described in any one of claims 1 to 5; characterized in that, include: Ultraviolet light with a wavelength of 200~450 nm is used as the writing light to increase the conductivity of the all-optically controlled memristor array, or visible light or infrared light with a wavelength of 500~1000 nm is used as the erasing light to decrease the conductivity of the all-optically controlled memristor array. The all-optically controlled memristor array can be controlled by the write light or the erase light.

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