Patterning method and semiconductor structure

Abstract

In the patterning method, a to-be-etched layer, a first mask layer and a second mask layer are sequentially stacked from bottom to top, the to-be-etched layer comprises an interconnection region and a peripheral non-interconnection region, the interconnection region comprises first regions and second regions arranged alternately along a first axis, and a part of the second regions comprise second portions protruding from boundaries of adjacent first regions along a second axis; a plurality of shielding layer grooves arranged along the first axis are formed in the second mask layer on the non-interconnection region, and the plurality of shielding layer grooves are distributed on side edges of the second portions; the plurality of shielding layer grooves are filled to form a plurality of shielding layers; a photoresist layer is formed on the second mask layer, the photoresist layer has a plurality of etching openings corresponding to the plurality of second regions and a plurality of auxiliary openings corresponding to the plurality of shielding layers, so that the manufacturing process window of the etching opening corresponding to the second portion can be increased in the photoetching process. The semiconductor structure is manufactured by using the above-mentioned patterning method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a patterning method and a semiconductor structure. Background Technology

[0002] In semiconductor device manufacturing processes, photolithography is typically used to transfer patterns from a photomask onto a substrate. The patterning process for semiconductor devices generally includes: providing a substrate; forming a photoresist layer on the substrate; exposing and developing the photoresist layer to form a patterned photoresist layer, thereby transferring the pattern from the photomask to the photoresist layer; etching the substrate using the patterned photoresist layer as a mask, thereby transferring the pattern from the photoresist layer to the substrate; and removing the photoresist.

[0003] As the feature size of semiconductor devices continues to shrink and the integration density continues to increase, patterning processes face many challenges. For example, the increasing complexity of patterns in photolithography leads to more and more process weaknesses.

[0004] Figures 1 to 3 This is a planar schematic diagram of different semiconductor structures. For example... Figures 1 to 3 As shown, the semiconductor structure includes interconnect regions and non-interconnect regions 103 located around the interconnect regions. The interconnect regions include multiple first regions 101 and multiple second regions 102, with the first regions 101 and second regions 102 arranged alternately in the X direction. A portion of the second regions 102 includes a first portion 102a and a second portion 102b. The first portion 102a of the second region is adjacent to two adjacent first regions 101, while the second portion 102b is not adjacent to any first region 101; that is, the second portion 102b can be referred to as an isolated region. When fabricating the patterns of the first regions 101 and 102, compared to the first portions 102a of the first regions 101 and 102, the fabrication window for the pattern of the second portion 102b of the second region is narrower, meaning that the pattern of the second portion 102b of the second region is prone to fabrication weaknesses. (Reference) Figures 1 to 3 The graphic within the dashed box is used as an example. Figure 1 isolated groove graphic endpoints in Figure 2 Head-to-head graphics and Figure 3 The weak points in the process, such as the multi-line bridge structure, are not affected by the surrounding patterns during the patterning process. Instead, they are formed directly through photolithography and etching processes. This can cause the weak points in the photolithography process to directly form patterning defects, resulting in poor performance of semiconductor devices. Summary of the Invention

[0005] This invention provides a patterning method that can increase the process window for fabricating isolated region patterns and improve the performance of semiconductor devices. This invention also provides a semiconductor structure fabricated using the aforementioned patterning method.

[0006] To achieve the above objectives, the present invention provides a graphical method. The graphical method includes:

[0007] The system provides a layer to be etched, a first mask layer, and a second mask layer stacked sequentially from bottom to top. The layer to be etched includes interconnect regions and non-interconnect regions located around the interconnect regions. The interconnect regions include a plurality of first regions and a plurality of second regions arranged alternately along a first axis. Both the first regions and the second regions extend along a second axis perpendicular to the first axis. Each of the plurality of second regions includes a first portion, which is adjacent to an adjacent first region. A portion of the second regions includes a second portion. The first portion and the second portion of the same second region are arranged along the second axis, and the second portion protrudes beyond the boundary of the adjacent first region.

[0008] The second mask layer is etched and stops on the upper surface of the first mask layer, forming a plurality of shielding layer grooves arranged along the first axis in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves all extend along the second axis and are distributed on the side of the second portion, and the projection of the shielding layer grooves and the second portion in the second axis at least partially overlaps;

[0009] Multiple shielding layers are formed by filling the grooves of the multiple shielding layers;

[0010] A photoresist layer is formed on the second mask layer, the photoresist layer having a plurality of etching openings corresponding to the plurality of second regions and a plurality of auxiliary openings corresponding to the plurality of masking layers; and

[0011] Using the photoresist layer and the plurality of masking layers as masks, the second mask layer is etched to form a plurality of second grooves corresponding to the plurality of second regions, and the bottom of the plurality of second grooves is exposed above the upper surface of the first mask layer.

[0012] Optionally, while forming the plurality of shielding layer grooves in the second mask layer on the non-interconnected area, a second dividing groove is formed in the second mask layer on a portion of the second area, the second dividing groove dividing the corresponding second area in the second axial direction.

[0013] Optionally, before forming the plurality of masking layer grooves, the patterning method includes: removing the second mask layer on the plurality of first regions to form a plurality of first grooves, the bottom of the plurality of first grooves exposing the upper surface of the first mask layer.

[0014] Optionally, the width of the shielding layer groove in the first axial direction is less than or equal to the width of the second dividing groove in the second axial direction.

[0015] Optionally, the method of filling the plurality of shielding layer grooves to form the plurality of shielding layers includes:

[0016] A filling material layer is formed, which covers the inner surfaces of the plurality of first grooves, the second dividing grooves and the plurality of shielding layer grooves, as well as the upper surface of the second mask layer;

[0017] The filling material layer is etched back until the upper surface of the second mask layer and the upper surface of the first mask layer located at the bottom of the plurality of first grooves are exposed. The filling material layer on the sidewalls of the plurality of first grooves is retained as sidewalls, and the filling material layer located in the second dividing groove and the plurality of shielding layer grooves is retained as the second dividing mask layer and the plurality of shielding layers, respectively.

[0018] Optionally, after etching the second mask layer to form the plurality of second grooves, the patterning method includes:

[0019] Remove the photoresist layer;

[0020] Using the second dividing mask layer, the sidewalls, the plurality of shielding layers and the remaining second mask layer as masks, the first mask layer and the layer to be etched are etched sequentially and the etching stops in the layer to be etched, so as to form corresponding patterns in the first region and the second region.

[0021] Optionally, the width of the shielding layer groove in the first axial direction is greater than the width of the second dividing groove in the second axial direction.

[0022] Optionally, a portion of the second zone may consist only of the first portion, and at least a portion of the shielding layer grooves may correspond to the positions of the second zones consisting only of the first portion and be disposed on the end sides of the corresponding second zones.

[0023] Optionally, the first and second portions of the same second region are connected; or, the first and second portions of the same second region are spaced apart along the second axis.

[0024] Another aspect of the present invention provides a semiconductor structure formed using the patterning method described above.

[0025] In the patterning method of the present invention, within the interconnect region of the layer to be etched, the second portion of the second region extends beyond the boundary of the first region adjacent to the second region, that is, the second portion of the second region is isolated from the first region and the first portion of the second region. Multiple shielding layer grooves are formed in the second mask layer on the non-interconnect region. These multiple shielding layer grooves extend along the second axial direction and are located on the side of the second portion. The shielding layer grooves and the projection of the second portion along the second axial direction at least partially overlap. The multiple shielding layer grooves are then filled to form multiple shielding layers. Next, a photoresist layer is formed on the second mask layer. The photoresist layer has multiple etching openings corresponding to multiple second regions and multiple... The multiple auxiliary openings corresponding to the shielding layer can increase the fabrication process window of the pattern (i.e., the etching opening) in the photolithography process, which helps to overcome the process weaknesses of the pattern corresponding to the second part. This can improve the accuracy of the pattern corresponding to the second part in the multiple second grooves formed by subsequent etching, and help improve the performance of the semiconductor device obtained later. Moreover, during the etching process of forming the multiple second grooves, multiple shielding layers are used as etching masks. Due to the obstruction of multiple shielding layers, the pattern of the multiple auxiliary openings will not be transmitted to the first mask layer and the layer to be etched below through the shielding layers, thus not affecting the original pattern structure of the semiconductor device.

[0026] The semiconductor structure of the present invention is fabricated using the above-described patterning method, and the semiconductor structure has the same or similar advantages as the above-described patterning method. Attached Figure Description

[0027] Figures 1 to 3 This is a planar schematic diagram of different semiconductor structures.

[0028] Figures 4 to 7 This is a schematic diagram of the process of fabricating a semiconductor structure using a graphical method.

[0029] Figure 8 This is a flowchart illustrating a graphical method according to an embodiment of the present invention.

[0030] Figures 9 to 21 This is a schematic diagram illustrating the process of fabricating a semiconductor structure using a graphical method according to an embodiment of the present invention. Detailed Implementation

[0031] The graphical method and semiconductor structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0032] Figures 4 to 7This is a schematic diagram of the process of fabricating a semiconductor structure using a graphical method.

[0033] in, Figures 4 to 7 All are top views of semiconductor structures. The following are combined with... Figures 4 to 7 The steps of this graphical method are described.

[0034] The graphical method mainly includes the following steps.

[0035] Step 1, refer to Figure 4 Provided from the bottom up (i.e., along) Figure 4 The etching layer, the first mask layer 20, and the second mask layer 30 are sequentially stacked in a direction perpendicular to the paper and outwards. The etching layer includes interconnect regions and non-interconnect regions located around the interconnect regions. The interconnect regions include multiple first regions ( Figure 4 (Not shown in the diagram) and multiple second regions 102, with the first and second regions 102 alternating along a first axial direction (e.g., the X-axis) and both extending along a second axial direction perpendicular to the first axial direction (e.g., the Y-axis). Each second region 102 includes a first portion 102a, and a portion of the second regions 102 includes a second portion 102b. The first portion 102a and the second portion 102b of the same second region are arranged sequentially along the second axial direction, and the second portion 102b extends beyond the boundary of the first region adjacent to the second region 102.

[0036] Step 2, refer to Figure 4 Remove multiple first zones ( Figure 4 The second mask layer (not shown) forms a plurality of first grooves 301, the bottom of the plurality of first grooves 301 being exposed above the upper surface of the first mask layer 20.

[0037] Step 3, as Figure 4 As shown, the second mask layer 30 is etched and stops on the upper surface of the first mask layer 20, forming a second dividing groove 302 on a portion of the second region 102. The second dividing groove 302 divides the second region 102 in the second axial direction.

[0038] Step four, as Figure 5 As shown, a filling material layer is deposited on the inner surfaces of a plurality of first grooves 301 and second dividing grooves 302, and the filling material layer in the plurality of first grooves 301 is etched back to form sidewalls 303 on the sidewalls of the plurality of first grooves 301 and a second dividing mask layer 302a in the second dividing groove 302.

[0039] Step 5, as Figure 6 As shown, a first segmentation mask layer 304 is formed in a portion of the first grooves 301, and the first segmentation mask layer 304 segments the first grooves 301 in the second axis.

[0040] Step six, as follows Figure 7 As shown, the remaining second mask layer 30 on the second region 102 is removed by photolithography and etching processes to form a plurality of second grooves 305.

[0041] Step 7: Using the sidewall 303, the second segmentation mask layer 302a, the first segmentation mask layer 304, and the remaining second mask layer 30 on the first mask layer 20 as masks, the first mask layer 20 and the layer to be etched are etched downwards in sequence and the etching stops in the layer to be etched, forming corresponding patterns in the first region and the second region 102 of the layer to be etched.

[0042] Since the second part 102b of the second region extends beyond the boundary of the adjacent first region, meaning that the second part 102b is a relatively isolated area, the pattern of the second part 102b of the second region is not affected by the sidewalls 303 and other patterns on the first region during the formation process. Instead, it is formed directly through photolithography and etching processes. This results in a narrow process window for the pattern fabrication of the second part 102b of the second region. The pattern of the second part 102b is prone to process weaknesses. This will cause the process weaknesses in the photolithography process to directly form patterning defects, which in turn leads to poor performance of the semiconductor device.

[0043] In order to increase the process window for patterning isolated regions (i.e., the second part of the second region) and improve the performance of semiconductor devices, this embodiment provides a patterning method. Figure 8 This is a flowchart illustrating a graphical method according to an embodiment of the present invention. Figure 8 As shown, the graphical method includes the following steps:

[0044] S1, providing a layer to be etched, a first mask layer, and a second mask layer stacked sequentially from bottom to top; the layer to be etched includes interconnect regions and non-interconnect regions located around the interconnect regions, the interconnect regions include a plurality of first regions and a plurality of second regions arranged alternately along a first axis, the first regions and the second regions both extending along a second axis perpendicular to the first axis; each of the plurality of second regions includes a first portion, the first portion being adjacent to an adjacent first region; a portion of the second regions includes a second portion, the first portion and the second portion of the same second region are arranged along the second axis, and the second portion protrudes beyond the boundary of the adjacent first region;

[0045] S2, etch the second mask layer and stop at the upper surface of the first mask layer, forming a plurality of shielding layer grooves arranged along the first axis in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves all extend along the second axis and are distributed on the side of the second portion, and the shielding layer grooves and the projection of the second portion in the second axis at least partially overlap.

[0046] S3, fill the multiple shielding layer grooves to form multiple shielding layers;

[0047] S4, a photoresist layer is formed on the second mask layer, the photoresist layer having a plurality of etching openings corresponding to the plurality of second regions and a plurality of auxiliary openings corresponding to the plurality of masking layers;

[0048] S5, using the photoresist layer and the plurality of masking layers as masks, the second mask layer is etched to form a plurality of second grooves corresponding to the plurality of second regions respectively, and the bottom of the plurality of second grooves is exposed on the upper surface of the first mask layer.

[0049] Figures 9 to 21 This is a schematic diagram illustrating the process of fabricating a semiconductor structure using a graphical method according to an embodiment of the present invention. Figure 9 , Figures 11 to 13 , Figure 15 , Figure 17 ,as well as Figures 19 to 21 This is a schematic diagram of the semiconductor structure process. Figure 10 , Figure 14 , Figure 16 and Figure 18 This is a schematic cross-sectional view of the semiconductor structure process. The following is combined with... Figures 9 to 21 The graphical method of this embodiment will be described.

[0050] Figure 9 This shows a planar schematic diagram of the layer to be etched in a semiconductor structure, for reference. Figure 9 In step S1, a layer 10 to be etched is first provided. The layer 10 to be etched includes an interconnect region and a non-interconnect region 103 located around the interconnect region. As an example, the non-interconnect region may surround the interconnect region. In one embodiment, the layer 10 to be etched is formed on a semiconductor substrate. In another embodiment, the layer 10 to be etched is part of the semiconductor substrate.

[0051] The etchable layer 10 can be a single material layer or a multilayer structure composed of stacked different material layers. Preferably, the etchable layer 10 may include a first material layer and a second material layer located on the first material layer. The dielectric constant of the second material layer is higher than that of the first material layer. Because the dielectric constant of the second material layer is higher than that of the first material layer, the second material layer experiences less etching loss during the subsequent etching process. Furthermore, the second material layer can serve as an etching stop layer for the first material layer. During the pattern transfer from the second material layer to the first material layer, the pattern transfer stability is higher, which helps to improve the overall pattern accuracy of the etchable layer 10 and improve the performance of the semiconductor device.

[0052] Specifically, the material of the first material layer may include silicon oxide or a low dielectric constant material with a dielectric constant (K) less than or equal to 3.9. The material of the second material layer may be a hard mask material, such as silicon nitride, titanium nitride, or silicon oxynitride.

[0053] The interconnection area includes a plurality of first areas 101 and a plurality of second areas 102, wherein the plurality of first areas 101 and the plurality of second areas 102 are alternately arranged along a first axial direction (e.g., the X-axis) and all extend along a second axial direction perpendicular to the first axial direction (e.g., the Y-axis). In this embodiment, the arrangement order of the plurality of first areas 101 and the plurality of second areas 102 along the first axial direction can be: first area 101, second area 102, first area 101, ..., second area 102, first area 101. In other embodiments, the arrangement order of the plurality of first areas 101 and the plurality of second areas 102 along the first axial direction can be: second area 102, first area 101, second area 102, ..., first area 101, second area 102.

[0054] Each of the plurality of second regions 102 includes a first portion 102a, which is adjacent to the adjacent first region 101. For example, when a second region 102 is located between two first regions 101, the first portion 102a of the second region is adjacent (connected) to the two adjacent first regions 101; when a second region 102 has a first region 101 on only one side, the first portion 102a of the second region is adjacent to the first region 101 on its side. A portion of the second regions 102 includes a second portion 102b. The first portion 102a and the second portion 102b of the same second region 102 are arranged sequentially along a second axis, and the second portion 102b extends beyond the boundary of the first region 101 adjacent to the second region 102; that is, the second portion 102b is a relatively isolated area. It should be noted that in this embodiment, a portion of the second regions 102 only includes the first portion 102a and does not have a second portion 102b.

[0055] like Figure 9 As shown, in this embodiment, the first portion 102a and the second portion 102b of the same second region 102 can be connected. In another embodiment, the first portion 102a and the second portion 102b of the same second region 102 can be arranged at intervals along the second axis, that is, the first portion 102a and the second portion 102b are not connected.

[0056] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the first mask layer and the second mask layer have been formed on the layer to be etched 10. (See attached image.) Figure 10As shown, a first mask layer 20 and a second mask layer 30 are sequentially stacked on the layer to be etched 10. The first mask layer 20 covers the upper surface of the layer to be etched 10, and the second mask layer 30 covers the upper surface of the first mask layer 20.

[0057] The first mask layer 20 can be a single-layer material layer or a multilayer structure composed of stacked different material layers. The material of the first mask layer 20 may include at least one of a polycrystalline silicon material layer, an amorphous silicon material layer, a silicon dioxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer. The second mask layer 30 can be a single-layer material layer or a multilayer structure composed of stacked different material layers. The material of the second mask layer 30 may include at least one of a polycrystalline silicon material layer, an amorphous silicon material layer, a silicon dioxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer.

[0058] It should be noted that when both the first mask layer 20 and the second mask layer 30 are single-layer material layers, the materials of the first mask layer 20 and the second mask layer 30 are different. When both the first mask layer 20 and the second mask layer 30 are multi-layer structures, the materials of the bottom material layer of the first mask layer 20 and the bottom material layer of the second mask layer 30 can be different.

[0059] In this embodiment, both the first mask layer 20 and the second mask layer 30 can be formed using chemical vapor deposition (CVD) and / or furnace tube processes. Examples of CVD methods include low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), thermally rapid chemical vapor deposition (RTCVD), or plasma-enhanced chemical vapor deposition (PECVD). However, this invention is not limited to these methods and does not restrict the formation method of the first mask layer 20 and the second mask layer 30.

[0060] Figure 11 This is a planar schematic diagram of the semiconductor structure after the first groove is formed in the second mask layer. Figure 11 As shown, after step S1 and before step S2, the graphical method may include: removing the second mask layer 30 on the plurality of first regions 101 to form a plurality of first grooves 301, the bottom of the plurality of first grooves 301 exposing the upper surface of the first mask layer 20.

[0061] Specifically, the method for forming the plurality of first grooves 301 may include: forming a patterned first photoresist layer (not shown in the figure) on the second mask layer 30; using the patterned first photoresist layer as a mask, etching the second mask layer 30 and stopping at the upper surface of the first mask layer 20 to form a plurality of first grooves 301 corresponding to the plurality of first regions 101 respectively, with the bottom of the plurality of first grooves 301 exposed on the upper surface of the first mask layer 20.

[0062] Figure 12This is a planar schematic diagram of the semiconductor structure after multiple masking layer grooves are formed in the second mask layer. (See diagram below.) Figure 12 As shown, after forming the plurality of first grooves 301, step S2 is performed to etch the second mask layer 30 and stop at the upper surface of the first mask layer 20. A plurality of shielding layer grooves 306 arranged along the first axial direction (X-axis) are formed in the second mask layer 30 on the non-interconnect region 103. The plurality of shielding layer grooves 306 extend along the second axial direction (Y-axis) and are distributed on the side of the second portion 102b. The projections of the shielding layer grooves 306 and the second portion 102b in the second axial direction at least partially overlap.

[0063] In one embodiment, the projections of each of the shielding layer grooves 306 and the second portion 102b in the second axial direction at least partially overlap. In another embodiment, the projections of a portion of the shielding layer grooves 306 and the second portion 102b in the second axial direction at least partially overlap; preferably, the projections of the shielding layer grooves 306 and the second portion 102b closest to the second portion 102b in the second axial direction at least partially overlap.

[0064] refer to Figure 9 and Figure 12 Some of the second zones 102 consist only of the first portion 102a adjacent to the first zone 101. For example, when ordered along the X-axis, the first and fourth second zones 102 consist only of the first portion 102a, while the second and third second zones 102 consist of the first portion 102a and the second portion 102b. In this embodiment, at least a portion of the shielding layer grooves 306 can correspond to the positions of the second region 102 that includes only the first portion and are disposed on the end side of the corresponding second region 102, so that the arrangement period of at least a portion of the shielding layer grooves 306 and the arrangement period of the second region 102 that includes only the first portion in the first axial direction are the same. This makes the arrangement period of the combination of the etching openings corresponding to the second portion 102b and multiple auxiliary patterns in the photoresist layer of the subsequent step S4 in the first axial direction the same as the arrangement period of the multiple second regions 102. Thus, in the process of patterning the photoresist layer in the patterning step S4, it helps to increase the fabrication process window of the pattern (etching opening) corresponding to the second portion 102b, helps to improve the accuracy of the pattern corresponding to the second portion 102b, and thus helps to improve the pattern accuracy of the second portion 102b.

[0065] In this embodiment, as Figure 12As shown, while etching the second mask layer 30 and stopping at the upper surface of the first mask layer 20 to form the plurality of shielding layer grooves 306, second dividing grooves 302 can be formed in the second mask layer 30 on a portion of the second regions 102. The second dividing grooves 302 divide the corresponding second regions 102 along the second axis. That is, in this embodiment, while forming the second dividing grooves 302 that divide a portion of the second regions 102, a plurality of shielding layer grooves 306 are formed. Therefore, forming a plurality of shielding layer grooves 306 does not increase the semiconductor structure fabrication process, does not add an additional photomask, and does not increase the semiconductor structure fabrication time. It should be noted that the final pattern of a portion of the second regions 102 is usually not continuous along the second axis, thus requiring the formation of second dividing grooves 302 so that a second dividing mask layer 302a can be subsequently formed to divide the corresponding second regions 102 along the second axis.

[0066] Figure 13 This is a planar schematic diagram of a semiconductor structure after forming multiple shielding layers in one embodiment of the present invention. Figure 13 As shown, after the plurality of shielding layer grooves 306 are formed, step S3 is performed to fill the plurality of shielding layer grooves 306 to form a plurality of shielding layers 307.

[0067] In one embodiment, the width of the shielding layer groove 306 in the first axial direction is less than or equal to the width of the second dividing groove 302 in the second axial direction. For example... Figure 13 As shown, while filling the plurality of shielding layer grooves 306 to form a plurality of shielding layers 307, sidewalls 303 can be formed on the sidewalls of the plurality of first grooves 301 and a second dividing mask layer 302a can be formed in the second dividing groove 302. This can simplify the semiconductor structure manufacturing process and save production costs.

[0068] Figure 14 for Figure 13 A cross-sectional view of the semiconductor structure along line AA. (Reference) Figure 13 and Figure 14The method for forming multiple shielding layers 307, sidewalls 303, and a second segmentation mask layer 302a may include: depositing a filling material layer that covers the inner surfaces of the multiple first grooves 301 and the upper surface of the second mask layer 30, and fills the second segmentation groove 302 and the multiple shielding layer grooves 306; etching back the filling material layer until the upper surface of the second mask layer 30 and the upper surface of the first mask layer 20 located at the bottom surface of the multiple first grooves 301 are exposed; retaining the filling material layer on the sidewalls of the multiple first grooves 301 as sidewalls 303; and retaining the filling material layer located in the second segmentation groove 302 and the multiple shielding layer grooves 306 as the second segmentation mask layer 302a and the multiple shielding layers 307, respectively. It should be noted that when the width of the multiple shielding layer grooves 306 is narrow (i.e., less than or equal to the width of the second segmentation groove 302 in the second axial direction), the shielding layer grooves 306 can be filled in one go.

[0069] Figure 15 This is a planar schematic diagram of the semiconductor structure after the shielding layer has been formed according to another embodiment of the present invention. In another embodiment, as... Figure 15 As shown, the width of the shielding layer groove 306 in the first axial direction is greater than the width of the second dividing groove 302 in the second axial direction. Because the width of the shielding layer groove 306 is relatively large, the shielding layer 307 can be formed by filling the shielding layer groove 306 multiple times, ensuring that the shielding layer groove 306 is completely filled.

[0070] Figure 16 for Figure 15 The diagram shows a cross-sectional view of the semiconductor structure along line BB. (Reference) Figure 15 and Figure 16The method for forming a plurality of masking layer 307, wherein the width of the masking layer groove 306 is greater than the width of the corresponding second region 102, may include: forming a first filling material layer 307a, the first filling material layer 307a covering the inner surfaces of the plurality of first grooves 301, the inner surfaces of the plurality of masking layer grooves 306, and the upper surface of the second mask layer 30, and filling the second dividing groove 302, wherein the first filling material layer 307a does not completely fill the masking layer grooves 306; forming a patterned layer 308 covering the upper surface of the first filling material layer 307a, the patterned layer 308 having a first opening, the first opening exposing the first filling material layer 307a located on the plurality of masking layer grooves 306. The upper surface of the first opening is then deposited; a second filler material layer 307b is formed, which fills the plurality of shielding layer grooves 306; a first back etching is performed until the upper surface of the first filler material layer 307a corresponding to the first opening is exposed; the patterned layer 308 is removed; a second back etching is performed until the upper surface of the second mask layer 30 and the upper surface of the first mask layer 20 at the bottom of the first groove 301 are exposed, the first filler material layer 307a on the sidewall of the first groove 301 is retained as a sidewall 303, the first filler material layer 307a in the second dividing groove 302 is retained as a second dividing mask layer 302a, and the remaining first filler material layer 307a and second filler layer 307b in the shielding layer groove 306 together serve as a shielding layer 307.

[0071] The patterned layer 308 can be a multi-layer structure, for example, including a first patterned layer 308a, a second patterned layer 308b, and a third patterned layer 308c sequentially stacked on a first filling material layer 307a; the first patterned layer 308a can be an oxide layer; the second patterned layer 308b can serve as a bottom anti-reflective layer, and its material can be a polymer with high carbon content; the third patterned layer 308c can be a photoresist layer, which can improve the accuracy of the formed first opening and also improve the shielding effect when etching back the second filling material layer 307b.

[0072] Figure 17This is a planar schematic diagram of the semiconductor structure after the formation of the first segmentation mask layer in one embodiment of the present invention. After forming multiple shielding layers 307 (specifically, for example, after forming sidewalls 303, a second segmentation mask layer 302a, and shielding layers 307), the patterning method may further include: forming a first segmentation mask layer 304 within a portion of the first grooves 301, wherein the first segmentation mask layer 304 segments the corresponding first grooves 301 along the second axial direction. It should be noted that the final pattern of a portion of the first regions 101 is typically not continuous along the second axial direction, therefore, a first segmentation mask layer 304 needs to be formed to segment the corresponding first regions 101 along the second axial direction.

[0073] In this embodiment, the method of forming the first segmentation mask layer 304 may include: forming a mask that covers the upper surface of the second mask layer 30 and fills the first groove 301; forming a first segmentation groove in the mask within a portion of the first grooves 301, the first segmentation groove exposing the upper surface of the first mask layer 20; filling the first segmentation groove to form the first segmentation mask layer 304; and removing the mask.

[0074] After forming a first dividing mask layer 304 in a portion of the first grooves 301, step S4 is performed to form a photoresist layer (hereinafter referred to as the second photoresist layer) on the second mask layer 30. The second photoresist layer has a plurality of etching openings corresponding to the plurality of second regions 102 and a plurality of auxiliary openings corresponding to the plurality of shielding layers 307.

[0075] Figure 18 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the second photoresist layer in one embodiment of the present invention. Figure 18 As shown, the second photoresist layer 309 has multiple etching openings 310 and multiple auxiliary openings 311. The etching openings 310 are located above the corresponding second region 102, and the auxiliary openings 311 are located above the corresponding shielding layer 307.

[0076] During the patterning process (including exposure and development) of the second photoresist layer 309, while forming multiple etching openings 310 corresponding to multiple second regions 102 (including the first part 102a and the second part 102b) in the second photoresist layer 309, multiple auxiliary openings 311 (i.e. auxiliary patterns) corresponding to multiple masking layers 307 are also formed. In this way, the fabrication process window of the pattern corresponding to the second part 102b (the part of the etching opening 310 corresponding to the second part 102b) can be increased in the photolithography process, which helps to overcome the process weaknesses of the pattern corresponding to the second part 102b and improve the accuracy of the etching openings 310 corresponding to the second part 102b.

[0077] Figure 19This is a planar schematic diagram of a semiconductor structure after the formation of a second groove in one embodiment of the present invention. After step S4, step S5 is executed, using the second photoresist layer 309 and the plurality of masking layers 307 as masks, the second mask layer 30 is etched to form a plurality of second grooves 305 corresponding to the plurality of second regions 102, with the bottom of the plurality of second grooves 305 exposed above the upper surface of the first mask layer 20. Because the etching opening 310 in the second photoresist layer 309 corresponding to the second portion 102b has high precision, the precision of the pattern corresponding to the second portion 102b in the plurality of second grooves 305 formed by etching the second mask layer 30 can be improved, which helps to improve the performance of the subsequently obtained semiconductor device.

[0078] It should be noted that in this embodiment, during the process of etching the second mask layer 30 to form a plurality of second grooves 305, in addition to using the second photoresist layer 309 and a plurality of shielding layers 307 as masks, the first dividing mask layer 304, the second dividing mask layer 302a and the sidewall 303 are also used as masks.

[0079] Figure 20 This is a planar schematic diagram of the semiconductor structure after etching the first mask layer according to an embodiment of the present invention. After etching the second mask layer 30 to form the plurality of second grooves 305, as... Figure 20 As shown, the patterning method may further include: removing the second photoresist layer 309; using the first segmentation mask layer 304, the second segmentation mask layer 30, the sidewalls 303, the multiple shielding layers 307 and the remaining second mask layer 30 as a mask, etching the first mask layer 20 and stopping on the upper surface of the layer 10 to be etched, so that the pattern formed by the first segmentation mask layer 304, the second segmentation mask layer 30, the sidewalls 303, the multiple shielding layers 307 and the remaining second mask layer 30 can be transferred to the first mask layer 20.

[0080] After etching the first mask layer 20, the etching continues downward to the layer to be etched 10 and stops in the layer to be etched 10, so as to transfer the pattern in the first mask layer 20 to the layer to be etched 10, so as to form corresponding patterns in the first region 101 and the second region 102.

[0081] Figure 21 This is a planar schematic diagram of the semiconductor structure after removing the first mask layer and the second mask layer in one embodiment of the present invention. Figure 21As shown, after the etching layer 10 is etched, a first etching trench 101' is formed in the first region 101, and a second etching trench 102' is formed in the second region 102. The second etching trench 102' may include a first sub-etching trench 102a' and a second sub-etching trench 102b'. The etchable layer 10 under the sidewall 303 and the first segmented mask layer 304 in the first region 101 is not etched, the etchable layer 10 under the second segmented mask layer 302a in the second region 102 is not etched, and the positions corresponding to the multiple shielding layers 307 in the non-interconnect region 103 are not etched.

[0082] After etching of the layer 10 to be etched is completed, the patterning method may further include: removing the second mask layer 30, the first mask layer 20, the sidewall 303, the first segmentation mask layer 304, the second segmentation mask layer 302a, and the shielding layer 307 from the layer 10 to be etched; filling the first etching trench 101' and the second etching trench 102' with conductive material to form an interconnect structure in the layer 10 to be etched. The conductive material may be a metal such as aluminum, copper, silver, or tungsten. However, it is not limited to this, and the conductive material may also be other materials such as conductive metal alloys.

[0083] This embodiment also provides a semiconductor structure, which is fabricated using the above-described patterning method. The semiconductor structure can be any semiconductor structure formed during the execution of the above-described patterning method.

[0084] It should be noted that, in this application, unless otherwise expressly defined and specified, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature are used to describe that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "below" the second feature are used to describe that the first feature is at a lower horizontal level than the second feature.

[0085] Although the terms "first," "second," "third," etc., are used in this application to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed above may be referred to as second components, regions, layers, and / or parts without departing from the embodiments of the present invention.

[0086] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A graphical method, characterized in that, include: The system provides a layer to be etched, a first mask layer, and a second mask layer stacked sequentially from bottom to top. The layer to be etched includes interconnect regions and non-interconnect regions located around the interconnect regions. The interconnect regions include a plurality of first regions and a plurality of second regions arranged alternately along a first axis. Both the first regions and the second regions extend along a second axis perpendicular to the first axis. Each of the plurality of second regions includes a first portion, which is adjacent to an adjacent first region. A portion of the second regions includes a second portion. The first portion and the second portion of the same second region are arranged along the second axis, and the second portion protrudes beyond the boundary of the adjacent first region. The second mask layer is etched and stops on the upper surface of the first mask layer, forming a plurality of shielding layer grooves arranged along the first axis in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves all extend along the second axis and are distributed on the side of the second portion, and the projection of the shielding layer grooves and the second portion in the second axis at least partially overlaps; Multiple shielding layers are formed by filling the grooves of the multiple shielding layers; A photoresist layer is formed on the second mask layer, the photoresist layer having a plurality of etching openings corresponding to the plurality of second regions and a plurality of auxiliary openings corresponding to the plurality of masking layers; as well as Using the photoresist layer and the plurality of masking layers as masks, the second mask layer is etched to form a plurality of second grooves corresponding to the plurality of second regions, and the bottom of the plurality of second grooves is exposed above the upper surface of the first mask layer.

2. The graphical method as described in claim 1, characterized in that, While forming the plurality of shielding layer grooves in the second mask layer on the non-interconnected area, a second dividing groove is formed in the second mask layer on a portion of the second area, the second dividing groove dividing the corresponding second area in the second axial direction.

3. The graphical method as described in claim 2, characterized in that, Before forming the plurality of shielding layer recesses, the patterning method includes: The second mask layer on the plurality of first regions is removed to form a plurality of first grooves, the bottom of the plurality of first grooves exposing the upper surface of the first mask layer.

4. The graphical method as described in claim 3, characterized in that, The width of the shielding layer groove in the first axial direction is less than or equal to the width of the second dividing groove in the second axial direction.

5. The graphical method as described in claim 4, characterized in that, The method of filling the plurality of shielding layer grooves to form the plurality of shielding layers includes: A filling material layer is formed, which covers the inner surface of the plurality of first grooves and the upper surface of the second mask layer, and fills the second dividing groove and the plurality of shielding layer grooves; The filling material layer is etched back until the upper surface of the second mask layer and the upper surface of the first mask layer located at the bottom of the plurality of first grooves are exposed. The filling material layer on the sidewalls of the plurality of first grooves is retained as sidewalls, and the filling material layer located in the second dividing groove and the plurality of shielding layer grooves is retained as the second dividing mask layer and the plurality of shielding layers, respectively.

6. The graphical method as described in claim 5, characterized in that, After etching the second mask layer to form the plurality of second grooves, the patterning method includes: Remove the photoresist layer; Using the second dividing mask layer, the sidewalls, the plurality of shielding layers and the remaining second mask layer as masks, the first mask layer and the layer to be etched are etched sequentially and the etching stops in the layer to be etched, so as to form corresponding patterns in the first region and the second region.

7. The graphical method as described in claim 2, characterized in that, The width of the shielding layer groove in the first axial direction is greater than the width of the second dividing groove in the second axial direction.

8. The graphical method as described in claim 1, characterized in that, A portion of the second zone comprises only the first portion, and at least a portion of the shielding layer grooves correspond to the positions of the second zones comprising only the first portion and are disposed on the end sides of the corresponding second zones.

9. The graphical method as described in claim 1, characterized in that, The first and second portions of the same second region are connected; or the first and second portions of the same second region are spaced apart along the second axis.

10. A semiconductor structure, characterized in that, Formed using the graphical method described in any one of claims 1 to 9.

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