Bandgap reference circuit and chip

Abstract

The present disclosure provides a bandgap reference circuit and a chip. The bandgap reference circuit comprises: a feedback transistor, a source of which is connected to a first power supply, and a drain of which is connected to a first node; a reference setting module, comprising a first bridge arm and a second bridge arm connected in parallel, the first bridge arm comprising a first resistance unit and a first voltage regulation unit connected in series, the second bridge arm comprising a second resistance unit, a third resistance unit and a second voltage regulation unit connected in series, the first resistance unit and the second resistance unit being connected to the first node and having equal resistance, the first voltage regulation unit and the second voltage regulation unit being grounded; an amplification module, an inverting input terminal of which is connected to the first bridge arm, a non-inverting input terminal of which is connected to the second bridge arm, and an output terminal of which is connected to a gate of the feedback transistor; and an output transistor, a gate of which is connected to the output terminal of the amplification module, a source of which is connected to the first power supply, and a drain of which is an output terminal of the bandgap reference circuit. The embodiments of the present disclosure can improve the driving capability and the gain of the bandgap reference circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a bandgap reference circuit and a chip applying the same. BACKGROUND

[0002] The bandgap reference circuit is a circuit for providing a constant reference voltage or reference current that is not affected by temperature for a circuit. The bandgap reference circuit in the related art has a relatively stable structure that has been applied for a long time. In the case where the output reference voltage or reference current is required to be determined, only the element parameters in the general bandgap reference circuit need to be adjusted. However, only adjusting the element parameters limits the output driving capability of the bandgap reference circuit, and in addition, there is room for improvement in the gain of the bandgap reference circuit.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a bandgap reference circuit and a chip applying the same, for at least partially improving the output driving capability and gain of the bandgap reference circuit.

[0005] According to a first aspect of the present disclosure, a bandgap reference circuit is provided, comprising: a feedback transistor, a source thereof being connected to a first power supply, a drain thereof being connected to a first node; a reference setting module, comprising a first bridge arm and a second bridge arm connected in parallel, the first bridge arm comprising a first resistance unit and a first voltage regulating unit connected in series, the second bridge arm comprising a second resistance unit, a third resistance unit and a second voltage regulating unit connected in series, the first resistance unit and the second resistance unit being connected to the first node and having equal resistance values, the first voltage regulating unit and the second voltage regulating unit being grounded; an amplification module, an inverting input terminal thereof being connected to the first bridge arm, a non-inverting input terminal thereof being connected to the second bridge arm, an output terminal thereof being connected to a gate of the feedback transistor; and an output transistor, a gate thereof being connected to the output terminal of the amplification module, a source thereof being connected to the first power supply, a drain thereof being an output terminal of the bandgap reference circuit.

[0006] In an exemplary embodiment of the present disclosure, the first voltage regulating unit comprises a first PNP transistor, an emitter of the first PNP transistor being connected to the first resistance unit, a base and a collector of the first PNP transistor being grounded; and the second voltage regulating unit comprises a plurality of second PNP transistors connected in parallel, an emitter of each of the second PNP transistors being connected to the third resistance unit, a base and a collector of each of the second PNP transistors being grounded.

[0007] In an example embodiment of the present disclosure, the first resistance unit and the second resistance unit each include a plurality of resistors connected in series, the non-inverting input of the amplification module is connected to a connection node of two resistors in the first resistance unit, the inverting input of the amplification module is connected to a connection node of two resistors in the second resistance unit, and the resistance between the non-inverting input and the first node is equal to the resistance between the inverting input and the first node.

[0008] In an example embodiment of the present disclosure, the first resistance unit includes a first adjustable resistor, the second resistance unit includes a second adjustable resistor, the resistance of the first adjustable resistor is equal to the resistance of the second adjustable resistor, and the resistance between the end of the first adjustable resistor away from the first node and the first node is equal to the resistance between the end of the second adjustable resistor away from the first node and the first node.

[0009] In an example embodiment of the present disclosure, the amplification module includes a first-stage amplification module and a bias unit, the bias unit includes a first-stage bias transistor, the first end of the first-stage amplification module is used to connect the first power supply, and the second end is connected to the drain of the first-stage bias transistor in the bias unit. The first-stage amplification module includes: a first P-type transistor, the source of which is connected to the first power supply, and the gate and the drain of which are both connected to a second node; a second P-type transistor, the source of which is connected to the first power supply, the gate of which is connected to the second node, and the drain of which is connected to a third node; a first amplification unit, including: a first N-type transistor, the gate of which is connected to the non-inverting input of the amplification module, the source of which is electrically connected to the drain of the first-stage bias transistor in the bias unit, and the drain of which is connected to a fourth node, the fourth node being electrically connected to the second node; a second N-type transistor, the gate of which is connected to the inverting input of the amplification module, the source of which is electrically connected to the drain of the first-stage bias transistor in the bias unit, and the drain of which is connected to a fifth node, the fifth node being electrically connected to the third node; wherein the gate of the first-stage bias transistor is used to receive a bias signal, and the source is grounded.

[0010] In an example embodiment of the present disclosure, the first amplification unit further includes: a third N-type transistor, the gate of which is connected to the second resistance unit, the source of which is connected to the fourth node, and the drain of which is connected to the second node; a fourth N-type transistor, the gate of which is connected to the first resistance unit, the source of which is connected to the fifth node, and the drain of which is connected to the third node; wherein the resistance between the gate of the third N-type transistor and the first node is equal to the resistance between the gate of the fourth N-type transistor and the first node, and the resistance between the gate of the third N-type transistor and the first node is less than the resistance between the gate of the first N-type transistor and the first node.

[0011] In an example embodiment of the present disclosure, the transistors in the first amplification unit are all thick gate oxide transistors, the first amplification module further comprises: a second amplification unit connected in parallel with the first amplification unit, the second amplification unit has the same circuit structure and input signals as the first amplification unit, and is configured to output a second amplified signal through the third node according to the input signals of the non-inverting input terminal and the inverting input terminal, and the transistors in the second amplification unit are all thin gate oxide transistors; and a control module configured to control the first amplification unit and the second amplification unit to have and only have one enabled at the same time.

[0012] In an example embodiment of the present disclosure, the biasing unit comprises a second biasing transistor, and the amplification module further comprises: a second amplification module, an input terminal of which is connected to the first amplification unit, a first terminal of which is connected to the first power supply, and a second terminal of which is connected to a drain of the second biasing transistor in the biasing unit, and the second amplification module is configured to perform secondary amplification on the output signal of the first amplification unit, a gate of the second biasing transistor is configured to receive the biasing signal, and a source of the second biasing transistor is grounded.

[0013] In an example embodiment of the present disclosure, the second amplification module comprises: a second amplification transistor, a gate of which is connected to the third node, a source of which is connected to the first power supply, and a drain of which is connected to a sixth node; a first switch tube, which is a P-type transistor, a first terminal of which is connected to the sixth node, a second terminal of which is connected to an output terminal of the amplification module, and a control terminal of which is connected to an inverted signal of a second gain enable signal; a second switch tube, which is a P-type transistor, a first terminal of which is connected to the third node, a second terminal of which is connected to the output terminal of the amplification module, and a control terminal of which is connected to the second gain enable signal; and a third switch tube, which is an N-type transistor, a first terminal of which is connected to the output terminal of the amplification module, a control terminal of which is connected to the second gain enable signal, and a second terminal of which is connected to the drain of the second biasing transistor.

[0014] In an example embodiment of the present disclosure, the second amplification transistor is a P-type transistor, and the bandgap reference circuit further comprises: an input signal exchange unit connected between the non-inverting input terminal and the inverting input terminal of the amplification module and the first bridge arm and the second bridge arm, configured to control the inverting input terminal of the amplification module to be connected to the first bridge arm and the non-inverting input terminal to be connected to the second bridge arm when the second gain enable signal is dormant, or to exchange the input signals of the non-inverting input terminal and the inverting input terminal of the amplification module when the second gain enable signal is active.

[0015] In an example embodiment of the present disclosure, when the first amplification unit comprises a third N-type transistor and a fourth N-type transistor, the bandgap reference circuit further comprises a gain control switching unit connected between the gate of the third N-type transistor, the gate of the fourth N-type transistor and the first resistance unit and the second resistance unit, for controlling the gate of the third N-type transistor to be connected to the second resistance unit and the gate of the fourth N-type transistor to be connected to the first resistance unit when the secondary gain enable signal is inactive, or for controlling the connection points of the gate of the third N-type transistor and the gate of the fourth N-type transistor to be exchanged when the secondary gain enable signal is active.

[0016] In an example embodiment of the present disclosure, the input signal switching unit comprises a fourth switch tube which is an N-type transistor, a first end of which is connected to the non-inverted input terminal, a second end of which is connected to the second bridge arm, and a gate of which is connected to an inverted signal of the secondary gain enable signal; a fifth switch tube which is an N-type transistor, a first end of which is connected to the non-inverted input terminal, a second end of which is connected to the first bridge arm, and a gate of which is connected to the secondary gain enable signal; a sixth switch tube which is an N-type transistor, a first end of which is connected to the inverted input terminal, a second end of which is connected to the second bridge arm, and a gate of which is connected to the secondary gain enable signal; and a seventh switch tube which is an N-type transistor, a first end of which is connected to the inverted input terminal, a second end of which is connected to the first bridge arm, and a gate of which is connected to an inverted signal of the secondary gain enable signal.

[0017] In an example embodiment of the present disclosure, the gain control switching unit comprises an eighth switch tube which is an N-type transistor, a first end of which is connected to the gate of the third N-type transistor, a second end of which is connected to the second resistance unit, and a gate of which is connected to an inverted signal of the secondary gain enable signal; a ninth switch tube which is an N-type transistor, a first end of which is connected to the gate of the third N-type transistor, a second end of which is connected to the first resistance unit, and a gate of which is connected to the secondary gain enable signal; a tenth switch tube which is an N-type transistor, a first end of which is connected to the gate of the fourth N-type transistor, a second end of which is connected to the second resistance unit, and a gate of which is connected to the secondary gain enable signal; and an eleventh switch tube which is an N-type transistor, a first end of which is connected to the gate of the fourth N-type transistor, a second end of which is connected to the first resistance unit, and a gate of which is connected to an inverted signal of the secondary gain enable signal.

[0018] In an example embodiment of the present disclosure, the bias unit further comprises a bias resistance unit having a first end connected to the first power supply and a second end connected to a bias node, the bias node being used for transmitting the bias signal, the bias resistance unit comprising an adjustable resistance; and a self-bias transistor having a gate and a drain both connected to the bias node and a source connected to the ground.

[0019] According to a second aspect of the present disclosure, there is provided a chip comprising the bandgap reference circuit according to any one of the preceding aspects.

[0020] The bandgap reference circuit provided by the embodiments of the present disclosure can provide a current related to the output signal of the amplification module to the reference setting module through the first power supply, instead of directly providing a current to the reference setting module through the output terminal of the amplification module, so that a greater current can be provided to the reference setting module, and the current driving capability of the bandgap reference circuit is improved.

[0021] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0023] Figure 1 is a structural schematic diagram of a bandgap reference circuit in an exemplary embodiment of the present disclosure.

[0024] Figure 2 is a schematic diagram of a voltage regulating unit in an embodiment of the present disclosure.

[0025] Figure 3 is a schematic diagram of a first resistance unit and a second resistance unit in another embodiment of the present disclosure.

[0026] Figure 4 is a schematic diagram of an amplification module in an embodiment of the present disclosure.

[0027] Figure 5 is a schematic diagram of an amplification module in another embodiment of the present disclosure.

[0028] Figure 6 is a schematic diagram of a first resistance unit and a second resistance unit in another embodiment of the present disclosure. Figure 5 is a schematic diagram of a connection relationship of a corresponding amplification module.

[0029] Figure 7 is a schematic diagram of a first-stage amplification module in an embodiment of the present disclosure.

[0030] Figure 8 is a schematic diagram of an amplification module in an embodiment of the present disclosure.

[0031] Figure 9is a schematic diagram of a two-stage amplification module in one embodiment of the present disclosure.

[0032] Figure 10 is a schematic diagram of a two-stage amplification module in one embodiment of the present disclosure. Figure 9 is a schematic diagram of a bandgap reference circuit corresponding to the embodiment shown.

[0033] Figure 11 is a schematic diagram of an input signal switching unit in one embodiment of the present disclosure.

[0034] Figure 12 is a schematic diagram of a bandgap reference circuit in yet another embodiment of the present disclosure.

[0035] Figure 13 is a schematic diagram of a gain control switching unit in one embodiment of the present disclosure.

[0036] Figure 14 is a schematic diagram of a bias unit in one embodiment of the present disclosure.

[0037] Figure 15 is a schematic diagram of an amplification module in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0039] In addition, the accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0040] Example implementations of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0041] Figure 1 is a structural schematic diagram of a bandgap reference circuit in an example embodiment of the present disclosure.

[0042] Reference Figure 1 , the bandgap reference circuit 100 can include:

[0043] a feedback transistor M1, a source for connecting a first power supply Vcc, and a drain for connecting a first node N1;

[0044] a reference setting module 11, including a first bridge arm 111 and a second bridge arm 112 connected in parallel, the first bridge arm 111 including a first resistance unit R1 and a first voltage regulation unit Z1 connected in series, the second bridge arm 112 including a second resistance unit R2, a third resistance unit R3 and a second voltage regulation unit Z2 connected in series, the first resistance unit R1 and the second resistance unit R2 are both connected to the first node N1 and have equal resistance values, and the first voltage regulation unit Z1 and the second voltage regulation unit Z2 are both grounded;

[0045] an amplification module 12, an inverting input terminal INN connected to the first bridge arm 111, a non-inverting input terminal INP connected to the second bridge arm 112, and an output terminal connected to a gate of the feedback transistor M1;

[0046] an output transistor M2, a gate connected to an output terminal of the amplification module 12, a source connected to the first power supply Vcc, and a drain as an output terminal of the bandgap reference circuit 100.

[0047] In an embodiment, the feedback transistor M1 and the output transistor M2 are both PMOS, and in other embodiments, the feedback transistor M1 and the output transistor M2 can also be implemented by other types of transistors, or by one or more elements combined to implement the function of a transistor, and the present disclosure does not make special limitations thereon.

[0048] Taking the feedback transistor M1 and the output transistor M2 as an example, in the embodiment shown in Figure 1 , the first power supply Vcc provides a current associated with the output voltage of the amplification module 12 to the first bridge arm 111 and the second bridge arm 112 through the feedback transistor M1 and the first node N1. When the voltage of the first bridge arm 111 and the second bridge arm 112 rises, causing the input voltage of the amplification module 12 to rise, the output voltage of the amplification module 12 rises, the drain current of the P-type feedback transistor M1 decreases, reducing the current of the first bridge arm 111 and the second bridge arm 112, and further reducing the input voltage of the amplification module 12, the output voltage of the amplification module 12, achieving negative feedback regulation, so that the output voltage of the amplification module 12 is maintained stable, and the output current of the output transistor M2 is maintained stable.

[0049] Compared with directly connecting the output end of the amplification module 12 to the first bridge arm 111 and the second bridge arm 112, the P-type feedback transistor M1 with the source connected to the first power supply Vcc and the gate connected to the output end of the amplifier 12 can provide greater and more stable current associated with the output of the amplification module 12, so that the first node N1 has greater current driving capability.

[0050] Figure 2 is a schematic diagram of a voltage regulation unit in one embodiment of the present disclosure.

[0051] Reference Figure 2 , the feedback transistor M1 and the output transistor M2 are both PMOS, and the drain of the output transistor M2 is used to output the bandgap reference current I. The first voltage regulation unit Z1 can include a first PNP transistor J1. The emitter of the first PNP transistor J1 is connected to the first resistance unit R1, and the base and the collector are both grounded. The second voltage regulation unit Z2 includes a plurality of second PNP transistors J2 connected in parallel, and the emitter of each second PNP transistor is connected to a third resistance unit R3, and the base and the collector are both grounded. The inverting input end INN of the amplification module 12 is connected to the emitter of the first PNP transistor J1 through node a, and the non-inverting input end INP is connected to the emitter of the second PNP transistor J2 through node b.

[0052] In the first voltage regulation unit Z1, the base and the collector of the first PNP transistor J1 are both grounded, and the equivalent resistance to ground is the emitter junction resistance Rbe1 of the first PNP transistor J1. In the second voltage regulation unit Z2, the base and the collector of each second PNP transistor J2 are both grounded, and the equivalent resistance to ground is the emitter junction resistance Rbe2 of the second PNP transistor J2. The equivalent resistance of the entire second voltage regulation unit Z2 is the equivalent resistance of a plurality of Rbe2 connected in parallel. Assuming that the number of second PNP transistors J2 is n, the resistance of the second voltage regulation unit Z2 is Rbe2 / n. In a PNP transistor with a grounded base, V CE = V BE , the transistor is in a saturated state, and therefore the first PNP transistor J1 and the plurality of second PNP transistors J2 respectively provide stable saturation currents for the first bridge arm 111 and the second bridge arm 112.

[0053] In Figure 2In the circuit shown, the voltage Vbe1 on the emitter junction resistance Rbe1 of the first PNP transistor J1 and the voltage Vbe2 on the emitter junction resistance Rbe2 of the second PNP transistor J2 are PN junction voltages, which are negative temperature coefficient characteristic voltages, i.e., the higher the temperature, the lower the junction voltage, and the lower the temperature, the higher the junction voltage. The voltages on the first resistance unit R1, the second resistance unit R2, and the third resistance unit R3 are all positive temperature coefficient characteristic voltages, i.e., the higher the temperature, the greater the resistance of the first resistance unit R1, the second resistance unit R2, and the third resistance unit R3, and the greater the voltage on the first resistance unit R1, the second resistance unit R2, and the third resistance unit R3 (i.e., the greater the voltage division).

[0054] According to the virtual short characteristic of the amplifier, the voltages of node a and node b are equal, and there is:

[0055] V(Z1) = V3 + V(Z2) (1)

[0056] V3 is the voltage on the third resistance unit R3, and V(Z1) and V(Z2) are the voltages on the first voltage regulating unit Z1 and the second voltage regulating unit Z2, respectively.

[0057] Since the voltage across the first resistance unit R1 is always equal to the voltage across the second resistance unit R2, and the resistance of the first resistance unit R1 is equal to the resistance of the second resistance unit R2, the current on the first bridge arm 111 is equal to the current on the second bridge arm 112, both of which are equal to the saturation current Ibe of the first PNP transistor J1. Therefore, there is the following formula:

[0058] V3 = V(Z1) - V(Z2) = ln(n) * V T = R3 * Ibe (2)

[0059] where n is the number of the second PNP transistor J2, ln(n) * V T is the difference between the base-emitter voltages of two bipolar transistors (BJTs) operating at different current densities, V T is the voltage equivalent of temperature, and V T = kt / q, k is the Boltzmann constant (1.38 x 10-23 J / K), T is the thermodynamic temperature, i.e., the absolute temperature (300 K), and q is the electronic charge (1.6 x 10-19 C). At room temperature, VT≈26 mV. V T is a positive temperature coefficient voltage.

[0060] Then the voltage Vbgr of the first node N1 is:

[0061] Vbgr = Vbe1 + R1 * Ibe = Vbe1 + R1 * [ln(n) * V T / R3] (3)

[0062] Therefore, the voltage Vbgr of the first node N1 is the sum of the positive temperature coefficient voltage and the negative temperature coefficient voltage, and by adjusting the number of n according to the values of Vbe1, R1 and R3, the Vbgr can be made to be a zero temperature coefficient voltage not affected by temperature, i.e. a constant bandgap reference voltage. In an embodiment, n is equal to 8, for example. Meanwhile, the source voltage and the drain voltage of the feedback transistor M1 are constant, the gate voltage Vout is constant, and the output current (i.e. the bandgap reference current I) of the output transistor M2 controlled by the gate voltage Vout of the feedback transistor M1 is constant.

[0063] By using a PNP transistor (BJT) to implement the voltage regulating unit, the collector and the emitter can be directly doped on the N-well of the substrate, which is easier to be processed by the CMOS process of the integrated circuit manufacturing process than manufacturing an NPN transistor, and therefore the manufacturing efficiency of the bandgap reference circuit in the chip can be improved.

[0064] Figure 3 is a schematic diagram of the first resistance unit and the second resistance unit in another embodiment of the present disclosure.

[0065] Reference Figure 3 In an embodiment, the first resistance unit R1 and the second resistance unit R2 each include a plurality of resistors connected in series, for example Figure 2 The first resistance unit R1 includes resistors R11, R12 and R13 connected in series, and the second resistance unit R2 includes resistors R21, R22 and R23 connected in series, the inverting input end INN of the amplification module 12 is connected to the connection node of two resistors in the first resistance unit R1 (for example Figure 3 the c node shown), and the non-inverting input end INP of the amplification module 12 is connected to the connection node of two resistors in the second resistance unit R2 (for example Figure 3 the d node shown), and the resistance between the inverting input end INN and the first node N1 is equal to the resistance between the non-inverting input end INP and the first node N1. In Figure 2 the embodiment shown, i.e. R11+R12=R21+R22, where R11, R12, R21 and R22 represent the resistance values of the resistors R11, R12, R21 and R22, respectively. The number of resistors in the first resistance unit R1 and the second resistance unit R2 can be equal or not equal, as long as the above defined condition is met.

[0066] By setting the connection node between the amplification module 12 and the first bridge arm 111 and the second bridge arm 112 between two resistors, instead of directly connecting the emitter of the first voltage regulation unit Z1 and one end of the third resistor unit R3, the input voltage of the amplification module 12 can be increased, the output voltage Vout of the amplification module 12 can be increased, the gate voltage of the output transistor M2 can be increased, and the current driving capability of the bandgap reference circuit can be improved.

[0067] In one embodiment, resistor R11 can be a first adjustable resistor, and resistor R21 can be a second adjustable resistor. The resistance value of the first adjustable resistor R11 is equal to the resistance value of the second adjustable resistor R21. The resistance between the end of the first adjustable resistor R11 furthest from the first node N1 and the first node N1 is equal to the resistance between the end of the second adjustable resistor R21 furthest from the first node N1 and the first node N1. Figure 3 In the embodiment shown, R11 = R21, R12 = R22, and R13 = R23, thereby keeping R1 = R2.

[0068] exist Figure 3 In the illustrated embodiment, both the first adjustable resistor R11 and the second adjustable resistor R21 are directly connected to the first node N1. In this case, the resistance value of the first adjustable resistor R11 is equal to the resistance value of the second adjustable resistor R21. When there are other resistors between the first adjustable resistor R11 and the first node N1, and / or when there are other resistors between the second adjustable resistor R21 and the first node N1, the equivalent resistance relationship remains the same: the resistance between node c and the first node N1 is always equal to the resistance between node d and the first node N1.

[0069] By simultaneously setting adjustable resistors with the same resistance value in the first resistor unit R1 and the second resistor unit R2, the resistance and current of the first bridge arm 111 and the second bridge arm 112 can be adjusted at the same time as the input voltage of the amplifier module 12.

[0070] Figure 4 This is a schematic diagram of the amplification module in one embodiment of this disclosure.

[0071] refer to Figure 4 In one embodiment of this disclosure, the amplification module 12 includes a first-stage amplification module 121 and a bias unit 122. The bias unit 122 includes a first-stage bias transistor MB1. A first terminal of the first-stage amplification module 121 is connected to a first power supply Vcc, and a second terminal is connected to the drain of the first-stage bias transistor MB1 in the bias unit 122. The first-stage amplification module 121 includes:

[0072] The first P-type transistor MP1 has its source connected to the first power supply Vcc, and its gate and drain both connected to the second node N2.

[0073] The second P-type transistor MP2 has a source connected to the first power supply Vcc, a gate connected to the second node N2, and a drain connected to the third node N3.

[0074] The first amplification unit 1211 comprises:

[0075] The first N-type transistor MN1 has a gate connected to the non-inverting input INP of the amplification module 12, a source electrically connected to the drain of the first-stage biasing transistor MB1 in the biasing unit 122, and a drain connected to the fourth node N4, which is electrically connected to the second node N2.

[0076] The second N-type transistor MN2 has a gate connected to the inverting input INN of the amplification module 12, a source electrically connected to the drain of the first-stage biasing transistor MB1 in the biasing unit 122, and a drain connected to the fifth node N5, which is electrically connected to the third node N3.

[0077] The gate of the first-stage biasing transistor MB1 is configured to receive a biasing signal Vbias, and the source is grounded.

[0078] Figure 4 The illustrated embodiments can be applied to Figures 1-3 In the illustrated circuit, the gate of the first N-type transistor MN1 is used as the non-inverting input INP of the amplification module 12, the gate of the second N-type transistor MN2 is used as the inverting input of the amplification module 12, and the third node N3 is used as the output of the amplification module 12.

[0079] In Figure 4 In the illustrated embodiments, the fourth node N4 is directly connected to the second node N2, and the fifth node N5 is directly connected to the third node N3,

[0080] Figure 5 is a schematic diagram of the amplification module in another embodiment of the present disclosure.

[0081] Referring to Figure 5 In another embodiment, the first amplification unit 1211 further comprises:

[0082] The third N-type transistor MN3 has a gate connected to the second resistance unit R2, a source connected to the fourth node N4, and a drain connected to the second node N2.

[0083] The fourth N-type transistor MN4 has a gate connected to the first resistance unit R1, a source connected to the fifth node N5, and a drain connected to the third node N3.

[0084] Among them, the resistance between the gate of the third N-type transistor MN3 and the first node N1 is equal to the resistance between the gate of the fourth N-type transistor MN4 and the first node N1, and the resistance between the gate of the third N-type transistor MN3 and the first node N1 is less than the resistance between the gate of the first N-type transistor MN1 and the first node N1.

[0085] like Figure 5 As shown, the gate connection bias voltage Pcas of the third N-type transistor MN3 and the gate connection bias voltage Ncas of the fourth N-type transistor MN4 are shown.

[0086] exist Figure 5 In the illustrated embodiment, the first amplification unit 121, after stacking the third N-type transistor MN3 and the fourth N-type transistor MN4, constitutes a cascade operational amplifier structure, i.e., a common-source common-gate amplification structure. MN1 and MN2 have their input terminals as gates and their output terminals as drains, forming a common-source amplification structure; while MN3 and MN4 have their input terminals as sources and their output terminals as drains, forming a common-gate amplification structure.

[0087] By employing a self-biased cascade current mirror in the amplifier module 12, the gain of the amplifier module 12 can be improved, and the power supply rejection ratio of the output voltage Vout can be increased, thereby enabling the amplifier module 12 to coordinate with the external circuit to generate a stable reference voltage with zero temperature coefficient.

[0088] To prevent the stacked third N-type transistor MN3 and fourth N-type transistor MN4 from becoming a bottleneck affecting the output drive capability of the amplifier module 12, when setting the bias voltage Pcas and bias voltage Ncas, it is necessary to ensure that the bias voltage Pcas is higher than the voltage of the non-inverting input terminal INP of the amplifier module 12, and the bias voltage Ncas is higher than the voltage of the inverting input terminal INN of the amplifier module 12.

[0089] Figure 6 Is with Figure 5 A schematic diagram showing the connection relationship of the corresponding amplification modules.

[0090] refer to Figure 6 The bias voltage Ncas is the voltage at node e, the connection point of the two resistors in the first resistor unit R1, and the bias voltage Pcas is the voltage at node f, the connection point of the two resistors in the second resistor unit R2. The resistance between node e and the first node N1 is equal to the resistance between node f and the first node N1. The resistance between node e and the first node N1 (e.g.) Figure 6 As shown, R11 is less than the resistance between node c and the first node N1 (e.g., Figure 6The voltage of node e is higher than that of node c, i.e., the voltage of the bias voltage Ncas is higher than the input voltage of the inverting input end INN of the amplification module 12; the resistance between node f and the first node N1 (e.g. Figure 6 The resistance between node d and the first node N1 (e.g. Figure 6 The voltage of node f is higher than that of node d, i.e., the voltage of the bias voltage Pcas is higher than the input voltage of the non-inverting input end INP of the amplification module 12.

[0091] In one embodiment, the resistance R11 can be a first adjustable resistance, and the resistance R21 can be a second adjustable resistance. The resistance value of the first adjustable resistance R11 is equal to the resistance value of the second adjustable resistance R21.

[0092] By setting the adjustable resistances with the same resistance value in the first bridge arm 111 and the second bridge arm 112, the simultaneous adjustment of the first bridge arm 111 and the second bridge arm 112 can be realized when adjusting the input voltage and the bias voltage Pcas and Ncas of the amplification module 12, so as to maintain Pcas=Ncas.

[0093] In one embodiment of the present disclosure, the transistors in the first amplification unit 1211 are all thick gate oxide transistors (Thick OX MOS) with high voltage resistance. The first P-type transistor MP1 and the second P-type transistor MP2 can also be thick gate oxide transistors to improve the voltage resistance of the first amplification module 121.

[0094] Figure 7 is a schematic diagram of the first amplification module in one embodiment of the present disclosure.

[0095] Reference Figure 7 When the transistors in the first amplification unit 1211 are all thick gate oxide transistors (Thick OX MOS), the first amplification module 121 can further include:

[0096] The second amplification unit 1212 is connected in parallel with the first amplification unit 1211. The second amplification unit 1212 has the same circuit structure and input signal as the first amplification unit 1211, and is configured to output a second amplification signal Vout' through a third node N3 according to the input signals of the non-inverting input end INP and the inverting input end INN. The transistors in the second amplification unit 1212 are all thin gate oxide transistors, i.e., the gate oxide thickness of at least the Nmos transistor in the second amplification unit 1212 is greater than the gate oxide thickness of the Nmos transistor in the first amplification unit 1211.

[0097] The control module 1213 is configured to control the first amplification unit 1211 and the second amplification unit 1212 to have and only have one enabled at the same time.

[0098] In Figure 7 In the embodiment shown, the control module 1213 is implemented by a first control transistor Mnpt1 connected between the first amplification unit 1211 and the second node N2, a second control transistor Mnpt2 connected between the first amplification unit 1211 and the third node N3, a third control transistor Mnpt3 connected between the first amplification unit 1211 and the bias unit 122, a fourth control transistor Mnpt4 connected between the second amplification unit 1212 and the second node N2, a fifth control transistor Mnpt5 connected between the second amplification unit 1212 and the third node N3, and a sixth control transistor Mnpt6 connected between the second amplification unit 1212 and the bias unit 122. The gates of the first control transistor Mnpt1, the second control transistor Mnpt2, and the third control transistor Mnpt3 are all connected to the first amplification unit enable signal ThickEn, and the gates of the fourth control transistor Mnpt4, the fifth control transistor Mnpt5, and the sixth control transistor Mnpt6 are all connected to the second amplification unit enable signal ThinEN. The first amplification unit enable signal ThickEn and the second amplification unit enable signal ThinEN control the first amplification unit 1211 and the second amplification unit 1212 to have and only have one enabled at the same time.

[0099] When the first control transistor Mnpt1, the second control transistor Mnpt2, the third control transistor Mnpt3, the fourth control transistor Mnpt4, the fifth control transistor Mnpt5, and the sixth control transistor Mnpt6 are all the same type of transistor, for example Figure 7 all N-type transistors, the phase of the first amplification unit enable signal ThickEn is opposite to that of the second amplification unit enable signal ThinEN.

[0100] In other embodiments, the control module 1213 can also have other forms, which are not particularly limited in the present disclosure. By using the control module 1213 to control the first amplification unit 1211 composed of thick gate oxide layer transistors and the second amplification unit 1212 composed of thin gate oxide layer transistors to have and only have one enabled at the same time, the first amplification unit 1211 can be enabled when higher voltage resistance is needed, and the second amplification unit 1212 can be enabled when faster response speed is needed, thereby achieving flexible setting of the amplification module 12.

[0101] Figure 8 is a schematic diagram of the amplification module in one embodiment of the present disclosure.

[0102] Referring to Figure 8 , in one embodiment of the present disclosure, the bias unit 122 includes a second-level bias transistor MB2, and the amplification module 12 further includes:

[0103] The second amplification module 123 is connected to the first amplification unit 121 at the input end, connected to the first power supply Vcc at the first end, and connected to the drain of the second bias transistor MB2 in the bias unit 122 at the second end, for performing secondary amplification on the output signal of the first amplification unit 121. The gate of the second bias transistor MB2 is used to receive the bias signal Vbias, and the source is grounded.

[0104] In the embodiment shown in Figure 8 In the embodiment shown in

[0105] The second amplification module 123 can be implemented by various circuits with amplification function, and can also be provided with an enable function to enable or disable the secondary amplification function. The setting of the second amplification module 123 can improve the gain of the amplification module 12.

[0106] In addition to the embodiment shown in Figure 8 In the embodiment shown in Figure 7 In the embodiment shown in Figure 15 In the embodiment shown in

[0107] Figure 9 FIG. 2 is a schematic diagram of a second amplification module in one embodiment of the present disclosure.

[0108] Referring to Figure 9 In one embodiment of the present disclosure, the second amplification module 123 can include:

[0109] The second amplification transistor M3 has the gate connected to the third node N3, the source connected to the first power supply Vcc, and the drain connected to the sixth node N6.

[0110] The first switch tube K1 is a P-type transistor, the first end of which is connected to the sixth node N6, the second end is connected to the output end of the amplification module 12, and the control end is connected to the inverse signal 2stgENF of the second gain enable signal 2stgEN.

[0111] The second switch tube K2 is a P-type transistor, the first end of which is connected to the third node N3, the second end is connected to the output end of the amplification module 12, and the control end is connected to the second gain enable signal 2stgEN.

[0112] The third switch tube K3 is an N-type transistor, the first end is connected to the output end of the amplification module 12, the control end is connected to the secondary gain enable signal 2stgEN, and the second end is connected to the drain of the secondary bias transistor MB2.

[0113] In Figure 9 In the circuit shown in the figure, when the secondary gain enable signal 2stgEN is high and the inverse signal 2stgENF of the secondary gain enable signal 2stgEN is low, the first switch tube K1 and the third switch tube K3 are both turned on, and the second switch tube K2 is turned off. At this time, the signal of the third node N3 output by the first-stage amplification module 121 controls the gate of the second-stage amplification transistor M3, the drain of the second-stage amplification transistor M3 is connected to the ground through the turned-on first switch tube K1, the turned-on third switch tube K3 and the biased secondary bias transistor MB2, and the output signal Vout of the amplification module 12 is the drain signal of the second-stage amplification transistor M3. The second-stage amplification transistor M3 constitutes a common-source stage amplification circuit, and the signal of the third node N3 is amplified twice, and Vout is opposite to the signal of the third node N3. The inverse signal 2stgEN of the secondary gain enable signal 2stgEN can be realized by a circuit with an inverting function connected to the input end of 2stgEN, and the present disclosure does not make special limitations on this.

[0114] When the secondary gain enable signal 2stgEN is low and the inverse signal 2stgENF of the secondary gain enable signal 2stgEN is high, the first switch tube K1 and the third switch tube K3 are both turned off, and the second switch tube K2 is turned on. The signal of the third node N3 is directly used as the output signal Vout of the amplification module 12, that is, the secondary amplification function is disabled.

[0115] In addition to Figure 9 the circuit shown in the figure, those skilled in the art can also set the secondary amplification circuit 123 through other circuits as long as the amplification function can be realized.

[0116] Figure 10 is one embodiment of the present disclosure Figure 9 The schematic diagram of the bandgap reference circuit corresponding to the embodiment shown in the figure.

[0117] In Figure 9 the embodiment shown in the figure, when the secondary amplification transistor is a P-type transistor, the output signal Vout of the amplification module 12 is opposite to the signal of the third node N3, that is, the output signal of the secondary amplification module 123 is opposite to the output signal of the first-stage amplification module 121.

[0118] In order to make the output signal of the secondary amplification module 123 represent the voltage difference of the bridge arm, rather than the opposite value of the voltage difference, the bandgap reference circuit can further include:

[0119] The input signal exchange unit 13 is connected between the non-inverting input INP and the inverting input INN of the amplification module 12 and the first bridge arm 111 and the second bridge arm 112, and is configured to control the inverting input INN of the amplification module 12 to be connected to the first bridge arm 111 and the non-inverting input INP to be connected to the second bridge arm 112 when the second-stage gain enable signal 2stgEN is inactive, or to control the input signal of the non-inverting input INP and the input signal of the inverting input INN of the amplification module 12 to be exchanged when the second-stage gain enable signal 2stgEN is active.

[0120] Figure 10 The input signal exchange unit 13 shown in the figure can be applied to any circuit provided with a second-stage amplification module 123 that inverts the output signal of the first-stage amplification module 121, including but not limited to a circuit provided with a second amplification unit 1212.

[0121] Figure 11 FIG. 1 is a schematic diagram of an input signal exchange unit according to an embodiment of the present disclosure.

[0122] Reference Figure 11 In an embodiment of the present disclosure, the input signal exchange unit 13 can include:

[0123] The fourth switch K4 is an N-type transistor, the first end of which is connected to the non-inverting input INP, the second end of which is connected to the second bridge arm 112, and the gate of which is connected to the inverting signal 2stgENF of the second-stage gain enable signal;

[0124] The fifth switch K5 is an N-type transistor, the first end of which is connected to the non-inverting input INP, the second end of which is connected to the first bridge arm 111, and the gate of which is connected to the second-stage gain enable signal 2stgEN;

[0125] The sixth switch K6 is an N-type transistor, the first end of which is connected to the inverting input INN, the second end of which is connected to the second bridge arm 112, and the gate of which is connected to the second-stage gain enable signal 2stgEN;

[0126] The seventh switch K7 is an N-type transistor, the first end of which is connected to the inverting input INN, the second end of which is connected to the first bridge arm 111, and the gate of which is connected to the inverting signal 2stgENF of the second-stage gain enable signal.

[0127] In Figure 11In the illustrated embodiment, when the secondary gain enable signal 2stgEN is high and its inverted signal 2stgENF is low, the fourth switch K4 is off, the fifth switch K5 is on, and the inverting input terminal INN is connected to the second bridge arm 112; when the fifth switch K5 is on, the seventh switch K7 is off, and the non-inverting input terminal INP is connected to the first bridge arm 111, thus exchanging the input signals at the two input terminals of the amplification module 12, thereby inverting the output signal (signal of the third node N3) of the first-stage amplification module 121 in the amplification module 12. Simultaneously, since the secondary amplification module 123 is enabled (see... Figure 9 In the embodiment shown, the output signal of the amplification module 12 is the inverse of the output signal of the first-stage amplification module 121. Therefore, the output signal of the amplification module 12 is in phase with the output signal of the first-stage amplification module 121.

[0128] When the secondary gain enable signal 2stgEN is low and its inverted signal 2stgENF is high, the fourth switch K4 is turned on, the fifth switch K5 is turned off, and the inverting input INN is connected to the first bridge arm 111; when the fifth switch K5 is turned off, the seventh switch K7 is turned on, and the non-inverting input INP is connected to the second bridge arm 112. Since the secondary amplifier module 123 is disabled at this time, the output signal Vout of the amplifier module 12 is the output signal of the primary amplifier module 121 (the signal of the third node N3). At this time, the circuit output performance is the same as when only the primary amplifier module 121 is set.

[0129] Figure 12 This is a schematic diagram of a bandgap reference circuit in yet another embodiment of this disclosure.

[0130] refer to Figure 12 In one embodiment of this disclosure, when the first amplification unit 1211 includes a third N-type transistor MN3 and a fourth N-type transistor MN4, the bandgap reference circuit further includes:

[0131] The gain control switching unit 14 is connected between the gate of the third N-type transistor MN3, the gate of the fourth N-type transistor MN4, and the first resistor unit R1 and the second resistor unit R2. It is used to control the gate of the third N-type transistor MN3 to be connected to the second resistor unit R2 and the gate of the fourth N-type transistor MN4 to be connected to the first resistor unit R1 when the second-level gain enable signal 2stgEN is in sleep mode, or to control the connection point of the gate of the third N-type transistor MN3 and the connection point of the gate of the fourth N-type transistor MN4 to be switched when the second-level gain enable signal 2stgEN is active.

[0132] The gain control switching unit 14 and the input signal switching unit 13 need to exist simultaneously to switch the bias voltage Pcas and the bias voltage Ncas of the sleeve structure corresponding to the input signal when the input signal of the amplification unit 12 is switched, so as to realize the input signal switching of the entire amplification unit (the first amplification unit 1211 and the second amplification unit 1212).

[0133] Figure 13 FIG. 1 is a schematic diagram of a gain control switching unit in one embodiment of the present disclosure.

[0134] Reference Figure 13 In one embodiment of the present disclosure, the gain control switching unit 14 can include:

[0135] The eighth switch tube K8 is an N-type transistor, the first end of which is connected to the gate of the third N-type transistor MN3, the second end of which is connected to the second resistance unit R2, and the gate of which is connected to the inverted signal 2stgENF of the secondary gain enable signal;

[0136] The ninth switch tube K9 is an N-type transistor, the first end of which is connected to the gate of the third N-type transistor MN3, the second end of which is connected to the first resistance unit R1, and the gate of which is connected to the secondary gain enable signal 2stgEN;

[0137] The tenth switch tube K10 is an N-type transistor, the first end of which is connected to the gate of the fourth N-type transistor MN4, the second end of which is connected to the second resistance unit R2, and the gate of which is connected to the secondary gain enable signal 2stgEN;

[0138] The eleventh switch tube K11 is an N-type transistor, the first end of which is connected to the gate of the fourth N-type transistor MN4, the second end of which is connected to the first resistance unit R1, and the gate of which is connected to the inverted signal 2stgENF of the secondary gain enable signal.

[0139] When the secondary gain enable signal 2stgEN is low and the inverse signal 2stgENF of the secondary gain enable signal 2stgEN is high, the eighth switch K8 and the eleventh switch K11 are turned on, the ninth switch K9 and the tenth switch K10 are turned off, the gate of the third N-type transistor MN3 is connected to the second resistance unit R2, and the gate of the fourth N-type transistor MN4 is connected to the first resistance unit R1, which is the same as when the secondary amplification module 123 is not set.

[0140] Figure 14 FIG. 1 is a schematic diagram of a bias unit in one embodiment of the present disclosure.

[0141] Reference Figure 14 In one embodiment of the present disclosure, the bias unit 122 further comprises:

[0142] a bias resistance unit Rbias, a first end of which is connected to a first power supply Vcc, and a second end of which is connected to a bias node Nbias, the bias node Nbias being used to transmit a bias signal Vbias, the bias resistance unit Rbias comprising an adjustable resistance RZ;

[0143] a self-bias transistor Mbias, the gate and the drain of which are connected to the bias node Nbias, and the source of which is grounded.

[0144] In Figure 14 In the embodiment shown, the bias resistance unit Rbias can comprise a plurality of resistances connected in series, one or more of which are adjustable resistances, to adjust the bias current Ibias flowing through the bias node Nbias. The gates of the first bias transistor MB1 and the second bias transistor MB2 in the foregoing embodiment are both connected to the bias node Nbias to receive the bias signal Vbias.

[0145] The bias unit 122 is used to provide a stable bias voltage for the first bias transistor MB1 and the second bias transistor MB2, and can also be implemented by various circuits, which can be set by the person skilled in the art according to the actual situation, and the present disclosure does not make special limitations on this.

[0146] Figure 15 is a circuit schematic diagram of the amplification module in one embodiment of the present disclosure.

[0147] With reference to Figure 15 The amplification module 12 includes a first amplification module 121, a second amplification module 123, and a bias unit 122, wherein the first amplification module 121 includes a first amplification unit 1211 and a second amplification unit 1212, the transistors in the first amplification unit 1211 are all thick gate oxide transistors, and the transistors in the second amplification unit 1212 are all thin gate oxide transistors. Through the control of a first amplification unit enable signal ThickEn, a second amplification unit enable signal ThinEn, and a second-stage gain enable signal 2stgEN, the amplification module 12 of the first amplification + thick gate oxide transistor, the amplification module 12 of the first amplification + thin gate oxide transistor, the amplification module 12 of the second amplification + thick gate oxide transistor, and the amplification module 12 of the second amplification + thin gate oxide transistor can be realized, so as to select different working modes and working parameters of the amplification module 12 under various working conditions.

[0148] Although the transistors in the first amplification unit 1211 are all thick gate oxide transistors, and the transistors in the second amplification unit 1212 are all thin gate oxide transistors in the embodiment of the present disclosure, in other embodiments, the transistors in the first amplification unit 1211 can be all thin gate oxide transistors, the transistors in the second amplification unit 1212 can be all thick gate oxide transistors, or only the first amplification unit 1211 can be provided.

[0149] According to a second aspect of the present disclosure, a chip is provided, comprising the bandgap reference circuit according to any one of the above embodiments.

[0150] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, such a division is not mandatory. Indeed, according to an implementation of the present disclosure, the features and functionalities of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functionalities of one module or unit described above can be further divided into several modules or units embodied.

[0151] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure that come within the scope of the claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

Claims

1. A bandgap reference circuit, characterized by, The application relates to a bandgap reference circuit. The feedback transistor has a source connected to a first power supply and a drain connected to a first node; The reference setting module comprises a first bridge arm and a second bridge arm connected in parallel, the first bridge arm comprises a first resistance unit and a first voltage regulating unit connected in sequence, the second bridge arm comprises a second resistance unit, a third resistance unit and a second voltage regulating unit connected in sequence, the first resistance unit and the second resistance unit are connected to the first node and have equal resistance, and the first voltage regulating unit and the second voltage regulating unit are grounded; The amplification module has a non-inverting input connected to the first bridge arm, an inverting input connected to the second bridge arm and an output connected to the gate of the feedback transistor; The output transistor has a gate connected to the output of the amplification module, a source connected to the first power supply and a drain as an output of the bandgap reference circuit; The amplification module comprises a first-stage amplification module and a bias unit, the bias unit comprises a first-stage bias transistor, the first-stage amplification module has a first end connected to the first power supply and a second end connected to the drain of the first-stage bias transistor in the bias unit, and the first-stage amplification module comprises: A first P-type transistor having a source connected to the first power supply, a gate and a drain connected to a second node; A second P-type transistor having a source connected to the first power supply, a gate connected to the second node and a drain connected to a third node; The first amplification unit comprises: A first N-type transistor having a gate connected to the non-inverting input of the amplification module, a source electrically connected to the drain of a first-stage bias transistor in the bias unit and a drain connected to a fourth node electrically connected to the second node; A second N-type transistor having a gate connected to the inverting input of the amplification module, a source electrically connected to the drain of a first-stage bias transistor in the bias unit and a drain connected to a fifth node electrically connected to the third node; The gate of the first-stage bias transistor is used for receiving a bias signal and the source is grounded. The first amplification unit further comprises: A third N-type transistor having a gate connected to the second resistance unit, a source connected to the fourth node and a drain connected to the second node; A fourth N-type transistor having a gate connected to the first resistance unit, a source connected to the fifth node and a drain connected to the third node; The resistance between the gate of the third N-type transistor and the first node is equal to the resistance between the gate of the fourth N-type transistor and the first node, and the resistance between the gate of the third N-type transistor and the first node is smaller than the resistance between the gate of the first N-type transistor and the first node.

2. The bandgap reference circuit of claim 1, wherein, The first voltage regulating unit comprises a first PNP transistor, the emitter of the first PNP transistor is connected to the first resistance unit, and the base and the collector are grounded; the second voltage regulating unit comprises a plurality of second PNP transistors connected in parallel, the emitter of each second PNP transistor is connected to the third resistance unit, and the base and the collector are grounded.

3. The bandgap reference circuit of claim 1 or 2, wherein The first resistance unit and the second resistance unit each comprise a plurality of series resistors, the non-inverting input of the amplification module is connected to a connection node of two resistors in the first resistance unit, the inverting input of the amplification module is connected to a connection node of two resistors in the second resistance unit, and the resistance between the non-inverting input and the first node is equal to the resistance between the inverting input and the first node.

4. The bandgap reference circuit of claim 3, wherein, The first resistance unit comprises a first adjustable resistor, the second resistance unit comprises a second adjustable resistor, the resistance value of the first adjustable resistor is equal to the resistance value of the second adjustable resistor, and the resistance between one end of the first adjustable resistor away from the first node and the first node is equal to the resistance between one end of the second adjustable resistor away from the first node and the first node.

5. The bandgap reference circuit of claim 1, wherein, The transistors in the first amplification unit are thick gate oxide transistors, and the first amplification module further comprises: a second amplification unit connected in parallel with the first amplification unit, the second amplification unit having the same circuit structure and input signal as the first amplification unit, and being configured to output a second amplified signal through the third node according to the input signals of the inverting input and the non-inverting input, and the transistors in the second amplification unit being thin gate oxide transistors; a control module configured to control the first amplification unit and the second amplification unit to be enabled at the same time and only one of them.

6. The bandgap reference circuit of claim 1 or 5, wherein, The bias unit comprises a second bias transistor, and the amplification module further comprises: a second amplification module having an input end connected to the first amplification module, a first end connected to the first power supply, and a second end connected to the drain of the second bias transistor in the bias unit, and being configured to perform secondary amplification on the output signal of the first amplification module, the gate of the second bias transistor being configured to receive the bias signal, and the source being grounded.

7. The bandgap reference circuit of claim 6, wherein, The second amplification module comprises: a second amplification transistor having a gate connected to the third node, a source connected to the first power supply, and a drain connected to a sixth node; a first switch tube being a P-type transistor, having a first end connected to the sixth node, a second end connected to the output end of the amplification module, and a control end connected to an inverted signal of a second gain enable signal; a second switch tube being a P-type transistor, having a first end connected to the third node, a second end connected to the output end of the amplification module, and a control end connected to the second gain enable signal; a third switch tube being an N-type transistor, having a first end connected to the output end of the amplification module, a control end connected to the second gain enable signal, and a second end connected to the drain of the second bias transistor.

8. The bandgap reference circuit of claim 7, wherein, The second amplification transistor is a P-type transistor, and the bandgap reference circuit further comprises: An input signal switching unit is connected between the non-inverting input terminal and the inverting input terminal of the amplification module and the first bridge arm and the second bridge arm, and is configured to control the non-inverting input terminal of the amplification module to be connected to the first bridge arm and the inverting input terminal of the amplification module to be connected to the second bridge arm when the secondary gain enable signal is inactive, or to control the input signal of the non-inverting input terminal of the amplification module and the input signal of the inverting input terminal of the amplification module to be exchanged when the secondary gain enable signal is active.

9. The bandgap reference circuit of claim 8, wherein, When the first amplification unit comprises a third N-type transistor and a fourth N-type transistor, the bandgap reference circuit further comprises: A gain control switching unit is connected between the gate of the third N-type transistor and the gate of the fourth N-type transistor and the first resistance unit and the second resistance unit, and is configured to control the gate of the third N-type transistor to be connected to the second resistance unit and the gate of the fourth N-type transistor to be connected to the first resistance unit when the secondary gain enable signal is inactive, or to control the connection point of the gate of the third N-type transistor and the connection point of the gate of the fourth N-type transistor to be exchanged when the secondary gain enable signal is active.

10. The bandgap reference circuit of claim 8, wherein, The input signal switching unit comprises: A fourth switch tube is an N-type transistor, a first end of which is connected to the non-inverting input terminal, a second end of which is connected to the second bridge arm, and a gate of which is connected to an inverted signal of the secondary gain enable signal; A fifth switch tube is an N-type transistor, a first end of which is connected to the non-inverting input terminal, a second end of which is connected to the first bridge arm, and a gate of which is connected to the secondary gain enable signal; A sixth switch tube is an N-type transistor, a first end of which is connected to the inverting input terminal, a second end of which is connected to the second bridge arm, and a gate of which is connected to the secondary gain enable signal; A seventh switch tube is an N-type transistor, a first end of which is connected to the inverting input terminal, a second end of which is connected to the first bridge arm, and a gate of which is connected to an inverted signal of the secondary gain enable signal.

11. The bandgap reference circuit of claim 9, wherein, The gain control switching unit comprises: An eighth switch tube is an N-type transistor, a first end of which is connected to the gate of the third N-type transistor, a second end of which is connected to the second resistance unit, and a gate of which is connected to an inverted signal of the secondary gain enable signal; A ninth switch tube is an N-type transistor, a first end of which is connected to the gate of the third N-type transistor, a second end of which is connected to the first resistance unit, and a gate of which is connected to the secondary gain enable signal; A tenth switch tube is an N-type transistor, a first end of which is connected to the gate of the fourth N-type transistor, a second end of which is connected to the second resistance unit, and a gate of which is connected to the secondary gain enable signal; An eleventh switch tube is an N-type transistor, a first end of which is connected to the gate of the fourth N-type transistor, a second end of which is connected to the first resistance unit, and a gate of which is connected to an inverted signal of the secondary gain enable signal.

12. The bandgap reference circuit of claim 1 or 5, wherein, The biasing unit further comprises: A biasing resistance unit has a first end connected to the first power supply and a second end connected to a biasing node, the biasing node being configured to transmit the biasing signal, and the biasing resistance unit comprises an adjustable resistance; A self-biasing transistor has a gate and a drain both connected to the biasing node and a source connected to the ground.

13. A bandgap reference circuit, characterized by The biasing unit further comprises: a feedback transistor, a source for connecting a first power supply, and a drain for connecting a first node; a reference setting module, comprising a first bridge arm and a second bridge arm connected in parallel, the first bridge arm comprising a first resistance unit and a first voltage regulating unit connected in series, the second bridge arm comprising a second resistance unit, a third resistance unit and a second voltage regulating unit connected in series, the first resistance unit and the second resistance unit being connected to the first node and having equal resistance, the first voltage regulating unit and the second voltage regulating unit being grounded; an amplification module, an inverting input end of which is connected to the first bridge arm, a non-inverting input end of which is connected to the second bridge arm, and an output end of which is connected to a gate of the feedback transistor; an output transistor, a gate of which is connected to an output end of the amplification module, a source of which is connected to the first power supply, and a drain of which is used as an output end of the bandgap reference circuit; the amplification module comprises a first-stage amplification module and a bias unit, the bias unit comprising a first-stage bias transistor, a first end of the first-stage amplification module being used for connecting the first power supply, a second end of the first-stage amplification module being connected to a drain of the first-stage bias transistor in the bias unit, and the first-stage amplification module comprising: a first P-type transistor, a source of which is connected to the first power supply, and a gate and a drain of which are both connected to a second node; a second P-type transistor, a source of which is connected to the first power supply, a gate of which is connected to the second node, and a drain of which is connected to a third node; a first amplification unit, comprising: a first N-type transistor, a gate of which is connected to a non-inverting input end of the amplification module, a source of which is electrically connected to a drain of a first-stage bias transistor in the bias unit, and a drain of which is connected to a fourth node, the fourth node being electrically connected to the second node; a second N-type transistor, a gate of which is connected to an inverting input end of the amplification module, a source of which is electrically connected to the drain of the first-stage bias transistor in the bias unit, and a drain of which is connected to a fifth node, the fifth node being electrically connected to the third node; wherein a gate of the first-stage bias transistor is used for receiving a bias signal, and a source of the first-stage bias transistor is grounded; all the transistors in the first amplification unit are thick-gate oxide transistors, and the first-stage amplification module further comprises: a second amplification unit, connected in parallel with the first amplification unit, the second amplification unit having the same circuit structure and input signal as the first amplification unit, and being used for outputting a second amplification signal through the third node according to input signals of the non-inverting input end and the inverting input end, all the transistors in the second amplification unit being thin-gate oxide transistors; a control module, used for controlling the first amplification unit and the second amplification unit to have and only have one enabled at the same time.

14. A bandgap reference circuit, characterized by comprising: a feedback transistor, a source of which is used for connecting a first power supply, and a drain of which is used for connecting a first node; a reference setting module, comprising a first bridge arm and a second bridge arm connected in parallel, the first bridge arm comprising a first resistance unit and a first voltage regulating unit connected in series, the second bridge arm comprising a second resistance unit, a third resistance unit and a second voltage regulating unit connected in series, the first resistance unit and the second resistance unit being connected to the first node and having equal resistance, the first voltage regulating unit and the second voltage regulating unit being grounded; An amplification module, an inverting input end of which is connected to the first bridge arm, a non-inverting input end of which is connected to the second bridge arm, and an output end of which is connected to a gate of the feedback transistor; An output transistor, a gate of which is connected to the output end of the amplification module, a source of which is connected to the first power supply, and a drain of which serves as an output end of the bandgap reference circuit; The amplification module comprises a first-stage amplification module and a biasing unit, the biasing unit comprises a first-stage biasing transistor, a first end of the first-stage amplification module is configured to be connected to the first power supply, and a second end of the first-stage amplification module is connected to a drain of the first-stage biasing transistor in the biasing unit, and the first-stage amplification module comprises: A first P-type transistor, a source of which is connected to the first power supply, and a gate and a drain of which are both connected to a second node; A second P-type transistor, a source of which is connected to the first power supply, a gate of which is connected to the second node, and a drain of which is connected to a third node; A first amplification unit, comprising: A first N-type transistor, a gate of which is connected to a non-inverting input end of the amplification module, a source of which is electrically connected to a drain of a first-stage biasing transistor in the biasing unit, and a drain of which is connected to a fourth node, the fourth node being electrically connected to the second node; A second N-type transistor, a gate of which is connected to an inverting input end of the amplification module, a source of which is electrically connected to the drain of the first-stage biasing transistor in the biasing unit, and a drain of which is connected to a fifth node, the fifth node being electrically connected to the third node; The gate of the first-stage biasing transistor is configured to receive a biasing signal, and the source of the first-stage biasing transistor is grounded. The biasing unit comprises a second-stage biasing transistor, and the amplification module further comprises: A second-stage amplification module, an input end of which is connected to the first-stage amplification module, a first end of which is connected to the first power supply, and a second end of which is connected to a drain of the second-stage biasing transistor in the biasing unit, the second-stage amplification module being configured to perform secondary amplification on an output signal of the first-stage amplification module, the gate of the second-stage biasing transistor being configured to receive the biasing signal, and the source of the second-stage biasing transistor being grounded; The second-stage amplification module comprises: A second-stage amplification transistor, a gate of which is connected to the third node, a source of which is connected to the first power supply, and a drain of which is connected to a sixth node; A first switch tube, which is a P-type transistor, a first end of which is connected to the sixth node, a second end of which is connected to an output end of the amplification module, and a control end of which is connected to an inverting signal of a second-stage gain enable signal; A second switch tube, which is a P-type transistor, a first end of which is connected to the third node, a second end of which is connected to the output end of the amplification module, and a control end of which is connected to the second-stage gain enable signal; A third switch tube, which is an N-type transistor, a first end of which is connected to the output end of the amplification module, a control end of which is connected to the second-stage gain enable signal, and a second end of which is connected to the drain of the second-stage biasing transistor.

15. A chip, characterized by The bandgap reference circuit comprises the bandgap reference circuit according to any one of claims 1 to 14.

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