Display panel, driving method thereof and display device

Abstract

The application discloses a display panel, a driving method thereof and a display device. The display panel comprises a plurality of pixel rows and a plurality of pixel columns arranged in an array. The display panel comprises an effective display area and an ineffective display area. The effective display area comprises at least one optional pixel column. The display panel further comprises a data latch unit arranged between a data signal line and a pixel column. The data latch unit is used to control the effective display area to transmit a data voltage provided by the data signal line for display based on a first effective control signal provided by the data signal line, and control the connection between the data signal line and the pixel column corresponding to the ineffective display area based on a second effective control signal. The data latch unit arranged between the data driving circuit and the data signal line realizes the display control of the effective display area and the display control of the ineffective display area, and effectively realizes the display control of the horizontal partition display.

Description

Technical Field

[0001] This application generally relates to the field of display technology, and specifically to a display panel, its driving method, and a display device. Background Technology

[0002] In the current display technology field, many manufacturers have proposed a zoned frequency conversion solution to save display power consumption. This involves dividing a display panel into multiple zones, each of which can be set with a different refresh rate. How to effectively implement arbitrary zoned frequency conversion has become a pressing issue. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel, its driving method and display device, which can realize display control of horizontal partition display, achieve display diversification and be applicable to a variety of application scenarios.

[0004] In a first aspect, this application provides a display panel, the display panel including a plurality of pixel rows and a plurality of pixel columns arranged in an array, the display panel including an effective display area and an ineffective display area, the effective display area including at least one optional pixel column, and the display panel further including:

[0005] The data driving circuit includes a plurality of data signal lines connected to the pixel column;

[0006] A data latch unit is disposed between the data signal line and the pixel column.

[0007] The data latch unit is used to control the effective display area to transmit the data voltage provided by the data signal line for display based on a first effective control signal provided by the data signal line, and to control the connection between the data signal line and the pixel column corresponding to the invalid display area based on a second effective control signal.

[0008] In some embodiments, the data latch unit includes a latch circuit and a gating circuit.

[0009] The latching circuit includes a latching capacitor, a first latching sub-circuit, and a second latching sub-circuit. The first terminal of the first latching sub-circuit is connected to a first voltage terminal, the first terminal of the second latching sub-circuit is connected to a second voltage terminal, the second terminals of the first and second latching sub-circuits are connected to the latching capacitor, and the control terminals of the first and second latching sub-circuits are both connected to the corresponding data signal lines.

[0010] The gating circuit includes a first gating sub-circuit, a first terminal of which is connected to the corresponding pixel column, a second terminal of which is connected to the corresponding data signal line, and a control terminal of which is connected to the latching capacitor.

[0011] In some embodiments, the gating circuit further includes a second gating sub-circuit, the first end of the second gating sub-circuit is connected to the corresponding pixel column, the second end of the second gating sub-circuit is connected to the third voltage terminal, and the control terminal of the second gating sub-circuit is connected to the latching capacitor;

[0012] The third voltage terminal is used to provide a third voltage. When the data latch unit disconnects the connection between the data signal line and the pixel column corresponding to the invalid display area based on the control of the second valid control signal, the data latch unit provides the third voltage to the invalid display area.

[0013] In some embodiments, the first voltage terminal is used to provide a first voltage for controlling the first gating sub-circuit to be turned on, and the second voltage terminal is used to control the second gating sub-circuit to be turned on with a second voltage.

[0014] In some embodiments, the first voltage and the second voltage are different signals.

[0015] In some embodiments, the refresh rate of the effective display area is higher than the refresh rate of the invalid display area.

[0016] In some embodiments, the display panel further includes a first gating unit.

[0017] The first gating unit is disposed between the data latching unit and the data signal line. The first gating unit is used to transmit the data voltage provided by the data signal line to the effective display area in response to the control of the first gating control signal.

[0018] In some embodiments, the display panel further includes a gate driving circuit and a second gating unit.

[0019] The gate driving circuit includes a plurality of scan signal lines connected to the meaning of the pixel row;

[0020] The second gating unit is disposed between the driving module and the scanning signal line. The second gating unit is used to transmit the scanning signal provided by the scanning signal line to the effective display area in response to the control of the second gating control signal.

[0021] Secondly, this application provides a driving method for a display panel, using the aforementioned display panel, the method comprising:

[0022] A first valid control signal is provided to the data latch unit corresponding to the effective display area, so that the data latch unit transmits the data voltage provided by the data signal line to the pixel column corresponding to the effective display area for display under the control of the first valid control signal;

[0023] A second valid control signal is provided to the data latch unit corresponding to the invalid display area, so that the data latch unit, under the control of the second valid control signal, disconnects the connection between the pixel column corresponding to the invalid display area and the data signal.

[0024] Thirdly, this application provides a display device, including the aforementioned display panel.

[0025] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0026] The display panel, driving method, and display device provided in this application embodiment, by setting a data latch unit between the data driving circuit and the data signal line, and controlling the connection or disconnection between the data signal line and the pixel column based on the control of the effective signal, realizes the display control of the effective display area and the display control of the wireless display area, effectively realizes the display control of horizontal partition display, realizes display diversification, and is suitable for various application scenarios. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0028] Figure 1 A schematic diagram of a pixel circuit provided for an embodiment of this application;

[0029] Figure 2 for Figure 1 Timing diagram corresponding to the pixel circuit;

[0030] Figure 3 This is a schematic diagram illustrating the control of different partition refreshes via gating control signals in related technologies.

[0031] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0032] Figure 5 This is a timing diagram corresponding to a display panel provided in an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the structure of a data latch unit provided in an embodiment of this application;

[0034] Figure 7This is a schematic diagram of another data latch unit provided in an embodiment of this application;

[0035] Figure 8 A schematic diagram of the structure of another data latch unit provided in the embodiments of this application;

[0036] Figure 9 A schematic diagram illustrating the division of display partitions provided in an embodiment of this application;

[0037] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0038] Figure 11 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0039] Figure 12 This is a timing diagram corresponding to another display panel provided in an embodiment of this application;

[0040] Figure 13 A flowchart illustrating a driving method for a display panel provided in an embodiment of this application. Detailed Implementation

[0041] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] As consumers demand lower power consumption from displays, LTPO (Low Temperature Polycrystalline Oxide) display panels have been designed to achieve low-frequency display, as low as 1Hz, thus reducing power consumption.

[0044] In related technologies, the pixel circuits used in LTPO display panels are mainly 7TIC and 8TIC. Among them, the 8TIC pixel circuit has better advantages in debugging VRR (Variable refresh rate, often referring to display panel frequency switching flicker) and Flicker (often referring to display panel static flicker). Based on this, a brief introduction to the 8TIC pixel circuit is given below.

[0045] refer to Figure 1The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a capacitor, and a light-emitting device.

[0046] The control terminal of the first transistor is connected to the first initialization signal control terminal N-Reset. The first terminal of the first transistor is connected to the second terminal of the second transistor, the second terminal of the third transistor, and the first terminal of the sixth transistor. The second terminal of the first transistor is connected to the input terminal of the first initialization voltage signal Vinit1.

[0047] The control terminal of the second transistor is connected to the first gate drive signal terminal Gate_N, and the first terminal of the second transistor is connected to the second terminal of the capacitor and the control terminal of the third transistor, respectively.

[0048] The first terminal of the third transistor is connected to the first terminal of the fourth transistor, the second terminal of the fifth transistor, and the first terminal of the eighth transistor, respectively.

[0049] The control terminal of the fourth transistor is connected to the second gate drive signal terminal Gate_P, and the second terminal of the fourth transistor is connected to the data signal input terminal Vdata.

[0050] The control terminal of the fifth transistor is connected to the light-emitting control signal terminal EM, and the first terminal of the fifth transistor is connected to the positive terminal of the power supply VDD.

[0051] The control terminal of the sixth transistor is connected to the light-emitting control signal terminal EM, and the second terminal of the sixth transistor is connected to the anode of the light-emitting device and the first terminal of the seventh transistor, respectively.

[0052] The control terminal of the seventh transistor is connected to the second initialization signal control terminal P_Reset, and the second terminal of the seventh transistor is connected to the second initialization voltage signal input terminal Vinit2.

[0053] The control terminal of the eighth transistor is connected to the second initialization signal control terminal P_Reset, and the second terminal of the eighth transistor is connected to the third initialization voltage signal input terminal Vinit3.

[0054] The cathode of the OLED light-emitting device is connected to the negative terminal VSS of the power supply.

[0055] It is understood that any transistor in the pixel circuit of this application can be an N-type transistor or a P-type transistor, whichever is chosen according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal. It is understood that the transistor can be a P-type transistor or an N-type transistor, whichever is chosen according to the actual situation, but the device connection method of the circuit needs to be adjusted accordingly, and the alternative solution is still within the protection scope of this application.

[0056] It is understood that the transistors used in the circuit of this application can be MOS transistors (metal-oxide-semiconductor field-effect transistors), TFT transistors (thin film transistors), or other types of transistors. The specific choice can be made according to the actual situation. The alternative solutions are still within the protection scope of this application. The connection method of TFT transistors or other types of transistors can be referred to the connection method of MOS transistors, which will not be repeated here. Figure 2 This is a timing diagram for an 8TIC pixel circuit.

[0057] However, saving display power consumption is not limited to this. Many terminal device manufacturers have proposed a partitioned frequency conversion solution, in which a screen is divided into several areas, and the refresh rate of each area can be set differently. How to effectively achieve arbitrary partitioning and avoid screen splitting caused by refresh rate has become an urgent problem to be solved.

[0058] First, let's briefly explain the partitioned refresh rate technology. Partitioned refresh rate solutions divide a display panel into multiple zones, each with a different refresh rate. Currently, most partitioned refresh rate solutions control the scanning signals of the display panel's pixel rows to prevent them from entering the pixel circuitry. Specifically, as shown... Figure 3 As shown, a gating control signal GE divides the display panel into multiple areas from top to bottom. Pulling the GE signal high or low controls whether the scan signal enters the pixel circuit, thus controlling the refresh rate of the display panel while keeping the refresh rate of the gate drive circuit constant.

[0059] As can be seen, conventional split-screen displays only divide the display panel vertically into three areas, and cannot achieve horizontal split-screen functionality. Based on this, this application proposes a display panel, its driving method, and a display device to achieve horizontally arbitrary split-screen refresh control.

[0060] See Figure 4 This application provides a display panel, including:

[0061] The array is configured with multiple pixel rows and multiple pixel columns, and the display panel includes an active display area and an inactive display area, wherein the active display area includes at least one optional pixel column.

[0062] The data driving circuit 100 includes a plurality of data signal lines DL connected to the pixel column.

[0063] The data latch unit 200 is disposed between the data signal line DL and the pixel column.

[0064] The data latch unit 200 is used to control the data voltage provided by the data signal line DL in the valid display area for display based on a first valid control signal provided by the data signal line DL, and to control the connection between the data signal line DL and the pixel column corresponding to the invalid display area based on a second valid control signal.

[0065] The display panel provided in this application embodiment sets up a data latch unit between the data driving circuit and the data signal line, and controls the connection or disconnection between the data signal line and the pixel column based on the control of the effective signal, thereby realizing the display control of the effective display area and the display control of the wireless display area, effectively realizing the display control of horizontal partition display, realizing display diversification, and applicable to a variety of application scenarios.

[0066] In this embodiment, the display panel includes multiple data signal lines DL and multiple scan signal lines GL. The data signal lines DL and scan signal lines GL are intersected to define multiple pixel units P. The multiple pixel units P are arranged in an array to form multiple pixel rows and multiple pixel columns. The multiple data signal lines DL extend along the column direction, and the multiple scan signal lines GL extend along the row direction. The scan signal lines GL correspond one-to-one with the pixel rows, and the data signal lines DL correspond one-to-one with the pixel columns. Each data signal line DL connects to one column of pixel units P, and each scan signal line GL connects to one row of pixel units P. The multiple data signal lines DL write data voltage into the pixel units P row by row.

[0067] The gate driving circuit 300 outputs a scan signal, which scans the pixel array line by line via the scan signal line GL. The data driving circuit 100 outputs a data signal, which is transmitted to the corresponding pixel unit P via the data signal line DL to achieve image grayscale. Specifically, during the display stage, the gate driving circuit 300 outputs scan signals line by line to the multi-line scan signal lines to activate the pixel unit P connected to each scan signal line GL line. Then, the required data signals are written to the activated sub-pixel units line by line via all column data signal lines DL, thereby achieving display.

[0068] Understandable, Figure 4In the example, multiple pixel units are arranged in multiple rows along a first direction (X direction in the figure) and in multiple columns along a second direction (Y direction in the figure). The first direction and the second direction intersect each other. In the embodiment of this application, the first direction and the second direction intersect perpendicularly, and the first direction and the second direction can be interchanged.

[0069] In the embodiments of this application, such as Figure 5 As shown, in one display cycle, the data driving circuit outputs a DATA_1 signal sequence containing a first valid control signal to the active display area and a DATA_2 signal sequence containing a second valid control signal to the inactive display area. The active display area, controlled by the first valid control signal, connects the data signal line DL to the pixel column, causing the display panel to display based on the data voltage provided by the data signal line. The inactive display area, controlled by the second valid control signal, disconnects the connection between the data signal line DL and the pixel column, and does not perform display updates.

[0070] In one feasible embodiment, such as Figure 6 As shown, the data latch unit 200 includes a latch circuit 210 and a gating circuit 220.

[0071] The latch circuit 210 includes a latch capacitor Cst, a first latch sub-circuit 211, and a second latch sub-circuit 212. The first terminal of the first latch sub-circuit 211 is connected to the first voltage terminal VG_1, and the first terminal of the second latch sub-circuit 212 is connected to the second voltage terminal VG_2. The second terminals of the first latch sub-circuit 211 and the second latch sub-circuit 212 are connected to the latch capacitor Cst. The control terminals of the first latch sub-circuit 211 and the second latch sub-circuit 212 are both connected to the corresponding data signal line DL.

[0072] The gating circuit 220 includes a first gating sub-circuit 221. The first end of the first gating sub-circuit 221 is connected to the corresponding pixel column, the second end of the first gating sub-circuit 221 is connected to the corresponding data signal line DL, and the control end of the first gating sub-circuit 221 is connected to the latching capacitor Cst.

[0073] In other words, during a display cycle, the data signal line DL outputs a first valid control signal or a second valid control signal to the latch circuit 210, controlling the first latch sub-circuit 211 or the second latch sub-circuit 212 in the latch circuit 210 to be turned on, and storing the selection voltage used to control the selection circuit 220 to be turned on in the latch capacitor Cst.

[0074] Optionally, the first valid control signal refers to a valid signal that can enable the first latch sub-circuit 211 or the second latch sub-circuit 212, and the second valid control signal refers to an invalid signal that enables the second latch sub-circuit 212 or the first latch sub-circuit 211. In different embodiments, the valid level signal can be a high level signal and the invalid level signal can be a low level signal; or, the valid level signal can be a low level signal and the invalid level signal can be a high level signal.

[0075] Specifically, when the data signal line DL outputs a first valid signal to the latch circuit 210, the first latch sub-circuit 211 or the second latch sub-circuit 212 in the latch circuit 210 is turned on, storing the first selection voltage used to control the selection circuit 220 in the latch capacitor Cst. The first selection voltage is the selection voltage used to control the first selection sub-circuit 221 to turn on. When the selection voltage stored in the latch capacitor Cst reaches the first selection voltage of the first selection sub-circuit 221, the first selection sub-circuit 221 is turned on, that is, the data signal line DL is connected to the pixel column corresponding to the effective display area, so that the pixel column is displayed according to the data voltage provided by the data signal line DL.

[0076] In one feasible embodiment, such as Figure 7 As shown, the gating circuit 220 also includes a second gating sub-circuit 222. The first end of the second gating sub-circuit 222 is connected to the corresponding pixel column, the second end of the second gating sub-circuit 222 is connected to the third voltage terminal VG_3, and the control terminal of the second gating sub-circuit 222 is connected to the latching capacitor.

[0077] The third voltage terminal VG_3 is used to provide a third voltage. When the data latch unit 200 disconnects the connection between the data signal line and the data column corresponding to the invalid display area based on the control of the second valid control signal, the data latch unit provides a third voltage to the invalid display area.

[0078] It should be noted that the third voltage is a constant voltage with a range of 0-7V. The specific setting can be adjusted according to the actual situation.

[0079] It should be understood that when the data signal line DL outputs a second valid signal to the latch circuit 210, the first latch sub-circuit 211 or the second latch sub-circuit 212 in the control latch circuit 210 is turned on, storing the second gate voltage used to control the gate selection circuit 220 in the latch capacitor Cst. The second gate voltage is the gate voltage used to control the second gate sub-circuit 221 to turn on. When the gate voltage stored in the latch capacitor Cst reaches the second gate voltage of the second gate sub-circuit 221, the second gate sub-circuit 221 is turned on, that is, the control data signal line DL and the pixel column corresponding to the invalid display area are disconnected, and a third voltage is provided to the invalid display area. By introducing the third voltage, problems such as screen brightness differences in the invalid display area are effectively avoided.

[0080] In one feasible embodiment, a first voltage terminal is used to provide a first voltage for controlling the first gating sub-circuit 221 to be turned on, and a second voltage terminal is used to control the second gating sub-circuit 222 to be turned on.

[0081] In other words, when the data signal line DL outputs the first valid control signal to the latch circuit 210, the first valid control signal controls the first latch sub-circuit 211 to turn on, so as to store the first voltage in the latch capacitor Cst, and when the voltage of the latch capacitor Cst reaches the first voltage, it controls the first selection sub-circuit 221 to turn on, and provides the data voltage provided by the data signal line DL to the pixel column.

[0082] Furthermore, when the data signal line DL outputs a second valid control signal to the latch circuit 210, the second valid control signal controls the second latch sub-circuit 211 to turn on, so as to store the second voltage in the latch capacitor Cst, and when the voltage of the latch capacitor Cst reaches the second voltage, it controls the second gating sub-circuit 221 to turn on, and provides the constant voltage provided by the third voltage terminal to the pixel column.

[0083] In one feasible embodiment, such as Figure 8 As shown, the first latch sub-circuit 211 includes a first transistor T1. The first terminal of the first transistor T1 is connected to the first voltage terminal VG_1, the second terminal of the first transistor T1 is connected to the latching capacitor Cst, and the control terminal of the first transistor T1 is connected to the data signal line DL.

[0084] The second latch sub-circuit 212 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the second voltage terminal VG_2, the second terminal of the second transistor T2 is connected to the latching capacitor Cst, and the control terminal of the second transistor T2 is connected to the data signal line DL.

[0085] The first selection sub-circuit 221 includes a third transistor T3. The first terminal of the third transistor T3 is connected to the corresponding pixel column, the second terminal of the third transistor T3 is connected to the data signal line DL, and the control terminal of the third transistor T3 is connected to the latching capacitor Cst.

[0086] The second gating sub-circuit 222 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the corresponding pixel column, the second terminal of the fourth transistor T4 is connected to the third voltage terminal VG_3, and the control terminal of the fourth transistor T4 is connected to the latching capacitor Cst.

[0087] It should be noted that the transistors used in all embodiments of this invention are thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, there is no difference between their source and drain. In the embodiments of this application, in order to distinguish the two poles of the transistor other than the gate, one pole is called the first terminal and the other pole is called the second terminal.

[0088] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. The following embodiments use N-type transistors as examples. When using an N-type transistor, the first terminal can be the source, and the second terminal can be the drain. It is conceivable that using a P-type transistor is easily conceived by those skilled in the art without inventive effort, and therefore falls within the scope of protection of this invention. As is known in the art, an N-type transistor is turned on by a high-level control signal and turned off by a low-level control signal; a P-type transistor is turned on by a low-level control signal and turned off by a high-level control signal.

[0089] Optionally, the first transistor T1 is either an N-type transistor or a P-type transistor, the second transistor T2 is either an N-type transistor or a P-type transistor, the third transistor T3 is either an N-type transistor or a P-type transistor, and the fourth transistor T4 is either an N-type transistor or a P-type transistor. For example, if the first transistor T1 is an N-type transistor, then the second transistor T2 is a P-type transistor; if the third transistor T3 is an N-type transistor, then the fourth transistor T4 is a P-type transistor. Alternatively, the first transistor T1 can be a P-type transistor, the second transistor T2 an N-type transistor, the third transistor T3 a P-type transistor, and the fourth transistor T4 an N-type transistor; this is not a limitation.

[0090] In one feasible embodiment, the first voltage and the second voltage are different signals. For example, the first voltage and the second voltage are opposite signals, wherein the first voltage can be a high level VGH and the second voltage can be a low level VGL.

[0091] In this embodiment, by using different types of transistors for the first transistor T1 and the second transistor T2, it is possible to achieve the following under the control of the same timing control signal: when the first transistor T1 is in the conducting state under the control of the first valid control signal, the second transistor T2 is in the off state under the same control signal. Similarly, by using different types of transistors for the third transistor T3 and the fourth transistor T4, it is possible to achieve the following under the control of the same timing control signal: when the third transistor T3 is in the conducting state under the control of the first voltage VG_1, the fourth transistor T4 is in the off state under the same control signal.

[0092] In the embodiments of this application, such as Figure 9 As shown, the display panel includes at least one effective display area M, and the refresh rate of the effective display area M is higher than the refresh rate of the ineffective display area. In this embodiment, the effective display area M has a high frequency relative to the refresh rate of the display panel. The overall refresh rate of the display panel depends on the refresh rate of the gate drive circuit 300. The effective display area M refers to a display area with a higher refresh rate. For example, if the overall refresh rate of the display panel is 1Hz, the refresh rate of the effective display area is 120Hz.

[0093] It is understood that the number of valid display partitions M is not limited in the embodiments of this application, and can be set as needed in different embodiments. When there are multiple valid display partitions M, the division method of the valid display partitions M is not limited. The size of each valid display partition M can be the same or different. At the same time, the refresh rate of each valid display partition M can be the same or different.

[0094] In this embodiment, by providing data latching units on each data signal line on the display panel, the refresh rate of the display partition can be adjusted at any location in different application scenarios. This allows for arbitrary division of the effective display partition M, enabling diverse display solutions. Of course, in other embodiments, the effective display partition M can be a fixed partition, such as a secondary screen. By providing data latching units 200 only on each data signal line DL corresponding to the effective display partition M, the refresh rate of the effective display partition M can be adjusted.

[0095] It is understood that the configuration positions of the transistors on the data latch unit 200 are not shown in this embodiment. The third transistor T3 on the first gating subunit 221 can correspond one-to-one with the data signal line DL, and the fourth transistor T4 on the second gating subunit 222 can also correspond one-to-one with the data signal line DL. In different embodiments, the configuration of the transistors on the data latch unit 200 can be adjusted according to the different driving methods of the data driving circuit 100.

[0096] The fourth transistor T4 on the second gating subunit 222 is used to control the access of each pixel column on the effective display partition M to the third voltage. In this embodiment, optionally, each fourth transistor T4 is connected to one or more pixel columns. In different embodiments, multiple pixel columns can share one fourth transistor T4, and the third voltage can be provided to multiple pixel columns simultaneously through one fourth transistor T4.

[0097] In one feasible embodiment, the embodiments of this application can also implement vertical partitioning frequency conversion. Optionally, such as Figure 10 As shown, the display panel includes a gate driving circuit 300 and a first gating unit 400.

[0098] The gate drive circuit 300 includes a plurality of scan signal lines GL that are connected one-to-one with the pixel rows.

[0099] The first gating unit 400 is disposed between the gate driving circuit 300 and the scan signal line. The first gating unit 400 is used to transmit the scan signal provided by the scan signal line to the effective display area in response to the control of the first gating control signal.

[0100] It should be noted that the first gating control signal is used to control the first gating unit 400 to turn on and off the connection between the gate drive circuit 300 and the scan signal line GL.

[0101] Furthermore, when there are many vertical partitions, it is difficult to control the non-refreshing areas to stop or maintain constant voltage when refreshing to any pixel row. Therefore, this application proposes to add a second gating unit to achieve gating control of the data signal lines during row-by-row refresh.

[0102] In one feasible embodiment, such as Figure 11 As shown, the display panel includes a second gating unit 500.

[0103] The second gating unit 500 is disposed between the data latch unit 200 and the pixel column. The second gating unit 500 is used to connect and disconnect the connection between the data latch unit 200 and the pixel column in response to the control of the second gating control signal.

[0104] In this embodiment, a second gating unit is set between the data latching unit and the pixel column to control the access of the pixel column to the data signal. This enables the matching of whether the scan signal is output and whether the data signal is output. For pixel rows that do not need to be refreshed, the data signal is not output, thereby saving power consumption.

[0105] The second gating unit 500 includes multiple fifth transistors T5. One end of the fifth transistor T5 is connected to the corresponding data latch unit, the second end of the fifth transistor T5 is connected to the corresponding pixel column, and the control end of the fifth transistor T5 is connected to the second gating control signal.

[0106] The diagram illustrating the relationship between the second gating control signal and the scan signal output is shown below. Figure 12 As shown, Nout is the scan signal received for each pixel row, i.e., the output signal of the first gating unit, N-mode represents the frames that all need to be refreshed, L-mode represents the frames that do not need to be refreshed for at least one undisplayed partition, and Frame represents "frame".

[0107] Based on the same inventive concept, this application provides a method for driving a display panel, employing any of the display panels described above, such as... Figure 13 As shown, the display panel includes an active display area and an inactive display area. The active display area includes at least one optional column of pixels. The driving method includes:

[0108] S101, a first valid control signal is provided to the data latch unit corresponding to the valid display area, so that the data latch unit, under the control of the first valid control signal, transmits the data voltage provided by the data signal line to the pixel column corresponding to the valid display area for display.

[0109] S102, a second valid control signal is provided to the data latch unit corresponding to the invalid display area, so that the data latch unit disconnects the connection between the pixel column corresponding to the invalid display area and the data signal under the control of the second valid control signal.

[0110] Refresh rate refers to the number of times an image is refreshed per second. In this embodiment, the refresh rate of the display panel includes the refresh rate of the scan signal of the gate driving circuit and the refresh rate of the data signal of the data driving circuit. In this embodiment, the gate driving circuit and the data driving circuit are driven by a line-by-line scanning method, which is described as an example. When it is determined that the refresh rate of the effective display partition M needs to be adjusted, when the data driving circuit scans the pixel column corresponding to the effective display partition M, it controls whether to refresh the corresponding pixel column, thereby achieving local refresh.

[0111] It is understood that the adjustment of the local refresh rate in this embodiment includes confirming the pixel column corresponding to the effective display partition M. This pixel column can be multiple consecutive columns or multiple non-consecutive columns. There can be multiple effective display partitions M on the display panel, which are confirmed according to the device or application scenario. When adjusting the refresh rate of the effective display partition M, the driving adjustment can be performed on one frame or multiple consecutive frames at intervals within one second. The adjustment is based on the target refresh rate of the effective partition M and the refresh rate of the data driving circuit.

[0112] This application provides a display device, including a display panel as described in any of the above descriptions.

[0113] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0114] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0115] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “set” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0116] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel rows and multiple pixel columns arranged in an array. The display panel includes an effective display area and an ineffective display area. The effective display area includes at least one optional pixel column. The display panel also includes: The data driving circuit includes a plurality of data signal lines connected to the pixel column; A data latch unit is disposed between the data signal line and the pixel column. The data latch unit is used to control the effective display area to transmit the data voltage provided by the data signal line for display based on a first effective control signal provided by the data signal line, and to control the connection between the data signal line and the pixel column corresponding to the invalid display area based on a second effective control signal. The data latch unit includes a latch circuit and a gating circuit. The latching circuit includes a latching capacitor, a first latching sub-circuit, and a second latching sub-circuit. The first terminal of the first latching sub-circuit is connected to a first voltage terminal, the first terminal of the second latching sub-circuit is connected to a second voltage terminal, the second terminals of the first and second latching sub-circuits are connected to the latching capacitor, and the control terminals of the first and second latching sub-circuits are both connected to the corresponding data signal lines. The gating circuit includes a first gating sub-circuit, a first terminal of which is connected to the corresponding pixel column, a second terminal of which is connected to the corresponding data signal line, and a control terminal of which is connected to the latching capacitor.

2. The display panel according to claim 1, characterized in that, The gating circuit further includes a second gating sub-circuit, the first end of which is connected to the corresponding pixel column, the second end of which is connected to the third voltage terminal, and the control terminal of which is connected to the latching capacitor. The third voltage terminal is used to provide a third voltage. When the data latch unit disconnects the connection between the data signal line and the pixel column corresponding to the invalid display area based on the control of the second valid control signal, the data latch unit provides the third voltage to the invalid display area.

3. The display panel according to claim 2, characterized in that, The first voltage terminal is used to provide a first voltage for controlling the first gating sub-circuit to be turned on, and the second voltage terminal is used to control the second gating sub-circuit to be turned on.

4. The display panel according to claim 1, characterized in that, The first voltage and the second voltage are different signals.

5. The display panel according to claim 1, characterized in that, The refresh rate of the effective display area is higher than that of the invalid display area.

6. The display panel according to claim 1, characterized in that, The display panel also includes a gate driving circuit and a first gating unit. The gate driving circuit includes a plurality of scan signal lines that are connected one-to-one with the pixel rows; The first gating unit is disposed between the gate driving circuit and the scan signal line. The first gating unit is used to transmit the scan signal provided by the scan signal line to the effective display area in response to the control of the first gating control signal.

7. The display panel according to claim 6, characterized in that, The display panel also includes a second gating unit. The second gating unit is disposed between the data latch unit and the pixel column. The second gating unit is used to connect and disconnect the connection between the data latch unit and the pixel column in response to the control of the second gating control signal.

8. A driving method for a display panel, characterized in that, The method, employing a display panel as described in any one of claims 1-7, comprises: A first valid control signal is provided to the data latch unit corresponding to the effective display area, so that the data latch unit transmits the data voltage provided by the data signal line to the pixel column corresponding to the effective display area for display under the control of the first valid control signal; A second valid control signal is provided to the data latch unit corresponding to the invalid display area, so that the data latch unit, under the control of the second valid control signal, disconnects the connection between the pixel column corresponding to the invalid display area and the data signal.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 7.

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