A sub-real-time processor, a real-time processor and a system-on-a-chip

Abstract

This invention discloses a sub-real-time processor, a real-time processor, and a system-on-a-chip (SoC). The sub-real-time processor includes: a control unit for generating corresponding control signals and sending them to other units; an instruction prefetching unit for acquiring instructions to be executed and sending them to an execution unit; an execution unit for acquiring a set interval time corresponding to the instruction to be executed and sending it to a comparison unit, and executing the instruction to be executed upon receiving a start execution signal; an interval time counting unit for counting pulses based on a time reference and acquiring the current interval time count value and sending it to the comparison unit; and a comparison unit for generating a start execution signal and sending it to the execution unit when it detects that the set interval time is equal to the current interval time count value. The technical solution of this embodiment, by employing an interval time counting unit, can achieve timed execution of instructions, thereby improving the timing accuracy and real-time performance of instruction execution.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a sub-real-time processor, a real-time processor, and a system-on-a-chip. Background Technology

[0002] In addition to processing the acquired data signals, system-on-a-chip (SoC) devices typically need to control peripheral devices. As the requirements for low latency become increasingly stringent, enabling SoC devices to have precise control over peripheral devices is gradually becoming one of the key research directions in the field of chip design.

[0003] Currently, existing digital signal processors (DSPs) and general-purpose processors are commonly used for real-time control of peripheral devices. However, due to their primarily computation-oriented pipelined design, instruction fetching and delivery require several clock cycles, and the processing time for interrupt responses from peripherals or on-chip modules is also relatively long. Furthermore, because they mainly control on-chip modules and peripherals through an on-chip complex bus, and the timers used for control are typically connected to the chip bus, which is often occupied by multiple modules, the accuracy of the acquired timing is low. Therefore, using DSPs or general-purpose processors to control peripheral devices results in low timing accuracy and poor real-time performance. Summary of the Invention

[0004] This invention provides a sub-real-time processor, a real-time processor, and a system-on-a-chip, which can achieve on-time startup, timed execution of instructions, improve the timing accuracy and real-time performance of instruction execution, and improve the timing accuracy of on-chip module control.

[0005] According to one aspect of the present invention, a sub-real-time processor is provided, comprising a control unit, an instruction prefetch unit, an interval time counting unit, a comparison unit, and an execution unit. The instruction prefetch unit is communicatively connected to the execution unit and the control unit, respectively. The interval time counting unit is communicatively connected to the execution unit through the comparison unit, and the execution unit is communicatively connected to the control unit.

[0006] The control unit is configured to enter an idle state when a power-on reset or module software reset is detected; when a sub-real-time processor is enabled, it transitions from the idle state to the instruction fetch state and generates an instruction fetch control signal to be sent to the instruction prefetch unit; when an instruction fetch completion signal is detected from the instruction prefetch unit, it transitions from the instruction fetch state to the execution state and generates an instruction execution control signal to be sent to the execution unit; when an execution completion signal is detected from the execution unit, it transitions from the execution state to the instruction fetch state; and when an instruction fetch state or the execution state detects that the sub-real-time processor in the register is not enabled, it transitions back to the idle state.

[0007] The instruction prefetching unit is used to acquire the instruction to be executed when it receives the instruction fetching control signal sent by the control unit, and send the instruction to be executed to the execution unit;

[0008] The execution unit is configured to, upon receiving an instruction execution control signal sent by the control unit, acquire a set interval time corresponding to the instruction to be executed and send it to the comparison unit; upon receiving a start execution signal corresponding to the instruction to be executed sent by the comparison unit, execute the instruction to be executed; and after the instruction to be executed is completed, generate an execution completion signal and send it to the control unit.

[0009] The interval time counting unit is used to count time intervals based on a time reference signal to obtain the current interval time count value, and send the current interval time count value to the comparison unit;

[0010] The comparison unit is used to compare the set interval time corresponding to the instruction to be executed sent by the execution unit with the current interval time count value sent by the interval time counting unit. If the set interval time is detected to be equal to the current interval time count value, a start execution signal corresponding to the instruction to be executed is generated and sent to the execution unit.

[0011] According to another aspect of the present invention, a real-time processor is provided, including at least one sub-real-time processor as described in any embodiment of the present invention, a bus slave interface, and a register, wherein the bus slave interface is communicatively connected to each of the sub-real-time processors through the register.

[0012] The bus slave interface is used to receive register configuration instructions and forward the register configuration instructions to the register;

[0013] The register is used to set the register state according to the register configuration instruction in order to obtain the current register state;

[0014] Each of the sub-real-time processors is used to process instructions based on the current register state of the register.

[0015] According to another aspect of the present invention, a system-on-a-chip is provided, including the real-time processor described in any embodiment of the present invention.

[0016] The technical solution of this invention involves a control unit generating corresponding control signals in different states and sending them to other units to control these units to read and execute instructions. An instruction prefetching unit acquires the instruction to be executed. Then, an execution unit acquires the set interval time corresponding to the instruction to be executed and an interval time counting unit acquires the current interval time count value. Further, a comparison unit generates a start execution signal corresponding to the instruction to be executed when it detects that the set interval time is equal to the current interval time count value. Finally, the execution unit executes the instruction to be executed according to the start execution signal. By employing an interval time counting unit, accurate acquisition of timing can be achieved, enabling timed execution of instructions, thereby improving the timing accuracy and real-time performance of instruction execution and enhancing the timing accuracy of on-chip module control.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1A This is a schematic diagram of the structure of a sub-real-time processor according to Embodiment 1 of the present invention;

[0020] Figure 1B This is a schematic diagram of another sub-real-time processor provided according to Embodiment 1 of the present invention;

[0021] Figure 2A This is a schematic diagram of the structure of a real-time processor according to Embodiment 2 of the present invention;

[0022] Figure 2B This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0023] Figure 2CThis is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0024] Figure 2D This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0025] Figure 2E This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0026] Figure 2F This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0027] Figure 2G This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0028] Figure 2H This is a schematic diagram of another real-time processor provided according to Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of a system-on-a-chip according to Embodiment 3 of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Example 1

[0033] Figure 1AThe present invention provides a structural diagram of a sub-real-time processor 100, which may include a control unit 110, an instruction prefetching unit 120, an interval time counting unit 130, a comparison unit 140, and an execution unit 150. The instruction prefetching unit 120 is communicatively connected to the execution unit 150 and the control unit 110, respectively. The interval time counting unit 130 is communicatively connected to the execution unit 150 through the comparison unit 140. The execution unit 150 is communicatively connected to the control unit 110.

[0034] The control unit 110 is configured to enter an idle state when a power-on reset or module software reset is detected; when the sub-real-time processor 100 is enabled, it switches from the idle state to the instruction fetch state and generates an instruction fetch control signal to be sent to the instruction prefetch unit 120; when an instruction fetch completion signal is detected from the instruction prefetch unit 120, it switches from the instruction fetch state to the execution state and generates an instruction execution control signal to be sent to the execution unit 150; when an execution completion signal is detected from the execution unit 150, it switches from the execution state to the instruction fetch state; and when an instruction fetch state or the execution state detects that the sub-real-time processor in the register is not enabled, it switches back to the idle state.

[0035] In this embodiment, the control unit 110 is used to generate the entire state machine, including an idle state, an instruction fetch state, and an execution state. The control unit 110 can switch between these states. Specifically, during instruction execution: First, after a power-on reset or module software reset, the control unit 110 enters an idle state. Then, when the current sub-real-time processor 100 is enabled, the control unit 110 jumps from the idle state to the instruction fetch state. Afterward, if an instruction fetch completion signal is received from the instruction prefetch unit 120, it indicates that the fetching of the current instruction to be executed has been completed. At this time, the control unit 110 can jump from the instruction fetch state to the execution state. Furthermore, if an execution completion signal is detected from the execution unit 150, it indicates that the current instruction to be executed has been completed. The control unit 110 can then jump back from the execution state to the instruction fetch state to restart instruction fetching.

[0036] Afterwards, the control unit 110 can repeatedly switch between the instruction fetch state and the execution state until it detects that the sub-real-time processor configured in the register is not enabled, that is, the current sub-real-time processor 100 becomes disabled, and the control unit 110 jumps back to the idle state.

[0037] The sub-real-time processor 100 is enabled, indicating that it is activated and begins processing instructions to be executed. The instruction fetch control signal can be a signal generated by the control unit 110 to instruct the instruction prefetch unit 120 to begin fetching instructions; the instruction fetch completion signal can be a signal generated by the instruction prefetch unit 120 to indicate that the current instruction fetch has been completed. The instruction execution control signal can be a signal generated by the control unit 110 to instruct the execution unit 150 to begin executing the currently pending instruction; correspondingly, the execution completion signal can be a signal generated by the execution unit 150 to indicate that the currently pending instruction has been executed.

[0038] In this embodiment, the sub-real-time processor 100 can be enabled by configuring the corresponding bit in the enable register (e.g., RTEP_EN) of the central processing unit (CPU). Alternatively, the startup time register (e.g., RTEPx_STR_TIME) corresponding to the sub-real-time processor 100 can be configured to enable the sub-real-time processor 100 at fixed times via hardware logic; wherein the time can be based on a specified startup timer.

[0039] In this embodiment, multiple bits of TIMER_SEL can be set in the sub-real-time processor startup control register (e.g., RTEPx_STR_CTRL) to specify the startup timer to be used. Specifically, the value of the specified startup timer is obtained in real time and compared with the startup time register. When the two are equal, the sub-real-time processor 100 can be controlled to enter the enabled state, that is, the sub-real-time processor 100 is started.

[0040] In addition, the sub-real-time processor 100 can be periodically started. Specifically, a periodic interrupt trigger enable bit (e.g., CYC_TRG_EN) is set in the sub-real-time processor startup control register. When this bit is enabled (typically, a value of 1), the hardware logic controls the sub-real-time processor 100 to enter the enabled state when the periodic interrupt is valid. Optionally, a periodic interrupt selection multi-bit (e.g., CYC_TRG_SEL) can also be set in the sub-real-time processor startup control register to select one periodic interrupt from multiple periodic interrupts. The periodic interrupt can be generated by a specified startup timer period, and a startup timer can have multiple periodic interrupts.

[0041] The instruction prefetching unit 120 is used to acquire the instruction to be executed when it receives the instruction fetching control signal sent by the control unit 110, and send the instruction to be executed to the execution unit 150.

[0042] The instruction prefetch unit 120 can fetch the next instruction after executing one instruction, based on the instruction fetch control signal from the control unit 110. Since each instruction has an execution interval, the instruction prefetch unit 120 can fetch instructions according to the instruction execution interval. Optionally, the instruction prefetch unit 120 can read the instructions to be executed one by one according to the principle of instruction address increment, or it can read the corresponding instruction to be executed according to a specified instruction address.

[0043] In this embodiment, the sub-real-time processor 100 can process events in the form of event groups. An event group can include multiple instructions to be executed, and each instruction corresponds to a specific event operation. Specifically, after being enabled, the sub-real-time processor 100 can begin acquiring and executing instructions to be executed. When it acquires a de-enabled instruction, it changes to a de-enabled state, indicating that one event group has been processed.

[0044] Optionally, the event processing mode of the sub-real-time processor 100 may include single-event group mode and multi-event group mode. Specifically, for each sub-real-time processor 100, a corresponding multi-event group working mode enable register (e.g., RTEPx_MEVTG_ENA) can be preset. When it is determined that the multi-event group mode is not enabled according to the multi-event group working mode enable register, the sub-real-time processor 100 operates in single-event group mode, that is, it processes only one event group. At this time, the instruction prefetch unit 120 can sequentially read each instruction of the event group, and the execution unit 150 executes each instruction.

[0045] Furthermore, when the multi-event group mode is enabled based on the multi-event group operating mode enable register, the sub-real-time processor 100 can poll and process multiple event groups. During the processing of each event group, the last disable instruction can be used as the end condition for the current event group, but the disable operation will not be executed; that is, the sub-real-time processor 100 will remain in the enabled state. Finally, when the multi-event group mode is detected to have changed to disabled, after the processing of the last disable instruction of the current event group is completed, the sub-real-time processor 100 ends the polling processing of each event group, enters the single-event group mode, and changes to the disabled state.

[0046] In this embodiment, a corresponding set of event group configuration registers can be set for each event group. For example, these registers may include the RTEPx_MEVTGn_IRAM_STR_ADDR register, the RTEPx_MEVTGn_IRAM_STR_VALID register, the RTEPx_MEVTGn_IRAM_STR_MASK register, the RTEPx_MEVTGn_CANCEL register, and the RTEPx_MEVTGn_WORK_STAT register. The RTEPx_MEVTGn_IRAM_STR_ADDR register can be used to store the starting address of the instructions to be executed in the event group, where n can represent the index of the event group. For example, RTEPx_MEVTG1_IRAM_STR_VALID can represent the register corresponding to the first event group.

[0047] Specifically, when the RTEPx_MEVTGn_IRAM_STR_VALID register corresponding to the current event group is detected to be valid, and the RTEPx_MEVTGn_IRAM_STR_MASK register is unmasked, instruction fetching for the current event group begins. After instruction fetching begins, the RTEPx_MEVTGn_IRAM_STR_VALID register is cleared, and during the execution of the current event group, the RTEPx_MEVTGn_WORK_STAT register is set to 1, indicating that the current event group is being processed. Furthermore, during the execution of the current event group, the RTEPx_MEVTGn_CANCEL register needs to be monitored. If cancellation is found to be valid, after the current instruction is executed, the remaining instructions pending execution in the current event group are cancelled, and the system automatically polls the configuration register for the next event group.

[0048] Furthermore, if the processing of the current event group ends normally, the RTEPx_MEVTGn_WORK_STAT register is set to 0; if it ends due to software cancellation, the register is set to 2; if it ends due to an instruction processing exception, the register is set to 3; and if it is masked, the register is set to 4. Normal end refers to an event group fetch reaching a disabled instruction.

[0049] Secondly, if the RTEPx_MEVTGn_IRAM_STR_VALID register corresponding to the current event group is detected to be valid, and the RTEPx_MEVTGn_IRAM_STR_MASK register is masked, the current event group can be ignored and the process can jump directly to the next event group.

[0050] Optionally, when the multi-event group mode is enabled, an event group polling counter (e.g., rtepx_mevtg_cnt) can be set with a reset value of 0. Specifically, after the sub-real-time processor 100 powers on, it checks the event group configuration register corresponding to the first event group. When it detects that the value of the RTEPx_MEVTG1_IRAM_STR_VALID register is valid (e.g., 1), if the RTEPx_MEVTG1_IRAM_STR_MASK register is unmasked, then rtepx_mevtg_cnt is incremented by 1. At this time, the RTEPx_MEVTG1_WORK_STAT register is set to the working state, indicating that the sub-real-time processor 100 starts fetching instructions while processing the first event group. After finishing processing the first event group, it continues to check whether the value of the RTEPx_MEVTG2_IRAM_STR_VALID register is valid.

[0051] In another scenario, if after a reset, the value of the RTPx_MEVTG1_IRAM_STR_VALID register is detected as valid, but the RTPx_MEVTG1_IRAM_STR_MASK register is masked, then rtepx_mevtg_cnt is incremented by 1, and the RTPx_MEVTG1_WORK_STAT register is set to a masked state, and the sub-real-time processor 100 does not fetch instructions. Then, if the value of the RTPx_MEVTG2_IRAM_STR_VALID register is detected as 1, and the RTPx_MEVTG2_IRAM_STR_MASK register is not masked, then rtepx_mevtg_cnt is incremented by 1 to become 2, and the RTPx_MEVTG2_WORK_STAT register is set to an active state, indicating that the second event group is being processed.

[0052] Then, the sub-real-time processor 100 begins fetching instructions until the processing of the second event group is completed. Further, the above steps are repeated until all event groups have been processed. During the processing of the first event group, the event group polling counter is set to 1, and during the processing of the second event group, the event group polling counter is set to 2. Thus, the number of event groups processed can be recorded using the event group polling counter.

[0053] Optionally, an event group status register, such as RTEPx_STATUS.cur_mevtg_cnt_stat, can be set to store the status of the event group currently being processed by the sub-real-time processor 100. For example, if the first event group is currently being processed, then RTEPx_STATUS.cur_mevtg_cnt_stat = 1.

[0054] In this embodiment, by pre-configuring multiple event groups for a sub-real-time processor 100, the response time of the sub-real-time processor 100 to complete the interrupt can be reduced, instructions and data can be pre-configured, scheduling delay time can be reduced, thereby improving real-time performance, and software can dynamically cancel events or event groups that have not been executed.

[0055] The execution unit 150 is configured to, upon receiving an instruction execution control signal sent by the control unit 110, acquire a set interval time corresponding to the instruction to be executed and send it to the comparison unit 140; upon receiving a start execution signal corresponding to the instruction to be executed sent by the comparison unit 140, execute the instruction to be executed; and after the instruction to be executed is completed, generate an execution completion signal and send it to the control unit 110.

[0056] The set interval time can be a pre-set instruction execution interval in the instruction. For example, a time interval of n indicates an interval of n clock cycles, where a clock cycle refers to the period of a selected timer. For an instruction to be executed with a set interval time, its execution time is after instruction parsing and waiting for the set interval time before execution. Optionally, if the corresponding set interval time is not obtained after parsing the instruction to be executed, the instruction to be executed can be processed directly without additional waiting time.

[0057] The interval time counting unit 130 is used to count time intervals based on a time reference signal to obtain the current interval time count value and send the current interval time count value to the comparison unit 140; wherein, the time reference signal is the counting unit of the interval time counting unit 130, and can be the reference time pulse of the timer bound to the current sub-real-time processor 100.

[0058] Optionally, the interval counting unit 130 may include two operating modes: an absolute timing mode and a relative timing mode. In the absolute timing mode, after an instruction with a set interval is executed, the interval counting unit 130 is not reset to zero and continues counting continuously. In the relative timing mode, after an instruction with a set interval is executed, the interval counting unit 130 is reset to zero. In the absolute timing mode, the set interval can be the instruction execution time point; while in the relative timing mode, the set interval can be the instruction execution interval itself.

[0059] The control unit 110 can generate a corresponding control signal and send it to the interval time counting unit 130 to control the interval time counting unit 130 to count the interval time or reset the count.

[0060] In this embodiment, the operating mode of the interval time counting unit 130 can be dynamically set via a no-operation instruction, or it can be set via a static register, such as the interval time counting unit operating mode bit (e.g., DETA_CNT_MODE) in the startup control register of the sub-real-time processor x (e.g., RTEPx_STR_CTRL). The CPU can change the operating mode of the interval time counting unit 130 by setting this bit.

[0061] The comparison unit 140 is used to compare the set interval time corresponding to the instruction to be executed sent by the execution unit 150 with the current interval time count value sent by the interval time counting unit 130. If the set interval time is detected to be equal to the current interval time count value, a start execution signal corresponding to the instruction to be executed is generated and sent to the execution unit 150.

[0062] Specifically, when the instruction to be executed has a corresponding set interval time, the comparison unit 140 is used to compare the set interval time with the current interval time count value to determine whether the set interval time has been reached. Then, when it is detected that the current interval time count value is equal to the set interval time, a start execution signal corresponding to the instruction to be executed is generated and sent to the execution unit 150 so that the execution unit 150 can start executing the instruction to be executed.

[0063] In this embodiment, by using the interval time counting unit 130 to obtain the timing time, the delay of the obtained timing time can be reduced, the accuracy of the obtained timing time can be improved, thereby enabling the timing execution of the instruction to be executed, and improving the real-time performance and timing accuracy of the instruction execution.

[0064] Optional, such as Figure 1B As shown, the sub-real-time processor 100 may further include an address generation unit 160, an arbitration unit 170, and an instruction storage unit 180. The address generation unit 160 is communicatively connected to the execution unit 150, the arbitration unit 170, and the control unit 110, respectively. The instruction storage unit 180 is communicatively connected to the address generation unit 160 and the instruction prefetching unit 120 through the arbitration unit 170, respectively.

[0065] The execution unit 150 is further configured to, when it detects that the instruction type of the instruction to be executed sent by the instruction prefetching unit 120 is an address jump instruction, obtain the jump address corresponding to the instruction to be executed and send it to the address generation unit 160, and generate a jump control signal and send it to the address generation unit 160 and the instruction prefetching unit 120 respectively.

[0066] The jump address can be the address of the next instruction to be executed specified by the current address jump instruction; the jump control signal can be a signal generated by the execution unit 150 to indicate that an address jump is to be performed.

[0067] In this embodiment, when an address jump instruction is executed, it jumps to a set address to fetch the instruction. The data structure of the address jump instruction is shown in Table 1. For the jump address parameter, 0 represents the address of the first instruction in instruction storage unit 180, 1 represents the address of the second instruction in instruction storage unit 180, and so on, with 63 representing the address of the 64th instruction in instruction storage unit 180.

[0068] Table 1. Data Structure of Address Jump Instructions

[0069] 31 28 27 20 19 14 13 0 Address redirection Custom Redirect address none Interval time

[0070] The address jump instruction can include a jump address parameter. When the instruction to be executed is an address jump instruction, it means that the next instruction to be processed is the instruction corresponding to that jump address.

[0071] The address generation unit 160 is configured to, upon receiving an instruction storage unit loading completion signal sent by the arbitration unit 170, obtain the instruction fetch address based on the sequential prefetch address; upon receiving a jump address and jump control signal sent by the execution unit 150, obtain the instruction fetch address based on the jump address; and send the instruction fetch address to the arbitration unit 170. The sequential prefetch address can be a sequentially increasing fetch address; for example, if the current address of the instruction to be executed is i, then the next sequential prefetch address is i+1, and the initial prefetch address can be preset through a register.

[0072] In this embodiment, the arbitration unit 170 can generate an instruction storage unit loading completion signal according to the read / write completion timing of the instruction storage unit 180 and send it to the address generation unit 160 and the instruction prefetch unit 120 respectively.

[0073] Specifically, during instruction fetching, in a typical scenario, the address generation unit 160 generates a sequential prefetch address as the instruction fetch address and sends it to the arbitration unit 170; simultaneously, the instruction prefetch unit 120 generates an instruction prefetch request signal and sends it to the arbitration unit 170. At this time, the instruction prefetch request signal is merely an indication signal, informing the arbitration unit 170 that instruction fetching is currently required, while the specific instruction address is generated by the address generation unit 160. The instruction prefetch unit 120 can fetch the instructions to be executed one by one, with the address incrementing sequentially.

[0074] However, if the current instruction to be executed is an address jump instruction, the address generation unit 160 uses the jump address as the instruction fetch address instead of using a sequentially incrementing address. Therefore, after sending the instruction prefetch request signal, the instruction prefetch unit 120 can obtain the instruction to be executed corresponding to the jump address.

[0075] The instruction prefetching unit 120 is used to generate an instruction prefetching request signal and send it to the arbitration unit 170 when it receives the instruction fetching control signal sent by the control unit 110, the storage unit loading completion signal sent by the arbitration unit 170, and the jump control signal sent by the execution unit 150, and to receive the instruction to be executed fed back by the arbitration unit 170.

[0076] In this embodiment, when the instruction prefetch unit 120 receives the memory cell loading completion signal sent by the arbitration unit 170, it indicates that the instruction prefetch unit 120 has successfully acquired the current instruction to be executed; then, when it receives the jump control signal sent by the execution unit 150, it indicates that the address jump instruction has been executed; furthermore, when it receives the instruction fetch control signal sent by the control unit 110, the instruction prefetch unit 120 can generate an instruction prefetch request signal and send it to the arbitration unit 170 to request the acquisition of the next instruction to be executed.

[0077] The arbitration unit 170 is used to generate an instruction storage unit loading completion signal and send it to the address generation unit 160 and the instruction prefetch unit 120; when simultaneously receiving the instruction fetch address sent by the address generation unit 160, the instruction prefetch request signal sent by the instruction prefetch unit 120, and the instruction storage unit read / write request signal sent by the bus slave interface, it sequentially sends the instruction storage unit read / write request signal, the instruction fetch address, and the instruction prefetch request signal to the instruction storage unit 180; it sends the stored instruction corresponding to the instruction storage unit read / write request signal fed back by the instruction storage unit 180 to the bus slave interface for forwarding, and sends the stored instruction corresponding to the instruction fetch address fed back by the instruction storage unit to the instruction prefetch unit 120.

[0078] The instruction storage unit read / write request signal can be a request signal generated by the CPU to read or write instructions stored in the instruction storage unit 180. Typically, the instruction storage unit read / write request signal may include chip select content (used to indicate which instruction storage unit the request signal corresponds to), operation type (e.g., instruction read operation or instruction write operation), address, and write data.

[0079] In this embodiment, when the arbitration unit 170 simultaneously receives an instruction storage unit read / write request signal and an instruction prefetch request signal, the arbitration unit 170 arbitrates the priority of the two request signals and first sends the arbitrated instruction storage unit read / write request signal to the instruction storage unit 180, and then sends the instruction prefetch request signal and the instruction fetch address to the instruction storage unit 180. In this embodiment, the priority of the instruction storage unit read / write request signal can be higher than that of the instruction prefetch request signal.

[0080] Specifically, when the instruction storage unit read / write request signal corresponds to an instruction read operation, the arbitration unit 170 can receive the stored instruction corresponding to the instruction storage unit read / write request signal from the instruction storage unit 180, and forward the stored instruction to the bus slave interface. Furthermore, the arbitration unit 170 can receive the stored instruction corresponding to the instruction fetch address from the instruction storage unit 180, and forward the stored instruction to the instruction prefetch unit 120.

[0081] The instruction storage unit 180 is used to update the stored instructions according to the instruction storage unit read / write request signal, or to obtain the stored instructions corresponding to the instruction storage unit read / write request signal and send them to the arbitration unit 170; and to obtain the stored instructions corresponding to the instruction fetch address and send them to the arbitration unit 170.

[0082] Specifically, when the instruction storage unit read / write request signal corresponds to an instruction write operation, the instruction storage unit 180 can write the write instruction into the memory according to the address and write instruction in the instruction storage unit read / write request signal; or, when the instruction storage unit read / write request signal corresponds to an instruction read operation, the instruction storage unit 180 can read the stored instruction corresponding to the address and send the stored instruction to the arbitration unit 170.

[0083] In this embodiment, each sub-real-time processor 100 may have a dedicated instruction storage unit 180. In the instruction storage unit 180, each stored instruction corresponds to a storage address. When searching for a stored instruction, the storage address can be used as an index to find a matching stored instruction. Typically, the instruction storage unit 180 may be random access memory (RAM).

[0084] The technical solution of this invention involves a control unit generating corresponding control signals in different states and sending them to other units to control these units to read and execute instructions. An instruction prefetching unit acquires the instruction to be executed. Then, an execution unit acquires the set interval time corresponding to the instruction to be executed and an interval time counting unit acquires the current interval time count value. Further, a comparison unit generates a start execution signal corresponding to the instruction to be executed when it detects that the set interval time is equal to the current interval time count value. Finally, the execution unit executes the instruction to be executed according to the start execution signal. By employing an interval time counting unit, accurate acquisition of timing can be achieved, enabling timed execution of instructions, thereby improving the timing accuracy and real-time performance of instruction execution and enhancing the timing accuracy of on-chip module control.

[0085] Example 2

[0086] Figure 2A This invention provides a structural diagram of a real-time processor according to Embodiment 2. The real-time processor 200 may include at least one sub-real-time processor 100 as described in Embodiment 1 of this invention, a bus slave device interface 210, and a register 220. The bus slave device interface 210 can communicate with each sub-real-time processor 100 through the register 220.

[0087] The bus slave interface 210 is used to receive register configuration instructions and forward the register configuration instructions to the register 220; wherein, the bus slave interface 210 is used to receive register configuration from the CPU. The register configuration instructions can be CPU-generated instructions used to set the register state of the real-time processor 200.

[0088] In this embodiment, the real-time processor 200 can receive various configuration instructions from the CPU via the bus device interface 210, such as register configuration instructions and event group configuration instructions, to assist the CPU in controlling on-chip modules and peripherals. Therefore, the real-time processor 200 in this embodiment can serve as an auxiliary processor for the CPU, enabling the system-on-a-chip to have real-time control capabilities over peripheral devices.

[0089] Register 220 is used to set the register state according to the register configuration instructions to obtain the current register state. Register 220 may include the registers corresponding to the aforementioned pending event groups. In a specific example, when register 220 is the sub-real-time processor startup time register, the CPU can send a pre-set startup time to register 220 via the bus from device interface 210. Register 220 can then set the values ​​of the corresponding bits according to the received startup time. Thus, when the pre-set startup time is reached, register 220 can control the corresponding sub-real-time processor 100 to start on a timed basis.

[0090] In this embodiment, by setting different register states, the enabling and operating modes of the sub-real-time processor 100 can be controlled, and the event processing process can be recorded. Typically, for each sub-real-time processor 100, a corresponding status register can be set to indicate the address of the instruction currently being fetched, the address of the instruction currently waiting to be executed or being executed, whether the sub-real-time processor 100 is in an disabled state or a normal operating state, and the specific operating state of the sub-real-time processor 100 when it is currently operating normally.

[0091] The advantage of the above setup is that it can avoid the timing delay caused by bus transmission in the prior art, and can achieve precise startup of the sub-real-time processor 100. Furthermore, through the interval time counting unit 130 in the sub-real-time processor 100, it can achieve precise processing of the events to be processed.

[0092] Each of the sub-real-time processors 100 is used to process instructions based on the current register state of the registers 220. Specifically, the sub-real-time processor 100 can determine the current event group mode and the event groups to be processed based on the current register state of each register 220; in addition, it can also determine the processing flow of each event group based on the current register state.

[0093] The technical solution of this invention receives register configuration instructions from the device interface via a bus, and sets the register state according to the register configuration instructions to obtain the current register state; finally, each sub-real-time processor processes the instructions according to the current register state; by using registers and sub-real-time processors, precise startup of the sub-real-time processors can be achieved, and the timing accuracy of event processing can be improved, thereby improving the timing accuracy of controlling on-chip modules and peripherals.

[0094] Optional, such as Figure 2BAs shown, the real-time processor 200 may further include a first arbiter 230 and an instruction memory 240. The instruction memory 240 is communicatively connected to each sub-real-time processor 100 through the first arbiter 230. The instruction memory 240 may be a common instruction memory 240 for each sub-real-time processor 100.

[0095] Each of the sub-real-time processors 100 is further configured to generate an instruction prefetch request signal and send it to the first arbitrator, and to execute the instruction to be executed when the first arbitrator sends an instruction to be executed back to it.

[0096] The first arbiter 230 is configured to, when detecting that the instruction prefetch request signals sent by each of the sub-real-time processors 100 meet the first preset conflict detection condition, forward the instruction prefetch request signals sent by each of the sub-real-time processors 100 to the instruction memory 240 in descending order of priority according to the priority of each sub-real-time processor 100, and receive the instruction to be executed fed back by the instruction memory 240, and forward the instruction to be executed to the corresponding sub-real-time processor 100; the instruction memory 240 is configured to, upon receiving the instruction prefetch request signal forwarded by the first arbiter 230, obtain the instruction to be executed corresponding to the instruction prefetch request signal and send it to the first arbiter 230.

[0097] The first preset conflict detection condition can be pre-set condition information for determining whether there is a conflict between each instruction prefetch request signal. For example, it can be receiving multiple instruction prefetch request signals at the same time, or receiving multiple instruction prefetch request signals in a short period of time.

[0098] In this embodiment, each sub-real-time processor 100 can send an instruction prefetch request signal to the first arbitrator 230 through the instruction prefetch unit 120; in addition, it can also send an instruction fetch address to the first arbitration unit 130 through the address generation unit 160, and the instruction fetch address corresponds one-to-one with the instruction prefetch request signal.

[0099] In a specific example, regarding the instruction memory 240 shared by all sub-real-time processors 100, when multiple sub-real-time processors 100 access it simultaneously—that is, when multiple sub-real-time processors 100 simultaneously send instruction prefetch request signals to the first arbitrator 230—the first arbitrator 230 can determine the priority of each sub-real-time processor 100 and forward the instruction prefetch request signals of each sub-real-time processor 100 to the instruction memory 240 in descending order of priority. The priority of each sub-real-time processor 100 can be preset; for example, the sub-real-time processor 100 with a smaller sequence number has a higher priority. Typically, the priority of each real-time processor 100 can be set through register 220.

[0100] The advantage of the above setup is that multiple sub-real-time processors 100 can work in parallel, and by configuring an arbitrator, conflicts between multiple sub-real-time processors 100 can be handled according to priority, which can be applied to complex application scenarios.

[0101] Optional, such as Figure 2C As shown, the bus slave interface 210 can also be connected to the instruction memory 240 through the first arbiter 230; the bus slave interface 210 is also used to acquire the instruction memory read / write request signal, forward the instruction memory read / write request signal to the first arbiter 230, and externally forward the stored instruction corresponding to the instruction memory read / write request signal forwarded by the first arbiter 230.

[0102] The first arbiter 230 is further configured to receive the instruction memory read / write request signal forwarded by the bus slave interface 210, and after forwarding the currently to-be-executed instruction to the corresponding sub-real-time processor 100, forward the instruction memory read / write request signal to the instruction memory 240, and forward the stored instruction corresponding to the instruction memory read / write request signal fed back by the instruction memory 240 to the bus slave interface 210; the instruction memory 240 is further configured to update the stored instruction according to the instruction memory read / write request signal, or obtain the stored instruction corresponding to the instruction memory read / write request signal and send it to the first arbiter 230.

[0103] The instruction memory read / write request signal can be a request signal for reading an instruction already stored in the instruction memory 240 or for writing a new instruction.

[0104] In a specific example, while the sub-real-time processor 100 begins to fetch and execute instructions one by one, the CPU can access the instruction memory 240 through the bus slave interface 210 and the first arbitrator 230 during the intervals when the sub-real-time processor 100 accesses the instruction memory 240, in order to read or rewrite the stored instructions, thereby realizing dynamic modification of the configured instructions. When the CPU performs continuous access to the instruction memory 240, that is, when the first arbitrator 230 continuously acquires multiple instruction memory read / write request signals, the instruction memory read / write request signal has a higher priority than the instruction prefetch request signal.

[0105] Therefore, after forwarding the pending instructions requested by the current sub-real-time processor 100 to the current sub-real-time processor 100, the first arbitrator 230 can sequentially send each instruction memory read / write request signal to the instruction memory 240 according to the reception time, and cache the instruction prefetch request signals sent by other sub-real-time processors 100. When the CPU finishes its continuous access to the instruction memory 240, the first arbitrator 230 can send the cached instruction prefetch request signals from each sub-real-time processor 100 to the instruction memory 240.

[0106] Optional, such as Figure 2D As shown, the real-time processor 200 may further include a second arbitrator 250, a peripheral configuration interface 260, and a general-purpose output interface 270. The peripheral configuration interface 260 and the general-purpose output interface 270 are respectively connected to each sub-real-time processor 100 through the second arbitrator 250. Each sub-real-time processor 100 is also used to execute general-purpose output operation instructions to generate a general-purpose output signal and send the general-purpose output signal to the second arbitrator 250; and to execute peripheral interface operation instructions to generate a peripheral data output control signal and send the peripheral data output control signal to the second arbitrator 250.

[0107] The data structure of the general output operation instruction is shown in Table 2. The general output operation instruction can be 32-bit data and can be used to set the level of the output signal. Specifically, when the mode selection bit is 0, it indicates that the general output (GPO) operation is in single-pin setting mode, supporting a maximum of 128 general outputs. These 128 general outputs can be divided into 8 groups of 16, with one output pin set at a time. After setting the output, the update can be in two modes: immediate update (corresponding value 0), where the corresponding output pin will be updated to the set value immediately after the instruction is executed; and waiting for update (corresponding value 1), where the output pin will only be updated to the set value after the update operation instruction is executed. This update mode is mainly used for assigning values ​​to multiple outputs simultaneously.

[0108] Table 2 Data Structure of General Output Operation Instructions

[0109]

[0110] Furthermore, when the mode selection bit is set to 1, it indicates that the GPO operation is in multi-pin setting mode, which supports setting the level of a maximum of 8 GPO pins simultaneously. In this mode, a maximum of 64 general-purpose outputs can be supported, i.e., 8 pins per group, for a maximum of 8 groups. The meaning of a group in multi-pin setting mode differs from that in single-pin setting mode. In single-pin setting mode, each group contains 16 GPO pins, while in multi-pin setting mode, each group contains only 8 GPO pins. The group selection relationship between these two modes is: group number in single-pin setting mode = group number in multi-pin setting mode / 2. For example, group 0 and group 1 in multi-pin setting mode correspond to the lower 8 bits and higher 8 bits of group 0 in single-pin setting mode, respectively.

[0111] Furthermore, in multi-pin configuration mode, if only the output level of a few GPO pins needs to be set simultaneously, the unnecessary GPOs can be masked by setting the RTEP_GPO_MASKx register. Optionally, the sub-real-time processor general-purpose output configuration register x (e.g., RTEP_GPOx) can also be set to configure the function corresponding to each general-purpose output signal, where x represents the group number of the single-pin configuration mode.

[0112] The second arbitrator 250 is used to, when it is detected that the general output signals sent by each sub-real-time processor 100 meet the second preset conflict detection condition, filter out the target general output signal with the highest priority from the general output signals and send the target general output signal to the general output interface 270; and when it is detected that the peripheral data output control signals sent by each sub-real-time processor 100 meet the third preset conflict detection condition, send each peripheral data output control signal to the peripheral configuration interface 260 in order of priority from high to low according to the priority of each sub-real-time processor 100.

[0113] The general-purpose output interface 270 is used to receive the target general-purpose output signal forwarded by the second arbitrator 250 and output the target general-purpose output signal; the peripheral configuration interface 260 is used to receive the peripheral data output control signal forwarded by the second arbitrator 250 and output the peripheral data output control signal.

[0114] The second preset conflict detection condition can be pre-set condition information used to determine whether there is a conflict among multiple general output signals. The third preset conflict detection condition can be pre-set condition information used to determine whether there is a conflict among multiple peripheral data output control signals.

[0115] In this embodiment, each sub-real-time processor 100 can set the GPO level by executing the GPO instruction to generate a general output signal; alternatively, the GPO level can also be set immediately by setting the RTEP_GPOx register. If multiple different methods are used to set the same GPO pin at the same time, a GPO conflict interrupt will occur and can be recorded in the interrupt status register. When a conflict interrupt occurs, the second arbitrator 250 can prioritize each setting request, and only the highest priority method will take effect. Typically, the register method has the highest priority, followed by sub-real-time processor 0, and the lowest priority is given to sub-real-time processor N.

[0116] The peripheral interface operation instructions are used to periodically send data from the internal memory of the on-chip peripheral interface controller, such as SPI (Serial Peripheral Interface), to configure other chips connected to the chip containing the real-time processor. In this embodiment, the data structure of the peripheral interface operation instructions can be as shown in Table 3.

[0117] Table 3 Data Structure of Peripheral Interface Operation Commands

[0118]

[0119] Peripheral interface operation commands can be used for both SPI and RFFE (Radio Frequency Front-End) operations. For SPI operations, regarding the data transmission start address parameter, 0 indicates the first 32-bit SPI data in internal memory, 1 indicates the second 32-bit SPI data, 2 indicates the third 32-bit SPI data, and so on. Regarding the data transmission quantity parameter, 0 indicates no data transmission, 1 indicates transmission of 1 data bit, 2 indicates transmission of 2 data bits, and so on. Regarding the SPI controller selection parameter, 0 indicates selection of the SPI0 controller, and 1 indicates selection of the SPI1 controller. It should be noted that SPI commands support a maximum transmission of 15 data bits; if more data needs to be transmitted, multiple SPI commands can be used.

[0120] Secondly, when the peripheral interface operation instruction is used for RFFE operation, for the RFFE command frame start address parameter, 0 indicates the first 32-bit SPI data in the internal memory, 1 indicates the second 32-bit SPI data in the internal memory, 2 indicates the third 32-bit SPI data in the internal memory, and so on; the data transmission quantity parameter is used to indicate the number of RFFE operation sequences, 0 indicates the transmission of 1 sequence, 1 indicates the transmission of 2 sequences, and so on.

[0121] In this embodiment, peripheral interface transmission can be initiated via either register mode or peripheral interface operation instructions from the sub-real-time processor 100. If these modes are initiated simultaneously, a peripheral interface operation conflict interruption will occur. When this conflict interruption occurs, the second arbitrator 250 can execute peripheral data output control signal transmission sequentially in the order of register mode having the highest priority, followed by sub-real-time processor 0, and then sub-real-time processor N having the lowest priority.

[0122] It should be noted that for a given sub-real-time processor 100, if three peripheral interface operation instructions are written consecutively, and the peripheral data output control signal transmission initiated by the first instruction has not yet been completed when the second instruction is executed, the second instruction will enter a waiting state. If the third instruction arrives during the waiting period of the second instruction, a peripheral interface operation conflict interruption will occur. Once this peripheral interface operation conflict interruption occurs, the third instruction will never be able to execute. Therefore, to avoid such conflicts, the set interval time in the peripheral interface operation instructions should be greater than the time required for the peripheral data output control signal transmission.

[0123] In this embodiment, the sub-real-time processor 100 can improve the timing accuracy of peripheral control by executing peripheral interface operation instructions through the peripheral configuration interface 260 on the precision timing control chip. Furthermore, the sub-real-time processor 100 can improve the timing accuracy of control over the chip's general-purpose output pins by executing general-purpose output operation instructions through the general-purpose output interface 270 on the precision timing control chip's general-purpose input / output module.

[0124] Optional, such as Figure 2E As shown, the real-time processor 200 may further include at least one timer interface 280, each timer interface 280 being communicatively connected to each sub-real-time processor 100; each timer interface 280 is used to acquire timing pulses and send the timing pulses to each sub-real-time processor 100; each sub-real-time processor 100 is also used to receive the timing pulses sent by each timer interface 280 and perform instruction processing according to each timing pulse.

[0125] Each timer interface 280 can be bound to one or more timers. Each timer can send its own timing pulse to the corresponding sub-real-time processor 100 through the bound timer interface 280 for the start-up and snapshot instructions of the sub-real-time processor 100. When a timer interface 280 is bound to multiple timers, if the timer interface 280 receives timing pulses from multiple timers simultaneously, it can send each timing pulse to the corresponding sub-real-time processor 100 in sequence according to the priority of each timer.

[0126] Specifically, the sub-real-time processor 100 can select the timing pulse of the timer used during event execution and use the acquired timing pulse for the interval time counting unit 130. In addition, the timer can send multiple configured periodic interrupt signals to the real-time processor 200 so that the real-time processor 200 can start each sub-real-time processor 100 in periodic interrupt trigger mode.

[0127] In this embodiment, the timer interface 280 and timer bound to the sub-real-time processor 100 during operation can be configured by setting register 220. For example, register RTEPx_STR_CTRL.TM_PULSE_SEL can be set to configure the current timer interface 280 and timer for the sub-real-time processor 100.

[0128] It is worth noting that when the sub-real-time processor 100 operates in multi-event group mode, different event groups can be bound to different timer interfaces 280 and timers, meaning different event groups can use different timing intervals. Specifically, the sub-real-time processor 100 can read the time of another timer at the precise time point of the current timer to achieve hardware snapshots between the two timers.

[0129] Optionally, the timer interface 280 can also communicate with each sub-real-time processor 100 via the second arbitrator 250. The timer interface 280 can also be used to acquire the timing pulses of each timer and send each timing pulse to the second arbitrator 250; the second arbitrator 250 can also be used to acquire the sub-real-time processor 100 corresponding to each timing pulse when multiple timing pulses are received simultaneously, and send each timing pulse to the corresponding sub-real-time processor 100 in descending order of priority according to the priority of each sub-real-time processor 100.

[0130] The advantages of the above configuration are that it can reduce the latency of general-purpose processors accessing timers via the bus in the prior art, enable the sub-real-time processor 100 to start at a precise time based on a certain timer, be applicable to complex application scenarios where multiple modes coexist, and allow multiple sub-real-time processors 100 to work simultaneously according to different timers, thus meeting the real-time control requirements under different modes.

[0131] Optional, such as Figure 2FAs shown, the real-time processor 200 may further include an on-chip module interrupt interface 290, a general-purpose processor interrupt interface 2100, and an on-chip module trigger interface 2110. The on-chip module interrupt interface 290 is communicatively connected to each sub-real-time processor 100, and the general-purpose processor interrupt interface 2100 and the on-chip module trigger interface 2110 are communicatively connected to each sub-real-time processor 100 through a second arbitrator 250. Each sub-real-time processor 100 is also used to execute trigger output operation instructions to generate trigger output pulse signals and send the trigger output pulse signals to the second arbitrator 250; execute interrupt operation instructions to generate interrupt signals and send the interrupt signals to the second arbitrator 250; and receive interrupt control signals sent by the on-chip module interrupt interface and execute the stored instructions in the instruction memory 240 corresponding to the interrupt control signals.

[0132] The second arbitrator 250 is also used to send each trigger output pulse signal to the on-chip module trigger interface 2110 in descending order of priority according to the priority of each sub-real-time processor 100 when trigger output pulse signals are received simultaneously from each sub-real-time processor 100; and to send each interrupt signal to the general processor interrupt interface 2100 in descending order of priority according to the priority of each sub-real-time processor 100 when interrupt signals are received simultaneously from each sub-real-time processor 100.

[0133] The on-chip module trigger interface 2110 is used to forward the trigger output pulse signal sent by the second arbitrator 250 to the corresponding on-chip module; the general-purpose processor interrupt interface 2100 is used to forward the interrupt signal sent by the second arbitrator 250 to the corresponding general-purpose processor; the on-chip module interrupt interface 290 is used to receive the interrupt control signal from the on-chip module and forward the interrupt control signal to the corresponding sub-real-time processor 100.

[0134] In this embodiment, when the sub-real-time processor 100 outputs a trigger output pulse signal and an interrupt signal, it can first send the signal to the arbitrator 250. If the arbitrator 250 receives only one trigger output pulse signal or interrupt signal at the same time, it can directly forward the current signal to the corresponding interface, which will then send it to the corresponding on-chip module or general-purpose processor. However, if it receives trigger output pulse signals from multiple sub-real-time processors 100 at the same time, it can arbitrate the signals and send them to the on-chip module trigger interface 2110 in sequence according to the priority of each sub-real-time processor 100. Similarly, if multiple interrupt signals are received at the same time, they can also be sent to the general-purpose processor interrupt interface 2100 in sequence according to the priority of each sub-real-time processor 100.

[0135] Secondly, when the on-chip module interrupt interface 290 receives multiple interrupt control signals from the on-chip module at the same time, the on-chip module interrupt interface 290 can obtain the sub-real-time processor 100 corresponding to each interrupt control signal, and send each interrupt control signal to the corresponding sub-real-time processor 100 in sequence according to the priority of each sub-real-time processor 100.

[0136] Optionally, the on-chip module interrupt interface 290 can also communicate with each sub-real-time processor 100 through the second arbitrator 250. In this case, the on-chip module interrupt interface 290 can directly send the received interrupt control signals to the second arbitrator 250, which will arbitrate the multiple interrupt control signals received at the same time and send them to the corresponding sub-real-time processor 100.

[0137] The trigger output operation instruction is used to generate an output pulse signal to produce a pulse of one beat. It supports a maximum of 256 trigger outputs, which can be divided into 16 groups of 16, with one output set each time. In this embodiment, the trigger output operation instruction is executed by the sub-real-time processor 100, which can generate multiple trigger output pulse signals and send them to different on-chip modules, enabling control of functions such as start, stop, and reset of each on-chip module.

[0138] The data structure for triggering the output operation instruction is shown in Table 4. There are two modes for updating the output after setting it: immediate update, where an output pulse signal is emitted immediately after the instruction is executed; and waiting update, where an output pulse signal is emitted only after the update operation instruction is executed. This update mode is mainly used when multiple output pulse signals are emitted simultaneously. The output pulse signals are mainly used to control the on-chip module's opening, closing, reset, clearing, or other triggering functions. The function corresponding to each output pulse signal can also be set through register 220 (e.g., RETP_TRGx).

[0139] Table 4 Data Structure for Triggering Output Operation Commands

[0140]

[0141] The data structure for the update operation instruction can be shown in Table 5. After executing this instruction, the signals that were previously waiting for updates after executing the general output operation instruction and the triggered output operation instruction will be updated immediately.

[0142] Table 5 Data Structure of Update Operation Instructions

[0143] 31 28 27 14 13 0 Update operation Custom none Interval time

[0144] In this embodiment, the sub-real-time processor 100 can control the working state of the on-chip module at precise time through the on-chip module trigger interface 2110 by executing a trigger output operation instruction, such as starting the module, thereby improving the timing accuracy of the control of the on-chip module.

[0145] In addition, interrupt operation instructions are used to periodically generate interrupt signals and send them to the corresponding on-chip general-purpose processor. The interrupt source can be recorded in the interrupt status register as any one of the 32 processor interrupts. The data structure of the interrupt operation instructions can be shown in Table 6. For the interrupt selection parameter, 0 indicates RTEP_INT0 (the first processor interrupt), 1 indicates RTEP_INT1 (the second processor interrupt), and so on, with 31 indicating RTEP_INT31 (the 32nd processor interrupt).

[0146] Table 6 Data Structure of Interrupt Operation Instructions

[0147] 31 28 27 23 22 14 13 0 Interruption 0x5 Interruption Selection none Interval time

[0148] The interrupt control signal may include the start and end addresses of the interrupt routine. In this embodiment, when the sub-real-time processor 100 receives an interrupt control signal from the on-chip module through the on-chip module interrupt interface 290, it can set a set of registers 220 for each on-chip module interrupt. For example, it may include a module interrupt handling enable register RTEP_RCV_INTi_EN, a sub-processor number register RTEP_RCV_INTi_SUBEP_ID corresponding to the module interrupt, and a sub-processor fetch register RTEP_RCV_INTi_SUBEP_STR_ADDR (including the start and end addresses of the instructions) corresponding to the module interrupt. When processing the interrupt event group of the on-chip module, the sub-real-time processor 100 can sequentially fetch the instructions of the interrupt event group from the instruction start address and execute them. In addition, the sub-real-time processor 100 can also set the interrupt mode enable register RTEPx_RCV_INT_ENA. When this bit is enabled, the sub-real-time processor 100 is only used to process the interrupt event group of the corresponding on-chip module; when this bit is disabled, it processes a single event group or multiple event groups pre-configured by the software.

[0149] Optional, such as Figure 2G As shown, the real-time processor 200 may also include a data memory 2120, which is communicatively connected to each of the sub-real-time processors 100 via a first arbitrator 230.

[0150] Each sub-real-time processor 100 is further configured to generate a data operation request signal and send it to the first arbitrator 230; the first arbitrator 230 is further configured to, when simultaneously receiving the data operation request signals sent by each sub-real-time processor 100, forward each data operation request signal to the data memory 2120 in descending order of priority according to the priority of each sub-real-time processor 100; the data memory 2120 is configured to receive the data operation request signals forwarded by the first arbitrator 230 and perform corresponding data operations on the stored data according to the data operation request signals.

[0151] In this embodiment, each sub-real-time processor 100 can perform read and write operations on the general-purpose data memory 2120 through data operation request signals. Specifically, each sub-real-time processor 100 first generates a data operation request signal and sends it to the first arbitrator 230. When the first arbitrator 230 receives data operation requests from multiple sub-real-time processors 100 simultaneously, it can forward each data operation request signal to the data memory 2120 in descending order of priority according to the priority of each sub-real-time processor 100.

[0152] In a specific example, the sub-real-time processor 100 can execute data assignment operation instructions to perform write operations on the data memory 2120, which can write 16 bits of data at a time. These data assignment operation instructions can include low-order data assignment instructions and high-order data assignment instructions. The data structure for the low-order data assignment instructions is shown in Table 7, and the data structure for the high-order data assignment instructions is shown in Table 8. For the storage data address parameter, 0 represents the address of the first data in the data memory 2120, 1 represents the address of the second data in the data memory 2120, and so on, with 1023 representing the address of the 1024th data in the data memory 2120.

[0153] Table 7 Data Structure of Low-Bit Assignment Instructions

[0154] 31 28 27 12 11 10 9 0 Data low-order assignment Custom data reserve Storage data address

[0155] Table 8. Data Structure of High-Bit Assignment Instructions

[0156] 31 28 27 12 11 10 9 0 High-order data assignment Custom data reserve Storage data address

[0157] In addition, the data memory 2120 can also be used to store the read / write operation addresses corresponding to register operation instructions, the condition addresses corresponding to conditional jump operation instructions, and the condition addresses corresponding to conditional setting operation instructions. In this embodiment, the data types stored in the data memory 2120 are not specifically limited.

[0158] Optional, such as Figure 2HAs shown, the real-time processor 200 also includes a bus master interface 2130, which is connected to each sub-real-time processor 100 through a second arbitrator 250.

[0159] Each sub-real-time processor 100 is also configured to execute register operation instructions to generate a register operation request signal and send the register operation request signal to the second arbitrator 250. The second arbitrator 250 is also configured to, when simultaneously receiving register operation request signals sent by each sub-real-time processor 100, forward the register operation request signals sent by each sub-real-time processor 100 to the bus master interface 2130 in descending order of priority, according to the priority of each sub-real-time processor 100. The bus master interface 2130 is configured to forward each register operation request signal forwarded by the second arbitrator 250 to the corresponding on-chip module register.

[0160] The data structure for register operation instructions can be shown in Table 9.

[0161] Table 9 Data Structure of Register Operation Instructions

[0162]

[0163] After executing the instruction, the sub-real-time processor 100 can generate a register operation request signal to perform read and write operations on the corresponding register 220 or other accessible registers 220. For the operation quantity parameter, 0 indicates 256 register operations, 1 indicates 1 register operation, and so on, with 255 indicating 255 register operations.

[0164] Furthermore, for the storage data address parameter, 0 represents the first data address of the data memory 2120 of the real-time processor 200, 1 represents the second data address of the data memory 2120, and so on, with 2047 representing the address of the 2048th data in the data memory 2120. Since the depth of the data memory 2120 is 2048, the address uses a maximum of 11 bits, i.e., bits 0 to 10. Secondly, since the storage data address is in WORD (32-bit) units, while the bus access data memory address is in BYTE units, the offset between the storage data address and the bus access data memory address is divided by 4.

[0165] For the bit selection parameter, when the condition is enabled, it is used to select one of 16 conditions, where 0 represents condition 0, corresponding to the setting array rtep_gpo

[112] , 1 represents condition 1, corresponding to rtep_gpo

[113] , and so on, with 15 representing condition 15, corresponding to rtep_gpo

[127] . When the interrupt is enabled, it is used to select one of 32 interrupts, where 0 represents selecting RTEP_INT0, 1 represents selecting RTEP_INT1, and so on, with 31 representing selecting RTEP_INT31. When both the condition and the interrupt are enabled, it means that the selected condition and the interrupt are the same number.

[0166] For interrupt enable, the interrupt here corresponds to one of the 32 interrupts in the interrupt operation instruction. If interrupt is enabled, after the register operation is completed, one of the 32 interrupts will be selected and issued. For condition enable, the condition here corresponds to one of the 16 conditions in the condition wait operation instruction. If condition is enabled, after the register operation is completed, one of the 16 conditions will be set to valid (i.e., set to 1).

[0167] In this embodiment, after the register operation instruction begins execution, if it is a write operation, the write operation register address can be read from a specified address, for example, j, in the data memory 2120, and register data can be read at j+1. Then, the register data is written to the specified register 220. If a write operation is performed on multiple registers 220, the write operation register address is read from the specified address j+2 in the data memory 2120, and register data is read at the specified address j+3. Then, the register data is written to the specified register 220. This process continues until the register operation instruction execution ends.

[0168] Secondly, for a read operation, the read operation register address can be read from the specified address in data memory 2120, and then the data in the specified register 220 can be read and written to the specified address j+1 in data memory 2120. If a read operation is performed on multiple registers 220, the read operation register address can be read from the specified address j+2 in data memory 2120, and then the data in the specified registers 220 can be read and written to the specified address j+3 in data memory 2120. This process continues until the register operation instruction is completed.

[0169] It should be noted that since multiple sub-real-time processors 100 share a single bus master interface 2130, if multiple sub-real-time processors 100 execute register operation instructions simultaneously, the second arbitrator 250 will simultaneously receive multiple register operation request signals from different sub-real-time processors 100, thus causing a register operation conflict. When this conflict occurs, the register operation request signals of each sub-real-time processor 100 can be sent to the bus master interface 2130 in the order of sub-real-time processor 0 having the highest priority and sub-real-time processor N having the lowest priority.

[0170] Furthermore, in another scenario, a sub-real-time processor 100 executes three register operation instructions consecutively. If the register operation initiated by the first instruction is not yet complete when the second instruction is executed, the second register operation instruction will be in a waiting state. If the third instruction arrives while the second instruction is waiting, a register operation conflict interruption will occur. When this conflict occurs, the third register operation instruction will never be executed. Therefore, when using register operation instructions, one or two instructions can be used to complete the operations on multiple registers 220 to avoid register operation conflict interruptions.

[0171] In this embodiment, the sub-real-time processor 100 can access the registers of each module on the chip at precise time through the bus master device interface 2130 by executing register operation commands, thereby improving the timing accuracy of controlling the on-chip modules.

[0172] Optionally, in this embodiment, the instructions that the sub-real-time processor 100 can execute may further include no-operation instructions, disable operation instructions, condition wait operation instructions, condition jump operation instructions, condition set operation instructions, and snap operation instructions.

[0173] The data structure of the no-operation instruction can be shown in Table 10. The no-operation instruction can include three working modes: no-operation mode, interval time counting unit working mode setting mode, and interval time counting unit clearing operation mode.

[0174] Table 10 Data Structure of No-Operation Instructions

[0175]

[0176] When the operating mode is set to no-operation mode, executing this instruction will not perform any operation. However, when the operating mode is set to interval time counter unit operating mode setting mode, executing this instruction can set the operating mode of interval time counter unit 130, including self-clearing mode and non-clearing mode. In addition, the operating mode of interval time counter unit 130 can also be set by the DELTA_CNT_MODE bit of the sub-real-time processor start control register (RTEPx_STR_CTRL).

[0177] When the interval time counter unit 130 operates in self-clearing mode, the interval time count value represents the time interval between the execution time of the current instruction and the execution time of the previous instruction. When the interval time counter unit 130 operates in non-clearing mode, the interval time count value represents the time interval between the execution time of the current instruction and the startup time of the sub-real-time processor 100. Furthermore, when the operating mode is selected as the interval time counter unit clearing operation mode, executing this instruction will clear the count value of the interval time counter unit 130 to zero.

[0178] The data structure for the disable operation instruction can be shown in Table 11. After executing the disable operation instruction, the current sub-real-time processor 100 enters the disable state.

[0179] Table 11 Data Structure for Disabling Operation Instructions

[0180] 31 28 27 14 13 0 Disable operation Custom none Interval time

[0181] The data structure for conditional wait operation instructions can be shown in Table 12. When the selected condition is 0, the sub-real-time processor 100 will remain in a waiting state, and the interval time counting unit 130 will stop counting. When the selected condition is 1, the sub-real-time processor 100 will continue to read the next instruction to be executed. Among them, for the condition selection parameter, 0 represents condition 0, corresponding to the setting array rtep_gpo

[112] , 1 represents condition 1, corresponding to rtep_gpo

[113] , and so on, 15 represents condition 15, corresponding to rtep_gpo

[127] . In this embodiment, a maximum of 16 conditions can be supported.

[0182] Table 12 Data Structure for Conditional Waiting Operation Instructions

[0183] 31 28 27 12 11 0 Conditional waiting Custom none Conditional selection

[0184] The data structure for conditional jump instructions is shown in Table 13. When the condition negation parameter is set to not negate, if the set condition is not 0, the program jumps to the set address in the instruction storage unit 180 of the current sub-real-time processor 100; if the set condition is 0, it continues to read the next instruction to be executed without jumping. Conversely, when the condition negation parameter is set to negate, if the set condition is 0, the program jumps to the set address in the instruction storage unit 180 of the current sub-real-time processor 100; if the set condition is not 0, it continues to read the next instruction to be executed without jumping.

[0185] Table 13 Data Structure of Conditional Jump Operation Instructions

[0186]

[0187] It is worth noting that the conditional jump operation instruction does not include an interval parameter, so this instruction can be executed immediately without waiting for an interval. Specifically, for the jump address parameter, 0 represents the address of the first instruction in instruction storage unit 180, 1 represents the address of the second instruction in instruction storage unit 180, and so on, with 63 representing the address of the 64th instruction in instruction storage unit 180.

[0188] The bit selection parameter is used to select a specific bit of the 32-bit data retrieved from the conditional address. For the conditional address parameter, 0 represents the address of the first data in the data memory 2120, 1 represents the address of the second data in the data memory 2120, and so on, with 1023 representing the address of the 1024th data in the data memory 2120.

[0189] The data structure for condition setting operation instructions is shown in Table 14. When this condition setting operation instruction is executed, the specified condition is operated on accordingly. It can be used to set the conditions used in condition jump operation instructions.

[0190] Table 14 Data Structure of Condition Setting Operation Instructions

[0191]

[0192] The bit selection parameter is used to select a specific bit of the 32-bit data that needs to be operated on for the storage condition address. For the storage condition address parameter, 0 represents the address of the first data in the data memory 2120, 1 represents the address of the second data in the data memory 2120, and so on, with 1023 representing the address of the 1024th data in the data memory 2120.

[0193] For mode selection parameters, setting and clearing require bit selection. Setting means setting the selected bit to 1, and clearing means clearing the selected bit to 0. Right shift means shifting the entire 32-bit data at the storage condition address to the right by 1 bit, filling the highest bit with 0. Left shift means shifting the entire 32-bit data at the storage condition address to the left by 1 bit, filling the lowest bit with 0. Decrement by 1 means decrementing the 32-bit data at the storage condition address by 1. Increment by 1 means incrementing the 32-bit data at the storage condition address by 1.

[0194] The data structure for the quick-capture operation instruction is shown in Table 15. After the sub-real-time processor 100 receives the quick-capture operation instruction, when the interval time counting unit 130 counts the set interval time, it latches the counter values ​​of each timer in the dedicated timer interface 280, including the counter values ​​of the timers bound to this sub-real-time processor 100, and stores them in the address of the data memory 2120 of this real-time processor 200. The storage starting address is the storage data address carried in the quick-capture operation instruction.

[0195] Table 15 Data Structure of Quick Shot Operation Command

[0196] 31 28 27 24 23 14 13 0 Quick shot operation Custom none Storage data address Interval time

[0197] In this embodiment, the instruction set definition can be as shown in Table 16.

[0198] Table 16 Instruction Set Definitions

[0199]

[0200] In this embodiment, a no-operation instruction is designed for time-waiting; a disable operation instruction is designed for shutting down the on-chip real-time processor 100 at a precise time; a general output operation instruction is designed for driving the general output pins of the chip at a precise time; a trigger output operation instruction is designed for triggering a certain behavior of the on-chip module at a precise time, such as turning it on or off; an update operation instruction is designed for simultaneously updating the signals used for waiting for update in the general output operation instruction and the trigger output operation instruction preceding this instruction; an interrupt operation instruction is designed for generating an interrupt for the on-chip general-purpose processor at a precise time; a peripheral interface operation instruction is designed for transmitting configuration commands and data to the hardware interface in real time; an address jump instruction is designed for jumping to a certain address of the instruction memory 240; and a condition wait operation is designed for... The system includes the following instructions: a general output signal driven by a general output operation instruction, used as a condition to control the real-time processor 200 to wait; a register operation instruction for accessing on-chip modules; a low-order data assignment instruction and a high-order data assignment instruction for writing data to the high and low bits of an address in the data memory 2120 of the real-time processor 200; a conditional jump operation instruction, where the condition is a bit of data at a certain address in the data memory 2120, and a jump to a certain address in the instruction memory 240 when the condition is met; a condition setting operation instruction for setting the condition data in the conditional jump operation instruction; and a snap operation instruction for reading the time of the target timer at a certain time point of the timer corresponding to the sub-real-time processor 100 and storing it in the data memory 2120. By executing the above instructions, the real-time processor 200 can achieve precise control of the on-chip modules.

[0201] Example 3

[0202] Figure 3 This invention provides a structural diagram of a system-on-a-chip (SoC) according to Embodiment 3. The SoC 300 may include the real-time processor 200 described in Embodiment 2. The number of real-time processors 200 may be one or more.

[0203] The technical solution of this invention employs a real-time processor 200 as a coprocessor or dedicated controller for the general-purpose processor of the system-on-a-chip 300 to handle on-chip or off-chip control tasks with high real-time and high precision requirements. This reduces the burden on the general-purpose processor, improves the timing accuracy of control, and enhances the programmability of the system-on-a-chip.

[0204] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0205] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A sub-real-time processor, characterized in that, It includes a control unit, an instruction prefetching unit, an interval time counting unit, a comparison unit, and an execution unit. The instruction prefetching unit is communicatively connected to both the execution unit and the control unit. The interval time counting unit is communicatively connected to the execution unit through the comparison unit. The execution unit is communicatively connected to the control unit. The control unit is configured to enter an idle state when a power-on reset or module software reset is detected; when a sub-real-time processor is enabled, it transitions from the idle state to the instruction fetch state and generates an instruction fetch control signal to be sent to the instruction prefetch unit; when an instruction fetch completion signal is detected from the instruction prefetch unit, it transitions from the instruction fetch state to the execution state and generates an instruction execution control signal to be sent to the execution unit; when an execution completion signal is detected from the execution unit, it transitions from the execution state to the instruction fetch state; and when an instruction fetch state or the execution state detects that the sub-real-time processor in the register is not enabled, it transitions back to the idle state. The instruction prefetching unit is used to acquire the instruction to be executed when it receives the instruction fetching control signal sent by the control unit, and send the instruction to be executed to the execution unit; The execution unit is configured to, upon receiving an instruction execution control signal sent by the control unit, acquire a set interval time corresponding to the instruction to be executed and send it to the comparison unit; upon receiving a start execution signal corresponding to the instruction to be executed sent by the comparison unit, execute the instruction to be executed; and after the instruction to be executed is completed, generate an execution completion signal and send it to the control unit. The interval time counting unit is used to count time intervals based on a time reference signal to obtain the current interval time count value, and send the current interval time count value to the comparison unit; The comparison unit is used to compare the set interval time corresponding to the instruction to be executed sent by the execution unit with the current interval time count value sent by the interval time counting unit. If the set interval time is detected to be equal to the current interval time count value, a start execution signal corresponding to the instruction to be executed is generated and sent to the execution unit.

2. The sub-real-time processor according to claim 1, characterized in that, It also includes an address generation unit, an arbitration unit, and an instruction storage unit. The address generation unit is communicatively connected to the execution unit, the arbitration unit, and the control unit, respectively. The instruction storage unit is communicatively connected to the address generation unit and the instruction prefetching unit through the arbitration unit, respectively. The execution unit is further configured to, when it detects that the instruction type of the instruction to be executed sent by the instruction prefetching unit is an address jump instruction, obtain the jump address corresponding to the instruction to be executed and send it to the address generation unit, and generate a jump control signal and send it to the address generation unit and the instruction prefetching unit respectively. The address generation unit is used to obtain the instruction fetch address according to the sequential prefetch address when it receives the instruction storage unit loading completion signal sent by the arbitration unit; and to obtain the instruction fetch address according to the jump address when it receives the jump address and jump control signal sent by the execution unit. Send the instruction fetch address to the arbitration unit; The instruction prefetching unit is configured to generate an instruction prefetching request signal and send it to the arbitration unit when it receives an instruction fetching control signal sent by the control unit, a storage unit loading completion signal sent by the arbitration unit, and a jump control signal sent by the execution unit, and to receive the instruction to be executed fed back by the arbitration unit. The arbitration unit is used to generate an instruction storage unit loading completion signal and send it to the address generation unit and the instruction prefetching unit; When simultaneously receiving the instruction fetch address sent by the address generation unit, the instruction prefetch request signal sent by the instruction prefetch unit, and the instruction storage unit read / write request signal sent by the bus slave interface, the instruction storage unit read / write request signal, the instruction fetch address, and the instruction prefetch request signal are sequentially sent to the instruction storage unit; the stored instruction corresponding to the instruction storage unit read / write request signal fed back by the instruction storage unit is sent to the bus slave interface for forwarding, and the stored instruction corresponding to the instruction fetch address fed back by the instruction storage unit is sent to the instruction prefetch unit; The instruction storage unit is configured to update the stored instructions according to the instruction storage unit read / write request signal, or obtain the stored instructions corresponding to the instruction storage unit read / write request signal and send them to the arbitration unit; and obtain the stored instructions corresponding to the instruction fetch address and send them to the arbitration unit.

3. A real-time processor, characterized in that, It includes at least one sub-real-time processor as described in claim 1 or 2, a bus slave interface, and a register, wherein the bus slave interface is communicatively connected to each of the sub-real-time processors through the registers; The bus slave interface is used to receive register configuration instructions and forward the register configuration instructions to the register; The register is used to set the register state according to the register configuration instruction in order to obtain the current register state; Each of the sub-real-time processors is used to process instructions based on the current register state of the register.

4. The real-time processor according to claim 3, characterized in that, It also includes a first arbiter and an instruction memory, wherein the instruction memory is communicatively connected to each of the sub-real-time processors through the first arbiter; Each of the sub-real-time processors is further configured to generate an instruction prefetch request signal and send it to the first arbitrator, and to execute the instruction to be executed when the first arbitrator sends back the instruction to be executed. The first arbitrator is configured to, when it detects that the instruction prefetch request signals sent by each of the sub-real-time processors meet the first preset conflict detection condition, forward the instruction prefetch request signals sent by each of the sub-real-time processors to the instruction memory in descending order of priority, and receive the instruction to be executed fed back by the instruction memory and forward the instruction to be executed to the corresponding sub-real-time processor. The instruction memory is used to retrieve the instruction to be executed corresponding to the instruction prefetch request signal and send it to the first arbitrator when it receives the instruction prefetch request signal forwarded by the first arbitrator.

5. The real-time processor according to claim 4, characterized in that, The bus slave interface is also communicatively connected to the instruction memory through the first arbiter; The bus slave interface is also used to acquire instruction memory read / write request signals, forward the instruction memory read / write request signals to the first arbitrator, and externally forward the stored instructions corresponding to the instruction memory read / write request signals forwarded by the first arbitrator. The first arbiter is further configured to receive the instruction memory read / write request signal forwarded by the bus slave device interface, and after forwarding the currently to-be-executed instruction to the corresponding sub-real-time processor, forward the instruction memory read / write request signal to the instruction memory, and forward the stored instruction corresponding to the instruction memory read / write request signal fed back by the instruction memory to the bus slave device interface. The instruction memory is further configured to update the stored instructions according to the instruction memory read / write request signal, or to obtain the stored instructions corresponding to the instruction memory read / write request signal and send them to the first arbitrator.

6. The real-time processor according to claim 3, characterized in that, It also includes a second arbitrator, a peripheral configuration interface, and a general output interface, wherein the peripheral configuration interface and the general output interface are respectively connected to each of the sub-real-time processors through the second arbitrator; Each of the sub-real-time processors is further configured to execute general output operation instructions to generate a general output signal and send the general output signal to the second arbitrator; And execute peripheral interface operation instructions to generate peripheral data output control signals, and send the peripheral data output control signals to the second arbitrator; The second arbitrator is used to filter out the target general output signal with the highest priority from the general output signals when it is detected that the general output signals sent by each of the sub-real-time processors meet the second preset conflict detection condition, and send the target general output signal to the general output interface. as well as When it is detected that the peripheral data output control signal sent by each of the sub-real-time processors meets the third preset conflict detection condition, the peripheral data output control signal is sent to the peripheral configuration interface in descending order of priority according to the priority of each of the sub-real-time processors. The general output interface is used to receive the target general output signal forwarded by the second arbitrator and to output the target general output signal. The peripheral configuration interface is used to receive peripheral data output control signals forwarded by the second arbitrator and to output the peripheral data output control signals.

7. The real-time processor according to claim 3, characterized in that, It also includes at least one timer interface, each of which is communicatively connected to each of the sub-real-time processors; Each of the aforementioned timer interfaces is used to acquire timing pulses and send the timing pulses to each of the aforementioned sub-real-time processors; Each of the sub-real-time processors is further configured to receive timing pulses sent by each of the timer interfaces and to perform instruction processing based on each of the timing pulses.

8. The real-time processor according to claim 6, characterized in that, It also includes an on-chip module interrupt interface, a general processor interrupt interface, and an on-chip module trigger interface. The on-chip module interrupt interface is communicatively connected to each of the sub-real-time processors, and the general processor interrupt interface and the on-chip module trigger interface are communicatively connected to each of the sub-real-time processors through the second arbitrator. Each of the sub-real-time processors is further configured to execute a trigger output operation instruction to generate a trigger output pulse signal and send the trigger output pulse signal to the second arbitrator; execute an interrupt operation instruction to generate an interrupt signal and send the interrupt signal to the second arbitrator; and receive an interrupt control signal sent by the on-chip module interrupt interface and execute the instruction stored in the instruction memory corresponding to the interrupt control signal. The second arbitrator is further configured to, when simultaneously receiving trigger output pulse signals sent by each of the sub-real-time processors, sequentially send each trigger output pulse signal to the on-chip module trigger interface in descending order of priority according to the priority of each sub-real-time processor; and when simultaneously receiving interrupt signals sent by each of the sub-real-time processors, sequentially send each interrupt signal to the general-purpose processor interrupt interface in descending order of priority according to the priority of each sub-real-time processor. The on-chip module trigger interface is used to forward the trigger output pulse signal sent by the second arbitrator to the corresponding on-chip module; The general-purpose processor interrupt interface is used to forward the interrupt signal sent by the second arbitrator to the corresponding general-purpose processor; The on-chip module interrupt interface is used to receive interrupt control signals from the on-chip module and forward the interrupt control signals to the corresponding sub-real-time processor.

9. The real-time processor according to claim 4, characterized in that, It also includes a data storage device, which is communicatively connected to each of the sub-real-time processors via the first arbiter; Each of the aforementioned sub-real-time processors is further configured to generate a data operation request signal and send it to the first arbitrator; The first arbitrator is further configured to, when simultaneously receiving data operation request signals sent by each of the sub-real-time processors, forward each data operation request signal to the data memory in descending order of priority according to the priority of each sub-real-time processor. The data storage device is used to receive data operation request signals forwarded by the first arbitrator, and to perform corresponding data operations on the stored data according to the data operation request signals.

10. The real-time processor according to claim 6, characterized in that, It also includes a bus master interface, which is communicatively connected to each of the sub-real-time processors through the second arbiter; Each of the sub-real-time processors is further configured to execute register operation instructions to generate a register operation request signal and send the register operation request signal to the second arbitrator; The second arbitrator is further configured to, when simultaneously receiving register operation request signals sent by each of the sub-real-time processors, forward the register operation request signals sent by each sub-real-time processor to the bus master interface in descending order of priority, according to the priority of each sub-real-time processor. The bus master interface is used to forward each of the register operation request signals forwarded by the second arbitrator to the corresponding on-chip module register.

11. A system-on-a-chip, characterized in that, Including the real-time processor as described in any one of claims 3-10.

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