Embedded thermal resistor and method of manufacturing the same

Abstract

This invention provides an embedded thermistor comprising a lower substrate, an upper substrate, and a plurality of thermistor stacks disposed between the upper and lower substrates. Each thermistor stack includes two resistor bodies separated by a via. Each resistor body includes a substrate layer, a dielectric layer, a metal layer, a resistive layer, a nano-metal layer, and a conductive layer. This invention, through the arrangement of multiple thermistor stacks, allows for greater diversity in the selection of resistive layer materials, and the embedded thermistor can possess a variety of thermal sensitivity capabilities.

Description

Technical Field

[0001] This invention relates to a resistive element and a method for manufacturing the same, and more particularly to an embedded thermistor and a method for manufacturing the same. Background Technology

[0002] In recent years, electronic devices have developed rapidly, with multifunctionality, high circuit density, and miniaturization being the main research directions. Embedding various electronic components within printed circuit boards (PCBs) is a common technique. For example, embedding various passive and / or active components within PCBs not only reduces the area and weight of the PCBs but also improves the reliability of electronic products. Summary of the Invention

[0003] One aspect of the present invention is to provide an embedded thermistor comprising a stack of multiple embedded thermistors.

[0004] Another aspect of the present invention is to provide a method for manufacturing an embedded thermistor.

[0005] According to one aspect of the present invention, an embedded thermistor is provided, comprising a lower substrate, an upper substrate disposed on the lower substrate, and a plurality of thermistor stacks disposed between the upper substrate and the lower substrate. Each thermistor stack comprises two resistor bodies separated by a slot. Each resistor body comprises a substrate layer, a dielectric layer disposed on the substrate layer, a metal layer disposed on the resistor layer, a nano-metal layer disposed on a portion of the metal layer and an end portion of the resistor layer, and a conductive layer, wherein the conductive layer covers a portion of the upper surface of the nano-metal layer and extends to the sidewalls of the nano-metal layer and the sidewalls of the resistor layer. The metal layer is not on the end portion of the resistor layer. The end portions of the resistor layers of the two resistor bodies surround the slot.

[0006] According to an embodiment of the present invention, the upper substrate and the lower substrate respectively include a substrate layer, a metal underlayer and a cover film.

[0007] According to one embodiment of the present invention, the cover film of the lower substrate has at least one opening.

[0008] According to one embodiment of the present invention, the conductive layer extends to a portion of the sidewall of the dielectric layer.

[0009] According to one embodiment of the present invention, the embedded thermistor further includes a plurality of adhesive layers disposed between the upper substrate, the lower substrate and the thermistor stack.

[0010] According to one embodiment of the present invention, the metal layer of one of the resistor bodies of at least one of the plurality of thermistors stacked includes a groove, and the groove is adjacent to the nanometal layer.

[0011] According to one embodiment of the present invention, the above-mentioned embedded thermistor further includes a plurality of conductive metals, which connect the thermistor stacked to the lower substrate.

[0012] According to one embodiment of the present invention, at least two of the thermistor stacks have different widths of the slots.

[0013] According to one embodiment of the present invention, at least two of the plurality of thermistors stacked together have the same width of the slot.

[0014] According to one embodiment of the present invention, the substrate layer has a gap, and the gap is directly below the nano-metal layer, but not entirely below the conductive layer.

[0015] According to another aspect of the present invention, a method for manufacturing an embedded thermistor is provided, comprising fabricating a plurality of thermistor stacks. Fabricating the thermistor stacks includes forming a stacked layer, wherein the stacked layer includes a dielectric layer, a resistive layer, and a metal layer, and the metal layer includes grooves; coating a nano-metal layer in the grooves and on a portion of the metal layer surrounding the grooves; forming a slot in the nano-metal layer, wherein the slot extends through the nano-metal layer and the stacked layer to separate the nano-metal layer and the stacked layer into a first portion and a second portion, respectively; depositing two conductive layers on portions of the top surface of the nano-metal layer in the first portion and the second portion, respectively, and extending to the sidewalls of the first portion and the second portion, respectively; and attaching substrate layers to the bottom of the first portion and the second portion, respectively. The method for manufacturing an embedded thermistor further includes fabricating an upper substrate and a lower substrate; and bonding the upper substrate, the plurality of thermistor stacks, and the lower substrate, wherein the plurality of thermistors are stacked between the upper substrate and the lower substrate.

[0016] According to one embodiment of the present invention, forming the stacked layer includes forming a resistive layer on a dielectric layer; forming a metal layer on the resistive layer; and forming the groove in the metal layer.

[0017] According to one embodiment of the present invention, forming the stacked layers further includes forming an adhesive layer under the dielectric layer, wherein the adhesive layer is removed after the two conductive layers are deposited respectively.

[0018] According to one embodiment of the present invention, after attaching the substrate layer, the method for manufacturing the embedded thermistor further includes forming a gap in the substrate layer, and the gap being directly below the nanometal layer.

[0019] According to an embodiment of the present invention, the method for manufacturing an embedded thermistor further includes forming an upper cover film on the upper substrate; and forming a lower cover film on the lower substrate, wherein the bottom of the lower cover film includes two openings, and the two openings expose the lower substrate.

[0020] The embedded thermistor and its manufacturing method of the present invention allow for a greater variety of material choices for the resistive layer by stacking multiple thermistors, reducing the area of ​​the resistive region, and providing a variety of thermistor capabilities. Attached Figure Description

[0021] A better understanding of the present invention will be obtained by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0022] Figures 1A to 1H A cross-sectional view illustrating an intermediate stage of a method for manufacturing a thermistor stack according to some embodiments of the present invention.

[0023] Figure 2A A cross-sectional view of a stack of thermistors according to some embodiments of the present invention is shown.

[0024] Figure 2B A cross-sectional view of a stack of thermistors according to other embodiments of the present invention is illustrated.

[0025] Figure 3A and Figure 3B A cross-sectional view illustrating an intermediate stage of a method for manufacturing an embedded thermistor according to some embodiments of the present invention.

[0026] Figure 4 A cross-sectional view of an embedded thermistor is shown according to some embodiments of the present invention.

[0027] Figure 5 A top view of a stack of thermistor layers according to some embodiments of the present invention is shown. Detailed Implementation

[0028] This invention provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying the invention. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the invention repeats element symbols and / or letters in various specific examples. This repetition is for the purpose of simplifying and clarifying the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0029] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to facilitate the description of the relationship between a part or feature depicted in the accompanying drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this invention can also be interpreted in this way.

[0030] As used in this invention, “around,” “about,” “approximately,” or “substantially” generally mean within 20 percent, 10 percent, or 5 percent of the stated value or range.

[0031] An embedded thermistor is a resistor embedded in a circuit board that exhibits different resistance values ​​depending on changes in the ambient temperature. Generally, the resistive layer material of an embedded thermistor must have a high temperature coefficient of resistance (TCR), meaning that the resistance value changes significantly with temperature variations. For example, the temperature coefficient of resistance of the resistive material in current embedded thermistors must be greater than 3000 ppm / ℃.

[0032] However, only a small number of pure metals possess the required temperature coefficient of resistance, such as nickel (Ni). Therefore, existing embedded thermistors are almost exclusively limited to nickel. Since nickel has a resistivity of only 6.9 μΩ·cm, to achieve a high resistance value for an embedded thermistor with a fixed resistive material thickness, it must have a large area or length, which is unsuitable for applications in electronic products with high-density circuitry. Therefore, this invention provides an embedded thermistor and its manufacturing method, which reduces the limitations on resistive material selection and the area of ​​the resistive region by using a substrate with a high coefficient of thermal expansion (CTE) and different configurations of thermistor stacks.

[0033] Please see Figures 1A to 1H This is a cross-sectional view illustrating an intermediate stage of a method for manufacturing a thermistor stack 100 according to some embodiments of the present invention. First, please refer to... Figure 1A This forms a stacked layer, which includes a dielectric layer 120, a resistive layer 130, and a metal layer 140. Next, please refer to... Figure 1B An adhesive layer 102 is then bonded beneath the dielectric layer 120. In some embodiments, the adhesive layer 102 comprises polyethylene terephthalate (PET). Then, as... Figure 1C As shown, the metal layer 140 is etched to form a groove O1, thereby exposing the resistor layer 130. During the etching of the metal layer 140, the metal layer 140 can be partially covered with developed photoresist, wherein the portion of the metal layer exposed by the photoresist is etched away to form the groove O1. In some embodiments, the metal layer 140 can be etched using an alkaline etching solution to form the groove O1.

[0034] Please see Figure 1D A nano-metal layer 150 is coated in the groove O1 and on the portion of the metal layer 140 surrounding the groove O1. Then, as... Figure 1E As shown, a slot V1 is formed in the nano-metal layer 150, and the slot V1 extends through the nano-metal layer 150, the resistive layer 130, the dielectric layer 120, and the adhesive layer 102, so that the stacked layer and the nano-metal layer 150 are separated into a first portion 105A and a second portion 105B, and slots V1 with different widths W1 are formed as required. In some embodiments, the slot V1 can be formed by laser processing.

[0035] Please see Figure 1FConductive layers 160 are deposited on portions of the top surfaces 150S of the nano-metal layers 150 of the first portion 105A and the second portion 105B, respectively, and the conductive layers 160 extend to cover the nano-metal layers 150 of the first portion 105A and the second portion 105B and the sidewalls of the stacked layers (including the resistive layer 130, the dielectric layer 120, and the adhesive layer 102). In some embodiments, the conductive layer 160 may selectively extend to portions of the bottom surface 102S of the adhesive layer 102, such as... Figure 1F As shown. In some embodiments, the conductive layer 160 may be deposited using electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable processes.

[0036] Next, please refer to Figure 1G Removing the adhesive layer 102 will also remove a portion of the conductive layer 160, and the remaining conductive layer 160 should extend at least to the sidewall of the resistive layer 130, preferably to the sidewall of the dielectric layer 120. Then, as Figure 1H As shown, the substrate layer 110 is bonded to the bottom of the first portion 105A and the second portion 105B, respectively, which are the bottom of the dielectric layer 120. The substrate layer 110 includes gaps O2 directly below the nanometal layer 150. In some embodiments, after forming the substrate layer 110 that completely covers the bottom of the dielectric layer 120, the substrate layer 110 is photolithographically and etched to form the gaps O2. In other embodiments, the substrate layer 110 may have at least two openings before being bonded to the bottom of the first portion 105A and the second portion 105B; these openings form the gaps O2 after the substrate layer 110 is bonded to the bottom of the first portion 105A and the second portion 105B.

[0037] Please see Figure 2A The diagram illustrates a cross-sectional view of a thermistor stack 100 according to some embodiments of the present invention. The thermistor stack 100 includes a resistor body 100A and a resistor body 100B. A slot V1 separates the resistor body 100A and the resistor body 100B. The resistor body 100A and the resistor body 100B respectively include a substrate layer 110, a dielectric layer 120, a resistive layer 130, a metal layer 140, a nano-metal layer 150, and a conductive layer 160.

[0038] In some embodiments, such as Figure 2AAs shown, a dielectric layer 120 is disposed on a substrate layer 110, a resistive layer 130 is disposed on the dielectric layer 120, and a metal layer 140 is disposed on the resistive layer 130, wherein the metal layer 140 is not located at the end portion of the resistive layer 130. Furthermore, a nano-metal layer 150 is disposed on a portion of the metal layer 140 and the end portion of the resistive layer 130, meaning the nano-metal layer 150 simultaneously contacts both the metal layer 140 and the resistive layer 130. A conductive layer 160 covers a portion of the upper surface of the nano-metal layer 150 and extends to the sidewalls of both the nano-metal layer 150 and the resistive layer 130. In some embodiments, the conductive layer 160 further extends to a portion or all of the sidewalls of the dielectric layer 120.

[0039] In some embodiments, the material of the dielectric layer 120 is a material with a high coefficient of thermal expansion (e.g., CTE greater than 50 ppm / ℃). For example, materials that can serve as the dielectric layer 120 include polyethylene terephthalate (PET), polyethylene (PE), polyamide (PA), polycarbonate (PC), polyester, polypropylene (PP), polystyrene (PS), rigid polyurethane (PUR), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), acrylonitrile butadiene styrene (ABS), cellulose acetate (CA), cellulose nitrate (CN), chlorinated polyvinyl chloride (CPVC), ebonite, ethylene ethyl acrylate (EEA), ethylene vinyl acetate (EVA), fluoroethylene propylene (FEP), phenolic resin, and combinations thereof.

[0040] Compared to existing limitations that require the use of resistive materials with high temperature coefficients of resistance, the material of the resistive layer 130 of the present invention is not particularly limited. Preferably, it can be a material with high sheet resistance to appropriately reduce the area of ​​the resistive region. In some embodiments, the resistive layer 130 comprises nickel phosphide (NiP), lanthanum boronide (LaB6), tantalum nitride (TaN), nickel chromium (NiCr), or other suitable materials.

[0041] In some embodiments, the substrate 110 is made of a material with a low coefficient of thermal expansion, so the area where the substrate 110 is disposed is less prone to expansion and contraction with temperature. For example... Figure 2A As shown, the substrate layer 110 has a gap O2. In some embodiments, the gap O2 is directly below the nanometal layer 150, and the gap O2 may be partially or not below the conductive layer 160. In other words, the gap O2 may partially overlap with or not overlap with the conductive layer 160 at all.

[0042] The purpose of the gap O2 is to provide better expansion and contraction capabilities for the tensile region A1. When the tensile region A1 expands due to temperature (e.g., temperature rise), the respective connector regions A2 of resistor bodies 100A and 100B can extend towards each other. Upon reaching a specific temperature, the connector regions A2 can contact and electrically connect, causing a decrease in resistance. In other words, as the temperature changes, the connector regions A2 may separate or connect, resulting in a change in the resistance of the thermistor stack 100.

[0043] The nanometal layer 150 is made of a conductive and ductile nanometal. Since the resistive layer 130 has poor ductility and may crack under temperature changes, the nanometal layer 150, with its superior tensile strength, can prevent crack formation, thereby preventing the thermistor stack 100 from failing. In some embodiments, the nanometal layer 150 is made of nanosilver, because nanosilver not only has good conductivity but also excellent tensile strength, making it less prone to cracking after expansion and contraction.

[0044] The material of the conductive layer 160 must have good electrical conductivity, such as copper. By providing the conductive layer 160 on the sidewalls of each layer in the junction area A2, a better electrical connection is achieved when the junction areas A2 of the resistor bodies 100A and 100B come into contact. Conversely, if the conductive layer 160 is not provided, a stable electrical connection may not be formed even if the two junction areas A2 come into contact.

[0045] The end portions of the resistive layers 130 of resistor bodies 100A and 100B surround the slot V1. In various embodiments, the width W1 of the slot V1 in each thermistor stack 100 may be the same or different. In some embodiments, the width of the slot V1 in the thermistor stack within the same layer is different, while the width of the slot V1 in the thermistor stacks across different layers may be the same or different. By configuring various widths W1, the resistor bodies 100A and 100B of each thermistor stack 100 may separate or connect under different temperature conditions, resulting in different resistance values, thus the resulting embedded thermistor can have better thermal sensitivity.

[0046] For example, in some embodiments where the material of the dielectric layer 120 is polyethylene (CTE of 200 ppm / °C), when the width W of the gap O2 in the substrate layer 110... O When the length is 2mm, and taking 25℃ as a reference (i.e., the tensile length of the stretching zone A1 is 0), the stretching zone A1 will have a length change of about 10μm at about 50℃ (i.e., the tensile length change rate is 0.50%). Therefore, if the two joint zones A2 are to be electrically connected at about 50℃, the width W1 of the slot V1 can be set to 20μm. Similarly, at about 75℃, about 100℃, and about 125℃, the stretching zone A1 will have a length change of about 20μm, 30μm, and 40μm, respectively. Therefore, if the two joint zones A2 are to be electrically connected at about 75℃, about 100℃, and about 125℃, respectively, the width W1 of the slot V1 can be set to 40μm, 60μm, and 80μm, respectively.

[0047] Please see Figure 2B This illustration depicts a cross-sectional view of a thermistor stack 200 according to other embodiments of the present invention. As described above, a slot V1 separates resistor body 200A and resistor body 200B. Similarly, resistor body 200A and resistor body 200B respectively include a substrate layer 110, a dielectric layer 120, a resistive layer 130, a metal layer 140, a nano-metal layer 150, and a conductive layer 160. Figure 2B As shown, a dielectric layer 120 is disposed on a substrate layer 110, a resistive layer 130 is disposed on the dielectric layer 120, and a metal layer 140 is disposed on the resistive layer 130, wherein the metal layer 140 is not located on the end portion of the resistive layer 130. A nano-metal layer 150 is disposed on a portion of the metal layer 140 and the end portion of the resistive layer 130, and a conductive layer 160 covers a portion of the upper surface of the nano-metal layer 150 and extends to the sidewalls of the nano-metal layer 150 and the sidewalls of the resistive layer 130.

[0048] The thermistor stack 200 differs from the thermistor stack 100 in that the metal layer 140 in the resistor body 200A includes a groove R1, and the groove R1 is adjacent to the nano-metal layer 150. In various embodiments, the width W of the groove R1 is... R They can be the same or different. The width W of the groove R1 R This will affect the resistance value, so different resistance values ​​can be designed for different layers of the circuit board to further improve the thermistor's thermal sensitivity.

[0049] Please see Figure 3A and Figure 3B This illustration depicts a cross-sectional view of an intermediate stage in a method for manufacturing an embedded thermistor 300 according to some embodiments of the present invention. First, please refer to... Figure 3A The method for manufacturing the embedded thermistor 300 includes fabricating multiple thermistor stacks (e.g., thermistor stack 100 or thermistor stack 200) according to the above method. Then, an upper substrate 310 and a lower substrate 320 are fabricated. In some embodiments, the upper substrate 310 includes a substrate layer 302 and a metal underlayer 304, while the lower substrate 320 includes a substrate layer 312 and a metal underlayer 314, wherein the metal underlayer 314 of the lower substrate 320 is subjected to a wire-breaking process to form an opening O3. Next, the upper substrate 310, the lower substrate 320, the thermistor stack layer 330, the thermistor stack layer 340, and the thermistor stack layer 350 are bonded together using an adhesive layer 360. It should be understood that... Figure 3A The illustration shows an embedded thermistor 300 comprising three thermistor stack layers, but the invention is not limited thereto, and the number of thermistor stack layers can be adjusted as needed.

[0050] Next, please refer to Figure 3B The thermistor stack 330, thermistor stack 340, thermistor stack 350 and the lower substrate 320 are electrically connected by a conductive metal 370. In other words, the conductive metal 370 extends downward from the metal layer 140 of the uppermost thermistor stack 330 to the metal bottom layer 314 of the lower substrate 320 to conduct electricity between the thermistor stack 330, thermistor stack 340, thermistor stack 350 and the lower substrate 320.

[0051] Then, please see Figure 4 The illustration depicts a cross-sectional view of an embedded thermistor 300 according to some embodiments of the present invention. Figure 3B The upper substrate 310 and lower substrate 320 of the structure shown are then respectively covered with a cover film 306 and a cover film 316. In some embodiments, the cover film 306 and the cover film 316 may be made of ink or other suitable materials. At this point, the structure of the embedded thermistor 300 in some embodiments of the present invention is essentially complete.

[0052] like Figure 4 As shown, the embedded thermistor 300 includes an upper substrate 310, a lower substrate 320, a thermistor stack layer 330, a thermistor stack layer 340, and a thermistor stack layer 350. The thermistor stack layers 330, 340, and 350 each include a plurality of the aforementioned thermistor stacks 100 or 200. The upper substrate 310, lower substrate 320, thermistor stack layers 330, 340, and 350 are bonded to each other by an adhesive layer 360, wherein the thermistor stack layers 330, 340, and 350 are disposed between the upper substrate 310 and the lower substrate 320.

[0053] In some embodiments, the upper substrate 310 includes a substrate layer 302, a metal underlayer 304, and a cover film 306, while the lower substrate 320 includes a substrate layer 312, a metal underlayer 314, and a cover film 316. In some embodiments, the materials of the substrate layer 302 and the substrate layer 312 are similar to the material of the base layer 110 described above, i.e., materials with a low coefficient of thermal expansion. In some embodiments, the metal underlayer 304 and the metal underlayer 314 may be formed, for example, from a copper clad laminate (CCL) or a resin-coated copper foil (RCC), or may contain materials similar to those of the metal layer 140 described above.

[0054] Metal substrates 304 and 314 are not fabricated with circuitry, but retain complete metal layers to improve thermal conductivity. However, the metal substrate 314 of the lower substrate 320 must undergo wire breaking to form the aforementioned opening O3 (see reference). Figure 3A or Figure 3B ),Right now Figure 4 The region X is shown. In some embodiments, the cover film 316 of the lower substrate 320 includes at least one opening. Figure 4 The diagram illustrates a cover film 316 comprising two openings O4. The openings O4 are configured to provide voltage across a resistor. In some embodiments, the two openings O4 are located at opposite ends of region X.

[0055] In some embodiments, the embedded thermistor 300 includes a conductive metal 370 to conduct the thermistor stack 330, thermistor stack 340, thermistor stack 350, and the lower substrate 320. The conductive metal 370 comprises a material with superior conductivity. In some embodiments, the material of the conductive metal 370 is the same as the material of the metal layer 140, such as copper.

[0056] In some embodiments, the widths W1 of the slot V1 included in the thermistor stack 330, W3 of the slot V2 included in the thermistor stack 340, and W5 of the slot V3 included in the thermistor stack 350 are all different. In other embodiments, at least two of the widths W1 of the slot V1, W3 of the slot V2, and W5 of the slot V3 are the same. In some embodiments, the metal layer 140 of at least one of the thermistor stacks 330, 340, and 350 includes a groove. Figure 4 As shown, the metal layer 140 of the thermistor stack 330 does not include a groove, while the metal layers 140 of the thermistor stack 340 and the thermistor stack 350 respectively include a groove R1 and a groove R2. In some embodiments, the width W2 of the groove R1 and the width W4 of the groove R2 are different so that they have different resistance values.

[0057] Please see Figure 5 This diagram illustrates a top view of a thermistor stack 330 according to some embodiments of the present invention. The thermistor stack 330 includes three thermistor stacks connected in parallel (e.g., thermistor stack 100 and / or thermistor stack 200). The three thermistor stacks each include a slot V11, a slot V12, and a slot V13. In some embodiments, the widths W11, W12, and W13 of slot V11, V12, and V13 are all different, so that each thermistor stack has different resistance values ​​under different temperature conditions. The metal layer 140 of one of the three thermistor stacks does not include a groove, while the metal layers 140 of the other two stacks each include grooves R01 and R02 to expose the resistive layer 130. In some embodiments, the resistive lines of the resistive layer 130 can be designed according to the specific application. Figure 4 The serpentine circuit shown is for illustrative purposes only. In some embodiments, the width W01 of groove R01 is different from the width W02 of groove R02 so that the resistance values ​​of the three stacked thermistors are different.

[0058] As described above, the present invention provides an embedded thermistor and its manufacturing method. By designing a stack of thermistors with different resistance values ​​and utilizing a dielectric layer with a high coefficient of thermal expansion, the stack of thermistors can be electrically connected under different temperature conditions, thereby reducing the limitations on the resistive layer material and reducing the area of ​​the resistive region. Furthermore, the embedded thermistor can have a variety of thermal sensitivity capabilities.

[0059] Although the present invention has been disclosed above with reference to several embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0060] [Symbol Explanation]

[0061] 100: Thermistor stack

[0062] 100A, 100B: Resistor body

[0063] 102: Adhesive layer

[0064] 102S: Bottom surface

[0065] 105A: Part One

[0066] 105B: Part Two

[0067] 110: Basal layer

[0068] 120: Dielectric layer

[0069] 130: Resistive layer

[0070] 140: Metal layer

[0071] 150: Nanometallic layer

[0072] 160: Conductive layer

[0073] 200: Thermistor Stack

[0074] 200A, 200B: Resistor body

[0075] 300: Embedded thermistor

[0076] 302: Substrate layer

[0077] 304: Metallic base

[0078] 306: Covering film

[0079] 310: Upper substrate

[0080] 312: Substrate layer

[0081] 314: Metal base layer

[0082] 316: Covering film

[0083] 320:Lower base plate

[0084] 330, 340, 350: Thermistor stacked layers

[0085] 360: Adhesive layer

[0086] 370: Conductive metal

[0087] A1: Tension Zone

[0088] A2: Connector Area

[0089] O1: Groove

[0090] O2: Gap

[0091] O3: Opening

[0092] O4: Opening

[0093] R1, R2: Grooves

[0094] R01, R02: Grooves

[0095] V1, V2, V3: Slots

[0096] V11, V12, V13: Slots

[0097] W1, W2, W3, W4, W5: Width

[0098] W11, W12, W13: Width

[0099] W01, W02: Width

[0100] W O :width

[0101] W R :width

[0102] X: Region.

Claims

1. An embedded thermistor, characterized in that, Include: lower base plate; An upper substrate is disposed on the lower substrate; and Multiple thermistors are stacked and disposed between the upper substrate and the lower substrate, wherein each thermistor stack includes two resistor bodies, wherein a slot separates the two resistor bodies, and each resistor body includes: basal layer; A dielectric layer is disposed on the substrate layer; A resistive layer is disposed on the dielectric layer; A metal layer is disposed on the resistive layer; A nano-metal layer is disposed on the upper surface of a portion of the metal layer and the end portion of the resistive layer, wherein the metal layer is not located on the end portion of the resistive layer; and A conductive layer covers a portion of the upper surface of the nano-metal layer and extends to the sidewalls of the nano-metal layer and the sidewalls of the resistive layer, wherein the end portions of the resistive layer of the two resistive bodies surround the slot.

2. The embedded thermistor according to claim 1, characterized in that, The upper substrate and the lower substrate respectively include a substrate layer, a metal underlayer and a cover film.

3. The embedded thermistor according to claim 2, characterized in that, The cover film of the lower substrate has at least one opening.

4. The embedded thermistor according to claim 1, characterized in that, The conductive layer extends onto a portion of the sidewall of the dielectric layer.

5. The embedded thermistor according to claim 1, characterized in that, Also includes: Multiple adhesive layers are disposed between the upper substrate, the lower substrate, and the multiple thermistor stacks.

6. The embedded thermistor according to claim 1, characterized in that, The metal layer of at least one of the resistor bodies of the plurality of thermistors stacked includes a groove, and the groove is adjacent to the nanometal layer.

7. The embedded thermistor according to claim 1, characterized in that, Also includes: Multiple conductive metals connect the multiple thermistors stacked on the lower substrate.

8. The embedded thermistor according to claim 1, characterized in that, The slot widths of at least two of the stacked thermistors are different.

9. The embedded thermistor according to claim 1, characterized in that, At least two of the stacked thermistors have the same width of the slot.

10. The embedded thermistor according to claim 1, characterized in that, The base layer has a gap, and the gap is directly below the nano-metal layer, but not entirely below the conductive layer.

11. A method for manufacturing an embedded thermistor, characterized in that, Include: Fabricate multiple thermistor stacks, including: A stacked layer is formed, wherein the stacked layer includes a dielectric layer, a resistive layer and a metal layer, and the metal layer includes grooves; A nano-metal layer is coated in the groove and on the portion of the metal layer surrounding the groove; A slot is formed in the nanometal layer, wherein the slot extends through the nanometal layer and the stacked layer to separate the nanometal layer and the stacked layer into a first part and a second part; Two conductive layers are deposited on portions of the top surface of the nano-metal layer in the first portion and the second portion, respectively, and extend to the sidewalls of the first portion and the second portion, respectively. as well as The base layer is respectively attached to the bottom of the first part and the second part; Fabricate the upper and lower substrates; as well as The upper substrate, the plurality of thermistors stacked together, and the lower substrate are bonded together, wherein the plurality of thermistors stacked between the upper substrate and the lower substrate.

12. The method for manufacturing an embedded thermistor according to claim 11, characterized in that, Forming the stacked layers includes: A resistive layer is formed on the dielectric layer; A metal layer is formed on the resistive layer; and The groove is formed in the metal layer.

13. The method for manufacturing an embedded thermistor according to claim 12, characterized in that, Forming the stacked layers further includes: An adhesive layer is formed under the dielectric layer, wherein the adhesive layer is removed after the two conductive layers are deposited respectively.

14. The method for manufacturing an embedded thermistor according to claim 11, characterized in that, After adhering to the substrate layer, it also includes: A gap is formed in the substrate layer, and the gap is directly below the nanometal layer.

15. The method for manufacturing an embedded thermistor according to claim 11, characterized in that, Also includes: An upper cover film is formed on the upper substrate; and A lower cover film is formed on the lower substrate, wherein the bottom of the lower cover film includes two openings, and the two openings expose the lower substrate.

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