Digital signal processing chip, signal processing method, communication device and communication system

Abstract

Embodiments of the present application disclose a digital signal processing chip, a signal processing method, a communication device and a communication system. The digital signal processing chip is applied to a device for communication based on an analog signal. In the digital signal processing chip, a plurality of signal processing units respectively process input signals to obtain output signals according to processing parameters of the signal processing units, a parameter determination unit obtains updated parameters based on a global cost function, each signal processing unit can update the processing parameter of the signal processing unit according to the updated parameters, and the updated parameters are iterated, so that each signal processing unit is coupled. After multiple iterations and optimization of the processing parameters and the updated parameters, the processing parameters of submodules in the digital signal processing chip can be adaptively adjusted, and the channel impairment compensation effects of the submodules in the digital signal processing chip are ensured.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a digital signal processing chip, a signal processing method, a communication device, and a communication system. Background Technology

[0002] In digital communication systems, due to channel impairments, it is necessary to process the digital signals to compensate for these impairments in order to ensure the accuracy of the transmitted digital signals.

[0003] Generally, a digital communication system includes a transmitter, a channel, and a receiver. The transmitter processes the digital signal to be transmitted (e.g., channel impairment compensation, digital-to-analog conversion, and modulation) and then sends it to the receiver via the channel. The receiver processes the received signal (e.g., demodulation, analog-to-digital conversion, and channel impairment compensation) to complete the transmission of the digital signal. Both the transmitter and the receiver include a digital signal processing (DSP) chip for channel impairment compensation of the digital signal. The DSP chip includes multiple DSP sub-modules, each of which is designed with different processing parameters for one or more specific channel impairments to compensate for the corresponding channel impairments.

[0004] However, these DSP submodules are independent of each other and can only guarantee their own channel impairment compensation effect. Adjusting the processing parameters of one DSP submodule may affect the compensation effect of other DSP submodules. Summary of the Invention

[0005] This application provides a digital signal processing chip for adaptively adjusting the processing parameters of submodules within the chip. This application also provides corresponding signal processing methods, communication devices, communication systems, and storage media.

[0006] This application provides a digital signal processing chip for use in communication equipment. The digital signal processing chip includes a first signal processing unit, a second signal processing unit, and a parameter determination unit. The first signal processing unit processes a first input digital signal according to first processing parameters to obtain a first output digital signal, and sends the first output digital signal as a second input digital signal to the second signal processing unit. The second signal processing unit processes a second input digital signal according to second processing parameters to obtain a second output digital signal. The parameter determination unit processes the second output digital signal and a reference digital signal based on a global cost function to obtain a first update parameter, where the global cost function is used to determine the difference between the second output digital signal and the reference digital signal. The second signal processing unit is further configured to update a second processing parameter according to the first update parameter, and / or the first signal processing unit is further configured to update the first processing parameter according to the second update parameter, wherein the second update parameter is determined by the second signal processing unit based on the first update parameter and the second input digital signal.

[0007] In this application, the digital signal processing chip is applied to communication equipment, such as a digital communication system or a digital communication device (e.g., a transmitter or receiver) within a digital communication system. In addition to processing the input digital signal based on processing parameters to achieve channel impairment compensation, the digital signal processing chip can also back-transmit update parameters based on the difference between the final output digital signal and the reference digital signal. Each signal processing unit in the digital signal processing chip can update its processing parameters according to its own update parameters.

[0008] In this application, a signal processing unit that updates the processing parameters is defined as a dynamic signal processing unit, and a signal processing unit that does not update its processing parameters is defined as a static signal processing unit. However, both dynamic and static signal processing units need to iteratively update the parameters in reverse.

[0009] The first signal processing unit in this application can be multiple.

[0010] In the first aspect, multiple signal processing units process the input signal according to their respective processing parameters to obtain the output signal. The parameter determination unit obtains the updated parameters based on the global cost function. Each signal processing unit can update its processing parameters according to the updated parameters and iterate the updated parameters, so that each signal processing unit is coupled. After multiple iterations and optimizations of the processing parameters and updated parameters, the processing parameters of the sub-modules in the digital signal processing chip can be adaptively adjusted to ensure the channel impairment compensation effect of each sub-module in the digital signal processing chip.

[0011] In one possible implementation of the first aspect, the first signal processing unit includes a first signal processing module, a first parameter update module, a first buffer module, and a first inverse parameter determination module. The first signal processing module processes a first input digital signal according to first processing parameters to obtain a first output digital signal. The first parameter update module updates the first processing parameters according to second update parameters. The first inverse parameter determination module determines a third update parameter based on the second update parameter and the first input digital signal. The first buffer module stores the first input digital signal, the first output digital signal, the first processing parameters, the second update parameter, and the third update parameter.

[0012] In this possible implementation, the first signal processing unit is a dynamic signal processing unit, which means that the first signal processing unit can update its processing parameters according to the received update parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0013] In one possible implementation of the first aspect, the first signal processing unit includes a first signal processing module, a first buffer module, and a first inverse parameter determination module, wherein the first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first inverse parameter determination module is used to determine a third update parameter according to the second update parameter and the first input digital signal; and the first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the second update parameter, and the third update parameter.

[0014] In this possible implementation, the first signal processing unit is a static signal processing unit, that is, the first signal processing unit does not update its processing parameters according to the received update parameters, but still generates new update parameters and transmits them in reverse to ensure the use of subsequent signal processing units and improve the feasibility of the solution.

[0015] In one possible implementation of the first aspect, the second signal processing unit includes a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module. The second signal processing module processes the second input digital signal according to second processing parameters to obtain a second output digital signal. The second parameter update module updates the second processing parameters according to a first update parameter. The second inverse parameter determination module determines a second update parameter based on the first update parameter and the second input digital signal. The second buffer module stores the second input digital signal, the second output digital signal, the second processing parameters, the first update parameter, and the second update parameter.

[0016] In this possible implementation, the second signal processing unit is a dynamic signal processing unit, which can update its processing parameters according to the received update parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0017] In one possible implementation of the first aspect, the second signal processing unit includes a second signal processing module, a second buffer module, and a second inverse parameter determination module. The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain a second output digital signal. The second inverse parameter determination module is used to determine a second update parameter according to the first update parameter and the second input digital signal. The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameters, the first update parameter, and the second update parameter.

[0018] In this possible implementation, the second signal processing unit is a static signal processing unit, meaning that the first signal processing unit does not update its processing parameters according to the received update parameters, but still generates new update parameters and transmits them in reverse to ensure the use of subsequent signal processing units and improve the feasibility of the solution.

[0019] In one possible implementation of the first aspect, the digital signal processing chip further includes: a decision unit for making a decision on the second output digital signal to obtain a reference digital signal.

[0020] In this possible implementation, the decision unit can generate a reference digital signal based on the digital signal finally output by the entire digital signal processing chip, which improves the feasibility of the solution.

[0021] In one possible implementation of the first aspect, the first signal processing unit is a circuit structure in a digital signal processing chip, and the second signal processing unit is a circuit structure in the digital signal processing chip.

[0022] In this possible implementation, the digital signal processing chip is a circuit structure that can be divided into multiple regions, each of which performs a different function. For example, the first region is a first signal processing unit, and the second region is a second signal processing unit. The first region is used to implement the function implemented by the first signal processing unit, and the second region is used to implement the function implemented by the second signal processing unit, thereby improving the feasibility of the solution.

[0023] A second aspect of this application provides a communication device comprising a digital signal processing chip as described in the first aspect or any possible implementation thereof, the second aspect having the same beneficial effects as the digital signal processing chip described in the first aspect or any possible implementation thereof.

[0024] A third aspect of this application provides a communication system comprising a transmitter and a receiver. The transmitter includes a first signal processing unit, a digital-to-analog converter (DAC), and a modulation unit. The receiver includes a demodulation unit, an analog-to-digital converter (ADC), a second signal processing unit, a third signal processing unit, and a parameter determination unit. The first signal processing unit processes a first input digital signal according to first processing parameters to obtain a first output digital signal. The DAC performs digital-to-analog conversion on the first output digital signal to obtain a first analog signal. The modulation unit modulates the first analog signal onto a carrier wave to obtain a modulated signal and transmits the modulated signal to the demodulation unit via a channel. The demodulation unit demodulates the modulated signal to obtain a second analog signal. The DAC performs analog-to-digital conversion on the second analog signal to obtain a digital signal and transmits the digital signal as a second input digital signal to the second signal processing unit. The system comprises a first signal processing unit and a second signal processing unit. The second signal processing unit processes the second input digital signal according to the second processing parameters to obtain a second output digital signal, and sends the second output digital signal as a third input digital signal to the third signal processing unit. The third signal processing unit processes the third input digital signal according to the third processing parameters to obtain a third output digital signal. The parameter determination unit processes the third output digital signal and a reference digital signal based on a global cost function to obtain a first update parameter, wherein the global cost function is used to determine the difference between the third output digital signal and the reference digital signal. The third signal processing unit is also used to update the third processing parameter according to the first update parameter, and / or the second signal processing unit is also used to update the second processing parameter according to the second update parameter, wherein the second update parameter is determined by the third signal processing unit based on the first update parameter and the third input digital signal.

[0025] In this application, the transmitter can process digital signals through its digital signal processing chip, and after digital-to-analog conversion and modulation, the modulated signal is sent to the receiver through the channel. The receiver can demodulate and perform analog-to-digital conversion on the received modulated signal, and process the digital signal through its digital signal processing chip.

[0026] In this application, the first signal processing unit in the transmitter can be regarded as its digital signal processing chip, and the second signal processing unit, the third signal processing unit and the parameter determination unit in the receiver can be regarded as its digital signal processing chip. There can be multiple first signal processing units and multiple second signal processing units, which means that the transmitter and receiver in the communication system both include the digital signal processing chip of the first aspect or any possible implementation of the first aspect.

[0027] The third aspect has the same beneficial effects as the digital signal processing chip of the first aspect or any possible implementation of the first aspect.

[0028] In one possible implementation of the third aspect, the second signal processing unit includes a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module. The second signal processing module processes the second input digital signal according to the second processing parameters to obtain a second output digital signal. The second parameter update module updates the second processing parameters according to the second update parameters. The second inverse parameter determination module determines a third update parameter based on the second update parameters and the second input digital signal. The second buffer module stores the second input digital signal, the second output digital signal, the second processing parameters, the second update parameters, and the third update parameters.

[0029] In this possible implementation, the second signal processing unit is a dynamic signal processing unit, which can update its processing parameters according to the received update parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0030] In one possible implementation of the third aspect, the second signal processing unit includes a second signal processing module, a second buffer module, and a second inverse parameter determination module. The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain a second output digital signal. The second inverse parameter determination module is used to determine a third update parameter according to the second update parameter and the second input digital signal. The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameter, the second update parameter, and the third update parameter.

[0031] In this possible implementation, the second signal processing unit is a static signal processing unit, meaning that the second signal processing unit does not update its processing parameters according to the received update parameters, but still generates new update parameters and transmits them in reverse to ensure the use of subsequent signal processing units and improve the feasibility of the solution.

[0032] In one possible implementation of the third aspect, the third signal processing unit includes a third signal processing module, a third parameter update module, a third buffer module, and a third inverse parameter determination module. The third signal processing module is used to process the third input digital signal according to the third processing parameters to obtain a third output digital signal; the third parameter update module is used to update the third processing parameters according to the first update parameters; the third inverse parameter determination module is used to determine a second update parameter according to the first update parameters and the third input digital signal; and the third buffer module is used to store the third input digital signal, the third output digital signal, the third processing parameters, the first update parameter, and the second update parameter.

[0033] In this possible implementation, the third signal processing unit is a dynamic signal processing unit, which can update its processing parameters according to the received updated parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0034] In one possible implementation of the third aspect, the third signal processing unit includes a third signal processing module, a third buffer module, and a third inverse parameter determination module. The third signal processing module is used to process the third input digital signal according to the third processing parameters to obtain a third output digital signal. The third inverse parameter determination module is used to determine a second update parameter according to the first update parameter and the third input digital signal. The third buffer module is used to store the third input digital signal, the third output digital signal, the third processing parameters, the first update parameter, and the second update parameter.

[0035] In this possible implementation, the third signal processing unit is a static signal processing unit, meaning that the third signal processing unit does not update its processing parameters according to the received update parameters, but still generates new update parameters and transmits them in reverse to ensure the use of subsequent signal processing units and improve the feasibility of the solution.

[0036] In one possible implementation of the third aspect, the communication system further includes: a channel model unit, configured to determine a fourth update parameter based on a first output digital signal and a third update parameter, and send the fourth update parameter to a first signal processing unit, wherein the third update parameter is determined by a second signal processing unit based on a second update parameter and a second input digital signal; the first signal processing unit is further configured to determine a fifth update parameter based on the fourth update parameter and the first input digital signal.

[0037] In this possible implementation, the channel model unit can couple the digital signal processing chip of the transmitter and the digital signal processing chip of the receiver to achieve more convenient joint optimization and ensure the optimal global channel impairment compensation effect in the entire communication system.

[0038] In one possible implementation of the third aspect, the first signal processing unit is further configured to update the first processing parameter according to the fourth update parameter.

[0039] In this possible implementation, the first signal processing unit is a dynamic signal processing unit, which means that the first signal processing unit can update its processing parameters according to the received update parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0040] In one possible implementation of the third aspect, the channel model unit is specifically used to process the first output digital signal according to the channel model parameters to obtain the channel model signal, and to determine the fourth update parameter according to the channel model signal and the third update parameter.

[0041] In this possible implementation, the channel model unit can generate a channel model signal based on the received first output digital signal and the stored channel model parameters, and use the channel model signal and the third update parameter to determine the fourth update parameter, or use the channel model signal to accelerate the calculation process of determining the fourth update parameter, thereby improving the feasibility of the scheme.

[0042] In one possible implementation of the third aspect, the channel model unit includes a channel model module, a channel buffer module, and a channel inverse parameter determination module. The channel model module is used to process the first output digital signal according to the channel model parameters to obtain the channel model signal; the channel inverse parameter determination module is used to determine the fourth update parameter according to the channel model signal and the third update parameter; and the channel buffer module is used to store the first output digital signal, the channel model signal, the channel model parameters, the third update parameter, and the fourth update parameter.

[0043] In this possible implementation, the channel model unit includes a channel model module, a channel buffer module, and a channel inverse parameter determination module. Each module is used to implement the function of the channel model unit, which improves the feasibility of the scheme.

[0044] In one possible implementation of the third aspect, the first signal processing unit includes a first signal processing module, a first parameter update module, a first buffer module, and a first inverse parameter determination module. The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first parameter update module is used to update the first processing parameters according to the fourth update parameters; the first inverse parameter determination module is used to determine a fifth update parameter according to the fourth update parameters and the first input digital signal; and the first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameters, the fourth update parameters, and the fifth update parameters.

[0045] In this possible implementation, the first signal processing unit is a dynamic signal processing unit, which means that the first signal processing unit can update its processing parameters according to the received update parameters, so that its processing parameters are not dependent on the calibration accuracy, but can be adaptively adjusted according to global requirements, ensuring that the channel impairment compensation effect of the entire digital signal processing chip is optimal.

[0046] In one possible implementation of the third aspect, the first signal processing unit includes a first signal processing module, a first buffer module, and a first inverse parameter determination module, wherein the first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first inverse parameter determination module is used to determine a fifth update parameter according to the fourth update parameter and the first input digital signal; and the first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the fourth update parameter, and the fifth update parameter.

[0047] In this possible implementation, the first signal processing unit is a static signal processing unit, that is, the first signal processing unit does not update its processing parameters according to the received update parameters, but still generates new update parameters and transmits them in reverse to ensure the use of subsequent signal processing units and improve the feasibility of the solution.

[0048] In one possible implementation of the third aspect, the communication system further includes:

[0049] The decision unit is used to make a decision on the third output digital signal to obtain a reference digital signal.

[0050] In this possible implementation, the decision unit can generate a reference digital signal based on the final digital signal output by the entire communication system, which improves the feasibility of the solution.

[0051] In one possible implementation of the third aspect, the first signal processing unit is a circuit structure in a digital signal processing chip, the second signal processing unit is a circuit structure in the digital signal processing chip, and the third signal processing unit is a circuit structure in the digital signal processing chip.

[0052] In this possible implementation, the digital signal processing chip is a circuit structure that can be divided into multiple regions, each of which performs a different function. For example, the first region is a first signal processing unit, and the second region is a second signal processing unit. The first region is used to implement the function implemented by the first signal processing unit, and the second region is used to implement the function implemented by the second signal processing unit, thereby improving the feasibility of the solution.

[0053] A fourth aspect of this application provides a signal processing method applied to a digital signal processing chip. The signal processing method includes: processing a first input digital signal according to first processing parameters to obtain a first output digital signal; processing a first output digital signal, which is a second input digital signal, according to second processing parameters to obtain a second output digital signal; processing the second output digital signal and a reference digital signal based on a global cost function to obtain a first update parameter, wherein the global cost function is used to determine the difference between the second output digital signal and the reference digital signal; updating a second processing parameter according to the first update parameter, and / or updating a first processing parameter according to the second update parameter, wherein the second update parameter is determined based on the first update parameter and the second input digital signal.

[0054] In one possible implementation of the fourth aspect, the signal processing method further includes: making a decision on the second output digital signal to obtain a reference digital signal.

[0055] The fourth aspect or the fourth aspect has the same beneficial effects as the digital signal processing chip of the first aspect or any possible implementation of the first aspect.

[0056] This application provides a signal processing method applied to a communication device. The signal processing method includes: processing a first input digital signal according to first processing parameters to obtain a first output digital signal; performing digital-to-analog conversion on the first output digital signal to obtain a first analog signal; modulating the first analog signal onto a carrier wave to obtain a modulated signal; demodulating the modulated signal to obtain a second analog signal; performing analog-to-digital conversion on the second analog signal to obtain a digital signal; processing the digital signal, which is a second input digital signal, according to second processing parameters to obtain a second output digital signal; processing the second output digital signal, which is a third input digital signal, according to third processing parameters to obtain a third output digital signal; processing the third output digital signal and a reference digital signal based on a global cost function to obtain a first update parameter, wherein the global cost function is used to determine the difference between the third output digital signal and the reference digital signal; updating the third processing parameter according to the first update parameter, and / or updating the second processing parameter according to the second update parameter, wherein the second update parameter is determined by a third signal processing unit based on the first update parameter and the third input digital signal.

[0057] In one possible implementation of the fifth aspect, the signal processing method further includes: determining a fourth update parameter based on a first output digital signal and a third update parameter, wherein the third update parameter is determined by a second signal processing unit based on a second update parameter and a second input digital signal; and determining a fifth update parameter based on the fourth update parameter and the first input digital signal.

[0058] In one possible implementation of the fifth aspect, the signal processing method further includes updating the first processing parameter according to the fourth update parameter.

[0059] In one possible implementation of the fifth aspect, the above step of determining the fourth update parameter based on the first output digital signal and the third update parameter includes: processing the first output digital signal according to the channel model parameters to obtain the channel model signal; and determining the fourth update parameter based on the channel model signal and the third update parameter.

[0060] In one possible implementation of the fifth aspect, the signal processing method further includes: making a decision on the second output digital signal to obtain a reference digital signal.

[0061] The fifth aspect or any possible implementation thereof has the same beneficial effects as the communication system of the third aspect or any possible implementation thereof.

[0062] The sixth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed, it implements the method as described in the fourth aspect above or any possible implementation of the fourth aspect.

[0063] The seventh aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed, it implements the method as described in the fifth aspect or any possible implementation of the fifth aspect above. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of the architecture of a digital communication system;

[0065] Figure 2 A schematic diagram of an embodiment of the digital signal processing chip provided in this application;

[0066] Figure 3 A schematic diagram of an embodiment of the dynamic signal processing unit provided in this application;

[0067] Figure 4 A schematic diagram of an embodiment of the static signal processing unit provided in this application;

[0068] Figure 5 This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0069] Figure 6 This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0070] Figure 7 This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0071] Figure 8 This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0072] Figure 9A This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0073] Figure 9B This is a schematic diagram of another embodiment of the digital signal processing chip provided in this application.

[0074] Figure 10 This is a schematic diagram comparing the performance of the digital signal processing chip provided in the embodiments of this application;

[0075] Figure 11 A schematic diagram of an embodiment of the communication device provided in this application;

[0076] Figure 12 A schematic diagram of an embodiment of the communication system provided in this application;

[0077] Figure 13A schematic diagram of an embodiment of the channel model unit provided in this application;

[0078] Figure 14 A schematic diagram of another embodiment of the communication system provided in this application;

[0079] Figure 15 A schematic diagram of an embodiment of the signal processing method provided in this application;

[0080] Figure 16 This is a schematic diagram of another embodiment of the signal processing method provided in this application.

[0081] Figure 17 This is a schematic diagram of another embodiment of the signal processing method provided in this application.

[0082] Figure 18 This is a schematic diagram of another embodiment of the signal processing method provided in this application. Detailed Implementation

[0083] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0084] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0085] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0086] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0087] This application provides a digital signal processing chip to ensure optimal channel impairment compensation across the entire chip. It also provides corresponding signal processing methods, communication devices, communication systems, and storage media. These will be described in detail below.

[0088] The following provides examples illustrating the application scenarios of embodiments of this application.

[0089] like Figure 1 As shown, the digital communication system 100 includes at least two communication devices (a first communication device 110 and a second communication device 120) and a channel 130. Taking the transmission of information (a digital signal transmitted between devices in the form of an analog signal) from the first communication device 110 to the second communication device 120 as an example, the first communication device 110 acts as a transmitter, and the second communication device 120 acts as a receiver. The transmitter's function is to load the information to be transmitted onto a suitable carrier and transmit it. The channel 130's function is to transmit the carrier loaded with information from the transmitter to the receiver. The receiver's function is to receive the carrier carrying information and recover the required information from it. Specifically, in the transmitter, the digital signal to be transmitted is converted into an analog signal after digital signal processing and digital-to-analog conversion, and then modulated onto a carrier wave and transmitted to the receiver through the channel for reception. The receiver demodulates the received signal to obtain an analog signal, which is then converted back into a digital signal after analog-to-digital conversion, and then processed again to obtain the final received digital signal.

[0090] It is understandable that the first communication device 110 can also perform the functions of a receiver, and the second communication device 120 can also perform the functions of a transmitter, that is, the second communication device 120 can also transmit digital signals to the first communication device 110.

[0091] Specifically, the transmitter includes a digital signal source 111, a first digital signal processing (DSP) chip 112, a digital-to-analog converter (DAC) 113, and a modulator 114. The first DSP chip 112 performs digital signal processing on the digital signal generated by the digital signal source. The DAC 113 converts the digital signal processed by the first DSP chip 112 into an analog signal. The modulator 114 loads the analog signal onto a carrier wave and transmits it. Channel 130 transmits the signal from the transmitter to the receiver. For example, in an optical fiber coherent communication system, the modulator 114 loads the analog signal onto a carrier wave to obtain an optical signal. Channel 130 is an optical fiber link, and the optical signal is transmitted to the receiver through the optical fiber link. The receiver includes a demodulator 121, an analog-to-digital converter 114, and a digital signal processing (DSP) chip 112. The system comprises a demodulator 121 (ADC) 122, a second digital signal processing chip 123, and a receiving module 124. The demodulator 121 demodulates the signal to obtain an analog signal, the analog-to-digital converter 122 performs analog-to-digital conversion on the analog signal to obtain a digital signal, the second digital signal processing chip 123 performs digital signal processing on the digital signal, and the signal is sent to the receiving module 124 to obtain the final received digital signal.

[0092] In the aforementioned communication process, the DSP chips in the transmitter and receiver employ methods including, but not limited to, encoding / decoding, equalization, and nonlinear compensation to process the digital signal, enabling more accurate transmission of information from the transmitter to the receiver. The digital signal is specifically represented in the DSP chip as a sequence of numbers arranged in chronological order; therefore, a digital signal can also be understood as a sequence. The DSP chip includes multiple DSP submodules, each designed with different processing parameters to address one or more specific channel impairments, thereby compensating for the corresponding channel impairments. Therefore, the architecture of the entire DSP chip can be designed to optimize its digital signal processing performance.

[0093] The following examples illustrate the digital signal processing chip provided in the embodiments of this application, using the aforementioned application scenarios as examples.

[0094] like Figure 2 As shown in the embodiment of the digital signal processing chip provided in this application, the digital signal processing chip 200 includes a first signal processing unit 201, a second signal processing unit 202, and a parameter determination unit 203.

[0095] The first signal processing unit 201 is used to process the first input digital signal according to the first processing parameters to obtain a first output digital signal; the second signal processing unit 202 is used to process the second input digital signal according to the second processing parameters to obtain a second output digital signal, wherein the second input digital signal is the first output digital signal; the parameter determination unit 203 is used to process the second output digital signal and the reference digital signal based on a global cost function to obtain a first update parameter, wherein the global cost function is used to determine the difference between the second output digital signal and the reference digital signal; the second signal processing unit 202 is also used to update the second processing parameter according to the first update parameter, and / or the first signal processing unit 201 is also used to update the first processing parameter according to the second update parameter, wherein the second update parameter is determined by the second signal processing unit 202 based on the first update parameter and the second input digital signal.

[0096] After the first input digital signal is input to the digital signal processing chip 200, it is processed by the first signal processing unit 201 and the second signal processing unit 202 to obtain a second output digital signal, which serves as the final output digital signal of the digital signal processing chip 200. Furthermore, the second output digital signal is also input to the parameter determination unit 203, causing the parameter determination unit 203 to determine a first update parameter and transmit it back to the second signal processing unit 202. The second signal processing unit 202 can also determine a second update parameter based on the first update parameter and the second input digital signal, and continue to transmit it back to the first signal processing unit 201. Similarly, when there are multiple first signal processing units 201, each first signal processing unit 201 can also determine a third update parameter and continue to transmit it back.

[0097] Specifically, the global cost function J is used to determine the difference between the input digital signal s and the reference digital signal d, where the input digital signal s is the final output digital signal of the digital signal processing chip, i.e., the second output digital signal, and the parameter digital signal d is the target that the second output digital signal needs to achieve. Then:

[0098] J = e(s,d)

[0099] Here, e represents a function that evaluates the difference between the input digital signal s and the reference digital signal d. The function e can be designed according to the actual application scenario and requirements. For example, the function e can be the mean square error function or the cross-entropy function, etc.

[0100] The parameter determination unit 203 can obtain the first update parameter g by processing the second output digital signal s and the reference digital signal d based on the global cost function J. out ,have:

[0101]

[0102] Furthermore, the first signal processing unit can be either a dynamic signal processing unit or a static signal processing unit, and the second signal processing unit can also be either a dynamic signal processing unit or a static signal processing unit. Therefore, a digital signal processing chip has the following three possible implementation methods:

[0103] Implementation method 1:

[0104] When the first signal processing unit is a dynamic signal processing unit and the second signal processing unit is a static signal processing unit, the first signal processing unit is further used to update the first processing parameter according to the second update parameter, wherein the second update parameter is determined by the second signal processing unit according to the first update parameter and the second input digital signal;

[0105] Implementation method 2:

[0106] When the first signal processing unit is a static signal processing unit and the second signal processing unit is a dynamic signal processing unit, the second signal processing unit is also used to update the second processing parameters according to the first update parameters;

[0107] Implementation method 3:

[0108] When both the first signal processing unit and the second signal processing unit are dynamic signal processing units, the second signal processing unit is further configured to update the second processing parameter according to the first update parameter, and the first signal processing unit is further configured to update the first processing parameter according to the second update parameter.

[0109] The dynamic signal processing unit and the static signal processing unit are described below:

[0110] I. Dynamic Signal Processing Unit

[0111] like Figure 3 As shown, the dynamic signal processing unit 300 includes a signal processing module 301, a parameter update module 302, a buffer module 303, and a reverse parameter determination module 304. The signal processing module 301, the parameter update module 302, and the buffer module 303 can communicate with each other, and the buffer module 303 also communicates with the reverse parameter determination module 304.

[0112] Specifically, the signal processing module 301 processes the input digital signal according to the processing parameters to obtain the output digital signal. The processing function of the signal processing module 301 can be described as a differentiable generalized function. For example, if the input digital signal is x, the processing parameter is w, and the output digital signal is y, then:

[0113] y = f(w, w * ,x,x * )

[0114] Where f represents a generalized function, the superscript * represents the complex conjugate, the processing parameter w is obtained from the parameter update module 302, the generalized function f and the initial processing parameter w can be designed according to the actual application scenario and requirements, after the signal processing module 301 processes the output digital signal y, it is also necessary to store the input digital signal x and the output digital signal y into the buffer module 303.

[0115] The reverse parameter determination module 304 is used to update parameter g based on the input. in The output update parameter g is determined by the input digital signal x. out ,have:

[0116] And the output update parameter g out Defined as the derivative of the global cost function J with respect to the input digital signal x, then:

[0117]

[0118] Wherein, function f x The inverse parameter determination module 304 calculates the required data, such as the processing parameter w and the input digital signal x, which represent the partial derivatives of the generalized function f with respect to the input digital signal x. This data can be obtained from the buffer module 303. When the inverse parameter determination module 304 obtains the output update parameter g... out Then, the update parameter g will be input. in and output update parameter g out Stored in cache module 303.

[0119] The parameter update module 302 is used to update processing parameters, including:

[0120] w new =u(w old ,x,y,g in )

[0121] Where u represents the generalized function used to update the processing parameters, w old For the old processing parameters, w new The generalized function u can be designed according to the actual application scenario and requirements to update the processing parameters. The parameter update module 302 calculates the required data, i.e., the old processing parameters w. old Input digital signal x, output digital signal y, and input update parameter g in It can be obtained from the cache module 303, when the parameter update module 302 obtains the updated processing parameter w. new Then, update the processing parameters w new It is provided to the signal processing module 301 for use and stored in the cache module 303.

[0122] Optionally, the parameter update module 302 may not use the input update parameter g. in To update, you will see:

[0123] w new =u(w old (x,y)

[0124] Update parameter g without using input in When updating processing parameters, information is extracted only from the input digital signal x and the output digital signal y for updating. This method can be used to compensate for channel impairments that rely on the statistical characteristics of the signal, such as sampling clock deviation compensation, thereby simplifying the updating of processing parameters. It can also be used for pre-convergence of processing parameters.

[0125] II. Static Signal Processing Unit

[0126] like Figure 4 As shown, the static signal processing unit 400 includes a signal processing module 401, a buffer module 402, and an inverse parameter determination module 403. The signal processing module 401 and the buffer module 402 communicate with each other, and the buffer module 402 also communicates with the inverse parameter determination module 403.

[0127] The difference between the static signal processing unit 400 and the dynamic processing unit is that the static signal processing unit 400 does not have a parameter update module, and the processing parameters in the signal processing module 401 are fixed. The remaining structure and implementation can be referred to the dynamic signal processing unit, and will not be described again in this embodiment.

[0128] The three implementation methods described above are described in detail below:

[0129] Implementation method 1:

[0130] like Figure 5 As shown, in the digital signal processing chip 500, the first signal processing unit 510 includes a first signal processing module 511, a first parameter update module 512, a first cache module 513, and a first inverse parameter determination module 514; the second signal processing unit 520 includes a second signal processing module 521, a second cache module 522, and a second inverse parameter determination module 523. The first signal processing unit 510 and the second signal processing unit 520 communicate with each other, and the second signal processing unit 520 and the parameter determination unit 530 communicate with each other.

[0131] The first signal processing module 511 processes the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first parameter update module 512 updates the first processing parameters according to the second update parameters; the first inverse parameter determination module 514 determines a third update parameter according to the second update parameters and the first input digital signal; and the first buffer module 513 stores the first input digital signal, the first output digital signal, the first processing parameters, the second update parameters, and the third update parameters. The second signal processing module 521 processes the second input digital signal according to the second processing parameters to obtain a second output digital signal; the second inverse parameter determination module 523 determines a second update parameter according to the first update parameters and the second input digital signal; and the second buffer module 522 stores the second input digital signal, the second output digital signal, the second processing parameters, the first update parameters, and the second update parameters.

[0132] The specific implementation of the first signal processing unit 510 can be referred to the foregoing description of the dynamic signal processing unit, and the specific implementation of the second signal processing unit 520 can be referred to the foregoing description of the static signal processing unit, and will not be repeated here.

[0133] Implementation method 2:

[0134] like Figure 6 As shown, in the digital signal processing chip 600, the first signal processing unit 610 includes a first signal processing module 611, a first buffer module 612, and a first inverse parameter determination module 613; the second signal processing unit 620 includes a second signal processing module 621, a second parameter update module 622, a second buffer module 623, and a second inverse parameter determination module 624. The first signal processing unit 610 and the second signal processing unit 620 communicate with each other, and the second signal processing unit 620 and the parameter determination unit 630 communicate with each other.

[0135] The first signal processing module 611 processes the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first inverse parameter determination module 613 determines a third update parameter according to the second update parameter and the first input digital signal; and the first buffer module 612 stores the first input digital signal, the first output digital signal, the first processing parameters, the second update parameter, and the third update parameter. The second signal processing module 621 processes the second input digital signal according to the second processing parameters to obtain a second output digital signal; the second parameter update module 622 updates the second processing parameters according to the first update parameter; the second inverse parameter determination module 624 determines a second update parameter according to the first update parameter and the second input digital signal; and the second buffer module 623 stores the second input digital signal, the second output digital signal, the second processing parameters, the first update parameter, and the second update parameter.

[0136] The specific implementation of the second signal processing unit 620 can be referred to the foregoing description of the dynamic signal processing unit, and the specific implementation of the first signal processing unit 610 can be referred to the foregoing description of the static signal processing unit, and will not be repeated here.

[0137] Implementation method 3:

[0138] like Figure 7 As shown, in the digital signal processing chip 700, the first signal processing unit 710 includes a first signal processing module 711, a first parameter update module 712, a first buffer module 713, and a first inverse parameter determination module 714; the second signal processing unit 720 includes a second signal processing module 721, a second parameter update module 722, a second buffer module 723, and a second inverse parameter determination module 724. The first signal processing unit 710 and the second signal processing unit 720 communicate with each other, and the second signal processing unit 720 and the parameter determination unit 730 communicate with each other.

[0139] The first signal processing module 711 processes the first input digital signal according to the first processing parameters to obtain a first output digital signal; the first parameter update module 712 updates the first processing parameters according to the second update parameters; the first inverse parameter determination module 714 determines a third update parameter according to the second update parameters and the first input digital signal; and the first buffer module 713 stores the first input digital signal, the first output digital signal, the first processing parameters, the second update parameters, and the third update parameters. The second signal processing module 721 processes the second input digital signal according to the second processing parameters to obtain a second output digital signal; the second parameter update module 722 updates the second processing parameters according to the first update parameters; the second inverse parameter determination module 724 determines a second update parameter according to the first update parameters and the second input digital signal; and the second buffer module 723 stores the second input digital signal, the second output digital signal, the second processing parameters, the first update parameters, and the second update parameters.

[0140] The specific implementation of the first signal processing unit 710 and the second signal processing unit 720 can be referred to the foregoing description of the dynamic signal processing unit, and will not be repeated here.

[0141] Optionally, there may be multiple first signal processing units, and the digital signal processing chip may further include a decision unit. For example, such as... Figure 8 As shown, in the digital signal processing chip 800, two first signal processing units 801 communicate with each other and both communicate with the second signal processing unit 802. The second signal processing unit 802 communicates with the parameter determination unit 803. The decision unit 804 communicates with the parameter determination unit 803 and the second signal processing unit 802 respectively.

[0142] The two first signal processing units 801 and the second signal processing unit 802 are respectively used to compensate for different channel impairments, and the decision unit 804 is used to make a decision on the second output digital signal to obtain a reference digital signal.

[0143] Optionally, the second signal processing unit is used to implement the function of the decision unit mentioned above, and the decision unit is not set up separately in the digital signal processing chip.

[0144] Optionally, the reference digital signal can be a training sequence obtained from training, generated by the decision unit, or manually set by the user; this application embodiment does not limit this.

[0145] After processing the input digital signal, the digital signal processing chip provided in this application embodiment needs to iterate in reverse according to the first update parameter determined by the parameter determination unit to generate new update parameters, and update the processing parameters of the first signal processing unit and / or the second signal processing unit until the second output digital signal and the reference digital signal are the same or different and meet the user's needs. Then the digital signal processing chip can be put into actual use. At this time, the second output digital signal is used as the digital signal finally received by the digital signal processing chip.

[0146] The following two examples illustrate the digital signal processing chip provided in the embodiments of this application.

[0147] Example 1

[0148] like Figure 9A As shown, in the digital signal processing chip used as a receiver in a coherent optical communication system, the digital signal processing chip 900 includes seven first signal processing units 901, second signal processing units 902, parameter determination units 903, and decision units 904.

[0149] Specifically, the seven first signal processing units are a clock recovery dynamic signal processing unit, a receiver nonlinearity compensation dynamic signal processing unit, a receiver linear compensation dynamic signal processing unit, a dispersion compensation static signal processing unit, a polarization demultiplexing dynamic signal processing unit, a carrier recovery dynamic signal processing unit, and a transmitter linear compensation dynamic signal processing unit. The second signal processing unit is a transmitter nonlinearity compensation dynamic signal processing unit. Among them, the dispersion compensation static signal processing unit is a static signal processing unit, and the rest are dynamic signal processing units. The specific implementation of each unit in the digital signal processing chip can be referred to the corresponding part above, and will not be repeated here.

[0150] After the input digital signal is sent to the clock recovery dynamic signal processing unit, it is processed sequentially by the first signal processing unit 901 and the second signal processing unit 902. Based on the first update parameters determined by the parameter determination unit 903, the processing parameters of the first signal processing unit 901 and the second signal processing unit 902 are updated in reverse iteration until the second output digital signal and the reference digital signal are the same or different and meet the user's requirements. Then the digital signal processing chip 900 can be put into practical use. The input digital signal can come from the analog-to-digital conversion unit or it can be a signal processed by other digital signal processing chips. That is, the digital signal processing chip provided in this application embodiment can be used in combination with other digital signal processing chips.

[0151] The clock recovery dynamic signal processing unit is used to compensate for clock impairments. It processes the input digital signal using frequency domain clock compensation algorithms or classical clock recovery algorithms (such as the Godard algorithm), and its parameter update module updates the processing parameters using the input update parameters. The receiver nonlinearity compensation dynamic signal processing unit is used to compensate for the nonlinear effects of the receiver devices. It processes the input digital signal using the Volterra equalization algorithm, and its parameter update module updates the processing parameters using the input update parameters. The receiver linearity compensation dynamic signal processing unit is used to compensate for the linear effects of the receiver devices. It employs a time-domain adaptive multiple-input multiple-output (MIMO) algorithm. Multiple-out (MIMO) equalization algorithms or frequency-domain adaptive MIMO equalization algorithms are used to process the input digital signal, and their parameter update modules use the input update parameters to update the processing parameters. A dispersion compensation static signal processing unit is used to compensate for the dispersion of the fiber optic link, using time-domain or frequency-domain dispersion compensation algorithms to process the input digital signal. A polarization demultiplexing dynamic signal processing unit is used to compensate for polarization effects, using time-domain or frequency-domain adaptive MIMO equalization algorithms to process the input digital signal, and its parameter update module uses the input update parameters to update the processing parameters. A carrier recovery dynamic signal processing unit is used to compensate for the frequency offset and phase noise of the coherent received local oscillator and carrier, using carrier and phase compensation algorithms to process the input digital signal. Its parameter update module updates the processing parameters using input update parameters, or it uses classic phase recovery algorithms (such as blind phase search algorithms and pilot-based phase recovery algorithms) to process the input digital signal. Its parameter update module does not use input update parameters to update the processing parameters. The transmitter linear compensation dynamic signal compensation unit compensates for the linear effects of the transmitter devices, using time-domain adaptive MIMO equalization algorithms or frequency-domain adaptive MIMO equalization algorithms to process the input digital signal. Its parameter update module uses input update parameters to update the processing parameters. The transmitter nonlinear compensation dynamic signal processing unit compensates for the nonlinear effects of the transmitter devices, using the Volterra equalization algorithm to process the input digital signal. Its parameter update module uses input update parameters to update the processing parameters.

[0152] The parameter determination module 903 uses the squared error function as the global cost function, then:

[0153] J = |sd| 2

[0154] Where s is the second output digital signal output by the nonlinear compensation dynamic signal processing unit, and d is the reference digital signal obtained by the decision unit after making a decision on the second output digital signal s.

[0155] Example 2

[0156] like Figure 9B As shown, in the digital signal processing chip used as the receiver in the direct modulation and direct detection optical communication system, the digital signal processing chip 910 includes four first signal processing units 911, second signal processing units 912, and parameter determination units 913.

[0157] Specifically, the four first signal processing units 911 are a clock recovery dynamic signal processing unit, a linear equalization dynamic signal processing unit, a nonlinear equalization dynamic signal processing unit, and a sequence detection dynamic signal processing unit, respectively. The second signal processing unit 912 is a decision dynamic signal processing unit. Both the first signal processing unit 911 and the second signal processing unit 912 are dynamic signal processing units. The specific implementation of each unit in the digital signal processing chip can be referred to the corresponding part above, and will not be repeated here.

[0158] The clock recovery dynamic signal processing unit is used to compensate for clock impairment. It uses clock compensation methods such as fractional delay filters or classical clock recovery algorithms (such as the Mueller-Muller algorithm) to process the input digital signal. Its parameter update module updates the processing parameters using the input update parameters.

[0159] The linear equalization dynamic signal processing unit is used to compensate for the linearity effect of the channel. It uses time-domain equalization algorithms to process the input digital signal, and its parameter update module uses the input update parameters to update the processing parameters.

[0160] The nonlinear equalization dynamic signal processing unit is used to compensate for the nonlinear effects of the channel. It uses time-domain nonlinear equalization algorithms to process the input digital signal, and its parameter update module uses the input update parameters to update the processing parameters.

[0161] The sequence detection dynamic signal processing unit is used to compensate for inter-symbol crosstalk. It uses classical sequence detection algorithms (such as the Viterbi-Viterbi algorithm) or machine learning-based sequence detection algorithms to process the input digital signal. Its parameter update module can update the processing parameters with or without using the input update parameters according to the actual situation.

[0162] The decision dynamic signal processing unit is used to make decisions on the input digital signal. It uses classical soft decision or machine learning-based decision methods to process the input digital signal. Its parameter update module does not use the input update parameters to update the processing parameters.

[0163] If parameter determination unit 913 uses the squared error function as the global cost function, then:

[0164] J = |sd| 2

[0165] Where s is the second output digital signal of the decision dynamic signal processing unit, and d is the training sequence input by the user as a reference digital signal.

[0166] like Figure 10 As shown, when the digital signal processing chip provided in this application embodiment is used in the receiver of a coherent optical communication system, it can achieve a lower bit error ratio (BER) and better receiving sensitivity compared to the digital signal processing chip in the receiver of the prior art.

[0167] As can be seen from the above embodiments, the beneficial effects brought about by the embodiments of this application include, but are not limited to, the following (1) to (3).

[0168] (1) The multiple signal processing units in the digital signal processing chip are coupled together. After multiple iterations of optimization of processing parameters and update parameters, the processing parameters of the sub-modules in the digital signal processing chip can be adaptively adjusted to ensure the channel impairment compensation effect of each sub-module in the digital signal processing chip, thereby ensuring the optimal global channel impairment compensation effect of the entire digital signal processing chip.

[0169] (2) The processing parameters and update parameters can be automatically iterated and updated, reducing the dependence of the performance of the digital signal processing chip on channel impairment calibration and reducing the workload of determining calibration parameters.

[0170] (3) The processing parameters and update parameters can be automatically iterated and updated. When the signal processing unit in the digital signal processing chip needs to be adjusted, the corresponding signal processing unit can be added or removed to achieve the adjustment without adjusting the parameters, thus reducing the difficulty of optimizing the overall digital signal processing chip after expansion.

[0171] The following example illustrates the communication device provided in the embodiments of this application, using the aforementioned digital signal processing chip as an example.

[0172] like Figure 11 As shown, in one embodiment of the communication device provided in this application, the communication device includes as follows: Figures 2-10 The digital signal processing chip described.

[0173] Specifically, the communication device 1100 can be used as a transmitter 1110 or a receiver 1120 during the communication process.

[0174] In the transmitter 1110 portion, the communication device 1100 includes a digital signal source 1111, a first signal processing chip 1112, a digital-to-analog converter 1113, and a modulator 1114, wherein the first signal processing chip 1112 is... Figures 2-10The described digital signal processing chip can perform digital signal processing on digital signals generated by digital signal sources. The digital-to-analog converter 1113 converts the digital signal processed by the first signal processing chip 1112 into an analog signal, and the modulator 1114 loads the analog signal onto a carrier wave and transmits it.

[0175] In the receiver 1120 portion, the communication device 1100 includes a demodulator 1124, an analog-to-digital converter 1123, a second signal processing chip 1122, and a receiving module 1121. The demodulator 1124 demodulates the signal to obtain an analog signal, the analog-to-digital converter 1123 performs analog-to-digital conversion on the analog signal to obtain a digital signal, and the second signal processing chip 1122... Figures 2-10 The described digital signal processing chip can perform digital signal processing on digital signals and send them to the receiving module 1121 to obtain the final received digital signal.

[0176] It is understandable that the communication device may also include only the transmitter part, which is used only to realize the function of the transmitter, or it may include only the receiver part, which is used only to realize the function of the receiver.

[0177] The communication system provided in the embodiments of this application will be illustrated below with reference to the aforementioned digital signal processing chip and communication equipment.

[0178] like Figure 12 As shown in the embodiment of the communication system provided in this application, the communication system 1200 includes a transmitter 1210 and a receiver 1220.

[0179] Specifically, the transmitter 1210 includes a first signal processing unit 1211, a digital-to-analog conversion unit 1212, and a modulation unit 1213, while the receiver 1220 includes a demodulation unit 1221, an analog-to-digital conversion unit 1222, a second signal processing unit 1223, a third signal processing unit 1224, and a parameter determination unit 1225.

[0180] The system includes a first signal processing unit 1211 for processing a first input digital signal according to first processing parameters to obtain a first output digital signal; a digital-to-analog conversion unit 1212 for performing digital-to-analog conversion on the first output digital signal to obtain a first analog signal; a modulation unit 1213 for modulating the first analog signal onto a carrier wave to obtain a modulated signal, and sending the modulated signal to a demodulation unit 1221 through a channel; a demodulation unit 1221 for demodulating the modulated signal to obtain a second analog signal; and an analog-to-digital conversion unit 1222 for performing analog-to-digital conversion on the second analog signal to obtain a digital signal. The second signal processing unit 1223... The second signal processing unit 1224 is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal, wherein the second input digital signal is the digital signal converted by the analog-to-digital converter 1222; the third signal processing unit 1224 is used to process the third input digital signal according to the third processing parameters to obtain the third output digital signal, wherein the third input digital signal is the second output digital signal; the parameter determination unit 1225 is used to process the third output digital signal and the reference digital signal based on the global cost function to obtain the first update parameter, wherein the global cost function is used to determine the difference between the third output digital signal and the reference digital signal.

[0181] It is understood that the first signal processing unit 1211 is the digital signal processing chip in the transmitter 1210, and the second signal processing unit 1223, the third signal processing unit 1224 and the parameter determination unit 1225 are the digital signal processing chips in the receiver 1220.

[0182] Furthermore, the second signal processing unit 1223 can be either a dynamic signal processing unit or a static signal processing unit, and the third signal processing unit 1224 can also be either a dynamic signal processing unit or a static signal processing unit. Therefore, the digital signal processing chip of the receiver 1220 has the following three possible implementations:

[0183] Implementation method 1:

[0184] When the second signal processing unit is a dynamic signal processing unit and the third signal processing unit is a static signal processing unit, the second signal processing unit is further used to update the second processing parameters according to the second update parameters, wherein the second update parameters are determined by the third signal processing unit according to the first update parameters and the third input digital signal.

[0185] For specific details, please refer to the following: Figure 5 The digital signal processing chip shown has a second signal processing unit comprising a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module, and a third signal processing unit comprising a third signal processing module, a third buffer module, and a third inverse parameter determination module.

[0186] The second signal processing module processes the second input digital signal according to the second processing parameters to obtain a second output digital signal; the second parameter update module updates the second processing parameters according to the second update parameters; the second inverse parameter determination module determines a third update parameter according to the second update parameters and the second input digital signal; and the second buffer module stores the second input digital signal, the second output digital signal, the second processing parameters, the second update parameters, and the third update parameters. The third signal processing module processes the third input digital signal according to the third processing parameters to obtain a third output digital signal; the third inverse parameter determination module determines the second update parameters according to the first update parameters and the third input digital signal; and the third buffer module stores the third input digital signal, the third output digital signal, the third processing parameters, the first update parameters, and the second update parameters.

[0187] The specific implementation of the second signal processing unit can be referred to the aforementioned description of the dynamic signal processing unit, and the specific implementation of the third signal processing unit can be referred to the aforementioned description of the static signal processing unit, and will not be repeated here.

[0188] Implementation method 2:

[0189] When the second signal processing unit is a static signal processing unit and the third signal processing unit is a dynamic signal processing unit, the third signal processing unit is also used to update the third processing parameters according to the first update parameters.

[0190] For specific details, please refer to the following: Figure 6 The digital signal processing chip shown has a second signal processing unit comprising a second signal processing module, a second buffer module, and a second inverse parameter determination module, and a third signal processing unit comprising a third signal processing module, a third parameter update module, a third buffer module, and a third inverse parameter determination module.

[0191] The second signal processing module processes the second input digital signal according to the second processing parameters to obtain a second output digital signal; the second inverse parameter determination module determines a third update parameter according to the second update parameter and the second input digital signal; and the second buffer module stores the second input digital signal, the second output digital signal, the second processing parameters, the second update parameter, and the third update parameter. The third signal processing module processes the third input digital signal according to the third processing parameters to obtain a third output digital signal; the third parameter update module updates the third processing parameters according to the first update parameter; the third inverse parameter determination module determines a second update parameter according to the first update parameter and the third input digital signal; and the third buffer module stores the third input digital signal, the third output digital signal, the third processing parameters, the first update parameter, and the second update parameter.

[0192] The specific implementation of the third signal processing unit can be referred to the aforementioned description of the dynamic signal processing unit, and the specific implementation of the second signal processing unit can be referred to the aforementioned description of the static signal processing unit, and will not be repeated here.

[0193] Implementation method 3:

[0194] When both the second signal processing unit and the third signal processing unit are dynamic signal processing units, the third signal processing unit is further used to update the third processing parameter according to the first update parameter, and the second signal processing unit is further used to update the second processing parameter according to the second update parameter.

[0195] For specific details, please refer to the following: Figure 7 The digital signal processing chip shown has a second signal processing unit comprising a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module, and a third signal processing unit comprising a third signal processing module, a third parameter update module, a third buffer module, and a third inverse parameter determination module.

[0196] The third signal processing module is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal; the second parameter update module is used to update the second processing parameters according to the second update parameters; the second inverse parameter determination module is used to determine the third update parameters according to the second update parameters and the second input digital signal; and the second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameters, the second update parameters, and the third update parameters. The third signal processing module is used to process the third input digital signal according to the third processing parameters to obtain the third output digital signal; the third parameter update module is used to update the third processing parameters according to the first update parameters; the third inverse parameter determination module is used to determine the second update parameters according to the first update parameters and the third input digital signal; and the third buffer module is used to store the third input digital signal, the third output digital signal, the third processing parameters, the first update parameters, and the second update parameters.

[0197] The specific implementation methods of the second signal processing unit and the third signal processing unit can be referred to the foregoing description of the dynamic signal processing unit, and will not be repeated here.

[0198] Optionally, the communication system further includes a channel model unit, which is used to determine a fourth update parameter based on the first output digital signal and the third update parameter, and send the fourth update parameter to the first signal processing unit. The third update parameter is determined by the second signal processing unit based on the second update parameter and the second input digital signal. The first signal processing unit is also used to determine a fifth update parameter based on the fourth update parameter and the first input digital signal.

[0199] The channel model unit communicates with the first signal processing unit in the transmitter and the second signal processing unit in the receiver. Specifically, the channel model unit processes the first output digital signal according to the channel model parameters to obtain the channel model signal, and determines the fourth update parameter according to the channel model signal and the third update parameter.

[0200] Specifically, such as Figure 13 As shown, the channel model unit 1300 includes a channel model module 1301, a channel buffer module 1302, and a channel inversion parameter determination module 1303. The channel model module 1301 is used to process the first output digital signal according to the channel model parameters to obtain the channel model signal; the channel inversion parameter determination module 1303 is used to determine the fourth update parameter according to the channel model signal and the third update parameter; the channel buffer module 1302 is used to store the first output digital signal, the channel model signal, the channel model parameters, the third update parameter, and the fourth update parameter.

[0201] The channel model module 1301 can be described by a generalized function c, then:

[0202] y = c(p,x,x) * )

[0203] Where x represents the first output digital signal, y represents the channel model signal (the channel model signal y does not need to be output), and p represents the channel model parameters, the processing procedure of the channel inverse parameter determination module 1303 can be described as follows:

[0204] g out =g in ×c x (p,x,x * )

[0205] Among them, g in g is the third update parameter input to the channel model unit from the receiver. out For the fourth update parameter, c x The partial derivative of the generalized function c with respect to the first output digital signal x is represented. The generalized function c and the channel model parameter p can be designed according to the characteristics and requirements of the actual channel. The data required for the channel model module 1301 to calculate, such as the first output digital signal, the channel model signal, the channel model parameters and the third update parameter, can be obtained from the channel buffer module 1302. The fourth update parameter obtained by the channel inverse parameter determination module 1303 needs to be stored in the channel buffer module 1302 and sent to the first signal processing unit.

[0206] During the calculation process of the channel inverse parameter determination module 1303, the channel model signal y obtained by the channel model module 1301 can be used, or the channel model signal y can be used to accelerate the calculation process. If the channel inverse parameter determination module 1303 does not need to use the channel model signal y, the channel model module 1301 may not process the first output digital signal.

[0207] It should be noted that the channel model unit 1301 can exist in hardware form, like other digital signal processing chips, such as digital circuits (e.g., field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) chips), or it can exist in software form, such as implementing the function of the channel model unit in a computer device. It can exist independently of the transmitter and receiver as a separate entity, or it can be integrated into the transmitter or receiver.

[0208] Furthermore, the first signal processing unit can be either a dynamic signal processing unit or a static signal processing unit. Therefore, based on the above three implementation methods, taking implementation method 3 as an example, the digital signal processing chip of the transmitter has the following two possible implementation methods:

[0209] Implementation method 4:

[0210] When the first signal processing unit is a dynamic signal processing unit, the first signal processing unit is also used to update the first processing parameter according to the fourth update parameter.

[0211] For specific details, please refer to the following: Figure 3 The dynamic signal processing unit shown includes a first signal processing module, a first parameter update module, a first buffer module, and a first inverse parameter determination module.

[0212] The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; the first parameter update module is used to update the first processing parameters according to the fourth update parameters; the first inverse parameter determination module is used to determine the fifth update parameters according to the fourth update parameters and the first input digital signal; and the first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameters, the fourth update parameters and the fifth update parameters.

[0213] The specific implementation of the first signal processing unit can be found in the foregoing description of the dynamic signal processing unit, and will not be repeated here.

[0214] Implementation method 5:

[0215] When the first signal processing unit is a static signal processing unit, the first signal processing unit does not update the first processing parameters.

[0216] For specific details, please refer to the following: Figure 4 The static signal processing unit shown includes a first signal processing module, a first buffer module, and a first inverse parameter determination module.

[0217] The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; the first inverse parameter determination module is used to determine the fifth update parameter according to the fourth update parameter and the first input digital signal; and the first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameters, the fourth update parameter and the fifth update parameter.

[0218] The specific implementation of the first signal processing unit can be referred to the foregoing description of the static signal processing unit, and will not be repeated here.

[0219] Optionally, there are multiple first signal processing units and multiple second signal processing units. The communication system also includes a channel modeling unit and a decision unit. For example, such as... Figure 14 As shown, in the communication system 1400, in the transmitter 1410, two first signal processing units 1411 communicate with each other and are also in communication with the digital-to-analog conversion unit 1412 and the modulation unit 1413. In the receiver 1420, the demodulation unit 1421 and the analog-to-digital conversion unit 1422 communicate with each other. The analog-to-digital conversion unit 1422 and the second signal processing unit 1423 communicate with each other. The two second signal processing units 1423 communicate with each other and are also in communication with the third signal processing unit 1424. The third signal processing unit 1424 communicates with the parameter determination unit 1425. The decision unit 1426 communicates with the parameter determination unit 1425 and the third signal processing unit 1424 respectively. The second signal processing unit 1423 also communicates with the first signal processing unit 1411 through the channel model unit 1430.

[0220] Among them, the two first signal processing units 1411 are used to compensate for different channel impairments in the transmitter 1410, the two second signal processing units 1423 and the third signal processing unit 1424 are used to compensate for different channel impairments in the receiver 1420, and the decision unit 1426 is used to make a decision on the third output digital signal to obtain a reference digital signal.

[0221] Optionally, the second signal processing unit is used to implement the functions of the decision unit mentioned above, and no separate decision unit is set up in the communication system.

[0222] Optionally, the reference digital signal can be a training sequence obtained from training, generated by the decision unit, or manually set by the user; this application embodiment does not limit this.

[0223] Optionally, the transmitter in this communication system can also be used for, for example Figure 11 The described communication device is used to implement the function of a transmitter, and the receiver can also be as follows: Figure 11 The described communication device is used to implement the function of a receiver. The digital signal processing chip in the communication device can be referred to the description of the corresponding part of the foregoing embodiments, and will not be repeated here.

[0224] After the digital signal processing chip in the transmitter processes the digital signal, it is transmitted to the receiver via the channel through digital-to-analog conversion and modulation. The receiver demodulates and converts the received signal to analog-to-digital to obtain a digital signal. After processing the digital signal, the digital signal processing chip in the receiver needs to iterate in reverse according to the first update parameter determined by the parameter determination unit to generate new update parameters and update the processing parameters of the first signal processing unit, the second signal processing unit and / or the third signal processing unit until the third output digital signal and the reference digital signal are the same or different and meet the user's requirements. At this time, the communication system can be put into actual use. The third output digital signal is taken as the digital signal finally received by the receiver in the communication system.

[0225] The following two examples illustrate the digital signal processing chip provided in the embodiments of this application.

[0226] Example 3

[0227] In a coherent optical communication system, the digital signal processing chip of the transmitter includes three first signal processing units, and the DSP chip of the receiver includes eight first signal processing units, second signal processing units, parameter determination units, and decision units.

[0228] For specific details, please refer to the following: Figure 12In the communication system shown, the digital signal processing chip of the transmitter has three first signal processing units: a transmitting-end nonlinear compensation static signal processing unit, a transmitting-end linear compensation static signal processing unit, and a quantization static signal processing unit. The digital signal processing chip of the receiver has eight second signal processing units: a clock recovery dynamic signal processing unit, a receiving-end nonlinear compensation dynamic signal processing unit, a receiving-end linear compensation dynamic signal processing unit, a dispersion compensation static signal processing unit, a polarization demultiplexing dynamic signal processing unit, a carrier recovery dynamic signal processing unit, a transmitting-end linear compensation dynamic signal compensation unit, and a transmitting-end nonlinear compensation dynamic signal processing unit. The third signal processing unit is a sequence detection dynamic signal processing unit. The three first signal processing units and the dispersion compensation static signal processing unit are static signal processing units, while the rest are dynamic signal processing units. Specific implementation methods for each unit in the digital signal processing chip can be found in the corresponding sections described above, and will not be repeated here.

[0229] After the first input digital signal generated by the transmitter is sent to the nonlinear compensation static signal processing unit at the transmitting end, it is processed by each of the aforementioned first signal processing units to obtain the first output digital signal. The first output digital signal is converted from digital to analog and modulated, and then sent to the receiver via the channel. The receiver demodulates and converts the received signal from analog to digital to obtain the second input digital signal. The second input digital signal is sent to the clock recovery dynamic signal processing unit, and then processed by each of the aforementioned second and third signal processing units to obtain the third output digital signal. The DSP chip in the receiver also needs to iterate in reverse according to the first update parameters determined by the parameter determination unit to generate new update parameters and update the processing parameters of the second and / or third signal processing units until the third output digital signal and the reference digital signal are the same or different and meet the user's requirements. At this point, the communication system can be put into practical use. The third output digital signal is then used as the final digital signal received by the receiver in the communication system.

[0230] In the transmitter, the transmitting-end nonlinear compensation static signal processing unit is used to pre-compensate the nonlinear effects of the transmitter devices. It uses the Volterra equalization algorithm to process the input digital signal, and its processing parameters are obtained through training and then fixed. The transmitting-end linear compensation static signal processing unit is used to pre-compensate the linear effects of the transmitter devices. It uses time-domain MIMO equalization algorithms or frequency-domain MIMO equalization algorithms to process the input digital signal, and its processing parameters are obtained through training and then fixed. The quantization static signal processing unit is used to quantize the signal and uses a quantization algorithm to process the input digital signal.

[0231] In the receiver, the sequence detection dynamic signal processing unit is used to perform sequence detection on the input digital signal. It employs classical sequence detection algorithms (such as maximum likelihood sequence estimation (MLSE)) or machine learning-based sequence detection algorithms to process the input digital signal. Its parameter update module can update the processing parameters with or without using the input update parameters. The specific functions and implementation of the second signal processing unit in the receiver can be found in the first and second signal processing units in Example 1, and will not be repeated here.

[0232] Since this communication system lacks a channel model unit, the input port of the inverse parameter determination module in the quantization static signal processing unit and the output port of the inverse parameter determination module in the clock recovery dynamic signal processing unit are left floating. It should be noted that a parameter determination unit can also be separately configured within the transmitter's digital signal processing chip. When a dynamic signal processing unit is included or expanded within the first signal processing unit, optimal global compensation can be achieved for the entire digital signal processing chip in the transmitter.

[0233] If the parameter determination unit uses the cross-entropy function as the global cost function, then:

[0234] J = ∑p(d)log(p(s))

[0235] Where s is the third output digital signal output by the sequence detection dynamic signal processing unit, d is the reference digital signal obtained by the decision unit after making a decision on the third output digital signal s, p(d) represents the probability of the reference digital signal, and p(s) represents the probability of the third output digital signal.

[0236] Example 4

[0237] In a coherent optical communication system, the transmitter's digital signal processing chip includes four first signal processing units, and the receiver's DSP chip includes nine first signal processing units, a second signal processing unit, a parameter determination unit, and a decision unit. The communication system also includes a channel modeling unit.

[0238] Based on Example 3, refer to, as follows Figure 14 The communication system shown has an additional encoding mapping dynamic signal processing unit in the first signal processing unit, an additional sequence detection dynamic signal processing unit in the second signal processing unit, and a de-mapping decoding dynamic signal processing unit in the third signal processing unit.

[0239] The encoding-mapping dynamic signal processing unit encodes and maps the input digital signal, employing a neural network-based encoding-mapping algorithm. Its parameter update module updates the processing parameters using the input update parameters. Similarly, the de-mapping-decoding dynamic signal processing unit de-maps and decodes the input digital signal, using a neural network-based de-mapping-decoding algorithm. Its parameter update module updates the processing parameters using the input update parameters.

[0240] The difference between this example and example 3 is that the input port of the inverse parameter determination module in the quantization static signal processing unit and the output port of the inverse parameter determination module in the clock recovery dynamic signal processing unit communicate with each other with the channel model unit. Furthermore, the quantization static signal processing unit also needs to send the first output digital signal to the channel model unit, and the channel model unit couples the digital signal processing chip in the transmitter and the digital signal processing chip in the receiver.

[0241] For details on the implementation of other units, please refer to Example 3. These details will not be repeated here.

[0242] As can be seen from the above embodiments, in addition to the beneficial effects of the digital signal processing chip, the embodiments of this application can also couple the digital signal processing chip of the transmitter and the digital signal processing chip of the receiver, realize more convenient joint optimization, and ensure the optimal global channel impairment compensation effect in the entire communication system.

[0243] The signal processing method provided in the embodiments of this application will be illustrated below with reference to the aforementioned digital signal processing chip.

[0244] like Figure 15 As shown, in one embodiment of the signal processing method provided in this application, the signal processing method is used in a digital signal processing chip, such as the digital signal processing chip provided in this application. The signal processing method includes:

[0245] S1501. The first input digital signal is processed according to the first processing parameters to obtain the first output digital signal.

[0246] S1502. The first output digital signal, which is the second input digital signal, is processed according to the second processing parameters to obtain the second output digital signal.

[0247] S1503. The first update parameter is obtained by processing the second output digital signal and the reference digital signal based on the global cost function.

[0248] The global cost function is used to determine the difference between the second output digital signal and the reference digital signal.

[0249] S1504. Update the second processing parameter according to the first update parameter, and / or update the first processing parameter according to the second update parameter.

[0250] The second update parameter is determined based on the first update parameter and the second input digital signal.

[0251] Optionally, the signal processing method further includes:

[0252] S1505. Make a decision on the second output digital signal to obtain a reference digital signal.

[0253] The specific implementation of the signal processing method provided in this application embodiment can be referred to the foregoing. Figures 2-10 The digital signal processing chip described herein has the same beneficial effects as the digital signal processing chip, and will not be elaborated further here.

[0254] The signal processing method provided in the embodiments of this application will be illustrated below with reference to the above-described communication system.

[0255] like Figure 16 As shown, in one embodiment of the signal processing method provided in this application, the signal processing method is used in a communication device, such as the communication system provided in this application. The signal processing method includes:

[0256] S1601. The first input digital signal is processed according to the first processing parameters to obtain the first output digital signal.

[0257] S1602. Perform digital-to-analog conversion on the first output digital signal to obtain the first analog signal.

[0258] S1603. Modulate the first analog signal onto the carrier wave to obtain the modulated signal.

[0259] S1604. Demodulate the modulated signal to obtain the second analog signal.

[0260] S1605. Perform analog-to-digital conversion on the second analog signal to obtain a digital signal.

[0261] S1606. The digital signal, which is the second input digital signal, is processed according to the second processing parameters to obtain the second output digital signal.

[0262] S1607. The second output digital signal, which is the third input digital signal, is processed according to the third processing parameters to obtain the third output digital signal.

[0263] S1608. The first update parameters are obtained by processing the third output digital signal and the reference digital signal based on the global cost function.

[0264] The global cost function is used to determine the difference between the third output digital signal and the reference digital signal.

[0265] S1609. Update the third processing parameter according to the first update parameter, and / or update the second processing parameter according to the second update parameter.

[0266] The second update parameter is determined by the third signal processing unit based on the first update parameter and the third input digital signal.

[0267] Optional, such as Figure 17 As shown, the signal processing method further includes:

[0268] S1701. Determine the fourth update parameter based on the first output digital signal and the third update parameter.

[0269] The third update parameter is determined by the second signal processing unit based on the second update parameter and the second input digital signal.

[0270] S1702. Determine the fifth update parameter based on the fourth update parameter and the first input digital signal.

[0271] S1703. Update the first processing parameter according to the fourth update parameter.

[0272] S1704. Make a decision on the second output digital signal to obtain a reference digital signal.

[0273] Optional, such as Figure 18 As shown, step S1701 specifically includes:

[0274] S1801. Process the first output digital signal according to the channel model parameters to obtain the channel model signal.

[0275] S1802. Determine the fourth update parameter based on the channel model signal and the third update parameter.

[0276] The specific implementation of the signal processing method provided in this application embodiment can be referred to the foregoing. Figures 12-14 The signal processing method has the same beneficial effects as the communication system described, and will not be elaborated further here.

[0277] In another embodiment of this application, a computer-readable storage medium is also provided, which stores a computer program. When at least one processor of the device executes the computer program, the device performs the above-described... Figure 15 The signal processing method described in some embodiments.

[0278] In another embodiment of this application, a computer-readable storage medium is also provided, which stores a computer program. When at least one processor of the device executes the computer program, the device performs the above-described... Figures 16 to 18 The signal processing method described in some embodiments.

[0279] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0280] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0281] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0282] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0283] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A digital signal processing chip, used in communication equipment, characterized in that, The digital signal processing chip includes a first signal processing unit, a second signal processing unit, and a parameter determination unit, wherein... The first signal processing unit is configured to process the first input digital signal according to the first processing parameters to obtain a first output digital signal, and send the first output digital signal as a second input digital signal to the second signal processing unit; The second signal processing unit is used to process the second input digital signal according to the second processing parameters to obtain a second output digital signal; The parameter determination unit is used to process the second output digital signal and the reference digital signal based on a global cost function to obtain a first update parameter. The global cost function is used to determine the difference between the second output digital signal and the reference digital signal. The second signal processing unit is further configured to update the second processing parameters according to the first update parameters, and / or The first signal processing unit is further configured to update the first processing parameter according to the second update parameter, wherein the second update parameter is determined by the second signal processing unit based on the first update parameter and the second input digital signal.

2. The chip according to claim 1, characterized in that, The first signal processing unit includes a first signal processing module, a first parameter update module, a first buffer module, and a first inverse parameter determination module, wherein, The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; The first parameter update module is used to update the first processing parameter according to the second update parameter; The first reverse parameter determination module is used to determine the third update parameter based on the second update parameter and the first input digital signal; The first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the second update parameter, and the third update parameter.

3. The chip according to claim 1, characterized in that, The first signal processing unit includes a first signal processing module, a first buffer module, and a first inverse parameter determination module, wherein, The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; The first reverse parameter determination module is used to determine the third update parameter based on the second update parameter and the first input digital signal; The first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the second update parameter, and the third update parameter.

4. The chip according to any one of claims 1-3, characterized in that, The second signal processing unit includes a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module, wherein, The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal; The second parameter update module is used to update the second processing parameter according to the first update parameter; The second inverse parameter determination module is used to determine the second update parameter based on the first update parameter and the second input digital signal; The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameters, the first update parameters, and the second update parameters.

5. The chip according to any one of claims 1-3, characterized in that, The second signal processing unit includes a second signal processing module, a second buffer module, and a second inverse parameter determination module, wherein, The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal; The second inverse parameter determination module is used to determine the second update parameter based on the first update parameter and the second input digital signal; The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameters, the first update parameters, and the second update parameters.

6. The chip according to any one of claims 1-3, characterized in that, Also includes: The decision unit is used to make a decision on the second output digital signal to obtain the reference digital signal.

7. The chip according to any one of claims 1-3, characterized in that, The first signal processing unit is a circuit structure in the digital signal processing chip, and the second signal processing unit is a circuit structure in the digital signal processing chip.

8. A communication device, characterized in that, Includes the digital signal processing chip as described in any one of claims 1-7.

9. A communication system, characterized in that, The system includes a transmitter and a receiver. The transmitter includes a first signal processing unit, a digital-to-analog conversion unit, and a modulation unit. The receiver includes a demodulation unit, an analog-to-digital conversion unit, a second signal processing unit, a third signal processing unit, and a parameter determination unit. The first signal processing unit is used to process the first input digital signal according to the first processing parameters to obtain a first output digital signal; The digital-to-analog conversion unit is used to perform digital-to-analog conversion on the first output digital signal to obtain a first analog signal; The modulation unit is used to modulate the first analog signal onto a carrier wave to obtain a modulated signal, and to send the modulated signal to the demodulation unit through a channel; The demodulation unit is used to demodulate the modulated signal to obtain a second analog signal; The analog-to-digital conversion unit is used to perform analog-to-digital conversion on the second analog signal to obtain a digital signal, and send the digital signal as a second input digital signal to the second signal processing unit; The second signal processing unit is used to process the second input digital signal according to the second processing parameters to obtain a second output digital signal, and send the second output digital signal as a third input digital signal to the third signal processing unit; The third signal processing unit is used to process the third input digital signal according to the third processing parameters to obtain a third output digital signal; The parameter determination unit is used to process the third output digital signal and the reference digital signal based on a global cost function to obtain the first update parameter, wherein the global cost function is used to determine the difference between the third output digital signal and the reference digital signal; The third signal processing unit is further configured to update the third processing parameters according to the first update parameters, and / or The second signal processing unit is further configured to update the second processing parameter according to the second update parameter, wherein the second update parameter is determined by the third signal processing unit based on the first update parameter and the third input digital signal.

10. The system according to claim 9, characterized in that, The second signal processing unit includes a second signal processing module, a second parameter update module, a second buffer module, and a second inverse parameter determination module, wherein, The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal; The second parameter update module is used to update the second processing parameter according to the second update parameter; The second reverse parameter determination module is used to determine the third update parameter based on the second update parameter and the second input digital signal; The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameter, the second update parameter, and the third update parameter.

11. The system according to claim 9, characterized in that, The second signal processing unit includes a second signal processing module, a second buffer module, and a second inverse parameter determination module, wherein, The second signal processing module is used to process the second input digital signal according to the second processing parameters to obtain the second output digital signal; The second reverse parameter determination module is used to determine the third update parameter based on the second update parameter and the second input digital signal; The second buffer module is used to store the second input digital signal, the second output digital signal, the second processing parameter, the second update parameter, and the third update parameter.

12. The system according to any one of claims 9-11, characterized in that, The third signal processing unit includes a third signal processing module, a third parameter update module, a third buffer module, and a third reverse parameter determination module, wherein... The third signal processing module is used to process the third input digital signal according to the third processing parameters to obtain the third output digital signal; The third parameter update module is used to update the third processing parameter according to the first update parameter; The third inverse parameter determination module is used to determine the second update parameter based on the first update parameter and the third input digital signal; The third buffer module is used to store the third input digital signal, the third output digital signal, the third processing parameter, the first update parameter, and the second update parameter.

13. The system according to any one of claims 9-11, characterized in that, The third signal processing unit includes a third signal processing module, a third buffer module, and a third inverse parameter determination module, wherein, The third signal processing module is used to process the third input digital signal according to the third processing parameters to obtain the third output digital signal; The third inverse parameter determination module is used to determine the second update parameter based on the first update parameter and the third input digital signal; The third buffer module is used to store the third input digital signal, the third output digital signal, the third processing parameter, the first update parameter, and the second update parameter.

14. The system according to any one of claims 9-11, characterized in that, Also includes: The channel model unit is configured to determine a fourth update parameter based on the first output digital signal and the third update parameter, and send the fourth update parameter to the first signal processing unit, wherein the third update parameter is determined by the second signal processing unit based on the second update parameter and the second input digital signal; The first signal processing unit is further configured to determine a fifth update parameter based on the fourth update parameter and the first input digital signal.

15. The system according to claim 14, characterized in that, The first signal processing unit is further configured to update the first processing parameter according to the fourth update parameter.

16. The system according to claim 14, characterized in that, The channel model unit is specifically used to process the first output digital signal according to the channel model parameters to obtain the channel model signal, and to determine the fourth update parameter according to the channel model signal and the third update parameter.

17. The system according to claim 16, characterized in that, The channel model unit includes a channel model module, a channel buffer module, and a channel inverse parameter determination module, wherein, The channel model module is used to process the first output digital signal according to the channel model parameters to obtain the channel model signal; The channel inverse parameter determination module is used to determine the fourth update parameter based on the channel model signal and the third update parameter; The channel buffer module is used to store the first output digital signal, the channel model signal, the channel model parameters, the third update parameter, and the fourth update parameter.

18. The system according to claim 15, characterized in that, The first signal processing unit includes a first signal processing module, a first parameter update module, a first buffer module, and a first inverse parameter determination module, wherein, The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; The first parameter update module is used to update the first processing parameter according to the fourth update parameter; The first reverse parameter determination module is used to determine the fifth update parameter based on the fourth update parameter and the first input digital signal; The first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the fourth update parameter, and the fifth update parameter.

19. The system according to claim 14, characterized in that, The first signal processing unit includes a first signal processing module, a first buffer module, and a first inverse parameter determination module, wherein, The first signal processing module is used to process the first input digital signal according to the first processing parameters to obtain the first output digital signal; The first reverse parameter determination module is used to determine the fifth update parameter based on the fourth update parameter and the first input digital signal; The first buffer module is used to store the first input digital signal, the first output digital signal, the first processing parameter, the fourth update parameter, and the fifth update parameter.

20. The system according to any one of claims 9-11, characterized in that, Also includes: The decision unit is used to make a decision on the third output digital signal to obtain the reference digital signal.

21. A signal processing method applied to a digital signal processing chip, characterized in that, include: The first input digital signal is processed according to the first processing parameters to obtain the first output digital signal; The second output digital signal is obtained by processing the first output digital signal, which is the second input digital signal, according to the second processing parameters. The first update parameter is obtained by processing the second output digital signal and the reference digital signal based on the global cost function, wherein the global cost function is used to determine the difference between the second output digital signal and the reference digital signal; Update the second processing parameters according to the first update parameters, and / or The first processing parameter is updated according to the second update parameter, which is determined based on the first update parameter and the second input digital signal.

22. The method according to claim 21, characterized in that, Also includes: The reference digital signal is obtained by making a decision on the second output digital signal.

23. A signal processing method applied to communication equipment, characterized in that, The communication device includes a third signal processing unit, and the method includes: The first input digital signal is processed according to the first processing parameters to obtain the first output digital signal; The first output digital signal is converted from digital to analog to obtain a first analog signal; The first analog signal is modulated onto a carrier wave to obtain a modulated signal; The modulated signal is demodulated to obtain a second analog signal; The second analog signal is converted to a digital signal by analog-to-digital conversion; The second output digital signal is obtained by processing the digital signal, which is the second input digital signal, according to the second processing parameters. The third output digital signal is obtained by processing the second output digital signal, which is the third input digital signal, according to the third processing parameters. The first update parameter is obtained by processing the third output digital signal and the reference digital signal based on the global cost function, wherein the global cost function is used to determine the difference between the third output digital signal and the reference digital signal; The third processing parameter is updated based on the first update parameter, and / or The second processing parameter is updated according to the second update parameter, which is determined by the third signal processing unit based on the first update parameter and the third input digital signal.

24. The method according to claim 23, characterized in that, The communication device further includes a second signal processing unit, and the method further includes: A fourth update parameter is determined based on the first output digital signal and the third update parameter, wherein the third update parameter is determined by the second signal processing unit based on the second update parameter and the second input digital signal; The fifth update parameter is determined based on the fourth update parameter and the first input digital signal.

25. The method according to claim 24, characterized in that, Also includes: The first processing parameter is updated according to the fourth update parameter.

26. The method according to claim 24 or 25, characterized in that, Determining the fourth update parameter based on the first output digital signal and the third update parameter includes: The channel model signal is obtained by processing the first output digital signal according to the channel model parameters; The fourth update parameter is determined based on the channel model signal and the third update parameter.

27. The method according to any one of claims 23-25, characterized in that, Also includes: The reference digital signal is obtained by making a decision on the second output digital signal.

28. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the method as described in claim 21 or 22.

29. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the method as described in any one of claims 23-27.

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